CN116405421B - Communication test method, system and storage medium of simulation chip test sorting machine - Google Patents
Communication test method, system and storage medium of simulation chip test sorting machine Download PDFInfo
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Abstract
The invention provides a communication test method, a system and a storage medium of an analog chip test separator, wherein the method comprises the following steps: generating target test parameters through a target simulation process, deploying the target test parameters in a target shared file, and sending a test starting instruction to an ATE control process; the ATE control process acquires target test parameters from the target shared file and sends the target test parameters to ATE test equipment for testing to obtain test data; the ATE test equipment returns the test data to an ATE control process, and the ATE control process stores the test data to a target shared file; and the target simulation process reads the test data from the target shared file and sends the test data to the upper computer, and the upper computer determines a communication test result according to the test data. According to the technical scheme provided by the embodiment of the invention, the target chip test separator can be simulated in the upper computer through the target simulation process, the target simulation process is in simulated communication with the upper computer in a file sharing mode, so that the simulated communication test is realized, the test cost is effectively reduced, and the test efficiency is improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a communication testing method, a communication testing system and a storage medium of an analog chip testing and sorting machine.
Background
The ATE equipment suite software uses modern computer languages (e.g., C, c++, java, python, labVIEW, or Smalltalk) and other statements to control the ATE equipment through standard and proprietary Application Programming Interfaces (APIs). The upper computer controls ATE equipment through a USB interface, and the mass production test of the chip is completed through GPIB, RS232 or TTL equipment matched with handler/ber communication.
After all functions of the software matched with the ATE equipment are realized, a communication module between the ATE equipment and a chip test sorting machine or a probe station is required to be verified, and the current method mainly performs a series of system verification by means of the chip test sorting machine or the probe station of an IC test sealing and testing factory, or a chip test equipment company purchases a corresponding model of test sorting machine or probe station to perform relative communication test, but the purchase cost of related equipment is high, equipment borrowing from the sealing and testing factory occupies the productivity of the equipment, and especially in the period of energy shortage, the equipment can not be borrowed, so that the test can not be normally performed.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides a communication test method, a communication test system and a communication test storage medium for a simulated chip test separator, which can simulate the communication test of the chip test separator, reduce the test cost and reduce the occupation of equipment.
In a first aspect, an embodiment of the present invention provides a communication test method for a test handler of an analog chip, where the test system includes an upper computer and an ATE test device, the upper computer is configured with a target simulation process, an ATE control process, and a target shared file, the target simulation process is used for simulating the test handler of the analog chip, the ATE test device is in communication connection with the ATE control process, and the target simulation process can read and write the target shared file through a communication protocol between the upper computer and the test handler of the analog chip, and the communication test method for the test handler of the analog chip includes:
generating target test parameters through the target simulation process, deploying the target test parameters in the target shared file, and sending a test starting instruction to the ATE control process;
the ATE control process responds to the test starting instruction to acquire the target test parameters from the target shared file, and sends the target test parameters to the ATE test equipment so that the ATE test equipment can test the obtained test data based on the target test parameters;
the ATE test equipment returns the test data to the ATE control process, and the ATE control process stores the test data to the target shared file;
and the target simulation process reads the test data from the target shared file and sends the test data to the upper computer so that the upper computer determines a communication test result according to the test data.
According to some embodiments of the present invention, a plurality of selectable shared files are preset in the upper computer, and the deploying the target test parameters in the target shared files includes:
when the ATE control process detects that the target simulation process is completely deployed, starting a test process based on the target simulation process, traversing the current optional shared file, determining the optional shared file corresponding to the target simulation process as the target shared file, and otherwise, creating the target shared file for the target simulation process.
According to some embodiments of the invention, the deploying the target test parameter in the target shared file includes:
reading preset parameter keywords in the target shared file through the target simulation process;
generating a configuration interface in the target simulation process, wherein the configuration interface comprises a test control key and a configuration area, the test control key is used for generating and sending the test starting instruction or the test ending instruction, and the configuration area corresponds to the parameter key;
when the test starting instruction is triggered through the test control key, acquiring the target test parameters input into the configuration area and sending the target test parameters to the target simulation process;
and emptying the content corresponding to the parameter keywords in the target shared file through the target simulation process, writing the target test parameters into the target shared file, and associating the corresponding parameter keywords.
According to some embodiments of the invention, the ATE control process, in response to the test initiation instruction, obtaining the target test parameters from the target shared file, comprises:
the ATE control process polls the target shared file;
when the content of the target shared file is detected to be changed in the polling process, and the content corresponding to the parameter key words in the target shared file is not empty, acquiring the target test parameters from the target shared file;
the ATE control process erases the target test parameters in the target shared file.
According to some embodiments of the invention, the method further comprises:
and when the target simulation process acquires new target test parameters before acquiring the test ending instruction, detecting that the content corresponding to the parameter keywords in the target shared file is empty, writing the new target test parameters into the target shared file and associating the corresponding parameter keywords.
According to some embodiments of the invention, after the target simulation process reads the test data from the target shared file and sends the test data to the host computer, the method further comprises:
when the test control key triggers the test ending instruction, the test ending instruction is sent to the ATE control process, so that the ATE control process stops polling the target shared file and controls the ATE test equipment to stop testing;
and emptying the target shared file through the target simulation process.
According to some embodiments of the invention, the test system further comprises the target chip test handler, and the method further comprises, prior to the generating target test parameters by the target simulation process:
when the registration information of the target chip test classifier on the upper computer is detected, generating the target test parameters through the upper computer, and sending the target test parameters to the target chip test classifier for testing;
or when the registration information of the target chip test handler on the upper computer is not detected, generating target test parameters through the target simulation process.
In a second aspect, an embodiment of the present invention provides a communication test system of an analog chip test handler, including at least one control processor and a memory for communication connection with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the communication test method of the analog chip test handler as described in the first aspect.
In a third aspect, an embodiment of the present invention provides a test system, including a communication test system of an analog chip test handler according to the second aspect.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions for performing the communication test method of the analog chip test handler according to the first aspect.
The communication test method of the simulation chip test sorting machine provided by the embodiment of the invention has at least the following beneficial effects: generating target test parameters through the target simulation process, deploying the target test parameters in the target shared file, and sending a test starting instruction to the ATE control process; the ATE control process responds to the test starting instruction to acquire the target test parameters from the target shared file, and sends the target test parameters to the ATE test equipment so that the ATE test equipment can test the obtained test data based on the target test parameters; the ATE test equipment returns the test data to the ATE control process, and the ATE control process stores the test data to the target shared file; and the target simulation process reads the test data from the target shared file and sends the test data to the upper computer so that the upper computer determines a communication test result according to the test data. According to the technical scheme provided by the embodiment of the invention, the simulation software can be set in the upper computer as the target simulation process of the target chip test handler, and the target simulation process is in simulation communication with the upper computer in a file sharing mode, so that the simulation communication test is realized, the test cost is effectively reduced, and the test efficiency is improved.
Drawings
FIG. 1 is a flow chart of a communication test method of an analog chip test handler according to an embodiment of the present invention;
FIG. 2 is a flow chart for creating a target shared file provided by another embodiment of the invention;
FIG. 3 is a flow chart of configuring target test parameters provided by another embodiment of the present invention;
FIG. 4 is a schematic diagram of a configuration area provided by another embodiment of the present invention;
FIG. 5 is a flow chart of ATE test equipment reading target test parameters according to another embodiment of the present invention;
FIG. 6 is a flow chart of configuring new target test parameters provided by another embodiment of the present invention;
FIG. 7 is a flow chart of ATE test equipment reading new target test parameters according to another embodiment of the present invention;
FIG. 8 is a flow chart of an end test provided by another embodiment of the present invention;
fig. 9 is a block diagram of a communication test system of an analog chip test handler according to another embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The embodiment of the invention provides a communication test method, a system and a storage medium of an analog chip test separator, wherein the communication test method of the analog chip test separator comprises the following steps: generating target test parameters through the target simulation process, deploying the target test parameters in the target shared file, and sending a test starting instruction to the ATE control process; the ATE control process responds to the test starting instruction to acquire the target test parameters from the target shared file, and sends the target test parameters to the ATE test equipment so that the ATE test equipment can test the obtained test data based on the target test parameters; the ATE test equipment returns the test data to the ATE control process, and the ATE control process stores the test data to the target shared file; and the target simulation process reads the test data from the target shared file and sends the test data to the upper computer so that the upper computer determines a communication test result according to the test data. According to the technical scheme provided by the embodiment of the invention, the simulation software can be set in the upper computer as the target simulation process of the target chip test handler, and the target simulation process is in simulation communication with the upper computer in a file sharing mode, so that the simulation communication test is realized, the test cost is effectively reduced, and the test efficiency is improved.
The control method of the embodiment of the invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a communication test method of a test handler for a simulation chip, where the method is applied to a test system, the test system includes an upper computer and an ATE test device, the upper computer is deployed with a target simulation process, an ATE control process and a target shared file, the target simulation process is used for simulating the test handler for the simulation chip, the ATE test device is communicatively connected with the ATE control process, the target simulation process can read and write the target shared file through a communication protocol between the upper computer and the test handler for the simulation chip, and the communication test method of the test handler for the simulation chip includes:
step S110, generating target test parameters through a target simulation process, deploying the target test parameters in a target shared file, and sending a test start instruction to an ATE control process;
step S120, the ATE control process responds to the test starting instruction to acquire target test parameters from the target shared file and sends the target test parameters to ATE test equipment so as to enable the ATE test equipment to test the obtained test data based on the target test parameters;
step S130, the ATE test equipment returns the test data to an ATE control process, and the ATE control process stores the test data to a target shared file;
and step S140, the target simulation process reads the test data from the target shared file and sends the test data to the upper computer so that the upper computer determines a communication test result according to the test data.
It should be noted that, the chip test Handler of the present embodiment may be a common Handler or a Prober machine, hereinafter referred to as a machine, and the following embodiments will not be repeated.
It should be noted that, the upper computer is provided with test matching software corresponding to the ATE test equipment, that is, the ATE control process in this embodiment, simulation software is further deployed in the upper computer, and the simulation software is used to start a target simulation process, where the target simulation process is used to send a test signal between the simulation machine and the ATE control process, return a software test signal, receive a return message of the ATE control process by the simulation machine, and so on, so that message interaction between the simulation machine and the ATE test equipment and between the simulation machine and the upper computer can be simulated.
It should be noted that, in the related art, the host computer and the machine platform of the entity are mainly in bidirectional communication through GPIB, and in this embodiment, after the machine platform is simulated through the target simulation process, the host computer and the target simulation process can be in bidirectional communication through a file sharing manner. It should be noted that the target shared file may be set in the upper computer, and because the communication protocol between the machine and the upper computer is known, in order to simulate the communication between the machine and the upper computer, the target simulation process and the upper computer may be configured based on the communication protocol, so that the upper computer accesses the target shared file through the communication protocol, and reads and writes the target shared file, thereby implementing communication simulation. Similarly, the communication between the ATE test device and the target shared file may also be configured according to the communication flow between the ATE test device and the machine, which is not repeated herein.
After the target simulation process simulates the Handler or the Prober test flow, the configured target test parameters are written into the target shared file, the data communication between the host computer and the machine is simulated, the ATE control process obtains the target test parameters from the target shared file and sends the target test parameters to the ATE test equipment for testing, so as to realize the communication simulation between the ATE test equipment and the machine.
It should be noted that after the test result is obtained, the machine is usually required to be transmitted back to the ATE test device, so that the test data can be transmitted back to the target shared file, and the upper computer can obtain the test data from the target shared file to complete the communication test of the whole test flow.
In addition, in an embodiment, a plurality of optional shared files are preset in the upper computer, referring to fig. 2, step S110 shown in fig. 1 further includes, but is not limited to, the following steps:
step S210, when the ATE control process detects that the target simulation process is completed, and starts a test process based on the target simulation process, the current optional shared file is traversed, the optional shared file corresponding to the target simulation process is determined as the target shared file, and otherwise, the target shared file is created for the target simulation process.
It should be noted that, in this embodiment, the simulation process is performed on the machine, and a corresponding shared file needs to be created when the simulation process is configured each time, so as to save a process, the created shared file may be reserved after the test is finished, and an identifier corresponding to the machine is set, so that after the deployment of the target simulation process is completed, an existing optional shared file may be traversed, for example, the traversing is performed through the machine identifier, when the optional shared file with the same identifier is detected, the optional shared file may be determined as the target shared file, and a subsequent operation is performed, and if the traversing fails, the target shared file is newly created, and a parameter keyword related to the test is configured in the target shared file.
In addition, referring to fig. 3, in an embodiment, step S110 shown in fig. 1 further includes, but is not limited to, the following steps:
step S310, reading preset parameter keywords in a target shared file through a target simulation process;
step S320, generating a configuration interface in the target simulation process, wherein the configuration interface comprises a test control key and a configuration area, the test control key is used for generating and sending a test starting instruction or a test ending instruction, and the configuration area corresponds to the parameter key;
step S330, when a test start instruction is triggered by a test control key, acquiring target test parameters input into a configuration area;
step S340, the content corresponding to the parameter keywords in the target shared file is cleared through the target simulation process, the target test parameters are written into the target shared file, and the corresponding parameter keywords are associated.
It should be noted that, the parameter keywords may be set according to a specific test machine, for example, for a handler machine, the parameter keywords may be site number setting, walking time setting, a current test state of the machine, and the like; for the prober machine, the parameter keywords may be site number setting, walking time setting, wafer id setting, XY coordinate setting, work order number setting, sheet returning and changing operation, etc., and those skilled in the art have an incentive to adjust the specific types of the parameter keywords according to actual requirements, which are not limited herein.
It should be noted that, when the test is started, in order to ensure the accuracy of the target test parameters, the content in the target shared file may be emptied through the target simulation process, and then the parameter writing is started.
It should be noted that, as shown in fig. 4, the configuration interface may be referred to in fig. 4, where a corresponding site may be selected by a checking manner, and a configuration area may be set to set a corresponding delay and SRQ value, and meanwhile, test control buttons are set in the configuration interface, where two test control buttons are set in this example, one is used to start a test and generate a test start instruction (such as "start Handler" shown in fig. 4), and one is used to stop the test and generate a test end instruction (such as "stop Handler" shown in fig. 4), and visual configuration of target test parameters is implemented through the configuration interface, where the target test parameters configured in the configuration interface are sent to a target simulation process, and the target simulation process writes the target test parameters into a target shared file, so that the ATE test device can acquire the corresponding target test parameters from the target shared file to perform a subsequent test, thereby simulating a communication test between devices.
In addition, referring to fig. 5, step S120 shown in fig. 1 further includes, but is not limited to, the following steps:
step S510, the ATE control process polls the target shared file;
step S520, when the change of the content of the target shared file is detected in the polling process, and the content corresponding to the parameter key words in the target shared file is not empty, acquiring the target test parameters from the target shared file;
in step S530, the ATE control process erases the target test parameters in the target shared file.
It should be noted that after the configuration of the target simulation process and the target shared file is completed, when the mass production test process is started in the ATE control process, the ATE control process polls the target shared file to simulate polling the machine, when it is detected that the content of the target shared file is changed and is not empty, it may be determined that the configuration of the target test parameters is completed according to the steps of the embodiment shown in fig. 3, the ATE control process acquires the corresponding target test parameters from the target shared file, erases the target test parameters in the target shared file, so that the target simulation process senses that the transfer of the target test parameters is completed, and may execute the next writing.
Additionally, in one embodiment, referring to FIG. 6, the steps of, but not limited to, the following:
in step S610, when the target simulation process acquires a new target test parameter before acquiring the test end instruction, and detects that the content corresponding to the parameter keyword in the target shared file is empty, the new target test parameter is written into the target shared file and the corresponding parameter keyword is associated.
It should be noted that, the test process may involve multiple parameter configurations, and after the ATE control process completes data acquisition and sends the data to the ATE test equipment once, the ATE control process erases the content in the target shared file, so when a new target test parameter (for example, a parameter corresponding to a new site) is set through the configuration interface, it is first detected whether the content of the target shared file is empty, when it is detected that the content is not empty, the parameter configured before is not yet read by the ATE control process, in order to avoid interference to the test, polling may be continued until it is detected that the content in the target shared file is empty, and then the new target test parameter is written in, and the steps shown in fig. 5 are repeated to perform an operation.
In addition, in an embodiment, referring to fig. 7, after step S140 shown in fig. 1 is performed, the following steps are included, but not limited to:
step S710, when the test end instruction is triggered by the test control key, the test end instruction is sent to the ATE control process, so that the ATE control process stops polling the target shared file and controls the ATE test equipment to stop testing;
in step S720, the target shared file is emptied through the target simulation process.
After the test ending instruction is triggered, the ATE control process does not poll the target shared file and stops the test, and erases the content of the target shared file at the same time.
In addition, in an embodiment, the test system further includes a target chip test handler, referring to fig. 8, before performing step S130 shown in fig. 1, further including, but not limited to, the following steps:
step S810, when the registration information of the target chip test classifier is detected, generating target test parameters through the upper computer, and sending the target test parameters to the target chip test classifier for testing;
in step S820, when the registration information of the target chip test handler on the host computer is not detected, the target test parameters are generated through the target simulation process.
It should be noted that, in the technical solution of this embodiment, not only the machine can be simulated, but also a conventional communication test can be performed with the physical machine in the case of having the physical machine, and in order to distinguish whether the physical machine is provided, in this embodiment, the judgment is performed by the registration information of the machine (i.e. the target chip test handler). Before the test starts, the machine needs to register the equipment on the upper computer, so that when registration information is detected, the machine can be determined to have the entity machine, and the test can be performed according to the conventional flow; when no registration information is detected, it may be determined that no physical machine is provided, and a simulation test is performed according to the method of the above embodiment.
It should be noted that, in order to implement the above-mentioned determination, this embodiment may be implemented in a code shielding manner, for example, two sets of process codes are deployed in the target simulation process and the supporting software of the ATE test device at the same time, one set is a conventional test process, and the other set is a simulation process described in the above-mentioned embodiment, when registration information is detected, the conventional test process is executed, and when registration information is not detected, the code of the conventional test process is shielded, so that each software executes the simulation process, and may also be selected in other manners, which is not limited herein.
In order to better illustrate the technical solution of the present embodiment, the following describes an exemplary simulation test procedure of the present embodiment, and in this example, the target simulation process is exemplified by simulation handler/ber software:
firstly, according to the flow of the handler/ber communication, the communication mode between the upper computer and the simulation handler/ber software is replaced by a shared file mode from GPIB lines, and the communication object is the simulation handler/ber software. In the matched software of the ATE test equipment, according to the interaction mode between the communication flow perfection and the shared file of the simulation handler/ber software, the specific interaction content can cover the acquisition of the test state from the machine, the acquisition of the test information from the machine, the transmission of the test result to the machine and the like. And isolating all the actual communication processes by using programming sentences, for example, different communication modules can be called by different macro definitions. And customizing keywords and contents related to the Handler/Prober communication used in the shared file according to information acquired by the actual Handler/Prober communication or information to be transmitted.
Secondly, according to the rule that the machine platform of the Handler/proger sends data to or receives data from a computer, a set of process that the sending information of the Handler/proger is compared with the obtaining information is realized in engineering, and according to the shared file receiving data and the sending data rule which are already customized by the matched software of ATE equipment, the sending rule customization and the receiving data processing rule customization are carried out. The method comprises the steps of obtaining a shared file path of a simulation Handler/proger on an interface of simulation software, setting a site number, setting a walking time and setting a current test state of a machine in a Handler mode, and setting the site number, the walking time, the wafer id, the XY coordinate, the work order number and the disc returning and changing operation in the proger mode.
Then, when the simulation Handler/proger is required to be used for verification, the codes related to the simulation Handler/proger are opened in the matched software of the ATE equipment, and the communication codes of the actual connecting machine are closed and compiled. After the software is started, clicking the start test software under the mass production interface can immediately detect whether the shared file exists, immediately creating and updating the corresponding keywords into the shared file if the shared file does not exist, reading the keywords in the shared file in a polling mode to wait for the test signal of simulating the Handler/Prober software to be transmitted, opening the simulating Handler/Prober software, selecting the shared file read by the matched software of the ATE equipment, and configuring according to some information of the test item of the current test, such as the test site number, the walking time of the machine and the test state of the current machine.
The configuration then completes clicking the start test button of the simulated Hanlder/Prober software. The contents of the keywords in the shared file are modified based on the actual configuration. When the matched software of the ATE test equipment reads that the current keyword is changed, the next operation is started, and the content of the keyword in the shared file is erased. When the simulation Handler/proger software reads the key words in the shared directory and erases the key words, and reads the information sent back from the ATE software, analysis and processing of the returned data of the ATE software can be started, when the returned information is correct, the sending instruction in the shared file is updated, and when the returned data is abnormal, the updating operation is stopped and the machine alarm prompt is simulated. After the data is returned, the ATE software can read the content in the shared file to see whether the content is changed, and once the content is updated, the ATE software can complete corresponding operation according to the instruction of actual update, and complete a round of complete test on the returned data. And when the equivalent production stops testing, the current keywords of the shared file are read, and the keywords are erased. And meanwhile, the simulation of the Handler/Prober software is stopped, and the keywords in the shared file are erased again as verification, so that the test is ended.
As shown in fig. 9, fig. 9 is a block diagram of a communication test system of an analog chip test handler according to an embodiment of the present invention. The invention also provides a communication test system of the simulation chip test sorting machine, which comprises:
the processor 901 may be implemented by a general purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing related programs to implement the technical solutions provided by the embodiments of the present application;
the Memory 902 may be implemented in the form of a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access Memory (Random Access Memory, RAM). The memory 902 may store an operating system and other application programs, and when the technical solution provided in the embodiments of the present application is implemented by software or firmware, relevant program codes are stored in the memory 902, and the processor 901 invokes a communication test method for executing the simulated chip test handler of the embodiments of the present application;
an input/output interface 903 for inputting and outputting information;
the communication interface 904 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g. USB, network cable, etc.), or may implement communication in a wireless manner (e.g. mobile network, WIFI, bluetooth, etc.);
a bus 905 that transfers information between the various components of the device (e.g., the processor 901, the memory 902, the input/output interface 903, and the communication interface 904);
wherein the processor 901, the memory 902, the input/output interface 903 and the communication interface 904 are communicatively coupled to each other within the device via a bus 905.
The embodiment of the application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program realizes the communication test method of the simulation chip test sorting machine when being executed by a processor.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The apparatus embodiments described above are merely illustrative, in which the elements illustrated as separate components may or may not be physically separate, implemented to reside in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (9)
1. The communication test method for the simulation chip test classifier is characterized by being applied to a test system, wherein the test system comprises an upper computer and ATE test equipment, the upper computer is provided with a target simulation process, an ATE control process and a target shared file, the target simulation process is used for simulating the target chip test classifier, the ATE test equipment is in communication connection with the ATE control process, the target simulation process can read and write the target shared file through a communication protocol between the upper computer and the target chip test classifier, and the communication test method for the simulation chip test classifier comprises the following steps:
generating target test parameters through the target simulation process, and reading preset parameter keywords in the target shared file through the target simulation process;
generating a configuration interface in the target simulation process, wherein the configuration interface comprises a test control key and a configuration area, the test control key is used for generating and sending the test starting instruction or the test ending instruction, and the configuration area corresponds to the parameter key;
when the test starting instruction is triggered through the test control key, acquiring the target test parameters input to the configuration area;
the target simulation process empties the content corresponding to the parameter keywords in the target shared file, writes the target test parameters into the target shared file, associates the corresponding parameter keywords, and sends a test starting instruction to the ATE control process;
the ATE control process responds to the test starting instruction to acquire the target test parameters from the target shared file, and sends the target test parameters to the ATE test equipment so that the ATE test equipment can test based on the target test parameters to obtain test data;
the ATE test equipment returns the test data to the ATE control process, and the ATE control process stores the test data to the target shared file;
and the target simulation process reads the test data from the target shared file and sends the test data to the upper computer so that the upper computer determines a communication test result according to the test data.
2. The communication test method of the simulated chip test handler according to claim 1, wherein a plurality of selectable shared files are preset in the upper computer, and the deploying the target test parameters in the target shared files comprises:
when the ATE control process detects that the target simulation process is completely deployed, starting a test process based on the target simulation process, traversing the current optional shared file, determining the optional shared file corresponding to the target simulation process as the target shared file, and otherwise, creating the target shared file for the target simulation process.
3. The communication test method of the analog chip test handler of claim 1, wherein the ATE control process obtaining the target test parameters from the target shared file in response to the test initiation instruction, comprising:
the ATE control process polls the target shared file;
when the content of the target shared file is detected to be changed in the polling process, and the content corresponding to the parameter key words in the target shared file is not empty, acquiring the target test parameters from the target shared file;
the ATE control process erases the target test parameters in the target shared file.
4. The communication test method of the analog chip test handler according to claim 3, further comprising:
and when the target simulation process acquires new target test parameters before acquiring the test ending instruction, detecting that the content corresponding to the parameter keywords in the target shared file is empty, writing the new target test parameters into the target shared file and associating the corresponding parameter keywords.
5. The communication test method of the simulation chip test handler according to claim 3, wherein after the target simulation process reads the test data from the target shared file and transmits the test data to the host computer, the method further comprises:
when the test control key triggers the test ending instruction, the test ending instruction is sent to the ATE control process, so that the ATE control process stops polling the target shared file and controls the ATE test equipment to stop testing;
and emptying the target shared file through the target simulation process.
6. The communication test method of a simulation chip test handler according to claim 1, wherein the test system further comprises the target chip test handler, the generating target test parameters by the target simulation process comprises:
when the registration information of the target chip test classifier on the upper computer is detected, generating the target test parameters through the upper computer, and sending the target test parameters to the target chip test classifier for testing;
or when the registration information of the target chip test handler on the upper computer is not detected, generating target test parameters through the target simulation process.
7. A communication test system for an analog chip test handler, comprising at least one control processor and a memory for communication connection with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the communication test method of the analog chip test handler of any one of claims 1 to 6.
8. A test system comprising a communication test system of the analog chip test handler of claim 7.
9. A computer-readable storage medium storing computer-executable instructions for causing a computer to execute the communication test method of the analog chip test handler according to any one of claims 1 to 6.
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