CN116404026A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN116404026A
CN116404026A CN202310370506.0A CN202310370506A CN116404026A CN 116404026 A CN116404026 A CN 116404026A CN 202310370506 A CN202310370506 A CN 202310370506A CN 116404026 A CN116404026 A CN 116404026A
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China
Prior art keywords
power supply
grounding
trace
substrate
wires
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CN202310370506.0A
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Chinese (zh)
Inventor
张�荣
李荣荣
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HKC Co Ltd
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HKC Co Ltd
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Priority to CN202310370506.0A priority Critical patent/CN116404026A/en
Publication of CN116404026A publication Critical patent/CN116404026A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application provides a display panel and a display device, wherein the display panel comprises a substrate, a data line, a scanning line, a pixel unit, a power supply wiring and a grounding wiring. The substrate is provided with a display area and a non-display area; the power supply wiring comprises a first power supply wiring and a second power supply wiring; the grounding trace includes a first grounding trace and a second grounding trace. The power supply wiring and the grounding wiring are distributed in a grid mode, and two adjacent rows of pixel units share one first power supply wiring or one first grounding wiring; a second power supply wire or a second grounding wire is arranged in a gap between at least two adjacent columns of pixel units; or, the orthographic projection of the second power supply wiring on the substrate and/or the orthographic projection of the second grounding wiring on the substrate are overlapped with the orthographic projection part of the pixel units on the substrate in the corresponding column direction, so that the wiring of the non-display area can be reduced to realize narrow frame design, and the problem of uneven display caused by voltage drop of the power supply wiring is solved.

Description

Display panel and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
Inorganic Micro light emitting diode (Micro Light Emitting Diode, micro LED) displays are one of the hot spots in the display research field today. The Micro LED has the advantages of high reliability, low power consumption, high brightness, high response speed and the like.
In the present day, where consumers are increasingly demanding with respect to the visual range of display panels, many manufacturers desire to design electronic device displays with narrow and even no borders. The lengths of the power supply wiring VDD and the ground wiring VSS on the display panel are longer, the VDD/VSS main line on the display panel is wider, and the wiring is complex to occupy more display areas, which is not beneficial to manufacturing borderless products and improving the resolution of the panel.
Disclosure of Invention
The technical problem that this application mainly solves is to provide a display panel and display device, solves among the prior art because of VDD/VSS walks complicated be unfavorable for the manufacturing borderless product and improves the problem of the resolution ratio of panel.
In order to solve the technical problem, the first technical scheme provided by the application is as follows: provided is a display panel including:
a substrate having a display region and a non-display region; a first metal layer and a second metal layer are laminated on one side of the substrate; the first metal layer is used for forming scanning lines, the second metal layer is used for forming power supply wires, grounding wires and data wires, and the power supply wires, the grounding wires and the data wires are mutually insulated;
the pixel units are arranged on one side, far away from the substrate, of the second metal layer and are arranged in an array; defining the row direction of the pixel units as a first direction and the column direction of the pixel units as a second direction;
the power supply wires are distributed in a grid mode and comprise a first power supply wire and a second power supply wire which are positioned in the display area and connected with each other;
the grounding wires are distributed in a grid mode and comprise a first grounding wire and a second grounding wire which are positioned in the display area and connected with each other;
two adjacent rows of pixel units share one first power supply wire or one first grounding wire;
one second power supply wire or one second grounding wire is arranged in a gap between at least part of two adjacent columns of pixel units; or, the orthographic projection of the second power supply wire on the substrate and/or the orthographic projection of the second grounding wire on the substrate are overlapped with the orthographic projection part of the pixel unit on the substrate corresponding to the column direction.
The first power supply wires extend along the first direction, the second power supply wires extend along the second direction, and each second power supply wire is connected with at least two first power supply wires; the first grounding wires extend along the first direction, the second grounding wires extend along the second direction, and each second grounding wire is connected with at least two first grounding wires.
The power supply wiring further comprises a power supply common line, wherein the power supply common line is arranged along the second direction and used for connecting the first power supply wiring and/or the second power supply wiring, and extends to the outside of the display area to be connected with a source driver; the grounding trace further comprises a grounding common line which is arranged along the second direction and used for connecting the first grounding trace and/or the second grounding trace, and extends to the outside of the display area to be connected with the source driver.
Each scanning line comprises a first scanning line segment and a second scanning line segment which are connected; the first scanning line segment extends along the first direction, one end of the second scanning line segment is connected with the first scanning line segment, and the other end of the second scanning line segment extends out of the display area along the second direction and is connected with the gate driver; the data line extends along the second direction and is connected with the source driver.
The power supply wiring and the grounding wiring are respectively connected with the source driver; the gate driver and the source driver are both arranged in the non-display area and are positioned on the same side of the display area along the second direction.
Wherein two adjacent second scanning line segments are positioned on two opposite sides of at least one row of the pixel units along the second direction; and one second power supply wire or one second grounding wire is arranged in a gap between at least two adjacent columns of pixel units.
The second scanning line segment and the pixel unit are partially overlapped in the direction perpendicular to the substrate; and the orthographic projection of the second power supply wire on the substrate and the orthographic projection of the second grounding wire on the substrate are overlapped with the orthographic projection part of the pixel unit on the substrate corresponding to the column direction.
The pixel unit comprises a first electrode used for being connected with the first power supply wire and a second electrode used for being connected with the first grounding wire; the first electrode and the second electrode of the pixel unit are respectively positioned at two opposite sides of the corresponding pixel unit along the second direction; the arrangement direction of the first and second electrodes of the pixel cells in the odd-numbered rows is opposite to the arrangement direction of the first and second electrodes of the pixel cells in the even-numbered rows.
The power supply wiring, the grounding wiring and the data line are arranged at the crossing position of each other in a crossing mode.
In order to solve the technical problem, the second technical scheme provided by the application is as follows: there is provided a display device including a housing and the display panel described above.
The beneficial effects of this application: unlike the prior art, the application provides a display panel and a display device, wherein the display panel comprises a substrate, data lines, scanning lines, pixel units, power supply wires and grounding wires. The substrate is provided with a display area and a non-display area; a first metal layer and a second metal layer are laminated on one side of the substrate; the first metal layer is used for forming scanning lines, the second metal layer is used for forming power supply wires, grounding wires and data wires, and the power supply wires, the grounding wires and the data wires are mutually insulated; the pixel units are arranged on one side, far away from the substrate, of the second metal layer and are arranged in an array; defining a row direction of the pixel units as a first direction and defining a column direction of the pixel units as a second direction; the power supply wires are distributed in a grid mode and comprise a first power supply wire and a second power supply wire which are positioned in the display area and connected with each other; the grounding wires are distributed in a grid mode and comprise a first grounding wire and a second grounding wire which are positioned in the display area and connected with each other; two adjacent rows of pixel units share a first power supply wiring or a first grounding wiring; a second power supply wire or a second grounding wire is arranged in a gap between at least part of two adjacent columns of pixel units; or, the orthographic projection of the second power supply wire on the substrate and/or the orthographic projection of the second grounding wire on the substrate are overlapped with the orthographic projection part of the pixel unit in the corresponding column direction on the substrate. The power supply wiring and the grounding wiring are distributed in a grid mode, and two adjacent rows of pixel units share one first power supply wiring or one first grounding wiring; and a second power supply wire or a second grounding wire is arranged in a gap between at least two adjacent rows of pixel units, or orthographic projection of the second power supply wire on the substrate and/or orthographic projection of the second grounding wire on the substrate are overlapped with orthographic projection parts of the pixel units on the substrate in the corresponding row direction, so that narrow frame design of wires in a non-display area can be reduced, and the problem of uneven display caused by voltage drop of the power supply wires is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without any inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a first embodiment of a display panel provided in the present application;
FIG. 2 is a schematic longitudinal sectional view of the display panel of FIG. 1;
FIG. 3 is a pixel drive circuit diagram provided herein;
fig. 4 is a schematic structural diagram of a second embodiment of a display panel provided in the present application;
FIG. 5 is a schematic diagram of a trace distribution structure of a fan-out area provided in the present application;
fig. 6 is a schematic structural diagram of a third embodiment of a display panel provided in the present application.
Reference numerals illustrate:
the display panel-100, the substrate-10, the display area-11, the non-display area-12, the pixel unit-20, the first electrode-21, the second electrode-22, the pixel driving circuit-23, the light emitting element-24, the first thin film transistor-T1, the second thin film transistor-T2, the Gate electrode-G, the source electrode-S, the drain electrode-D, the capacitor-C, the power supply trace-VDD, the first power supply trace-31, the second power supply trace-32, the power supply common line-33, the first partition-34, the ground trace-VSS, the first ground trace-41, the second ground trace-42, the ground common line-43, the second partition-44, the metal lead-50, the Data line-Data/D1/D2 … … Dn, the scan line-Gate/G1/G2 … … Gm, the first scan line segment-61, the second scan line segment-62, the first metal layer-101, the first insulating layer-102, the second metal layer-103, the second Gate insulating layer-104, the Gate insulating layer-105, the first driver-X-Y direction and the fan-Y direction 107.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," and the like in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of a first embodiment of a display panel provided in the present application, and fig. 2 is a schematic longitudinal sectional structural diagram of the display panel in fig. 1.
The present application provides a display panel 100. The display panel 100 includes a substrate 10 and a pixel unit 20. A first metal layer 101 and a second metal layer 103 are stacked on one side of the substrate 10. Specifically, the display panel 100 includes a first metal layer 101, a first insulating layer 102, a second metal layer 103, and a second insulating layer 104, which are sequentially stacked on one side of the substrate 10. The first metal layer 101 is used to form a scan line Gate. The second metal layer 103 is used for forming a power trace VDD, a ground trace VSS and a Data line Data, and the power trace VDD, the ground trace VSS and the Data line Data are mutually insulated from each other.
The substrate 10 has a display region 11 and a non-display region 12. The non-display area 12 is disposed on at least one side of the display area 11, and is not limited herein, and is selected according to actual requirements.
The pixel units 20 are disposed on a side of the second metal layer 103 away from the substrate 10, and are arranged in an array. Specifically, the pixel unit 20 is disposed on a side of the second insulating layer 104 away from the substrate 10. The row direction of the pixel cells 20 is defined as a first direction X and the column direction of the pixel cells 20 is defined as a second direction Y. The first direction X and the second direction Y may be disposed vertically or non-vertically, where no limitation is imposed, and selection is made according to actual requirements.
The first direction X does not refer to a specific direction. The first direction X may be parallel to the extending direction of the Data line Data or may be parallel to the extending direction of the scan line Gate.
In the present embodiment, the first direction X is perpendicular to the second direction Y, and the first direction X is parallel to a side of the display panel 100. The first direction X is parallel to the extending direction of the scan line Gate, and the second direction Y is parallel to the extending direction of the Data line Data.
Further, the pixel unit 20 includes a light emitting element 24. The Light Emitting element 24 may be an LED (Light-Emitting Diode), an OLED (Organic Light-Emitting Diode), or other Light Emitting devices, which are not limited in this regard. The LEDs may be Micro LEDs (Micro light emitting diodes) or Mini LEDs (sub-millimeter light emitting diodes), etc. In the present embodiment, the light emitting element 24 is a Micro LED.
The Data lines Data are respectively denoted as D1 and D2 … … Dn, the scan lines Gate are respectively denoted as G1 and G2 … … Gm, where n and m are both natural numbers, and the sizes of n and m are not limited herein and can be selected according to actual needs. The plurality of Data lines Data are connected to the source driver 106, respectively, and the plurality of scan lines Gate are connected to the Gate driver 105, respectively.
In the present embodiment, the source driver 106 is located at one side of the display area 11 along the second direction Y, and the gate driver 105 is located at one side of the display area 11 along the first direction X. The pixel unit 20 is located in an area defined by the Data line Data and the scan line Gate in a crisscross manner. In other embodiments, in the direction perpendicular to the substrate 10, a portion of the pixel units 20 may overlap with the area defined by the Data lines Data and the scan lines Gate, and a portion of the pixel units 20 extends beyond the area defined by the Data lines Data and the scan lines Gate.
The power supply wires VDD are distributed in a grid. The power supply trace VDD includes a first power supply trace 31 and a second power supply trace 32 which are located in the display area 11 and connected. The ground traces VSS are distributed in a grid. The ground trace VSS includes a first ground trace 41 and a second ground trace 42 which are located in the display area 11 and connected. Two adjacent rows of pixel units 20 share a first power supply wire 31 or a first grounding wire 41, and a second power supply wire 32 or a second grounding wire 42 is arranged in a gap between at least part of two adjacent columns of pixel units 20; alternatively, the orthographic projection of the second power trace 32 on the substrate 10 and/or the orthographic projection of the second ground trace 42 on the substrate 10 are disposed so as to overlap with the orthographic projection portions of the pixel units 20 in the corresponding column direction on the substrate 10.
Specifically, the first power trace 31 and the second power trace 32 are multiple. The first power supply wires 31 extend along the first direction X, the second power supply wires 32 extend along the second direction Y, and each second power supply wire 32 is connected with at least two first power supply wires 31. That is, each of the second power traces 32 may be connected to all of the first power traces 31, respectively. Each second power supply wire 32 may be connected to a part of the first power supply wires 31, and the number of the first power supply wires 31 connected to each second power supply wire 32 may be the same or different, which only needs to ensure that all the second power supply wires 32 and all the first power supply wires 31 are mutually communicated.
In the present embodiment, each of the second power traces 32 is connected to all of the first power traces 31, respectively.
The power supply trace VDD further includes a power supply common line 33. The power common line 33 extends along the second direction Y, is used for connecting the first power trace 31 and/or the second power trace 32, and extends to the outside of the display area 11 to be connected with the source driver 106. That is, the first and second power traces 31 and 32 are connected to the high-level common voltage through the power common line 33 connected to the source driver 106. It should be understood that the power common line 33 may be extended in other directions, so long as it is ensured that the power common line 33 extends outside the display area 11 to be connected to the source driver 106.
In this application, "a and/or B" means that only a, only B, or both a and B are included.
The first grounding trace 41 and the second grounding trace 42 are multiple. The first grounding trace 41 extends along the first direction X, the second grounding trace 42 extends along the second direction Y, and each second grounding trace 42 is connected to at least two first grounding traces 41. The connection manner of the ground trace VSS and the power trace VDD is the same, and will not be described herein too much, please refer to the description of the first power trace 31 and the second power trace 32.
In the present embodiment, each second grounding trace 42 is connected to all the first grounding traces 41 respectively.
The ground trace VSS further includes a ground common line 43. The ground common line 43 is disposed along the second direction Y, is used for connecting the first ground trace 41 and/or the second ground trace 42, and extends to the outside of the display area 11 to be connected with the source driver 106. That is, the first and second ground wirings 41 and 42 are connected to the low-level common voltage through the ground common line 43 connected to the source driver 106. It should be understood that the ground common line 43 may be extended in other directions, so long as the ground common line 43 is ensured to extend outside the display area 11 to be connected to the source driver 106.
In the present embodiment, the power common line 33 and the ground common line 43 are disposed on the same side of the non-display area 12 along the second direction Y of the display area 11, so as to connect the source driver 106, reduce the wiring of the non-display area 12, and realize a narrow frame design.
Further, two adjacent rows of pixel units 20 share one first power supply trace 31 or one first ground trace 41, that is, the first power supply trace 31 and the first ground trace 41 are not simultaneously located in the gap between the two same adjacent rows of pixel units 20. It is understood that the first power traces 31 and the first ground traces 41 are alternately arranged along the second direction Y. The alternating sequence of the first power trace 31 and the second power trace 32 is not limited herein, and may be selected according to actual requirements. The first row of pixel units 20 at the edge of the display area 11 share a first power supply trace 31 or a first ground trace 41 on a side away from the display area 11, and the last row of pixel units 20 at the edge of the display area 11 share a first power supply trace 31 or a first ground trace 41 on a side away from the display area 11. It can be understood that, when the pixel units 20 are in even rows, one side of the first row of pixel units 20 away from the display area 11 shares one first power supply trace 31 or one first ground trace 41, and the trace shared by the side of the last row of pixel units 20 away from the display area 11 is the same type of trace as the trace shared by the side of the first row of pixel units 20 away from the display area 11. It should be noted that the same type of traces in this application refer to the first power traces 31 or the first ground traces 41. The pixel units 20 are in odd rows, one side of the first row of pixel units 20 far from the display area 11 shares one of the first power supply trace 31 and the first ground trace 41, and one side of the last row of pixel units 20 far from the display area 11 shares the other of the first power supply trace 31 and the first ground trace 41.
In the present embodiment, the pixel units 20 are in even rows, one side of the pixel units 20 of the first row far from the display area 11 shares a first power line 31, and one side of the pixel units 20 of the last row far from the display area 11 shares a first power line 31.
In some embodiments, when one second power trace 32 or one second ground trace 42 is disposed in the gap between at least some adjacent two columns of pixel units 20, it is understood that one second power trace 32 or one second ground trace 42 is disposed in the gap between all adjacent two columns of pixel units 20. Or a second power supply wire 32 or a second grounding wire 42 is arranged in the gap between two adjacent columns of pixel units 20, and the second power supply wire 32 and the second grounding wire 42 are not arranged in the gap between two adjacent columns of pixel units 20.
In other embodiments, when the orthographic projection of the second power trace 32 on the substrate 10 and/or the orthographic projection of the second ground trace 42 on the substrate 10 are disposed to overlap with the orthographic projection portion of the pixel unit 20 on the substrate 10 in the corresponding column direction, it can be understood that the second power trace 32 is disposed to overlap with the pixel unit 20 in the corresponding column direction in the direction perpendicular to the substrate 10; and/or the second ground trace 42 is disposed to partially overlap the pixel cells 20 in the corresponding column direction in a direction perpendicular to the substrate 10. The traces are disposed to partially overlap with the pixel units 20 in the corresponding column direction in the direction perpendicular to the substrate 10, and it is understood that one trace is disposed to partially overlap with one column of the pixel units 20 in the direction perpendicular to the substrate 10.
In the present embodiment, one second power trace 32 or one second ground trace 42 is disposed in the gaps between all adjacent two rows of pixel units 20. That is, the second power traces 32 and the second ground traces 42 are alternately arranged along the first direction X, and the alternating sequence of the second power traces 32 and the second ground traces 42 is not limited herein, and is selected according to the actual requirement. In conjunction with the above description of the first power trace 31 and the first ground trace 41, it may be understood that the first power trace 31 and the second power trace 32 crisscross to define a plurality of first partitions 34, and each first partition 34 includes four pixel units 20 not located in the same row. The first grounding trace 41 and the second grounding trace 42 crisscross to define a plurality of second partitions 44, and each second partition 44 includes four pixel units 20 not located in the same row. The first partition 34 partially overlaps the second partition 44.
Further, the pixel unit 20 includes a first electrode 21 for connecting the first power supply wiring 31 and a second electrode 22 for connecting the first ground wiring 41. The first electrode 21 and the second electrode 22 of the pixel unit 20 are respectively located at opposite sides of the corresponding pixel unit 20 along the second direction Y. The arrangement direction of the first electrodes 21 and the second electrodes 22 of the pixel cells 20 of the odd-numbered rows is opposite to the arrangement direction of the first electrodes 21 and the second electrodes 22 of the pixel cells 20 of the even-numbered rows.
The first electrode 21 of the pixel unit 20 corresponds to one of the cathode and the anode of the light emitting element 24, and the second electrode 22 corresponds to the other of the cathode and the anode of the light emitting element 24.
In the present embodiment, the first electrode 21 is an anode of the light emitting element 24, and the second electrode 22 is a cathode of the light emitting element 24.
Referring to fig. 1 to 3, fig. 3 is a circuit diagram of a pixel driving circuit provided in the present application.
The display panel 100 further includes a pixel driving circuit 23. The pixel driving circuit 23 is located in an area defined by the Data line Data and the scan line Gate. The pixel driving circuit 23 is for driving the light emitting element 24 to emit light. The pixel driving circuit 23 includes a first thin film transistor T1, a second thin film transistor T2, and a capacitor C. The source electrode S of the first thin film transistor T1 is connected with the Data line Data, the drain electrode D of the first thin film transistor T1 is connected with the grid electrode G of the second thin film transistor T2, and the grid electrode G of the first thin film transistor T1 is connected with the scanning line Gate. The source S of the second thin film transistor T2 is connected to the cathode of the light emitting element 24, and the drain D of the second thin film transistor T2 is connected to the ground trace VSS. One end of the capacitor C is connected with the grid G of the first thin film transistor T1, and the other end of the capacitor C is connected with the drain D of the second thin film transistor T2.
Further, the first metal layer 101 also forms the gate G of the first thin film transistor T1 and the gate G of the second thin film transistor T2. The second metal layer 103 also forms a source S of the first thin film transistor T1 and a drain D of the first thin film transistor T1, and the second metal layer 103 also forms a source S of the second thin film transistor T2 and a drain D of the second thin film transistor T2.
In this embodiment, the crossing of the power trace VDD, the ground trace VSS and the Data line Data is set by using a cross line, so that the power trace VDD, the ground trace VSS and the Data line Data are located on the same metal layer and still can be insulated from each other although they are located at the crossing.
The arrangement direction of the first electrodes 21 and the second electrodes 22 of the pixel units 20 of the odd-numbered rows is opposite to the arrangement direction of the first electrodes 21 and the second electrodes 22 of the pixel units 20 of the even-numbered rows, the paths of the metal wires 50 communicating with the anode of the light emitting element 24 and the power supply wiring VDD and the paths of the metal wires 50 communicating with the cathode of the light emitting element 24 and the source S of the second thin film transistor T2 can be reduced, and the manufacturing process can be simplified.
In the embodiment, the power supply wiring VDD and the ground wiring VSS are both arranged in a grid shape and distributed in the display area 11, so that the wiring of the non-display area 12 can be reduced, the narrow frame arrangement is further realized, and the problem of uneven display of the power supply wiring VDD caused by voltage drop is solved; and, the adjacent two rows of pixel units 20 share one first power trace 31 or one first grounding trace 41, so as to reduce the number of the first power traces 31 and the second power traces 32, which is beneficial to improving the resolution of the display panel 100.
Referring to fig. 1, fig. 4 and fig. 5, fig. 4 is a schematic structural diagram of a second embodiment of a display panel provided in the present application, and fig. 5 is a schematic structural diagram of a routing distribution of a fan-out area provided in the present application.
The second embodiment of the display panel 100 provided in the present application is substantially the same as the first embodiment of the display panel 100 provided in the present application, except that: each scan line Gate includes a first scan line segment 61 and a second scan line segment 62 connected; the first scan line segment 61 extends along the first direction X, one end of the second scan line segment 62 is connected to the first scan line segment 61, and the other end extends along the second direction Y to the outside of the display area 11 to be connected to the gate driver 105. Two adjacent second scan line segments 62 are located on opposite sides of at least one row of pixel units 20 along the second direction Y.
In the present embodiment, each scan line Gate includes a first scan line segment 61 and a second scan line segment 62 connected. The first scan line segment 61 extends along the first direction X, one end of the second scan line segment 62 is connected to the first scan line segment 61, and the other end extends along the second direction Y to the outside of the display area 11 to be connected to the gate driver 105. The Data line Data extends along the second direction Y and is connected to the source driver 106.
Further, the power trace VDD and the ground trace VSS are connected to the source driver 106, respectively. The gate driver 105 and the source driver 106 are disposed in the non-display region 12 and are located on the same side of the display region 11 along the second direction Y. The non-display area 12 where the gate driver 105 and the source driver 106 are located is defined as a fan-out area 107. It will be appreciated that in this embodiment, the fan-out area 107 is located on one side of the display area 11 in the second direction.
The gate driver 105 and the source driver 106 are both disposed in the fan-out area 107, and the fan-out area 107 is located at one side of the display area 11 along the second direction Y, so that only the non-display area 12 located at one side of the display area 11 is provided with the wiring, and the other three sides of the display area 11 can be free of the non-display area 12, i.e. the non-display area 12 is located at one side of the display area 11, so as to realize the three-sided borderless narrow frame design of the display panel 100.
Two adjacent second scan line segments 62 are located on opposite sides of at least one row of pixel units 20 along the second direction Y. That is, when two adjacent second scan line segments 62 are located on opposite sides of one row of pixel units 20 along the second direction Y, the second scan line segments 62 are alternately arranged with each row of pixel units 20 along the second direction Y, i.e. one second scan line segment 62 is disposed in a gap between two adjacent rows of pixel units 20. When two or more adjacent second scan line segments 62 are located on two or more opposite sides of the pixel units 20 along the second direction Y, the pitches of all the two adjacent second scan line segments 62 may be equal, or the pitches of part of the two adjacent second scan line segments 62 may be unequal, or the pitches of all the two adjacent second scan line segments 62 may be unequal, that is, no second scan line segment 62 is disposed in the gap between part of the two adjacent columns of pixel units 20.
It should be noted that the arrangement of the second scan line segment 62 is related to the number of rows and columns of the pixel unit 20.
In the present embodiment, the number of rows of the pixel units 20 is equal to the number of columns of the pixel units 20. The second scan line segments 62 are alternately arranged with each column of pixel units 20 in the second direction Y.
A second power trace 32 or a second ground trace 42 is disposed in a gap between at least some adjacent columns of pixel cells 20, and will not be described in detail herein, with reference to the foregoing description. In the present embodiment, one second power trace 32 or one second ground trace 42 is disposed in the gaps between all adjacent two rows of pixel units 20.
Compared with the first embodiment of the display panel 100 provided in the present application, the source driver 106 and the gate driver 105 are disposed on the non-display area 12 and on the same side of the display area 11 on the basis of realizing a narrow frame and improving display unevenness, so as to reduce the number of frames of the display panel 100 and facilitate the manufacture of borderless products.
Referring to fig. 1, fig. 4 to fig. 6, fig. 6 is a schematic structural diagram of a third embodiment of a display panel provided in the present application.
The third embodiment of the display panel 100 provided in the present application is basically the same as the second embodiment of the display panel 100 provided in the present application, except that: the second scan line segment 62 is disposed to partially overlap the pixel unit 20 in a direction perpendicular to the substrate 10; the front projection of the second power trace 32 on the substrate 10 and the front projection of the second ground trace 42 on the substrate 10 are both overlapped with the front projection of the pixel unit 20 on the substrate 10 in the corresponding column direction.
In the present embodiment, the second scan line segment 62 is disposed to partially overlap the pixel unit 20 in the direction perpendicular to the substrate 10. It will be appreciated that one second scan line segment 62 is disposed partially overlapping a corresponding column of pixel cells 20 in a direction perpendicular to the substrate 10.
The front projection of the second power trace 32 on the substrate 10 and the front projection of the second ground trace 42 on the substrate 10 are both overlapped with the front projection of the pixel unit 20 on the substrate 10 in the corresponding column direction.
The Data line Data is disposed to partially overlap the pixel unit 20 in a direction perpendicular to the substrate 10. It can be understood that, in the direction perpendicular to the substrate 10, a portion of the pixel units 20 is overlapped with the area defined by the Data line Data and the first scan line segment 61 in a crisscross manner, and a portion of the pixel units 20 extends beyond the area defined by the Data line Data and the first scan line segment 61 in a crisscross manner.
In this embodiment, since the power supply trace VDD, the ground trace VSS and the Data line Data are all located on different layers with the pixel unit 20, and the power supply trace VDD, the ground trace VSS and the Data line Data are all located on one side of the pixel unit 20 away from the light emitting side of the display panel 100, that is, the second power supply trace 32, the second ground trace 42, the Data line Data and the second scan line segment 62 can be disposed directly under the pixel unit 20, under the condition that the normal display of the display panel 100 is not affected, compared with the second embodiment of the display panel 100 provided in the present application, the space between two adjacent columns of pixel units 20 can be reduced, thereby increasing the resolution of the display panel 100 and being more convenient for manufacturing borderless products.
The present application provides a display panel 100. The display panel 100 includes a substrate 10, data lines Data, scan lines Gate, pixel cells 20, power supply lines VDD and ground lines VSS. The substrate 10 has a display region 11 and a non-display region 12; a first metal layer 101 and a second metal layer 103 are stacked on one side of the substrate 10; the first metal layer 101 is used for forming a scan line Gate, the second metal layer 103 is used for forming a power supply wire VDD, a ground wire VSS and a Data line Data, and the power supply wire VDD, the ground wire VSS and the Data line Data are mutually insulated; the plurality of pixel units 20 are arranged on one side of the second metal layer 103 away from the substrate 10 and are arranged in an array; defining a row direction of the pixel units 20 as a first direction X and defining a column direction of the pixel units 20 as a second direction Y; the power supply wires VDD are distributed in a grid and comprise a first power supply wire 31 and a second power supply wire 32 which are positioned in the display area 11 and connected with each other; the ground wires VSS are distributed in a grid and comprise a first ground wire 41 and a second ground wire 42 which are positioned in the display area 11 and connected with each other; two adjacent rows of pixel units 20 share one first power supply wire 31 or one first grounding wire 41; a second power trace 32 or a second ground trace 42 is disposed in a gap between at least some adjacent two columns of pixel units 20; alternatively, the orthographic projection of the second power trace 32 on the substrate 10 and/or the orthographic projection of the second ground trace 42 on the substrate 10 are disposed so as to overlap with the orthographic projection portions of the pixel units 20 in the corresponding column direction on the substrate 10. By arranging the power supply wires VDD and the ground wires VSS in a grid distribution, two adjacent rows of pixel units 20 share one first power supply wire 31 or one first ground wire 41, and one second power supply wire 32 or one second ground wire 42 is arranged in a gap between at least two adjacent rows of pixel units 20; alternatively, the front projection of the second power trace 32 on the substrate 10 and/or the front projection of the second ground trace 42 on the substrate 10 are overlapped with the front projection of the pixel unit 20 on the substrate 10 in the corresponding column direction, so that the narrow frame design of the traces of the non-display area 12 can be reduced, and the problem of uneven display of the power trace VDD caused by voltage drop can be improved.
The present application provides a display device including a housing and the display panel 100 described above.
The foregoing is only the embodiments of the present application, and therefore, the patent protection scope of the present application is not limited thereto, and all equivalent structures or equivalent processes using the contents of the present application specification and the drawings are included in the patent protection scope of the present application, or directly or indirectly applied to other related technical fields.

Claims (10)

1. A display panel, the display panel comprising:
a substrate having a display region and a non-display region; a first metal layer and a second metal layer are laminated on one side of the substrate; the first metal layer is used for forming scanning lines, the second metal layer is used for forming power supply wires, grounding wires and data wires, and the power supply wires, the grounding wires and the data wires are mutually insulated;
the pixel units are arranged on one side, far away from the substrate, of the second metal layer and are arranged in an array; defining the row direction of the pixel units as a first direction and the column direction of the pixel units as a second direction;
the display device is characterized in that the power supply wires are distributed in a grid mode and comprise a first power supply wire and a second power supply wire which are positioned in the display area and connected with each other;
the grounding wires are distributed in a grid mode and comprise a first grounding wire and a second grounding wire which are positioned in the display area and connected with each other;
two adjacent rows of pixel units share one first power supply wire or one first grounding wire;
one second power supply wire or one second grounding wire is arranged in a gap between at least part of two adjacent columns of pixel units; or, the orthographic projection of the second power supply wire on the substrate and/or the orthographic projection of the second grounding wire on the substrate are overlapped with the orthographic projection part of the pixel unit on the substrate corresponding to the column direction.
2. The display panel according to claim 1, wherein the first power supply wires are disposed to extend in the first direction, the second power supply wires are disposed to extend in the second direction, and each of the second power supply wires is connected to at least two of the first power supply wires; the first grounding wires extend along the first direction, the second grounding wires extend along the second direction, and each second grounding wire is connected with at least two first grounding wires.
3. The display panel according to claim 2, wherein the power supply trace further comprises a power supply common line disposed along the second direction for connecting the first power supply trace and/or the second power supply trace and extending outside the display area to be connected with a source driver; the grounding trace further comprises a grounding common line which is arranged along the second direction and used for connecting the first grounding trace and/or the second grounding trace, and extends to the outside of the display area to be connected with the source driver.
4. The display panel of claim 1, wherein each of the scan lines comprises a first scan line segment and a second scan line segment connected; the first scanning line segment extends along the first direction, one end of the second scanning line segment is connected with the first scanning line segment, and the other end of the second scanning line segment extends out of the display area along the second direction and is connected with the gate driver; the data line extends along the second direction and is connected with the source driver.
5. The display panel according to claim 4, wherein the power supply wiring and the ground wiring are connected to the source driver, respectively; the gate driver and the source driver are both arranged in the non-display area and are positioned on the same side of the display area along the second direction.
6. The display panel according to claim 4, wherein two adjacent second scan line segments are located on opposite sides of at least one row of the pixel units along the second direction; and one second power supply wire or one second grounding wire is arranged in a gap between at least two adjacent columns of pixel units.
7. The display panel according to claim 4, wherein the second scan line segment is disposed to partially overlap the pixel unit in a direction perpendicular to the substrate; and the orthographic projection of the second power supply wire on the substrate and the orthographic projection of the second grounding wire on the substrate are overlapped with the orthographic projection part of the pixel unit on the substrate corresponding to the column direction.
8. The display panel according to claim 1, wherein the pixel unit includes a first electrode for connecting the first power supply wiring and a second electrode for connecting the first ground wiring; the first electrode and the second electrode of the pixel unit are respectively positioned at two opposite sides of the corresponding pixel unit along the second direction; the arrangement direction of the first and second electrodes of the pixel cells in the odd-numbered rows is opposite to the arrangement direction of the first and second electrodes of the pixel cells in the even-numbered rows.
9. The display panel of claim 1, wherein the power trace, the ground trace, and the data line are disposed across from one another.
10. A display device comprising a housing and the display panel of any one of claims 1 to 9.
CN202310370506.0A 2023-04-03 2023-04-03 Display panel and display device Pending CN116404026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310370506.0A CN116404026A (en) 2023-04-03 2023-04-03 Display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310370506.0A CN116404026A (en) 2023-04-03 2023-04-03 Display panel and display device

Publications (1)

Publication Number Publication Date
CN116404026A true CN116404026A (en) 2023-07-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310370506.0A Pending CN116404026A (en) 2023-04-03 2023-04-03 Display panel and display device

Country Status (1)

Country Link
CN (1) CN116404026A (en)

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