CN116401980A - Automatic simulation verification method and system for full working condition of circuit schematic diagram - Google Patents
Automatic simulation verification method and system for full working condition of circuit schematic diagram Download PDFInfo
- Publication number
- CN116401980A CN116401980A CN202310197394.3A CN202310197394A CN116401980A CN 116401980 A CN116401980 A CN 116401980A CN 202310197394 A CN202310197394 A CN 202310197394A CN 116401980 A CN116401980 A CN 116401980A
- Authority
- CN
- China
- Prior art keywords
- circuit
- schematic diagram
- test
- test case
- working condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 title claims abstract description 87
- 238000004088 simulation Methods 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000012795 verification Methods 0.000 title claims abstract description 20
- 238000012360 testing method Methods 0.000 claims abstract description 140
- 230000002159 abnormal effect Effects 0.000 claims abstract description 9
- 238000013461 design Methods 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 4
- 238000012937 correction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a full-working-condition automatic simulation verification method of a circuit schematic diagram, which comprises the following steps: adding the simulation model into the element symbol; drawing a circuit schematic diagram by using components with simulation models to obtain a tested circuit; finding out all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram, and connecting the input/output ports with the working condition control circuit module by using the network labels; writing a test case set covering all working conditions of a tested circuit in EXCEL; running a simulation process management program to interpret test cases; and (3) positioning the part of the EXCEL table, in which the interpretation result is False and the test case execution condition is abnormal, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram. The method of the invention tests the function of the tested circuit under all the possible working conditions, judges whether the circuit function is normal or not, judges whether the problems of wrong connection, wrong network mark and the like exist in the schematic diagram, and performs error positioning.
Description
Technical Field
The invention relates to the technical field of aerospace power supplies, in particular to a full-working-condition automatic simulation verification method and system for a circuit schematic diagram.
Background
The traditional flow of the circuit design of the aerospace power supply controller is as follows: the correctness of the circuit is verified by simulation in special circuit simulation software (such as Saber), then a schematic diagram is drawn in schematic diagram/PCB design software, and then PCB design and subsequent production links are entered.
When the schematic diagram is complex, there are often low-level problems such as connection errors, network label errors, etc. in the schematic diagram due to negligence. The currently adopted schematic diagram error correction method is a manual visual method, and a designer repeatedly performs manual check on the schematic diagram. The method is time-consuming and labor-consuming, and can not find all problems of the schematic diagram frequently, so that the problems are brought into a production link, and the error correction cost is increased exponentially.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention provides a full-working-condition automatic simulation verification method and a full-working-condition automatic simulation verification system for a circuit schematic diagram, which do not need to manually search low-level problems such as connection errors, network label errors and the like in the schematic diagram, and check whether each function of the circuit is normal or not by performing simulation test on the full working condition of the circuit, so that the problems in the automatic positioning schematic diagram are realized, and the problem searching is more convenient and comprehensive.
The technical scheme adopted by the invention is as follows: a full-working-condition automatic simulation verification method of a circuit schematic diagram comprises the following steps:
s1, adding a simulation model into a component symbol;
s2, drawing a circuit schematic diagram by using components with simulation models to obtain a tested circuit;
s3, all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram are found out, and the input/output ports are connected with the working condition control circuit module by utilizing network labels;
s4, writing a test case set covering all working conditions of the tested circuit in the EXCEL;
s5, running a simulation process management program, and judging test cases;
s6, positioning the part of the EXCEL table, wherein the part is the part with the interpretation result of False and the part is the part with the abnormal execution condition of the test case, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram; if yes, modifying the schematic diagram of the circuit and then re-simulating the corresponding test working condition; if not, deducing that the simulation process management program is modified and then re-simulating the corresponding test working condition because of the fault of the simulation process management program.
Further, in the step S1, a simulation model with the lowest calculation complexity is selected and added to the component symbol.
Further, the working condition control circuit module comprises three types of circuits:
the pure resistance circuit is used for controlling the short circuit or open circuit of the circuit port, wherein the short circuit is represented when the resistance value is 0, and the open circuit is represented when the resistance value is infinity;
the current source is used for simulating solar array output;
RLC circuitry to simulate the load characteristics of the circuit ports.
Further, each test case in the EXCEL table includes:
testing the name of the working condition;
a state prejudging part: noting the expected value of the actual value of the part of the reserved parameter for the part of the key components or the electric parameters before the test working condition is set as the target working condition;
test condition setting method part: describing in a form of component position number plus parameter value, namely setting the component of the target position number as a parameter value, and obtaining the test working condition; the component position numbers are all from the working condition control circuit module;
parameter interpretation section: noting the electrical parameters and expected values thereof which can be used for judging whether the circuit works normally under the target test working condition; reserving a filling position of an actual value of a parameter and a filling position of a interpretation result;
test case execution feedback section: and reserving a filling position for recording whether the test case is normally executed or not.
Further, the process of the simulation process management program comprises the following steps:
s51, starting simulation;
s52, i=1; i is the test case number;
s53, calling an API interface which is opened to the outside by the EXCEL, and reading an ith test case from the API interface;
s54, reading actual values of parameters related to a status prejudging part of an ith test case from a circuit schematic diagram or a simulation result, and writing the actual values into a corresponding position of EXCEL;
s55, judging whether the actual value of the status prejudging part meets the requirement of the expected value, and if so, turning to S56; otherwise, go to S516;
s56, setting component parameter values according to the test case 'test condition setting part' of the ith test case, constructing a test condition, and turning to S57;
s516, setting parameter values of components in the working condition control circuit module according to the expected value requirement of the state prejudging part, and turning to S517;
s517, after S516 is finished, judging whether the actual value of the status prejudging part meets the requirement of the expected value or not again; if yes, go to S56; if not, go to S518;
s518, filling in ' exception ' at the execution condition of the ith test case, and not successfully setting a parameter value of a certain parameter ', and turning to S515;
s515, finishing simulation;
s57, reading parameter values of components written in a test working condition setting part of an ith test case from the schematic circuit diagram, and comparing the parameter values with the parameter values expected to be set;
s58, judging whether the component parameter values are successfully set in S57; if yes, go to S59; if not, go to S518;
s59, waiting for t seconds;
s510, reading actual values of parameters of an electric parameter interpretation part from the circuit schematic diagram, and writing the actual values into corresponding positions of the EXCEL table;
s511, judging whether the actual value of the electric parameter judging part meets the requirement of the expected value, if so, turning to S512, and if not, turning to S519;
s512, writing Ture at the 'interpretation result' of the ith test case, representing that the test passes, and turning to S513;
s519, writing False at the 'interpretation result' of the ith test case, adding a red background to indicate that the test fails, and turning to S513;
S513，i＝i+1；
s514, judging whether i is larger than imax, wherein imax represents the total number of test cases; if yes, go to S515; if not, the process goes to S53.
Further, in the step S54, a schematic diagram is used to design or simulate a read instruction built in the software when the actual value of the parameter is read; and calling an API interface which is open to the outside of the EXCEL when writing the content into the corresponding position in the EXCEL.
Further, in S59, t is set according to the time that the circuit reaches the steady state, where t is set to be greater than 1.
The circuit schematic diagram full-working condition automatic simulation verification system based on the method comprises the following steps:
the first module is used for adding the simulation model into the element symbol, and drawing a circuit schematic diagram by using the element drawing with the simulation model to obtain a tested circuit; finding out all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram, and connecting the input/output ports with the working condition control circuit module by using the network labels;
the second module is used for compiling a test case set covering all working conditions of the tested circuit in the EXCEL;
the third module is used for running a simulation process management program and judging test cases; positioning the part of the EXCEL table, wherein the part is the part of which the interpretation result is False and the part of which the test case execution condition is abnormal, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram; if yes, modifying the schematic diagram of the circuit and then re-simulating the corresponding test working condition; if not, deducing that the simulation process management program is modified and then re-simulating the corresponding test working condition because of the fault of the simulation process management program.
Compared with the prior art, the invention has the advantages that:
(1) The method reduces the circuit simulation calculated amount, improves the simulation speed, checks low-level problems such as connection errors, network label errors and the like by performing functional verification on the circuit, and is not used for testing the performance of the circuit, so that the requirement on the model accuracy is not high, and the component model accuracy can meet the requirement on the functional verification;
(2) The method can simulate based on the schematic diagram after the schematic diagram of the circuit is drawn; the switching of the test working conditions can be realized under the condition that the tested schematic diagram is not changed at all, and errors caused by the change of the tested schematic diagram can be avoided; the simulation of the actual operation condition of the circuit can be realized by changing the parameters of components in the condition control circuit module; the port of the resistance control circuit is short-circuited or open-circuited, the port is short-circuited when the resistance value is 0, and the port is open-circuited when the resistance value is infinity; the RLC series circuit is connected with the RLC parallel circuit in parallel, so that various load characteristics are simulated equivalently;
(3) Compared with the method for editing the test cases in the program script, the method for editing the test cases in the EXCEL is convenient and quick, and is convenient to communicate; the sufficiency of the schematic diagram test is ensured through the test case set covering all working conditions, so that the comprehensiveness of error searching is ensured; the current working condition is prejudged, and the abnormal working state of the circuit caused by the direct switching working condition can be avoided. For example: before loading the bus with 5A, it is first predetermined whether the current source in the circuit is capable of supplying 5A. If not, loading 5A for the bus directly will cause abnormal working state of the circuit. The setting method of the test working condition is described in the form of 'component position number plus parameter value', so that the program language is convenient to understand and execute; facilitating a comparison of the actual value and the desired value of the parameter of interest.
(4) The method of the invention opens up a communication interface between the schematic diagram design software and the EXCEL to realize the bidirectional transmission of information; the data in the schematic diagram file is read under the condition of not interrupting the simulation test process, so that the total simulation time is saved; the current circuit state is prejudged, and the current state is changed into the expected state when the current state does not meet the requirement, rather than being directly changed into the expected state. The method can reduce the change of circuit parameters as much as possible, and avoid the slow simulation speed caused by the recalculation of the circuit model by the computer as much as possible; if the circuit cannot be changed into the expected state, the simulation program is proved to be wrong, the simulation result has no reference value any more, and the simulation is stopped immediately.
(5) According to the invention, under the condition of not interrupting the simulation process, the circuit can be converted to operate under the expected working condition by automatically changing the parameters of components in the working condition control circuit module; the invention checks whether the working condition of the circuit is successfully changed or not and timely discovers the condition that the working condition is not successfully changed.
Drawings
FIG. 1 is a schematic block diagram of a circuit schematic diagram full-condition automatic simulation verification method of the invention;
FIG. 2 is a schematic diagram of a signal transmission mode between a schematic circuit diagram and a "duty control circuit module";
FIG. 3 is a flowchart of a simulation process management program.
Detailed Description
The invention is described with reference to the accompanying drawings.
As shown in FIG. 1, the full-working-condition automatic simulation verification method of the circuit schematic diagram comprises the following steps:
s1, adding the simulation model into the component symbol. In order to obtain higher simulation speed, selecting a model with the lowest calculation complexity from all the available simulation models;
s2, drawing a circuit schematic diagram by using components with simulation models to obtain a tested circuit;
and S3, finding out all input/output ports facing the outside of the schematic diagram in the schematic diagram, and connecting the input/output ports with the working condition control circuit module shown in FIG. 2 by utilizing network labels according to the characteristics of port signals.
The working condition control circuit module comprises three types of circuits:
1. a pure resistor circuit. The function is as follows: the control circuit port is short-circuited or open-circuited (the short circuit is represented when the resistance value is 0, and the open circuit is represented when the resistance value is infinity);
2. a current source. The function is as follows: simulating solar array output;
rlc circuitry. The function is as follows: the load characteristics of the circuit ports are simulated.
S4, writing a test case set covering all working conditions of the tested circuit in the EXCEL. Each test case consisted of five parts, formatted as shown in table 1:
1. testing the name of the working condition;
2. and a state pre-judging part. Note that the test conditions are set to the expected values for some of the critical components/electrical parameters before the target conditions. Filling positions of actual values of the partial reservation parameters;
3. and a test working condition setting method part. The description is in the form of component position number plus parameter value, which means that the component with the target position number is set as a certain parameter value, and the test working condition can be obtained. The component bit numbers are all from the working condition control circuit module;
4. and a parameter interpretation section. And noting the electrical parameters and expected values thereof which can be used for judging whether the circuit works normally under the target test working condition. Reserving a filling position of an actual value of a parameter and a filling position of a interpretation result;
5. and the test case execution condition feedback part. And reserving a filling position for recording whether the test case is normally executed or not.
S5, writing a simulation process management program based on a script development environment of the schematic diagram/PCB design software. The simulation process management program flow is shown in fig. 3, and comprises the following steps:
s51, starting simulation;
s52, i=1, i represents a test case number;
s53, calling an API interface which is opened to the outside by the EXCEL, and reading an ith test case from the API interface;
s54, reading the actual value of the parameter related to the status prejudging part of the ith test case from the schematic diagram or the simulation result, and writing the actual value into the corresponding position of the EXCEL. When the actual value of the parameter is read, a built-in reading instruction in the schematic diagram design/simulation software is utilized; calling an API interface which is open to the outside of the EXCEL when writing the content into the corresponding position in the EXCEL;
s55, judging whether the actual value of the status prejudging part meets the requirement of the expected value, and if so, turning to S56; otherwise, go to S516;
s56, setting component parameter values according to the test case 'test condition setting part' of the ith test case, constructing a test condition, and turning to S57;
s516, setting parameter values of components in the working condition control circuit module according to the expected value requirement of the state prejudging part, and turning to S517;
s517, after S516 is finished, judging whether the actual value of the status prejudging part meets the requirement of the expected value or not again; if yes, go to S56; if not, go to S518;
s518, filling in ' exception ' at the execution condition of the ith test case, and not successfully setting a parameter value of a certain parameter ', and turning to S515;
s515, finishing simulation;
s57, reading parameter values of components written in a test working condition setting part of an ith test case from the schematic diagram, and comparing the parameter values with the parameter values expected to be set;
s58, judging whether the component parameter values are successfully set in S57; if yes, go to S59; if not, go to S518;
s59, waiting for t seconds, wherein t is set according to the time of the circuit reaching a steady state, and is generally set to be greater than 1;
s510, reading the actual value of the parameter of the electric parameter interpretation part from the schematic diagram, and writing the actual value into the position corresponding to the EXCEL;
s511, judging whether the actual value of the electric parameter judging part meets the requirement of the expected value, if so, turning to S512, and if not, turning to S519;
s512, writing Ture at the 'interpretation result' of the ith test case, representing that the test passes, and turning to S513;
s519, writing False at the 'interpretation result' of the ith test case, and adding a red background. Representing that the test fails, go to S513;
s513, i=i+1, go to the next test case;
s514, judging whether i is larger than imax, wherein imax represents the total number of test cases; if yes, go to S515; if not, go to S53;
s6, positioning the part of the EXCEL with the interpretation result of False and the abnormal execution condition of the test case, and analyzing whether the analysis is caused by drawing errors of the schematic diagram; if yes, modifying the schematic diagram and then re-simulating the corresponding test working condition; if not, it can be inferred that the program is modified and the corresponding test conditions are re-simulated due to the simulation driver error.
The circuit schematic diagram full-working condition automatic simulation verification system according to the simulation verification method comprises the following steps:
the first module is used for adding the simulation model into the element symbol, and drawing a circuit schematic diagram by using the element drawing with the simulation model to obtain a tested circuit; finding out all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram, and connecting the input/output ports with the working condition control circuit module by using the network labels;
the second module is used for compiling a test case set covering all working conditions of the tested circuit in the EXCEL;
the third module is used for running a simulation process management program and judging test cases; positioning the part of the EXCEL table, wherein the part is the part of which the interpretation result is False and the part of which the test case execution condition is abnormal, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram; if yes, modifying the schematic diagram of the circuit and then re-simulating the corresponding test working condition; if not, deducing that the simulation process management program is modified and then re-simulating the corresponding test working condition because of the fault of the simulation process management program.
Examples:
the signal transmission mode between the tested circuit schematic diagram and the working condition control circuit module is shown in fig. 2 and is connected through network marks. The j1 and j2 terminals of the relay together form an external input port of the relay. If the port is short-circuited, the relay coil is electrified with current, and the relay acts; if the port is kept open, the relay coil is not energized and the relay is not operated. The port is connected with a pure resistor circuit port, when Rj is assigned to 0 ohm, the relay j acts, and when Rj is assigned to infinity, the relay j does not act. The solar array input terminal m+ and the solar array input terminal m-form an mth solar array input port together. The port is connected with the port of the current source circuit, and the current value output by the current source is the current value input by the mth solar array port in the schematic diagram. The load output terminal k+ and the load output terminal k-together constitute a kth load output port. The port is connected with the RLC circuit, and different loads of the port can be simulated by changing parameters of the RLC circuit.
The test case description is shown in table 1. The test case is used for testing whether the circuit works normally or not after the power distribution 1 is switched from the unopened state to the opened state. The state prejudging part requires that the expected value of the Current1 parameter is more than 4A and less than 5A, so as to ensure that the input Current of the tested circuit is approximately equal to the output Current of the real solar array. The switch state indication signal of the power distribution 1 is required to be 0-0.5V, so as to ensure that the power distribution 1 is not switched on currently. The test condition setting method part requires that R1 be set to 0 ohms in order to short the port controlling the power distribution 1 to be turned on, so that the power distribution 1 is turned on (as shown in fig. 2). The electric parameter interpretation part requires the expected value of the switch state indication of the power distribution 1 to be 3V-3.2V, so as to judge whether the output voltage of the power distribution 1 meets the requirement or not according to the switch state indication, and further judge whether the circuit works normally or not.
TABLE 1 test case Table
The invention, in part not described in detail, is within the skill of those skilled in the art.
Claims (10)
1. The full-working-condition automatic simulation verification method for the circuit schematic diagram is characterized by comprising the following steps of:
s1, adding a simulation model into a component symbol;
s2, drawing a circuit schematic diagram by using components with simulation models to obtain a tested circuit;
s3, all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram are found out, and the input/output ports are connected with the working condition control circuit module by utilizing network labels;
s4, writing a test case set covering all working conditions of the tested circuit in the EXCEL;
s5, running a simulation process management program, and judging test cases;
s6, positioning the part of the EXCEL table, wherein the part is the part with the interpretation result of False and the part is the part with the abnormal execution condition of the test case, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram; if yes, modifying the schematic diagram of the circuit and then re-simulating the corresponding test working condition; if not, deducing that the simulation process management program is modified and then re-simulating the corresponding test working condition because of the fault of the simulation process management program.
2. The automatic simulation verification method for full operating mode of circuit schematic diagram according to claim 1, wherein in S1, a simulation model with lowest calculation complexity is selected and added into a component symbol.
3. The circuit schematic full-working condition automatic simulation verification method according to claim 1, wherein the working condition control circuit module comprises three types of circuits:
the pure resistance circuit is used for controlling the short circuit or open circuit of the circuit port, wherein the short circuit is represented when the resistance value is 0, and the open circuit is represented when the resistance value is infinity;
the current source is used for simulating solar array output;
RLC circuitry to simulate the load characteristics of the circuit ports.
4. The method for automatically simulating and verifying the full working condition of the schematic circuit diagram according to claim 1, wherein each test case in the EXCEL table comprises:
testing the name of the working condition;
a state prejudging part: noting the expected value of the actual value of the part of the reserved parameter for the part of the key components or the electric parameters before the test working condition is set as the target working condition;
test condition setting method part: describing in a form of component position number plus parameter value, namely setting the component of the target position number as a parameter value, and obtaining the test working condition; the component position numbers are all from the working condition control circuit module;
parameter interpretation section: noting the electrical parameters and expected values thereof which can be used for judging whether the circuit works normally under the target test working condition; reserving a filling position of an actual value of a parameter and a filling position of a interpretation result;
test case execution feedback section: and reserving a filling position for recording whether the test case is normally executed or not.
5. The method for automatically simulating and verifying full-operation condition of circuit schematic according to claim 4, wherein the process of the simulation process management program comprises the following steps:
s51, starting simulation;
s52, i=1; i is the test case number;
s53, calling an API interface which is opened to the outside by the EXCEL, and reading an ith test case from the API interface;
s54, reading actual values of parameters related to a status prejudging part of an ith test case from a circuit schematic diagram or a simulation result, and writing the actual values into a corresponding position of EXCEL;
s55, judging whether the actual value of the status prejudging part meets the requirement of the expected value, and if so, turning to S56; otherwise, go to S516;
s56, setting component parameter values according to the test case 'test condition setting part' of the ith test case, constructing a test condition, and turning to S57;
s516, setting parameter values of components in the working condition control circuit module according to the expected value requirement of the state prejudging part, and turning to S517;
s517, after S516 is finished, judging whether the actual value of the status prejudging part meets the requirement of the expected value or not again; if yes, go to S56; if not, go to S518;
s518, filling in ' exception ' at the execution condition of the ith test case, and not successfully setting a parameter value of a certain parameter ', and turning to S515;
s515, finishing simulation;
s57, reading parameter values of components written in a test working condition setting part of an ith test case from the schematic circuit diagram, and comparing the parameter values with the parameter values expected to be set;
s58, judging whether the component parameter values are successfully set in S57; if yes, go to S59; if not, go to S518;
s59, waiting for t seconds;
s510, reading actual values of parameters of an electric parameter interpretation part from the circuit schematic diagram, and writing the actual values into corresponding positions of the EXCEL table;
s511, judging whether the actual value of the electric parameter judging part meets the requirement of the expected value, if so, turning to S512, and if not, turning to S519;
s512, writing Ture at the 'interpretation result' of the ith test case, representing that the test passes, and turning to S513;
s519, writing False at the 'interpretation result' of the ith test case, adding a red background to indicate that the test fails, and turning to S513;
S513，i＝i+1；
s514, judging whether i is larger than imax, wherein imax represents the total number of test cases; if yes, go to S515; if not, the process goes to S53.
6. The automatic simulation verification method for full operating mode of circuit schematic diagram according to claim 5, wherein in S54, the actual values of parameters are read by using a schematic diagram design or a read instruction built in simulation software; and calling an API interface which is open to the outside of the EXCEL when writing the content into the corresponding position in the EXCEL.
7. The method for automatically simulating and verifying full-operation mode of circuit schematic according to claim 5, wherein in S59, t is set to be greater than 1 according to the time when the circuit reaches steady state.
8. The utility model provides a full operating mode automatic simulation verification system of circuit schematic diagram which characterized in that includes:
the first module is used for adding the simulation model into the element symbol, and drawing a circuit schematic diagram by using the element drawing with the simulation model to obtain a tested circuit; finding out all input/output ports facing the outside of the schematic diagram in the circuit schematic diagram, and connecting the input/output ports with the working condition control circuit module by using the network labels;
the second module is used for compiling a test case set covering all working conditions of the tested circuit in the EXCEL;
the third module is used for running a simulation process management program and judging test cases; positioning the part of the EXCEL table, wherein the part is the part of which the interpretation result is False and the part of which the test case execution condition is abnormal, and analyzing whether the part is caused by the drawing error of the circuit schematic diagram; if yes, modifying the schematic diagram of the circuit and then re-simulating the corresponding test working condition; if not, deducing that the simulation process management program is modified and then re-simulating the corresponding test working condition because of the fault of the simulation process management program.
9. The circuit schematic full-condition automatic simulation verification system according to claim 8, wherein the condition control circuit module comprises three types of circuits:
the pure resistance circuit is used for controlling the short circuit or open circuit of the circuit port, wherein the short circuit is represented when the resistance value is 0, and the open circuit is represented when the resistance value is infinity;
the current source is used for simulating solar array output;
an RLC circuit for simulating load characteristics of the circuit port;
each test case in the EXCEL table includes:
testing the name of the working condition;
a state prejudging part: noting the expected value of the actual value of the part of the reserved parameter for the part of the key components or the electric parameters before the test working condition is set as the target working condition;
test condition setting method part: describing in a form of component position number plus parameter value, namely setting the component of the target position number as a parameter value, and obtaining the test working condition; the component position numbers are all from the working condition control circuit module;
parameter interpretation section: noting the electrical parameters and expected values thereof which can be used for judging whether the circuit works normally under the target test working condition; reserving a filling position of an actual value of a parameter and a filling position of a interpretation result;
test case execution feedback section: and reserving a filling position for recording whether the test case is normally executed or not.
10. The system of claim 9, wherein the process of the simulation process management program comprises:
s51, starting simulation;
s52, i=1; i is the test case number;
s53, calling an API interface which is opened to the outside by the EXCEL, and reading an ith test case from the API interface;
s54, reading actual values of parameters related to a status prejudging part of an ith test case from a circuit schematic diagram or a simulation result, and writing the actual values into a corresponding position of EXCEL;
s55, judging whether the actual value of the status prejudging part meets the requirement of the expected value, and if so, turning to S56; otherwise, go to S516;
s56, setting component parameter values according to the test case 'test condition setting part' of the ith test case, constructing a test condition, and turning to S57;
s516, setting parameter values of components in the working condition control circuit module according to the expected value requirement of the state prejudging part, and turning to S517;
s517, after S516 is finished, judging whether the actual value of the status prejudging part meets the requirement of the expected value or not again; if yes, go to S56; if not, go to S518;
s518, filling in ' exception ' at the execution condition of the ith test case, and not successfully setting a parameter value of a certain parameter ', and turning to S515;
s515, finishing simulation;
s57, reading parameter values of components written in a test working condition setting part of an ith test case from the schematic circuit diagram, and comparing the parameter values with the parameter values expected to be set;
s58, judging whether the component parameter values are successfully set in S57; if yes, go to S59; if not, go to S518;
s59, waiting for t seconds;
s510, reading actual values of parameters of an electric parameter interpretation part from the circuit schematic diagram, and writing the actual values into corresponding positions of the EXCEL table;
s511, judging whether the actual value of the electric parameter judging part meets the requirement of the expected value, if so, turning to S512, and if not, turning to S519;
s512, writing Ture at the 'interpretation result' of the ith test case, representing that the test passes, and turning to S513;
s519, writing False at the 'interpretation result' of the ith test case, adding a red background to indicate that the test fails, and turning to S513;
S513，i＝i+1；
s514, judging whether i is larger than imax, wherein imax represents the total number of test cases; if yes, go to S515; if not, the process goes to S53.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310197394.3A CN116401980A (en) | 2023-03-02 | 2023-03-02 | Automatic simulation verification method and system for full working condition of circuit schematic diagram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310197394.3A CN116401980A (en) | 2023-03-02 | 2023-03-02 | Automatic simulation verification method and system for full working condition of circuit schematic diagram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116401980A true CN116401980A (en) | 2023-07-07 |
Family
ID=87013175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310197394.3A Pending CN116401980A (en) | 2023-03-02 | 2023-03-02 | Automatic simulation verification method and system for full working condition of circuit schematic diagram |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116401980A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116933707A (en) * | 2023-09-15 | 2023-10-24 | 北京开源芯片研究院 | Test method, device, equipment and medium for design circuit |
-
2023
- 2023-03-02 CN CN202310197394.3A patent/CN116401980A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116933707A (en) * | 2023-09-15 | 2023-10-24 | 北京开源芯片研究院 | Test method, device, equipment and medium for design circuit |
| CN116933707B (en) * | 2023-09-15 | 2023-12-22 | 北京开源芯片研究院 | Test method, device, equipment and medium for design circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204116943U (en) | Vehicle-mounted electronic control unit CAN communication automation system proving installation | |
| CN104267715A (en) | Vehicle-mounted electronic control unit LIN bus communication automatic testing device and system | |
| CN104298224A (en) | Automatic vehicle-mounted electronic control unit CAN bus communication testing device and system | |
| CN101175285A (en) | Automatic testing method and system for mobile phone software | |
| CN116401980A (en) | Automatic simulation verification method and system for full working condition of circuit schematic diagram | |
| CN204116942U (en) | Vehicle-mounted electronic control unit LIN bus communication automatic test device | |
| CN107727961B (en) | Automatic comprehensive detection equipment and detection method for electrical accessories of ejection seat | |
| CN113341917A (en) | Internet of vehicles remote control end cloud integrated automatic test system and method | |
| CN109933521A (en) | Automated testing method, device, computer equipment and storage medium based on BDD | |
| CN210666480U (en) | Vehicle test system | |
| CN110632511B (en) | Engine on-line monitoring test system and method | |
| CN100533314C (en) | Cold-storage container micro controller fault diagnosing system | |
| CN106291329A (en) | A kind of have the automatic test system detecting and joining the distant function of a terminal three | |
| CN117148115A (en) | Chip testing method and device based on FPGA | |
| CN111444109B (en) | Mobile terminal UI automatic test method and system | |
| CN110887518A (en) | Test method of combination instrument | |
| CN109815635B (en) | Boiler MFT automatic design system and method | |
| US8271460B2 (en) | Computer program and computer system for producing test flow | |
| CN113691669B (en) | Android mobile phone APP control vehicle full-process test analysis system and method | |
| US20060026479A1 (en) | Verification vector creating method, and electronic circuit verifying method using the former method | |
| CN111179676B (en) | Virtual simulation training platform of air supply system | |
| CN114148866B (en) | Verification method, device and equipment of elevator door lock detection system and storage medium | |
| Gao et al. | Circuit FMEA method by fault simulation based on saber | |
| JP3689537B2 (en) | IDDQ test cycle selective extraction device | |
| CN116736025B (en) | Closed loop automatic test device and method for analog quantity acquisition equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |