CN116400202A - Chip logic function cross-validation test method - Google Patents
Chip logic function cross-validation test method Download PDFInfo
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- CN116400202A CN116400202A CN202310664604.5A CN202310664604A CN116400202A CN 116400202 A CN116400202 A CN 116400202A CN 202310664604 A CN202310664604 A CN 202310664604A CN 116400202 A CN116400202 A CN 116400202A
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- 238000002790 cross-validation Methods 0.000 title claims abstract description 11
- 238000010998 test method Methods 0.000 title abstract description 4
- 238000012360 testing method Methods 0.000 claims abstract description 86
- 239000013598 vector Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 21
- 238000012795 verification Methods 0.000 claims description 12
- 238000007781 pre-processing Methods 0.000 claims description 3
- 238000002864 sequence alignment Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a chip logic function cross-validation test method, which relates to the technical field of chip test, wherein test vectors are sequentially input into chips to be tested according to time sequences according to test parameters, and output signals of the chips to be tested are collected; and performing exclusive OR operation on output signals of N chips to be tested in the same clock period to realize batch cross-validation, thereby realizing batch cross-validation of chip logic functions.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip logic function cross-validation testing method.
Background
With the development of new energy automobiles, the verification problem of the automobile-scale chip needs to be solved urgently.
The traditional IC test is generally to manually operate a probe to detect whether the input and output data of the chip are correct, which is obviously only suitable for the performance verification of a single chip, and for a large number of chips to be tested, the problems of long time consumption, low test efficiency and the like of a test flow exist.
In view of this, the present invention has been made.
Disclosure of Invention
In order to solve the technical problems, the invention provides a chip logic function cross-validation test method, which realizes batch test of logic functions; moreover, by cross-verifying the output signals of each same clock cycle, the verification is refined to each clock cycle, and the logic function of the chip can be tested more accurately.
The embodiment of the invention provides a chip logic function cross-validation testing method, which comprises the following steps:
s1, setting test parameters of N chips to be tested; the N chips to be tested are in the same batch, the same style and the same specification;
s2, establishing a test vector set of the chip to be tested; the test vector is logic 1 and logic 0 data for test or operation applied to the device pins every clock cycle;
s3, inputting the test vectors into the chips to be tested according to the time sequence according to the test parameters, and collecting output signals of the chips to be tested;
s4, performing exclusive OR operation on the output signals of each same clock cycle of the N chips to be tested to realize batch cross verification.
Optionally, the test parameters include at least: power supply voltage, input voltage, output current load, test frequency, input signal timing, and output signal timing.
Optionally, after the step S3, the method further includes:
and carrying out data preprocessing on output signals of the N chips to be detected by using a time sequence alignment algorithm, and aligning logic output values of each clock cycle.
Optionally, the S4 includes:
s41, if the exclusive OR result is logic 0, passing the test; if the exclusive or result is logic 1, the test result is recorded as an error;
s42, dividing the chip with the test result recorded as the error into two equal parts, and repeating the steps S3-S4 in parallel for the two equal parts of chips to be tested, so as to gradually reduce the test range until the fault chip is found out.
Optionally, the S41 includes:
performing bit-wise exclusive OR operation on logic output values of any two chips to be tested in each clock period one by one according to the sequence;
stopping the exclusive or operation when the bitwise exclusive or result first appears 1, and recording the test result as an error; when all bit exclusive OR results are 0, the test is passed.
Optionally, after S4, the method further includes:
s5, traversing in the test vector set until all the test vectors participate in the test.
The invention adopts the mode of inputting the test vector and collecting the logic signal for exclusive or cross verification, and can improve the efficiency of the functional test of the chip and the accuracy of the test when testing a plurality of chips with the same batch and the same model. The invention can rapidly and accurately complete the test of a large number of chips without the need of operators to have much professional knowledge. Further, for enterprises, the earlier the chip faults are found, the production and manufacturing cost can be reduced, and precious time is striven for design and manufacturing. The method can help enterprises to find chip-level safety defects, avoid safety risks and perfect product functions, and provides corresponding test technical methods and guarantees for the development of vehicle-mounted safety chips and the rapid landing of national security technologies in the chips. By cross-verifying the output signals of each same clock cycle, the verification of each clock cycle is refined, and the logic function of the chip can be tested more accurately.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for testing cross-validation of logic functions of a chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the invention, are within the scope of the invention.
Fig. 1 is a flowchart of a method for testing cross-validation of logic functions of a chip according to an embodiment of the present invention, including the following operations:
s1, setting test parameters of N chips to be tested; the N chips to be tested are in the same batch, the same style and the same specification.
In the test system, test parameters of the chip to be tested, such as power supply voltage, input voltage, output current load, test frequency, input signal time sequence, output signal time sequence and the like, are set.
S2, establishing a test vector set of the chip to be tested; the test vectors are logic 1 and logic 0 data applied to the device pins for test or operation every clock cycle.
The set of test vectors includes a plurality of test vectors, which may be provided by a design engineer, a test engineer, or a verification engineer.
S3, inputting the test vectors into the chips to be tested according to the test parameters and the time sequence order, and collecting the output signals of the chips to be tested.
N (N is more than or equal to 3 and less than or equal to m, m is the maximum value of the number of chips which can be accommodated in the test system) chips to be tested in the same batch, the same style and the same specification are placed in the test system, and functional test is performed. The test system sequentially applies the input waveforms of the test vectors to the chip under test according to the user settings and monitors the output signals of each clock cycle.
After S3, the method further includes: and carrying out data preprocessing on output signals of the N chips to be detected by using a time sequence alignment algorithm, and aligning logic output values of each clock cycle.
S4, performing exclusive OR operation on the output signals of each same clock cycle of the N chips to be tested to realize batch cross verification.
S41, if the exclusive OR result is logic 0, passing the test; if the exclusive OR result is a logic 1, the test result is recorded as an error.
Performing bit-wise exclusive OR operation on logic output values of any two chips to be tested in each clock period one by one according to the sequence;
the exclusive OR principle is as follows:
0 ^ 0 = 0 ,
0 ^ 1 = 1,
1 ^ 0 = 1 ,
1 ^ 1 = 0 ,
stopping the exclusive or operation when the bitwise exclusive or result first appears 1, and considering at least one of the two chips to be detected as abnormal, and recording the detection result as error; if the exclusive or result is 0, the two chips to be tested pass the test.
S42, dividing the chip with the test result recorded as the error into two equal parts, and repeating the steps S3-S4 in parallel for the two equal parts of chips to be tested, so as to gradually reduce the test range until the fault chip is found out. For any equal part of chips to be tested, taking output results of any two chips to be tested, carrying out bit exclusive OR operation one by one according to the sequence, recording the two chips to be tested as errors when the exclusive OR operation is 1 for the first time, and continuing the subsequent two equal parts of operations.
S5, traversing in the test vector set until all the test vectors participate in the test.
And inputting excitation to the test system to traverse the test vectors in the test vector set until all chips pass through the cross verification system, and ending the test.
The invention adopts the mode of inputting the test vector and collecting the logic signal for exclusive or cross verification, and can improve the efficiency of the functional test of the chip and the accuracy of the test when testing a plurality of chips with the same batch and the same model. The invention can rapidly and accurately complete the test of a large number of chips without the need of operators to have much professional knowledge. Further, for enterprises, the earlier the chip faults are found, the production and manufacturing cost can be reduced, and precious time is striven for design and manufacturing. The method can help enterprises to find chip-level safety defects, avoid safety risks and perfect product functions, and provides corresponding test technical methods and guarantees for the development of vehicle-mounted safety chips and the rapid landing of national security technologies in the chips. By cross-verifying the output signals of each same clock cycle, the verification of each clock cycle is refined, and the logic function of the chip can be tested more accurately.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. As used in this specification, the terms "a," "an," "the," and/or "the" are not intended to be limiting, but rather are to be construed as covering the singular and the plural, unless the context clearly dictates otherwise. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements.
It should also be noted that the positional or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.
Claims (6)
1. A method for cross-validation testing of a logic function of a chip, comprising:
s1, setting test parameters of N chips to be tested; the N chips to be tested are in the same batch, the same style and the same specification;
s2, establishing a test vector set of the chip to be tested; the test vector is logic 1 and logic 0 data for test or operation applied to the device pins every clock cycle;
s3, inputting the test vectors into the chips to be tested according to the time sequence according to the test parameters, and collecting output signals of the chips to be tested;
s4, performing exclusive OR operation on the output signals of each same clock cycle of the N chips to be tested to realize batch cross verification.
2. The method according to claim 1, wherein the test parameters comprise at least: power supply voltage, input voltage, output current load, test frequency, input signal timing, and output signal timing.
3. The method of claim 1, further comprising, after S3:
and carrying out data preprocessing on output signals of the N chips to be detected by using a time sequence alignment algorithm, and aligning logic output values of each clock cycle.
4. The method according to claim 1, wherein S4 comprises:
s41, if the exclusive OR result is logic 0, passing the test; if the exclusive or result is logic 1, the test result is recorded as an error;
s42, dividing the chip with the test result recorded as the error into two equal parts, and repeating the steps S3-S4 in parallel for the two equal parts of chips to be tested, so as to gradually reduce the test range until the fault chip is found out.
5. The method of claim 4, wherein S41 comprises:
performing bit-wise exclusive OR operation on logic output values of any two chips to be tested in each clock period one by one according to the sequence;
stopping the exclusive or operation when the bitwise exclusive or result first appears 1, and recording the test result as an error; when all bit exclusive OR results are 0, the test is passed.
6. The method of claim 1, further comprising, after S4:
s5, traversing in the test vector set until all the test vectors participate in the test.
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| CN202310664604.5A CN116400202B (en) | 2023-06-07 | 2023-06-07 | Chip logic function cross-validation test method |
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Citations (8)
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|---|---|---|---|---|
| JP2001033522A (en) * | 1999-07-19 | 2001-02-09 | Nec Eng Ltd | Logic verification system |
| JP2004012283A (en) * | 2002-06-06 | 2004-01-15 | Matsushita Electric Ind Co Ltd | Inspection device and inspection method for semiconductor integrated circuit |
| WO2006102325A1 (en) * | 2005-03-22 | 2006-09-28 | Advanced Micro Devices, Inc. | Simultaneous core testing in multi-core integrated circuits |
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| JP2008084472A (en) * | 2006-09-28 | 2008-04-10 | Oki Electric Ind Co Ltd | Semiconductor device |
| CN102466776A (en) * | 2010-11-19 | 2012-05-23 | 北京自动测试技术研究所 | Batch testing method for complex programmable logic device |
| CN115706022A (en) * | 2021-08-16 | 2023-02-17 | 长鑫存储技术有限公司 | Test method and structure for positioning fault transistor |
| CN115963385A (en) * | 2022-12-29 | 2023-04-14 | 成都蜀郡微电子有限公司 | High-precision chip life detection circuit and integrated circuit chip |
-
2023
- 2023-06-07 CN CN202310664604.5A patent/CN116400202B/en active Active
Patent Citations (10)
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| JP2001033522A (en) * | 1999-07-19 | 2001-02-09 | Nec Eng Ltd | Logic verification system |
| JP2004012283A (en) * | 2002-06-06 | 2004-01-15 | Matsushita Electric Ind Co Ltd | Inspection device and inspection method for semiconductor integrated circuit |
| WO2006102325A1 (en) * | 2005-03-22 | 2006-09-28 | Advanced Micro Devices, Inc. | Simultaneous core testing in multi-core integrated circuits |
| CN101147077A (en) * | 2005-03-22 | 2008-03-19 | 先进微装置公司 | Simultaneous core testing in multi-core integrated circuits |
| JP2008084472A (en) * | 2006-09-28 | 2008-04-10 | Oki Electric Ind Co Ltd | Semiconductor device |
| JP4951304B2 (en) * | 2006-09-28 | 2012-06-13 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| CN1924823A (en) * | 2006-09-29 | 2007-03-07 | 北京中星微电子有限公司 | Method and system for testing chip |
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