CN116389762B - Video data SpeedHQ coding method and device - Google Patents
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Abstract
The invention discloses a method and a device for encoding video data SpeedHQ, wherein the method comprises the following steps: collecting video data to be encoded and storing the video data according to rows; after each time of storing the video data of the preset line number, reading the video data stored currently and distributing the video data to a plurality of coding units in sequence; in the encoding process of each encoding unit, each encoding unit is controlled to exchange data with an adjacent encoding unit respectively, so that the data streams of the adjacent encoding units are linked to finish the data encoding of each encoding unit; and (3) sequentially splicing the data encoded by each encoding unit, and then recombining to obtain final encoded data output. The invention has the advantages of simple implementation method, low cost, small consumption of memory bandwidth and capacity, low delay and the like.
Description
Technical Field
The invention relates to the technical field of video coding, in particular to a method and a device for coding video data SpeedHQ by an NDI (Network Device Interface, network equipment interface) protocol.
Background
Video IP (Internet Protocol ) based transmission has become the dominant technology for video transmission. Among video IP technologies, NDI technology is most widely used. The NDI is an interface protocol of IP network equipment, compared with the use of coaxial cables, the NDI is more stable in transmission and stronger in anti-interference capability, and can transmit and receive multiple broadcast-level quality signals in real time through an IP network, and meanwhile, the NDI has the characteristics of low delay, accurate frame video, mutual identification of data streams, communication and the like. There are two versions of NDI: NDI FULL (also known as NDI high bandwidth) and NDI HX, wherein NDI FULL adopts a speedHQ coding mode.
In the prior art, speedHQ encoding is usually performed by buffering at least 1 frame of original video into a DDR (Double Data Rate) memory before encoding, i.e. video data is collected in units of frames, and after storing one frame of data, an encoding module reads data from DDR for encoding. Taking the encoding module as an example of 16x16 macro block encoding as shown in fig. 1, the original video data is obtained from the video interface and then stored into the DDR, the DDR stores one frame of data and then notifies the encoding unit to encode, the one frame of data is divided into a plurality of 16x16 macro blocks and is divided into each encoding unit, and each encoding unit encodes each responsible macro block independently to form a SpeedHQ stream and stores the SpeedHQ stream into the DDR memory. The above SpeedHQ coding method has the following problems:
1. since the video data is collected in units of frames, the bandwidth and capacity of DDR are increased, the DDR memory is required to rely on a large capacity, and a large amount of DDR bandwidth is consumed to buffer the original video.
2. Delay is also incurred because at least 1 frame of original video must be buffered to DDR before encoding can begin.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides a video data SpeedHQ coding method and device which have the advantages of simple implementation method, low cost, small consumption of storage bandwidth and capacity and low time delay.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a method of encoding video data SpeedHQ, comprising the steps of:
collecting video data to be encoded and storing the video data according to rows;
after storing video data of a preset line number, reading the currently stored video data and sequentially distributing the video data to a plurality of coding units, wherein the preset line number is smaller than the line number corresponding to one frame of data;
in the encoding process of each encoding unit, controlling each encoding unit to respectively perform data exchange and data link with the adjacent encoding units so as to finish the data encoding of each encoding unit, wherein the data exchange comprises the exchange of prediction values generated by the encoding units;
and (3) sequentially splicing the data encoded by each encoding unit, and then recombining to obtain final encoded data output.
Further, when the video data to be encoded is collected, the collected video data is stored in an On-Chip Memory (OCM) in a row, and data storage and reading are performed by adopting a ping-pong operation.
Further, the data storage and reading by adopting the ping-pong operation comprises: and after the storage of the preset number of lines is completed, transferring to an encoding unit for encoding, and simultaneously starting to acquire the video data of the next preset number of lines and storing the video data into a second storage part of the on-chip memory, and circulating until one frame of data is acquired.
Further, the reading the video data currently stored and sequentially distributing to the plurality of encoding units includes: and reading the video data of the preset line number stored currently and dividing the video data into macro blocks of N m multiplied by m pixels, and sequentially distributing each macro block to each coding unit, wherein N is the number of the coding units, and m is the preset line number.
Further, when each coding unit is controlled to perform data exchange and data linking with an adjacent coding unit, through performing predictive value exchange in a coding stage, each coding unit generates a predictive value to a next coding unit and receives the predictive value of a previous coding unit at the same time, so as to keep stream data linking between adjacent macro blocks, and further complete coding of each coding unit.
Further, splicing the data encoded by each encoding unit in sequence and then reorganizing the data comprises: the step of recombining the data encoded by each encoding unit after sequential splicing comprises the following steps: the first m lines, the (n+1) th m lines, the (2N+1) th m lines … … th k of the coded data of each coding unit 1 N+1 m rows are spliced in sequence and then sent to a first recombination strip for recombination, wherein k is 1 Is an integer greater than 2, and satisfies (k 1 N+1）m<M, M is the total number of video lines; second m-th, n+2m-th, 2n+2m-th, … … kth 2 N+2 m rows are spliced in sequence and then sent to a second recombination strip for recombination, wherein k is the same as the first recombination strip 2 Is an integer greater than 2, and satisfies (k 2 N+2）m<=m; and so on until the nth m row, the 2 nth m row, the 3 nth m row … … kth 3 N m rows are spliced in sequence and then sent to an N recombination strip for recombination, wherein k is the same as the N 3 Is an integer greater than 3, and satisfies (k 3 N）m<=m; and splicing the recombined data of each recombined stripe unit to obtain final encoded data output.
Further, video data distribution is started after 16 lines of video data are stored, the currently stored data are read according to the width and the height of 64x16 pixels, and macro blocks which are divided into four 16x16 pixels are distributed to 4 coding units in sequence until all the codes of the currently stored 16 lines of video data are finished.
A video data SpeedHQ coding apparatus comprising a plurality of coding units for coding received video data, further comprising:
the data acquisition and storage module is used for acquiring video data to be encoded and storing the video data according to the rows;
the distribution control module is used for reading the currently stored video data and sequentially distributing the video data to the plurality of coding units after storing the video data with preset line numbers each time, wherein the preset line numbers are smaller than the line numbers corresponding to one frame of data;
the data stream re-linking module is used for controlling each coding unit to respectively exchange data with the adjacent coding units in the coding process of each coding unit, so that the data streams of the adjacent coding units are linked to finish the data coding of each coding unit;
and the data reorganization module is used for reorganizing the data coded by each coding unit after sequential splicing to obtain final coded data output.
Further, each coding unit comprises a transformation subunit, a quantization subunit, a Zigzag coding (Zigzag), an entropy coding subunit, a stream packing subunit and a transmission module which are sequentially connected, and the stream packing subunits of two adjacent coding units realize data interaction through the transmission module.
Further, the data acquisition and storage module comprises an acquisition unit and an on-chip memory, and performs data storage and reading by adopting ping-pong operation.
Compared with the prior art, the invention has the advantages that: the invention starts to distribute to the coding unit for coding each time after storing the video data with preset line number in the process of caching the acquired original video data based on the SpeedHQ coding mode, does not need to wait for coding after completely acquiring one frame of data, can effectively reduce the bandwidth and capacity required by storage, and can meet the storage requirement by using a small-capacity memory; and because the video data with preset line numbers are stored each time, the data stream is further linked by controlling each coding unit to exchange data with the adjacent coding units in the coding process, and then the data coded by each coding unit are spliced in sequence and then recombined to obtain final correct coded data, so that the real-time coding of the cached data is realized, the data delay can be effectively avoided while the coding accuracy is ensured, and the cache bandwidth, capacity and delay of the speedhQ coding are effectively reduced.
Drawings
FIG. 1 is a flow diagram of an implementation of conventional SpeedHQ encoding.
Fig. 2 is a flowchart illustrating an implementation of the video data SpeedHQ encoding method according to the present embodiment.
FIG. 3 is a flow chart of data storage reading in an embodiment of the invention.
Fig. 4 is a schematic diagram of an implementation principle of implementing SpeedHQ encoding of video data in an embodiment of the present invention.
Detailed Description
The invention is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the invention is not limited thereby.
As used in this disclosure, the terms "a," "an," "the," and/or "the" are not intended to be limiting, but rather are to be construed as covering the singular and the plural, unless the context clearly dictates otherwise. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
As shown in fig. 2, the steps of the video data SpeedHQ encoding method of the present embodiment include:
s01, collecting video data (original video data) to be encoded and storing the video data according to rows;
s02, after storing video data with preset line numbers, reading the currently stored video data and sequentially distributing the video data to a plurality of coding units, wherein the preset line numbers are smaller than the line numbers corresponding to one frame of data;
s03, controlling each coding unit to respectively perform data exchange and data connection with adjacent coding units in the coding process of each coding unit so as to finish coding of each coding unit, wherein the data exchange comprises exchange of prediction values generated by the coding units;
s04, sequentially splicing the data encoded by the encoding units, and then recombining the data to obtain final encoded data output.
In the process of caching the acquired original video data based on the SpeedHQ coding mode, the video data is distributed to the coding unit for coding every time after the video data with the preset number of lines are stored, and coding is not needed until one frame of data is completely acquired, so that the bandwidth and capacity required by storage can be effectively reduced, and the storage requirement can be met by using a small-capacity memory; and because the video data of the preset line number is stored each time, the data in each coding unit is not continuous, the data stream is linked again by further controlling each coding unit to exchange data with the adjacent coding unit in the coding process, and then the data coded by each coding unit is spliced in sequence and then recombined, so that the real-time coding of the cache data can be realized, the data delay can be effectively avoided while the coding accuracy is ensured, and the cache bandwidth, capacity and delay of the speedhQ coding are effectively reduced.
In the embodiment, when the video data to be encoded is collected in step S01, the collected video data is stored in the on-chip memory according to the line, and the on-chip memory is utilized to realize rapid storage and reading of the data. Preferably, the data storage and reading are performed in the on-chip memory by adopting a ping-pong operation, and the steps comprise: and after the storage is completed by a preset number of lines, transferring to a coding unit for coding, and simultaneously starting to acquire the video data of the next preset number of lines and storing the video data into a second storage part of the on-chip memory, and repeating the steps until one frame of data is acquired.
Taking an on-chip memory with 256 KBYTE storage capacity as an example for data storage, the memory is divided into A, B parts, the capacity of the memory is 128KBYTE respectively, the maximum storable resolution is 4096X2160, the color space is 422 and 16 lines of 8 bits of data are stored, and as shown in FIG. 3, the steps of storing and reading by adopting ping-pong operation are as follows: after processing from the video input interface (such as hdmi, sdi, usb interface, etc.), the video data is stored in the a part of the on-chip memory, after 16 lines are stored, the original video data is notified to be read and distributed, and the second 16 lines of data are collected and stored in the B part of the on-chip memory, and the process is sequentially circulated until one frame of data is collected.
In step S02 of this embodiment, the method for reading the video data currently stored and sequentially distributing the video data to the plurality of encoding units specifically includes: and reading the video data of the preset line number stored currently and dividing the video data into N macro blocks of m multiplied by m pixels, and sequentially distributing each macro block to each coding unit, wherein N is the number of the coding units, and m is the preset line number and the preset column number. Taking the 256 KBYTE on-chip memory as an example, after receiving a notification of storing 16 lines, starting to read the data of the A part stored in the on-chip memory, reading according to 64 (width) x16 (height) pixels, splitting into four 16x16 pixel macro blocks, sequentially distributing the macro blocks to four coding units respectively for coding until all the 16 lines are coded, transferring the data to the B part in the on-chip memory for distributing, and sequentially cycling until one frame of data is acquired.
Since video data is distributed to each coding unit after being stored in a specified line number, the data of each coding unit is discontinuous, and each coding unit cannot independently complete coding. According to the embodiment, each coding unit is controlled to be respectively linked with the adjacent coding units through data in the process of exchanging data in the coding process, namely, the data between the adjacent coding units are linked in the coding process, so that the link between adjacent macro blocks is ensured, continuous and complete data can be obtained by combining the data link between the adjacent coding units for coding, and therefore, each coding unit can finish correct coding. When each coding unit performs coding, transformation (FDCT), quantization (Quantize), zigzag coding (Zigzag), entropy coding (Entropy), and stream packing (BitPack) are sequentially required, where data continuity needs to be ensured in the stream packing (BitPack) process, in step S03 of this embodiment, when each coding unit is controlled to perform data exchange (prediction value and stream data) with an adjacent coding unit, specifically, data exchange is performed in the Zigzag coding stage and the stream packing stage in the coding process, so as to keep data link between adjacent macro blocks when the prediction value exchange and the stream packing stage are implemented in the Zigzag coding stage, and coding of each coding unit is completed.
In this embodiment, the original video data is transformed and quantized, and then the zig-zag encoding is performed, and the prediction value exchange is implemented in the stage of the zig-zag encoding, where each m×m pixel macroblock is divided into several blocks, for example, 422 encoding is adopted, and 16×16 pixel macroblock is divided into four 8×8 luminance blocks and four 8×8 chrominance blocks, where the four chrominance blocks are further divided into two 8×8U and two 8×8V, and each individual 8×8 data block requires a prediction value when performing the zig-zag encoding, and this prediction value is generated by the previous 8×8 data block, so that each 16×16 pixel macroblock needs to generate a prediction value for the next encoding unit and receive the prediction value of the previous encoding unit for exchange when performing the zig-zag encoding.
Because the standard of SpeedHQ coding is required to be compatible, that is, four slices are generated after one frame of video data is coded, and the video content corresponding to each slice is fixed, the embodiment further needs to repackage after coding according to the steps above, that is, data reorganization is performed. In step S04 of this embodiment, the step of sequentially splicing and then reorganizing the data encoded by each encoding unit specifically includes: the first m lines, the (n+1) th m lines, the (2N+1) th m lines … … th k of the coded data of each coding unit 1 N+1 m rows (where k 1 Is an integer greater than 2, and satisfies (k 1 N+1）m<=m, M is the video master line) are sequentially spliced and then sent to the first reorganization strip for reorganization, the second M line, the n+2th M line, the 2n+2th M line … … kth 2 N+2 m rows (where k 2 Is an integer greater than 2, and satisfies (k 2 N+2）m<=m, M is the video head line) are sequentially spliced and then sent to a second reassembly stripe for reassembly, and so on until the nth M line, the 2 nth M line, the 3 nth M line … … kth 3 N m rows (where k 3 Is an integer greater than 3, and satisfies (k 3 N）m<=m, M is video head office) in sequence and then sent to the nth reorganization strip for reorganization; and splicing the recombined data of each recombined stripe unit to obtain final encoded data output.
Taking an on-chip memory with a storage capacity of 256 KBYTE as an example, as shown in fig. 4, after 16 lines of original video data are collected and stored in the on-chip memory, the 16 lines of data are read from the on-chip memory according to 64x16 and distributed to four coding units in a way of dividing into four 16x16 macro blocks, and each coding unit performs data interaction with adjacent coding units through data stream reconnection in the coding process, so that each coding unit finishes the required data coding; after stream data is obtained from the data stream reconnection, respectively packaging the stream data into four strips, and storing the four strips into a DDR specified address, wherein the first 16 rows and the fifth 16 rows of the data encoded by the encoding units 1,2,3 and 4 are sequentially spliced and then sent to the recombination strip 1; the second 16 rows and the sixth 16 rows of the encoded data of the encoding units 1,2,3 and 4 are spliced in sequence and then sent to the recombination strip 2; the third 16 rows and the seventh 16 rows of the encoded data of the encoding units 1,2,3 and 4 are spliced in sequence and then sent to the recombination strip 3; the fourth 16 lines and the eighth 16 lines of the encoded data of the encoding units 1,2,3 and 4 are spliced in sequence and then sent to the recombination strip 4 so as to ensure the sequence and the integrity of the data, and finally, the complete and correct encoded data is obtained.
The video data SpeedHQ coding apparatus of this embodiment includes a plurality of coding units for coding received video data, and further includes:
the data acquisition and storage module is used for acquiring video data to be encoded and storing the video data according to the rows;
the distribution control module is used for reading the video data stored currently and sequentially distributing the video data to the plurality of coding units after the video data of the preset line number are stored each time;
the data stream re-linking module is used for controlling each coding unit to respectively exchange data with the adjacent coding units in the coding process of each coding unit, so that the data streams of the adjacent coding units are linked to finish the data coding of each coding unit;
and the data reorganization module is used for reorganizing the data coded by each coding unit after sequential splicing to obtain final coded data output.
In this embodiment, each coding unit includes a transform subunit, a quantization subunit, a Zigzag coding subunit, an entropy coding subunit, a stream packing subunit and a transmission module that are sequentially connected, where the Zigzag coding subunit and the stream packing subunit in two adjacent coding units implement data interaction and data linking through the transmission module, and the previous coding unit interacts data with the next coding unit through the transmission module, so as to ensure linking between adjacent macro blocks. The transmission module is specifically used for completing data exchange and data link of the Zigzag coding subunit and the stream packing subunit.
In this embodiment, the data acquisition and storage module includes an acquisition unit and an on-chip memory, and the on-chip memory uses ping-pong operation to store and read data.
The video data SpeedHQ encoding device and the video data SpeedHQ encoding method in this embodiment are in one-to-one correspondence, and will not be described in detail herein.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention shall fall within the scope of the technical solution of the present invention.
Claims (8)
1. A method for encoding video data SpeedHQ, comprising the steps of:
collecting video data to be coded and storing the video data in rows;
each time after storing video data of a preset line number, reading the video data stored currently and dividing the video data into macro blocks of N m multiplied by m pixels, sequentially distributing each macro block to a plurality of coding units, wherein the preset line number is smaller than the line number corresponding to one frame of data, N is the number of the coding units, and m is the preset line number and the column number;
in the encoding process of each encoding unit, controlling each encoding unit to respectively perform data exchange and data link with the adjacent encoding units so as to finish the data encoding of each encoding unit, wherein the data exchange comprises the exchange of prediction values generated by the encoding units;
the data coded by each coding unit are spliced in sequence and then recombined, and final coded data output is obtained;
the step of recombining the data encoded by each encoding unit after sequential splicing comprises the following steps: the first m lines, the (n+1) th m lines, the (2N+1) th m lines … … th k of the coded data of each coding unit 1 N+1 m rows are spliced in sequence and then sent to a first recombination strip for recombination, wherein k is 1 Is an integer greater than 2, and satisfies (k 1 N+1)m<M, M is the total number of video lines; second m-th, n+2m-th, 2n+2m-th, … … kth 2 N+2 m rows are spliced in sequence and then sent to a second recombination strip for recombination, wherein k is the same as the first recombination strip 2 Is an integer greater than 2, and satisfies (k 2 N+2)m<=m; and so on until the nth m row, the 2 nth m row, the 3 nth m row … … kth 3 N m rows are spliced in sequence and then sent to an N recombination strip for recombination, wherein k is the same as the N 3 Is an integer greater than 3, and satisfies (k 3 N)m<=m; and splicing the recombined data of each recombined stripe unit to obtain final encoded data output.
2. The method for encoding the video data SpeedHQ according to claim 1, wherein when the video data to be encoded is acquired, the acquired video data is stored in the on-chip memory in rows, and the data storage and reading are performed by using a ping-pong operation.
3. The method of claim 2, wherein the performing data storage and reading using a ping-pong operation comprises: and after the storage of the preset number of lines is completed, the video data distributed to a plurality of coding units is carried out to code, and meanwhile, the next video data of the preset number of lines is started to be collected and stored in a second storage part of the on-chip memory, and the cycle is performed until one frame of data is collected.
4. The method according to claim 1, wherein the control of each coding unit performs data exchange and data linking with neighboring coding units by performing prediction value exchange during the coding stage, each coding unit generates a prediction value for the next coding unit while receiving the prediction value of the previous coding unit to maintain stream data linking between neighboring macro blocks, thereby completing coding of each coding unit.
5. The method according to any one of claims 1 to 4, wherein video data distribution is started every time 16 lines of video data are stored, the currently stored data are read according to the width and height of 64x16 pixels, and the four 16x16 pixel macro blocks are split into four 16x16 pixel macro blocks and sequentially distributed to 4 encoding units until all the encoding of the currently stored 16 lines of video data is completed.
6. A video data SpeedHQ encoder comprising a plurality of encoding units for encoding received video data, characterized by further comprising:
the data acquisition and storage module is used for acquiring video data to be encoded and storing the video data according to the rows;
the distribution control module is used for reading the video data stored at present and dividing the video data into N macro blocks of m multiplied by m pixels after storing the video data with preset line numbers each time, and sequentially distributing each macro block to a plurality of coding units, wherein the preset line numbers are smaller than the line numbers corresponding to one frame of data, N is the number of the coding units, and m is the preset line number and the column number;
the data stream reconnection module is used for controlling each coding unit to respectively perform data exchange and data link with the adjacent coding units in the coding process of each coding unit so as to finish the data coding of each coding unit, wherein the data exchange comprises the exchange of predicted values generated by the coding units;
the data reorganization module is used for reorganizing the data coded by each coding unit after sequential splicing to obtain final coded data output;
the step of recombining the data encoded by each encoding unit after sequential splicing comprises the following steps: the first m lines, the (n+1) th m lines, the (2N+1) th m lines … … th k of the coded data of each coding unit 1 N+1 m rows are spliced in sequence and then sent to a first recombination strip for recombination, wherein k is 1 Is an integer greater than 2, and satisfies (k 1 N+1)m<M, M is the total number of video lines; second m-th, n+2m-th, 2n+2m-th, … … kth 2 N+2 m rows are spliced in sequence and then sent to a second recombination strip for recombination, wherein k is the same as the first recombination strip 2 Is an integer greater than 2, and satisfies (k 2 N+2)m<=m; and so on until the nth m row, the 2 nth m row, the 3 nth m row … … kth 3 N m rows are spliced in sequence and then sent to an N recombination strip for recombination, wherein k is the same as the N 3 Is an integer greater than 3, and satisfies (k 3 N)m<=m; and splicing the recombined data of each recombined stripe unit to obtain final encoded data output.
7. The apparatus according to claim 6, wherein each of the encoding units includes a transform subunit, a quantization subunit, a Zigzag encoding subunit, an entropy encoding subunit, a stream packing subunit, and a transmission module, which are sequentially connected, and the stream packing subunits of two adjacent encoding units implement data interaction through the transmission module.
8. The video data SpeedHQ coder of claim 6 or 7, wherein the data acquisition and storage module comprises an acquisition unit and an on-chip memory, and performs data storage and reading using a ping-pong operation.
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