CN116388925A - Method, system, chip and storage medium for communication between cores of multi-core heterogeneous chip - Google Patents
Method, system, chip and storage medium for communication between cores of multi-core heterogeneous chip Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention provides a method, a system, a chip and a storage medium for communication among cores of a multi-core heterogeneous chip, wherein the method comprises the following steps: partitioning a fixed address space for each processor; setting a first protection mechanism and a second protection mechanism for each address space; when communication occurs between the processors, the sending end adds check data for the communication data and stores the communication data into the address space of the sending end; the first protection mechanism performs error checking and correction on the current communication data; the receiving end acquires the communication data from the address space of the transmitting end meeting the second protection mechanism, and when the verification data is successfully analyzed, the communication data is successfully acquired; otherwise, the acquisition fails, so that the secure communication among the cores of the multi-core heterogeneous chip is realized. The invention adopts an internal inter-process communication mode, reduces the load of CPU operation, not only meets the requirement of function safety ASIL D level, but also ensures that the communication among all processors is not mutually interfered.
Description
Technical Field
The invention relates to the field of automatic driving domain control, in particular to a multi-core heterogeneous chip inter-core communication method, a system, a chip and a storage medium.
Background
In the autopilot domain control product, the autopilot domain controller bears the data processing calculation force required by autopilot, including but not limited to millimeter wave radar, cameras, laser radar, GPS, inertial navigation and other equipment data processing, also bears the safety of bottom layer core data and networking data under autopilot, and serves as a central, and the autopilot domain controller bears the top and bottom of the autopilot domain, thereby serving the intellectualization of the automobile well. The system architecture design of the traditional technical scheme adopts an MCU and a SoC, the MCU and the SoC are communicated in an SPI, UART or Ethernet mode, and the technical scheme of a domain controller MCU+SoC of the system has the following technical problems:
the requirements of the functional safety ASIL D level are not met, and the software and hardware design needs to meet the following 9 failure modes for the communication bus module: the communication node is lost; message corruption; unacceptable latency of messages; message loss; unexpected message repetition; message sequence errors; message insertion; message masquerading; message addressing errors;
there is interference between processors and the load of the CPU operation is large.
Disclosure of Invention
Therefore, the invention aims to provide a multi-core heterogeneous chip inter-core communication method, a system, a chip and a storage medium, which adopt an internal inter-process communication mode to reduce the load of CPU operation, not only meet the requirement of functional safety ASIL D class, but also realize that the communication among all processors is not mutually interfered.
The invention provides a communication method between cores of a multi-core heterogeneous chip, which comprises the following steps:
partitioning a fixed address space for each processor;
setting a first protection mechanism and a second protection mechanism for each address space;
when communication occurs between the processors, the sending end adds check data for the communication data and stores the communication data into the address space of the sending end;
the first protection mechanism performs error checking and correction on the current communication data;
the receiving end acquires the communication data from the address space of the transmitting end meeting the second protection mechanism, and when the verification data is successfully analyzed, the communication data is successfully acquired; otherwise, the acquisition fails.
Preferably, the partitioning of the fixed address space for each processor specifically includes: the same number of address spaces as the processors are divided in the shared memory, and each processor corresponds to an independent address space.
Preferably, the verification data specifically includes:
first check data for checking repetition, loss, insertion, incorrect sequence and blocking of the communication data;
second check data for checking loss, delay, and blocking of the communication data;
third verification data for verifying disguise, incorrect addressing, and insertion of the communication data;
fourth check data for checking corruption and asymmetry of the communication data.
Preferably, the first protection mechanism performs error checking and correction on the current communication data, and specifically includes: checking the communication data, judging whether the communication data has 2-bit errors, if so, reporting the current errors, and ending the flow; otherwise, judging whether the communication data has 1-bit error, if so, correcting the error correction of the current 1-bit, otherwise, the communication data is correct, and storing the communication data in an address space of the communication data.
Preferably, the second protection mechanism specifically includes: and controlling each processor to only perform read-write access operation on the own address space, and controlling each processor to only perform read operation on the non-own address space, wherein the write operation cannot be performed, otherwise, resetting and restarting the system.
As another preferred aspect, the present invention also provides a secure communication system between cores of a multi-core heterogeneous chip, the system at least comprising:
the controller comprises a plurality of processors.
A memory for partitioning a fixed address space for each processor; the memory is provided with a first protection module and a second protection module.
And the communication module is used for data interaction between the processors.
Preferably, the first protection module is configured to verify the communication data stored in the address space, and correct the current 1-bit error when the 1-bit error occurs in the data; when 2-bit errors occur in the data, the current errors are reported.
The second protection module is used for controlling each processor to only perform read-write access operation on the address space of the processor; and controlling each processor to only perform read operation on a non-self address space and not perform write operation, otherwise, resetting and restarting the system.
Preferably, the communication module is provided with a verification module for adding verification data to the communication data or analyzing the verification data.
As another preferred aspect, the present invention also provides a chip comprising: and a processor for calling and running the computer program from the local storage unit, so that the device installed with the chip executes the multi-core heterogeneous chip inter-core communication method.
As another preferred, a storage medium, located at any control unit, includes a computer program executable by a processor for performing the multi-core heterogeneous chip inter-core communication method as described above.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the verification data is added to the communication data of the multi-core heterogeneous chip of the autopilot domain control product, so that the functional safety design requirement of a communication module can be met, a first protection mechanism is arranged for each address space, the current communication data can be subjected to error checking and correction, data damage is avoided, and a second protection mechanism is arranged for each address space, so that the mutual interference and illegal tampering of the communication data among cores can be avoided, and the functional safety ASIL D level design requirement is met.
Drawings
FIG. 1 is a flow chart of a method for communication between cores of a multi-core heterogeneous chip according to a preferred embodiment of the invention.
FIG. 2 is a schematic diagram of a secure communication system between cores of a multi-core heterogeneous chip according to a preferred embodiment of the present invention.
FIG. 3 is a diagram illustrating a second protection mechanism for protecting an address space according to a preferred embodiment of the present invention.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
Referring to fig. 1, in a preferred embodiment, a method for inter-core communication between heterogeneous multi-core chips includes:
partitioning a fixed address space for each processor;
setting a first protection mechanism and a second protection mechanism for each address space;
when communication occurs between the processors, the sending end adds check data for the communication data and stores the communication data into the address space of the sending end;
the first protection mechanism performs error checking and correction on the current communication data;
the receiving end acquires the communication data from the address space of the transmitting end meeting the second protection mechanism, and when the verification data is successfully analyzed, the communication data is successfully acquired; otherwise, the acquisition fails.
In the implementation process, a fixed address space is divided for each processor through a double rate synchronous dynamic random access memory DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) of peripheral storage equipment, and the fixed address space is used for exchanging IPC (Inter-Process Communications) communication read-write data between cores; the verification data is added to the communication data, so that the safety mechanism protection of the software is increased; the first protection mechanism is arranged in the address space and used for protecting the correctness of communication data; by setting a second protection mechanism in the address space, the method is used for preventing unexpected data tampering between cores.
The data delivery is carried out among the processors by adopting an inter-process communication IPC mode; preferably, the check data can be obtained by adding an E2E (End-to-End) End-to-End mechanism in the IPC communication protocol.
Preferably, the partitioning of the fixed address space for each processor specifically includes: the same number of address spaces as the processors are divided in the shared memory, and each processor corresponds to an independent address space.
In this embodiment, the verification data specifically includes:
first check data for checking repetition, loss, insertion, incorrect sequence and blocking of the communication data;
second check data for checking loss, delay, and blocking of the communication data;
third verification data for verifying disguise, incorrect addressing, and insertion of the communication data;
fourth check data for checking corruption and asymmetry of the communication data.
In the implementation process, the check data is an E2E end-to-end protection mechanism,
the first check data may be a frame count Counter, the second check data may be a frame Timeout, the third check data may be a data frame ID, and the fourth check data may be a CRC check, please refer to the following table:
| E2E protection mechanism | Detecting failure modes | Remarks |
| Frame count Counter | Duplication, loss, insertion, incorrect sequence, blocking of information | Counting per frame, cyclically incrementing |
| Frame Timeout | Loss, delay, blocking of information | Frame timeout determination |
| Data frame ID Data ID | Camouflage, incorrect addressing, insertion of information | Unique ID for each message |
| CRC check | Corruption of information, asymmetry | Cyclic Redundancy Check (CRC) -16 |
In the technical scheme, 9 failure modes in the prior art can be solved by adding the E2E protection mechanism, and the end-to-end protection of the safety mechanism of the software is added.
In order to further understand the IPC communication, the technical scheme of the IPC communication is as follows: the multi-core task can read the data of the same channel, and zero copy is performed to further improve the performance; data is kept in the effective window period, and error processing is carried out when the effective window period exceeds the effective window period; controlling the available space to be distributed to control a distribution period; writing the data into the shared memory through the virtual IO immediately when the data of the processor arrives; and reading out the current latest data of the shared memory at the moment when the algorithm starts to calculate, wherein the virtual IO is an abstract layer positioned on the equipment in the paravirtualized Hypervisor, and an I/O paravirtualized solution is a set of general I/O equipment virtualization programs and is an abstraction of a set of general I/O equipment in the paravirtualized Hypervisor.
In a preferred embodiment, the step S100 specifically includes:
the same number of address spaces as the processors are divided in the shared memory, and each processor corresponds to an independent address space.
For ease of understanding, please refer to fig. 2, which is a schematic diagram of a secure communication system between heterogeneous multi-Core chips, the chips are exemplarily composed of 5 cores including SoC a Core, MCU1, mc2_0, mcu2_1, mcu3_0, and fixed address spaces ipc1_0, ipc2_0, ipc2_1, ipc3_0, and ipc_a are partitioned for each Core in the DDR memory space, and are used for exchanging data for and writing data for IPC communication between cores.
Preferably, the first protection mechanism performs error checking and correction on the current communication data, and specifically includes: checking the communication data, judging whether the communication data has 2-bit errors, if so, reporting the current errors, and ending the flow; otherwise, judging whether the communication data has 1-bit error, if so, correcting the error correction of the current 1-bit, otherwise, the communication data is correct, and storing the communication data in an address space of the communication data.
In a specific implementation process, the first protection mechanism is an error checking and correcting protection mechanism, and specifically includes: when the communication data has 1bit error, correcting the error of the current 1 bit; when 2bit errors occur in the communication data, the current errors are reported.
By way of example, ECC protection, i.e., error checking and correction protection, is performed on the address space of the communication, and the data can be corrected when 1bit errors occur; 2 bits of data appear, and errors can be found; and protecting the correctness of the communication data through ECC check.
In this embodiment, the second protection mechanism is a firewall protection mechanism, and specifically includes: and controlling each processor to only perform read-write access operation on the own address space, and controlling each processor to only perform read operation on the non-own address space, wherein the write operation cannot be performed, otherwise, resetting and restarting the system.
Referring to fig. 3, an exemplary firewall function is started, where the firewall protects address spaces ipc1_0, ipc2_0, ipc2_1, ipc3_0 and ipc_a, preventing unexpected tampered data between cores, and R is a read and W is a write in fig. 3.
Such as: the firewall protects the IPC1_0 address space of the MCU1 Core, the MCU1 can perform read-write access operation on the IPC1_0 address space, other cores MCU2_0, MCU2_1, MCU3_0 and A Core can only perform read operation, write operation cannot be performed, and otherwise, system reset restarting occurs;
such as: the firewall protects the IPC2_0 address space of the MCU2_0 Core, the MCU2_0 can perform read-write access operation on the IPC2_0 address space, other cores MCU1, MCU2_1, MCU3_0 and A Core can only perform read operation, cannot perform write operation, and otherwise, the system is reset and restarted;
such as: the firewall protects the IPC2_1 address space of the MCU2_1 Core, the MCU2_1 can perform read-write access operation on the IPC2_1, and other cores MCU1, MCU2_0, MCU3_0 and A Core can only perform read operation and cannot perform write operation, otherwise, the system is reset and restarted;
such as: the firewall protects the IPC3_0 address space of the MCU3_0 Core, the MCU3_0 can perform read-write access operation on the IPC3_0 address space, other cores MCU1, MCU2_0, MCU2_1 and A Core can only perform read operation, cannot perform write operation, and otherwise, the system is reset and restarted;
such as: the firewall protects the IPC_A address space of the A Core, the A Core can perform read-write access operation on the IPC_A address space, other cores MCU1, MCU2_0, MCU2_1 and MCU3_0 can only perform read operation and cannot perform write operation, and otherwise, the system is reset and restarted.
In this embodiment, the step S300 specifically includes:
s301: when communication occurs between the processors, the transmitting end adds check data for the communication data and stores the check data in the address space of the transmitting end.
S302: checking the communication data, judging whether the communication data has 2-bit errors, if so, reporting the current errors, and ending the flow; otherwise, S303 is entered.
S303: judging whether the communication data has 1-bit error, if so, correcting the error correction of the current 1-bit, otherwise, the communication data is correct, and storing the communication data in an address space of the communication data.
In summary, the invention realizes that the inter-core communication protocol of the multi-core heterogeneous chip of the autopilot domain control product adds an E2E check protection mechanism, adds a Data frame ID number, a frame count Counter, a frame Timeout and CRC check to communication Data, meets the functional safety design requirement of a communication module, implements an ECC protection mechanism to the DDR memory address space of IPC communication, can correct 1-bit error when 1-bit error occurs, can detect 2-bit error, avoids Data damage, adopts firewall protection to the IPC address space of the memory space DDR of multi-core heterogeneous inter-core communication, can perform read-write access operation to the address space of the core, can only perform read-write access operation to the address space of other cores, can not perform write access operation, avoids the mutual interference and illegal tampering of the communication Data between the cores, and meets the functional safety ASIL D class design requirement.
As another preferred aspect, the present invention also provides a secure communication system between cores of a multi-core heterogeneous chip, the system at least comprising:
the controller comprises a plurality of processors.
A memory for partitioning a fixed address space for each processor; the memory is provided with a first protection module and a second protection module.
The communication module is used for data communication between the processors; the communication module is provided with a verification module for adding verification data to communication data or analyzing the verification data.
In this embodiment, the first protection module is configured to verify the communication data stored in the address space, and correct the error of the current 1bit when the 1bit error occurs in the data; when 2-bit errors occur in the data, the current errors are reported.
The second protection module is used for controlling each processor to only perform read-write access operation on the address space of the processor; and controlling each processor to only perform read operation on a non-self address space and not perform write operation, otherwise, resetting and restarting the system.
Referring to fig. 2 to 3, the Domian is a controller, and is composed of 5 processors, namely, soC a Core, MCU1, mcc2_0, MCU2_1, MCU3_0, wherein DDR is a memory, and is divided into five address spaces, namely ipc1_0, ipc2_0, ipc2_1, ipc3_0 and ipc_a, the communication module is an IPC communication module, and ECC is a first protection module, and ECC protection, i.e., error checking and correction protection, is performed on the address spaces of communication, and when 1bit error occurs, correction is possible; 2 bits of data appear, and errors can be found; the correctness of the communication data is protected through ECC verification; firewall is a second protection module, namely a Firewall module, and the Firewall protects address spaces IPC1_0, IPC2_0, IPC2_1, IPC3_0 and IPC_A to prevent unexpected data falsification between cores.
As another preferred aspect, the present invention also provides a chip comprising: and a processor for calling and running the computer program from the local storage unit, so that the device installed with the chip executes the multi-core heterogeneous chip inter-core communication method.
As another preferred, a storage medium, located at any control unit, includes a computer program executable by a processor for performing the multi-core heterogeneous chip inter-core communication method as described above.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above illustrative embodiments are merely illustrative and are not intended to limit the scope of the present invention thereto. Various changes and modifications may be made therein by one of ordinary skill in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various system and method embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some of the modules according to embodiments of the present invention may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present invention can also be implemented as a system program (e.g., a computer program and a computer program product) for executing a part or all of the methods described herein. Such a program embodying the present invention may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
In the several embodiments provided in this application, it should be understood that the disclosed systems and methods may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the division of functionality is merely a logical division of functionality, and there may be additional divisions of actual implementation, e.g., multiple tools or components may be combined or integrated into another system, or some features may be omitted, or not performed.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
While the invention has been described in conjunction with the specific embodiments above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, all such alternatives, modifications, and variations are included within the spirit and scope of the following claims.
Claims (10)
1. A method of multi-core heterogeneous chip inter-core communication, the method comprising:
partitioning a fixed address space for each processor;
setting a first protection mechanism and a second protection mechanism for each address space;
when communication occurs between the processors, the sending end adds check data for the communication data and stores the communication data into the address space of the sending end;
the first protection mechanism performs error checking and correction on the current communication data;
the receiving end acquires the communication data from the address space of the transmitting end meeting the second protection mechanism, and when the verification data is successfully analyzed, the communication data is successfully acquired; otherwise, the acquisition fails.
2. The method for communication between cores of a heterogeneous multi-core chip according to claim 1, wherein said partitioning a fixed address space for each processor specifically comprises: the same number of address spaces as the processors are divided in the shared memory, and each processor corresponds to an independent address space.
3. The method for communication between cores of a heterogeneous multi-core chip according to claim 2, wherein the check data includes at least:
first check data for checking repetition, loss, insertion, incorrect sequence and blocking of the communication data;
second check data for checking loss, delay, and blocking of the communication data;
third verification data for verifying disguise, incorrect addressing, and insertion of the communication data;
fourth check data for checking corruption and asymmetry of the communication data.
4. The method for inter-core communication between heterogeneous multi-core chips according to claim 3, wherein said first protection mechanism performs error checking and correction on said communication data at present, and specifically comprises:
checking the communication data, judging whether the communication data has 2-bit errors, if so, reporting the current errors, and ending the flow; otherwise, judging whether the communication data has 1-bit error, if so, correcting the error correction of the current 1-bit, otherwise, the communication data is correct, and storing the communication data in an address space of the communication data.
5. The method for communication between cores of a heterogeneous multi-core chip according to claim 4, wherein the second protection mechanism specifically comprises: and controlling each processor to only perform read-write access operation on the own address space, and controlling each processor to only perform read operation on the non-own address space, wherein the write operation cannot be performed, otherwise, resetting and restarting the system.
6. A system employing the multi-core heterogeneous chip inter-core communication method of any of claims 1-5, the system comprising at least:
the controller comprises a plurality of processors;
a memory for partitioning a fixed address space for each processor; the memory is provided with a first protection module and a second protection module;
and the communication module is used for data interaction between the processors.
7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,
the first protection module is used for checking the communication data stored in the address space, and correcting the current 1-bit error when the 1-bit error occurs to the data; when 2bit errors occur in the data, reporting the current errors;
the second protection module is used for controlling each processor to only perform read-write access operation on the address space of the processor; and controlling each processor to only perform read operation on a non-self address space and not perform write operation, otherwise, resetting and restarting the system.
8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,
the communication module is provided with a verification module for adding verification data to the communication data or analyzing the verification data.
9. A chip, wherein the chip is a multi-core heterogeneous chip, and is configured to implement the multi-core heterogeneous chip inter-core communication method according to any one of claims 1 to 5.
10. A storage medium located in any control unit, the storage medium comprising a computer program executable by a processor for performing the multi-core heterogeneous chip inter-core communication method of any of claims 1-5.
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