CN116388783A - Low-power-consumption long-distance downlink receiver circuit - Google Patents

Abstract

The invention relates to a low-power consumption long-distance downlink receiver circuit, which comprises: the Chirp despreading circuit is used for generating a despread difference frequency signal; the energy accumulation amplifying circuit is used for accumulating the energy of the signals to amplify the signals and generating blank intervals required for separating the adjacent two sections of signals before and after; the normalization circuit performs normalization processing on the amplified signal through a voltage comparator; the low-power consumption decoding circuit integrates the whole signal through an energy integrator, so that signal decoding is realized; the threshold detector detects the level of the signal and sends it to the processor. The Chirp signal demodulation and despreading mechanism of the invention suppresses interference caused by environmental signals during long-distance transmission. Second, the energy of the received signal is accumulated using the resonator without consuming external energy, thereby achieving zero-power consumption signal amplification. Finally, the decoding function is realized by using an energy integration mode.

Description

Low-power-consumption long-distance downlink receiver circuit

Technical Field

The invention relates to the technical field of the Internet of things, in particular to a low-power-consumption long-distance downlink receiver circuit.

Background

When an internet of things (IOT) system is deployed, communication connection needs to be established between a gateway and a large number of terminals, and it is important for pursuing low-power consumption and widely covered weak terminals to realize low-power consumption, long-distance and reliable downlink; the conventional downlink adopts a high-performance superheterodyne receiver, and long-distance reception can be achieved. However, deploying such a receiver on a weak terminal may significantly increase the overall power consumption of the terminal, e.g., a typical superheterodyne receiver includes three high-power-consumption signal processing stages, such as amplifying the received signal using a Low Noise Amplifier (LNA), generating a high frequency carrier with a frequency synthesizer for signal demodulation, and performing decoding based on ADC high-speed sampling. These steps result in power consumption of tens of milliwatts (mW), which is tens of times that of other devices such as processors and sensors on the weak terminals.

In order to achieve low power consumption and long distance communication, in recent years, many weak terminals introduce a Chirp spread spectrum (Chirp Spread Spectrum, CSS) mechanism on an uplink back-scatter link, and achieve hundreds of meters or even thousands of meters of uplink back-scatter communication with power consumption in microwatts. However, in the downlink reception, these weak terminals use envelope detection circuits with micro watt power consumption, and the signal reception distance is very limited. The circuit does not use a frequency synthesizer with high energy consumption to generate carrier waves, but only uses a passive device such as a diode, and the like, so that the envelope of the signal can be extracted, and therefore, the Amplitude Shift Keying (ASK) signal can be demodulated with micro-watt power consumption. However, receivers based on envelope detection circuits have two limitations. First, the envelope detection circuit itself has low sensitivity, it is difficult to detect a low-intensity signal, and the receiver cannot use a low-noise amplifier with power consumption as high as ten to several tens of milliwatts to improve the reception sensitivity, in view of reducing power consumption. Second, the envelope detection circuit cannot recognize and reject the envelope of the interference signal, and therefore can only operate if the signal strength is much greater than the interference strength, for example, if the SINR is greater than 10dB or more. These limitations significantly reduce the reception distance and reliability of an envelope detection receiver, for example, conventional envelope detection circuits, which typically only receive 20-30 meters in signal reception distance; it can be seen that neither the conventional superheterodyne receiver nor the envelope detection receiver can simultaneously realize long-distance, low-power consumption and anti-interference signal reception.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides a low-power-consumption long-distance downlink receiver circuit, and solves the contradiction that the conventional receiver cannot realize long-distance and low-power-consumption reception at the same time.

The aim of the invention is achieved by the following technical scheme: a low-power consumption long-distance downlink receiver circuit comprises a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifying circuit, a normalization circuit, a zero-power consumption synchronization and low-power consumption decoding circuit, a threshold detector and a processor;

the Chirp despreading circuit is connected with the receiving antenna and is used for mixing two paths of wideband Chirp signals transmitted by the receiving antenna from the transmitter at the same time to realize demodulation and despreading of the Chirp signals and generate a despread difference frequency signal;

the energy accumulation amplifying circuit is connected with the Chirp despreading circuit and is used for accumulating the energy of the signals to amplify the signals and generating a blank interval required for separating two adjacent sections of signals before and after;

the normalization circuit is connected with the energy accumulation amplifying circuit, and performs normalization processing on the amplified signal through a voltage comparator, so that the high level of the signal is converted into a preset voltage value;

the low-power consumption decoding circuit is connected with the normalization circuit, and integrates the whole signal through the energy integrator, so that signal decoding is realized;

the threshold detector detects the level of the signal and sends the signal level to the processor;

the processor detects the first rising edge of the output signal of the normalization circuit to correct clock drift, calibrate the self synchronous clock, and control zero power consumption synchronization and switching of the synchronization function and the decoding function in the low power consumption decoding circuit.

The Chirp despreading circuit comprises a mixer composed of two parallel radio frequency diodes, wherein the anode of one radio frequency diode is connected with a receiver, the anode of the other radio frequency diode is grounded, the mixer is realized based on the nonlinear mixing principle of nonlinear devices such as diodes, for example, the mixer can be realized by connecting the anode of one radio frequency diode with a receiver antenna and the anode of the other radio frequency diode is grounded, and other circuit topologies which can utilize the nonlinear mixing characteristics of the diodes can also be used; the mixer mixes the two paths of Chirp signals to generate a difference frequency signal S _beat By measuring S _beat The duration of the signal determines the time length of the two paths of Chirp signals sent by the transmitter, and the codes are expressed as different binary symbols by changing the time length of the two paths of Chirp signals sent by the transmitter.

The energy accumulation amplifying circuit comprises an LC resonant circuit composed of an inductor connected in series with the mixer and a first capacitor grounded, wherein energy in the circuit is alternately converted between magnetic potential energy and electric potential energy under the action of the first capacitor and the inductor, and the energy accumulation amplifying circuit is used for accumulating the energy of a signal to amplify the signal to obtain amplified S _beat The signal, i.e. the resonant signal.

The symbols encoded into different binary representations include: will amplify S _beat The signal with long duration is represented by binary symbol 1, and amplified S _beat A signal with a short duration of the signal is represented by a binary symbol 0;

the energy of the last symbol is released from the LC tank in advance before the energy of the next symbol begins to accumulate in the LC tank, thereby forming a period of one-end resonance stop, i.e., a blanking interval, separating the two symbols before the next symbol arrives.

The low-power consumption decoding circuit comprises a low-power consumption energy integrator consisting of a resistor R connected in series with the normalization circuit and a grounded second capacitor, and the energy integrator integrates the whole symbol, so that symbol decoding is realized.

And an NMOS switch SW is connected in parallel with the second capacitor, and the processor controls the switch SW to be closed after the former one accords with the completion of charging, so that the second capacitor is rapidly discharged, the initialization of the second capacitor is realized, and the influence of residual electric energy on the charging result of the next symbol is avoided.

The resistor R2 and the NMOS switch SW2 are connected in parallel at two ends of the resistor R, the resistor R2 and the NMOS switch SW3 are connected in parallel at the connecting end of the resistor R and the second capacitor, and the other end of the switch SW3 is grounded;

when receiving the synchronous symbol, the switch SW2 and the switch SW3 are closed under the control of the processor, so that the resistors R2 and R3 are connected into the circuit, the resistance of the whole RC circuit is further reduced, the charging speed of the RC circuit is further increased, the electric energy in the second capacitor is rapidly released below a detection threshold before the next symbol arrives, the jump of the output signal of the threshold detector from high to low is triggered, the processor is used for controlling the switch SW to be closed to completely release the electric energy in the second capacitor after the jump is monitored, and when the symbol synchronization is carried out, the symbol synchronization can be realized by taking a plurality of continuous symbols as synchronous symbols when the processor sequentially detects the high level of the corresponding number.

The invention has the following advantages: a low-power consumption long-distance downlink receiver circuit is based on a Chirp signal demodulation and despreading mechanism of a passive device, so that the receiver can work under a negative SINR (signal to interference plus noise ratio), thereby inhibiting interference caused by environmental signals during long-distance transmission. Second, the receiver accumulates the energy of the received signal using a resonator without consuming external energy, thereby achieving zero-power consumption signal amplification. Finally, the receiver implements the decoding function using energy integration, avoiding the high power consumption caused by the use of high power analog-to-digital converter (ADC) sampling in conventional decoding schemes.

Drawings

FIG. 1 is a schematic diagram of the circuit principle of the present invention;

FIG. 2 is a schematic diagram of a downstream Chirp signal and its represented symbols and despreading circuit;

FIG. 3 is a schematic diagram of an energy accumulation amplifying circuit;

FIG. 4 is a schematic diagram of a low power consumption decoding circuit;

FIG. 5 is a schematic diagram of a decoding circuit with synchronization function;

fig. 6 is a waveform diagram of a decoding circuit with synchronization.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Accordingly, the following detailed description of the embodiments of the present application, provided in connection with the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application. The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, the present invention relates to a receiver circuit with microwatts power consumption and several hundred meters of receiving distance, which can work under the conditions of high interference intensity and signal intensity (i.e. SINR is less than 0), and the Chirp signal demodulation and despreading mechanism based on passive devices enables the receiver to work under the negative SINR (signal to interference plus noise ratio), so as to inhibit the interference caused by the environmental signal during long-distance transmission. Second, the receiver accumulates the energy of the received signal using a resonator without consuming external energy, thereby achieving zero-power consumption signal amplification. Finally, the receiver implements the decoding function using energy integration, avoiding the high power consumption caused by the use of high power analog-to-digital converter (ADC) sampling in conventional decoding schemes.

The device specifically comprises a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifying circuit, a normalization circuit, a zero power consumption synchronization and low power consumption decoding circuit, a threshold detector and a processor;

the Chirp despreading circuit is connected with the receiving antenna and is used for mixing two paths of wideband Chirp signals transmitted by the receiving antenna from the transmitter at the same time to realize demodulation and despreading of the Chirp signals and generate a despread difference frequency signal; the energy accumulation amplifying circuit is connected with the Chirp despreading circuit and is used for accumulating the energy of the signals to amplify the signals and generating a blank interval required for separating two adjacent sections of signals before and after; the normalization circuit is connected with the energy accumulation amplifying circuit, and performs normalization processing on the amplified signal through a voltage comparator, so that the high level of the signal is converted into a preset voltage value; the low-power consumption decoding circuit is connected with the normalization circuit, and integrates the whole signal through the energy integrator, so that signal decoding is realized; the threshold detector detects the level of the signal and sends the signal level to the processor; the processor detects the first rising edge of the output signal of the normalization circuit to correct clock drift, calibrate the self synchronous clock and control zero power consumption synchronization and switching of the synchronous function and the decoding function in the low power consumption decoding circuit.

Further, as shown in fig. 2, the invention floats the high-frequency carrier and Down-Chirp signal generating function to the gateway of the internet of things so as to reduce the power consumption of the receiver, and the transmitter of the gateway can simultaneously transmit two paths of Chirp signals with wide frequency bands. After receiving the two paths of Chirp signals, the receiver mixes the two paths of Chirp signals to realize demodulation and despreading of the Chirp signals, so as to generate a despread point frequency signal. It can be understood that one of the two paths of Chirp signals transmitted by the gateway actually plays the dual roles of the high-frequency carrier and the Down-Chirp signal, so that a receiver is not required to regenerate the high-frequency carrier and the Down-Chirp signal.

Specifically, the two paths of Chirp signals in fig. 2 may be referred to as "Chirp 0" and "Chirp 1", respectively. They have the same frequency modulation slope (i.e., frequency increase rate in hz/sec) and therefore there is a constant frequency difference between them. Unlike narrowband signals such as Amplitude Shift Keying (ASK) or frequency shift keying (Frequency Shift Keying, FSK) signals, these two wideband Chirp signals are not covered by narrowband interference.

Two radio frequency diodes are used as mixers to mix two paths of Chirp signals, and the positive half-cycle and the negative half-cycle radio frequency signals received by the positive electrode and the negative electrode of the antenna can participate in the mixing, so that a high-frequency signal with the frequency being the sum of the frequencies of the two Chirp signals and a low-frequency difference frequency signal (marked as S _beat ). Using LC resonance circuit to filter out high frequency and harmonic signals, the filtered signals can be retained only by S _beat . If the receiver detects S _beat It can be inferred that the transmitter of the gateway is transmitting two Chirp signals. Further, by measuring S _beat The duration of the signal, the receiver can know the time duration of the Chirp signal sent by the transmitter. Thus, symbols representing different binary values are encoded by varying the length of time that the transmitter transmits the Chirp signal.

Theoretically, the despreading mechanism of the present invention will only be interfered by the Chirp spread spectrum signal satisfying the following conditions: the Chirp signal needs to have the same frequency modulation slope as the two Chirp signals transmitted by the transmitter, and the frequency difference between the Chirp signal and the two Chirp signals needs to be f ₁ -f ₀ Is also very unlikely to occur in practical applications.

As shown in fig. 3, the invention utilizes an LC resonant circuit to accumulate signal energy, the LC circuit is placed after a despreading circuit and consists of an inductor connected in series in the circuit and a capacitor connected to ground, and the energy in the circuit is magnetically conducted under the action of the capacitor and the inductorThe force potential energy and the electric potential energy are alternately converted. The specific principle is that the magnetic potential energy formed after the energy enters the inductor can charge the capacitor, so that electric potential energy is formed between two polar plates of the capacitor, and vice versa. The input signal of the LC circuit is S _beat I.e. the difference frequency signal generated after the Chirp signal is despread. If S _beat Resonant frequency f of frequency and potential energy conversion of signal _res Equally, the energy will accumulate in the LC circuit in the form of resonance, which is the amplified signal. Therefore, the resonant circuit functions as both a filter and an amplifier, and only the frequency f _res Is provided.

The invention uses amplified S _beat The duration of the signal (i.e. the resonant signal) represents a signal having a binary value of "1" or "0", with two segments of S being adjacent one after the other _beat The signals are separated by a blank interval. Will have S of different duration _beat And the interval thereafter is referred to as symbol 1 or symbol 0, and S _beat The duration in symbol 1 is longer than in symbol 0, symbol 1 containing more energy than symbol 0.

Further, in order to generate a blank interval required to separate the symbols, the energy of the previous symbol should be released in advance from the LC circuit before the energy of the next symbol starts to accumulate in the resonant circuit, thereby forming a period of time during which resonance stops, i.e., a blank interval, before the next symbol arrives.

Higher rate symbols require shorter symbol intervals and thus require faster discharge rates for the LC circuit. The discharge rate of the resonant circuit depends on its quality factor Q, i.e. a smaller Q value is required to increase the rate of discharge. However, a smaller Q value also means that the signal amplifying capability of the LC circuit is weaker. Thus, the receiver needs to make a trade-off between amplification performance and communication rate.

The definition formula of the quality factor is:

wherein P is _{d ss} Represents the average scattered power, E, of the energy dissipated in the resistor during a resonant period _store Representing the total energy stored in the LC for one resonance period, this means that a higher Q value means that the LC circuit is more capable of storing energy, meaning that it can accumulate more signal energy, but at the same time means that it requires more time to release the energy in the circuit.

In order to select the most optimal resonant circuit, the invention uses various commercial inductors and capacitors to build a plurality of LC circuits suitable for different symbol rates, actually measures the discharge time of the LC circuits, and calculates the Q value of the LC circuits by using the following formula.

Wherein R is _nner Is the internal resistance of the LC resonant circuit.

Selectable LC circuit parameter tables at different symbol rates

The table shows the circuit parameters, discharge time and measured amplification performance of the optional LC tank circuit at different symbol rates, and in practical implementations, a selection may be made among them according to the data rate requirements. In the table, "V _out /V _in "means resonant circuit amplification S _beat Amplification factor of voltage at signal time, T _dis Is the measured discharge time. For example, for a symbol rate of 2ksps, the third row of resonant circuit parameters in the table may be selected with a discharge time of 100 microseconds. This means that within the total length of the symbol of 500 microseconds, a time interval of more than 100 microseconds is left to distinguish between two consecutive symbols.

The third resonant circuit scheme in the table is selected to have a resonant frequency of 43kHz on prototypes with symbol rates of 1ksps and 2ksps, and the fifth resonant circuit scheme is selected to have a resonant frequency of 32.8kHz on a 5ksps prototype.

The invention uses the amplified S _beat Representing symbols carrying different binary information. For example, symbol "1" has a longer S than symbol "0 _beat The signal duration, and therefore the energy of the symbol "1" is higher than the symbol "0". If an integrator is capable of integrating the symbol energy, symbols with different energy levels will produce different integration results that can be used to distinguish between symbols. Therefore, a low power energy integrator is designed to integrate the whole symbol, thereby achieving symbol decoding. When decoding the same symbol, compared with the ADC which needs to repeat the operations of sampling, amplifying and integrating tens of times, the energy integrator only needs to perform the operation of integrating once, thus being expected to remarkably reduce the decoding power consumption.

As shown in FIG. 4, S _beat The high level portion of (2) may charge the capacitor C1 through the resistor R. Due to S _beat The signal duration is longer, the symbol "1" can charge the capacitor to a higher peak voltage, which can be detected by the threshold detector and converted into a high level signal representing a binary value "1"; conversely, the symbol "0" is due to S _beat The signal duration is short and the capacitor voltage cannot be raised to the detection threshold, so the threshold detector will output a low level representing a binary value "0". In order to reduce the power consumption of the integrator, the resistance value of R may be increased, so that the internal current is suppressed to a level of only several microamps, and the power consumption of the integrator may be reduced to about 10 microwatts.

In practical application, the peak voltage of capacitor C1 during charging is not only dependent on S _beat The duration of (2) also depends on S _beat Is used for the signal amplitude of the signal. For example, when the receiver is placed close to the gateway transmitter, the strength of the Chirp signal received by the receiver is high, which ultimately results in an amplified Sbeat signal having a high amplitude, such that the high amplitude S _beat Resulting in an increased capacitor charging rate. In this case, although S in the symbol "0 _beat The duration of the signal is longer thanShort, but may also rapidly charge the capacitance to the threshold voltage of the threshold detector. This will result in the symbol "0" being incorrectly identified as the symbol "1". Conversely, when the receiver is placed at a location remote from the gateway transmitter, symbol "1" may also be erroneously identified as symbol "0". In order to solve the problem, the design scheme performs normalization processing on the amplified Sbest signal. Specifically, a voltage comparator is placed between the LC amplification circuit and the RC integration circuit to compare S _beat The high level of the signal is converted into a preset voltage value.

The threshold detector determines the binary value represented by each symbol based on the peak voltage reached by the capacitor charge. Therefore, the capacitor needs to release the power completely quickly before the next symbol arrives after the charging of one symbol is completed, so as to avoid the residual power from affecting the charging result of the next symbol. The self-discharge effect of the capacitor is insufficient to accomplish the discharge of electrical energy, since the time taken for the capacitor to self-discharge is typically calculated in seconds or even minutes, which significantly reduces the communication rate. To solve this problem, the present design connects an NMOS switch in parallel between the two plates of the capacitor, as shown in fig. 4. At the end of each symbol, the switch will close, thereby achieving a rapid discharge.

To receive the decoding result, the processor needs to know the exact end time of each symbol and read the output result of the threshold detector at this time. Otherwise, the processor reads the output of the threshold detector at the wrong time (e.g., when integration has not been completed), resulting in the receipt of the wrong decoding solution. That is, the processor needs to synchronize with the symbols sent by the gateway. The common symbol synchronization method is to send a pre-agreed preamble symbol before communication, and the processor can identify the preamble symbol after sampling by using the ADC, thereby realizing synchronization. However, the decoding circuit of the present invention cannot sample using an ADC, and thus it does not seem to achieve synchronization and decoding of any one symbol.

To solve this problem, the decoder circuit includes a synchronization function, and the circuit can perform the synchronization function and the decoding functionSwitching is performed by a program. As shown in fig. 5 and 6, two NMOS switches and two resistors are added to the circuit to achieve the synchronization function. Upon receipt of the synchronization symbol, the switches SW2 and SW3 will be closed under the control of the processor, such that the resistors R2 and R3 are switched into the circuit. At this time, the parallel resistors R and R2 will form a smaller resistor, thereby increasing the charging speed of the RC circuit. With these resistances, even the symbol "0" can charge the capacitor to the threshold of the threshold detector, and due to the presence of R3, the power in the capacitor can be quickly released below the detection threshold before the next symbol arrives, triggering a high-to-low transition of the threshold comparator output signal. After the jump is detected, the processor will close the SW to completely release the power in the capacitor. Analysis to this point, the receiver can completely use consecutive symbols "0" as synchronization symbols when the receiver performs symbol synchronization. Symbol synchronization may be achieved when the processor detects that a corresponding number of high levels arrive in sequence. The reason why symbol "1" is not used herein as a synchronization symbol is that S in symbol "1 _beat The duration of the signal is too long, which can cause the capacitor to charge to too high a voltage. In this case, even if R3 is used for discharging, the discharging time thereof is long, and thus the receiver has to increase the interval time between the synchronization symbols, resulting in an increase in the time consumption of the synchronization operation.

As shown in fig. 5, the clock of the terminal processor continuously drifts in operation, so that the synchronization state of the processor deviates, and as the deviation accumulates, the signal decoding will finally go wrong. To address this problem, the processor will calibrate its own synchronizing clock by detecting its first rising edge as each symbol arrives.

The present invention requires the participation of a processor. However, the processor need only consult the decoding for a brief period of time between the arrival of each symbol and the arrival of the next symbol. Specifically, the processor need only read the output of the threshold detector at the end of a symbol, briefly close the switch SW to initialize the capacitance, and detect its first rising edge to calibrate the clock when the next symbol arrives. Other times the processor may enter a sleep state. In the sleep state, the processor only turns on the timing and wake-up circuit, and the power consumption is only nanowatt level.

The invention reduces the power consumption by reducing the charging current in the RC circuit, and the charging current of the circuit can be expressed as:

wherein V is _ref Representing the charge voltage applied between the plates of the capacitor, equal to the reference voltage for the normalized voltage comparator, I is suppressed by increasing the resistance R and decreasing the capacitance C2 _charge At the same time, the measure can ensure that the product RC of the capacitance value and the resistance value and the charging speed of the circuit are kept unchanged. For example, at a symbol rate equal to 5ksps, the appropriate R and C values should be 220kΩ and 330pF, at which point the power consumption of the RC circuit is 12 microwatts.

The invention can realize the receiving distance of hundreds of meters with the power consumption of microwatts level. In this scheme, a first Chirp despreading mechanism based on passive devices is proposed, which successfully reduces the Chirp signal despreading power consumption from several milliwatts to zero by floating the high power carrier and Down-Chirp signal generation function to the gateway. Secondly, a novel zero-power-consumption amplification technology based on an LC resonance circuit and a coding mechanism capable of being applied to the LC resonance amplifier are provided, so that the receiving sensitivity is effectively improved. Finally, a decoding mechanism based on energy accumulation is proposed to replace the high power consumption decoding mechanism based on ADC sampling. The design is subjected to extensive experimental evaluation under different scenes. Experimental test results show that mu Mote can support a reception distance of up to 400 meters with a power consumption of 62.07 microwatts at a communication bit rate of 2 kbps. Mu Mote can increase the downlink communication distance by a factor of 8.65 compared with the existing low-power-consumption receiver, and the power consumption is reduced by 63.2%.

The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (7)

1. A low power long distance downstream receiver circuit, characterized by: the device comprises a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifying circuit, a normalization circuit, a low-power consumption decoding circuit, a threshold detector and a processor;

the Chirp despreading circuit is connected with the receiving antenna and is used for mixing two paths of wideband Chirp signals transmitted by the receiving antenna from the transmitter at the same time to realize demodulation and despreading of the Chirp signals and generate a despread difference frequency signal;

the energy accumulation amplifying circuit is connected with the Chirp despreading circuit and is used for accumulating the energy of the signals to amplify the signals and generating a blank interval required for separating two adjacent sections of signals before and after;

the normalization circuit is connected with the energy accumulation amplifying circuit, and performs normalization processing on the amplified signal through a voltage comparator, so that the high level of the signal is converted into a preset voltage value;

the low-power consumption decoding circuit is connected with the normalization circuit, and integrates the whole signal through the energy integrator, so that signal decoding is realized;

the threshold detector detects the level of the signal and sends the signal level to the processor;

the processor detects the first rising edge of the output signal of the normalization circuit to correct clock drift, calibrate the self synchronous clock, and control zero power consumption synchronization and switching of the synchronization function and the decoding function in the low power consumption decoding circuit.

2. A low power long range downlink receiver circuit according to claim 1, wherein: the Chirp despreadingThe frequency circuit comprises a mixer consisting of two radio frequency diodes connected in parallel, wherein the anode of one radio frequency diode is connected with the receiver, and the anode of the other radio frequency diode is grounded; the mixer mixes the two paths of Chirp signals to generate a difference frequency signal S _beat By measuring S _beat The duration of the signal determines the time length of the two paths of Chirp signals sent by the transmitter, and the codes are expressed as different binary symbols by changing the time length of the two paths of Chirp signals sent by the transmitter.

3. A low power long range downlink receiver circuit according to claim 2, wherein: the energy accumulation amplifying circuit comprises an LC resonant circuit composed of an inductor connected in series with the mixer and a first capacitor grounded, wherein energy in the circuit is alternately converted between magnetic potential energy and electric potential energy under the action of the first capacitor and the inductor, and the energy accumulation amplifying circuit is used for accumulating the energy of a signal to amplify the signal to obtain amplified S _beat The signal, i.e. the resonant signal.

4. A low power long range downlink receiver circuit according to claim 3, wherein: the symbols encoded into different binary representations include: will amplify S _beat The signal with long duration is represented by binary symbol 1, and amplified S _beat A signal with a short duration of the signal is represented by a binary symbol 0;

the energy of the last symbol is released from the LC tank in advance before the energy of the next symbol begins to accumulate in the LC tank, thereby forming a period of one-end resonance stop, i.e., a blanking interval, separating the two symbols before the next symbol arrives.

5. A low power long range downlink receiver circuit according to claim 2, wherein: the low-power consumption decoding circuit comprises a low-power consumption energy integrator consisting of a resistor R connected in series with the normalization circuit and a grounded second capacitor, and the energy integrator integrates the whole symbol, so that symbol decoding is realized.

6. The low power long range downlink receiver circuit of claim 5, wherein: and an NMOS switch SW is connected in parallel with the second capacitor, and the processor controls the switch SW to be closed after the former one accords with the completion of charging, so that the second capacitor is rapidly discharged, the initialization of the second capacitor is realized, and the influence of residual electric energy on the charging result of the next symbol is avoided.

7. The low power long range downlink receiver circuit of claim 5, wherein: the resistor R2 and the NMOS switch SW2 are connected in parallel at two ends of the resistor R, the resistor R2 and the NMOS switch SW3 are connected in parallel at the connecting end of the resistor R and the second capacitor, and the other end of the switch SW3 is grounded;

when receiving the synchronous symbol, the switch SW2 and the switch SW3 are closed under the control of the processor, so that the resistors R2 and R3 are connected into the circuit, the resistance of the whole RC circuit is further reduced, the charging speed of the RC circuit is further increased, the electric energy in the second capacitor is rapidly released below a detection threshold before the next symbol arrives, the jump of the output signal of the threshold detector from high to low is triggered, the processor is used for controlling the switch SW to be closed to completely release the electric energy in the second capacitor after the jump is monitored, and when the symbol synchronization is carried out, the symbol synchronization can be realized by taking a plurality of continuous symbols as synchronous symbols when the processor sequentially detects the high level of the corresponding number.

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