CN116388783A - Low-power-consumption long-distance downlink receiver circuit - Google Patents

Abstract

The invention relates to a low-power long-distance downlink receiver circuit, which includes: a Chirp despreading circuit for generating a difference frequency signal after despreading; an energy accumulation and amplification circuit for accumulating the energy of the signal to realize signal Amplify and generate the blank interval required to separate the two adjacent signals; the normalization circuit normalizes the amplified signal through a voltage comparator; the low-power decoding circuit uses an energy integrator to normalize the entire signal Integration is performed to decode the signal; a threshold detector detects the high or low signal level and sends it to the processor. The Chirp signal demodulation and despreading mechanism of the present invention suppresses interference caused by environmental signals during long-distance transmission. Secondly, without consuming external energy, the resonator is used to accumulate the energy of the received signal, thereby realizing signal amplification with zero power consumption. Finally, the decoding function is realized by means of energy integration.

Description

A low-power long-distance downlink receiver circuit

technical field

The invention relates to the technical field of the Internet of Things, in particular to a low-power long-distance downlink receiver circuit.

Background technique

When the Internet of Things (IOT) system is deployed, it is necessary to establish a communication connection between the gateway and a large number of terminals. For weak terminals that pursue low power consumption and wide coverage, it is crucial to achieve low power consumption, long distance and reliable downlink. Important; the traditional downlink uses a high-performance superheterodyne receiver, which can achieve long-distance reception. However, deploying such a receiver on a weak terminal will significantly increase the overall power consumption of the terminal. For example, a typical superheterodyne receiver includes three high-energy-consuming signal processing links, such as using a low-noise amplifier (LNA) to amplify the received signal, A frequency synthesizer is used to generate a high-frequency carrier for signal demodulation, and decoding is realized based on ADC high-speed sampling. These steps result in tens of milliwatts (mW) of power consumption, tens of times that of other devices such as processors and sensors on weak terminals.

In order to achieve low power consumption and long-distance communication, many weak terminals have introduced the Chirp Spread Spectrum (CSS) mechanism on the uplink backscatter link in recent years, and achieved hundreds of meters or even uplink communication with microwatt-level power consumption. Kilometer uplink backscatter communication. However, in terms of downlink reception, these weak terminals use envelope detection circuits with microwatt-level power consumption, and their signal receiving distance is very limited. This circuit does not use a high-energy frequency synthesizer to generate a carrier, but only uses passive devices such as diodes to extract the envelope of the signal, so it can demodulate amplitude shift keying (ASK) signals with microwatt-level power consumption . However, receivers based on envelope detection circuits have two limitations. First of all, the envelope detection circuit itself has low sensitivity, making it difficult to detect low-intensity signals, and for the sake of reducing power consumption, the receiver cannot use low-noise amplifiers with power consumption as high as ten to tens of milliwatts to improve receiving sensitivity. Secondly, the envelope detection circuit cannot identify and eliminate the envelope of the interference signal, so it can only work when the signal strength is much greater than the interference strength, for example, when the SINR is higher than 10dB. These limitations significantly reduce the receiving distance and reliability of the envelope detection receiver, for example, the conventional envelope detection circuit, its signal receiving distance is usually only 20-30 meters; it can be seen that whether it is a traditional superheterodyne receiver , or envelope detection receivers, are unable to achieve long-distance, low power consumption and anti-interference signal reception at the same time.

It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the prior art, provide a low-power long-distance downlink receiver circuit, and solve the contradiction that the existing receiver cannot realize long-distance and low-power reception at the same time.

The purpose of the present invention is achieved through the following technical solutions: a low-power long-distance downlink receiver circuit, which includes a receiving antenna, Chirp despreading circuit, energy accumulation amplifier circuit, normalization circuit, zero power consumption synchronization and low Power consumption decoding circuit, threshold detector and processor;

The Chirp despreading circuit is connected with the receiving antenna, and is used to mix the two-way broadband Chirp signals simultaneously sent by the receiving antenna from the transmitter to realize demodulation and despreading of the Chirp signals, and generate a difference after despreading frequency signal;

Described energy accumulating amplifying circuit is connected with Chirp despreading circuit, is used for accumulating the energy of signal to realize the amplification of signal, and generates and separates the required blank interval of adjacent two sections of signals before and after;

The normalization circuit is connected to the energy accumulation amplifier circuit, and a voltage comparator is used to normalize the amplified signal, thereby converting the high level of the signal into a preset voltage value;

The low-power decoding circuit is connected to the normalization circuit, and the entire signal is integrated by an energy integrator, thereby realizing signal decoding;

The threshold detector detects the level of the signal and sends it to the processor;

The processor detects the first rising edge of the output signal of the normalization circuit to correct the clock drift, calibrates its own synchronization clock, and controls the switching between the synchronization function and the decoding function in the zero-power synchronization and low-power decoding circuit.

The Chirp despreading circuit includes a mixer composed of two parallel RF diodes, wherein the anode of one RF diode is connected to the receiver, and the anode of the other RF diode is grounded. The principle of nonlinear frequency mixing can be implemented, for example, by using the anode of one of the RF diodes connected to the receiver antenna, and the anode of the other RF diode is grounded, or other circuit topologies that can take advantage of the nonlinear mixing characteristics of diodes Realization of the structure; mix the two Chirp signals through a mixer to generate a difference frequency signal S _beat , determine the duration of the two Chirp signals sent by the transmitter by measuring the duration of the S _beat signal, and change the transmitter to send the two Chirp signals The time length of the Chirp signal is encoded in different binary symbols.

The energy accumulating amplifying circuit includes an LC resonant circuit composed of an inductor connected in series with the mixer and a grounded first capacitor, and the energy in the circuit alternates between magnetic potential energy and electric potential energy under the action of the first capacitor and the inductor The conversion is used to accumulate the energy of the signal to realize the amplification of the signal, and obtain the amplified S _beat signal, that is, the resonance signal.

Said encoding as different binary symbols includes: representing the signal with a long duration of the amplified S _beat signal with a binary symbol 1, and representing the signal with a short duration of the amplified S _beat signal with a binary symbol 0;

Before the energy of the next symbol in the LC resonant circuit starts to accumulate, the energy of the previous symbol is released from the LC resonant circuit in advance, thus forming a period of time when the resonance stops at one end before the arrival of the next symbol, that is, the blank time interval, and the blank time Space to separate two symbols.

The low-power decoding circuit includes a low-power energy integrator composed of a resistor R connected in series with the normalization circuit and a grounded second capacitor. The whole symbol is integrated by the energy integrator to realize symbol decoding.

An NMOS switch SW is connected in parallel to the second capacitor. After the previous charging is completed, the processor controls the switch SW to close, and quickly discharges the second capacitor to realize the initialization of the second capacitor and avoid residual electric energy from affecting the next symbol. charging results.

A resistor R2 and an NMOS switch SW2 are connected in parallel at both ends of the resistor R, a resistor R2 and an NMOS switch SW3 are connected in parallel at the connection end of the resistor R and the second capacitor, and the other end of the switch SW3 is grounded;

When receiving a synchronous symbol, the switch SW2 and the switch SW3 are closed under the control of the processor, so that the resistors R2 and R3 are connected to the circuit, thereby reducing the resistance of the overall RC circuit, thereby speeding up the charging speed of the RC circuit. In the next symbol Before the arrival, the electric energy in the second capacitor will be quickly released below the detection threshold, thereby triggering the jump of the output signal of the threshold detector from high to low, and the processor will control the switch SW to be closed after detecting the jump to completely release the second capacitor. The electric energy in the capacitor, when performing symbol synchronization, uses multiple consecutive symbols as synchronization symbols, and when the processor sequentially detects a corresponding number of high levels, symbol synchronization can be achieved.

The present invention has the following advantages: a low-power consumption long-distance downlink receiver circuit, based on the Chirp signal demodulation and despreading mechanism of passive devices, so that the receiver can work under negative SINR (signal-to-interference-plus-noise ratio), In this way, interference caused by environmental signals during long-distance transmission is suppressed. Secondly, without consuming external energy, the receiver uses a resonator to accumulate the energy of the received signal, thereby realizing zero-power consumption signal amplification. Finally, the receiver uses energy integration to realize the decoding function, which avoids the high power consumption caused by the high power consumption analog-to-digital converter (ADC) sampling in the traditional decoding scheme.

Description of drawings

Fig. 1 is the circuit schematic diagram of the present invention;

Fig. 2 is a schematic diagram of a downlink Chirp signal and its represented symbols and a despreading circuit;

Fig. 3 is a schematic diagram of the principle of the energy accumulation amplifier circuit;

FIG. 4 is a schematic diagram of the principle of a low-power decoding circuit;

Fig. 5 is a schematic diagram of a decoding circuit with a synchronization function;

FIG. 6 is a schematic waveform diagram of a decoding circuit with a synchronization function.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only It is a part of the embodiments of this application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the application provided in conjunction with the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 1, the present invention specifically relates to a receiver circuit with microwatt-level power consumption and a receiving distance of hundreds of meters, which can also work under the conditions of high interference intensity and signal intensity (ie, when the SINR is less than 0) , Based on the Chirp signal demodulation and despreading mechanism of passive devices, the receiver can work under negative SINR (signal-to-interference-plus-noise ratio), thereby suppressing the interference caused by environmental signals during long-distance transmission. Secondly, without consuming external energy, the receiver uses a resonator to accumulate the energy of the received signal, thereby realizing zero-power consumption signal amplification. Finally, the receiver uses energy integration to realize the decoding function, which avoids the high power consumption caused by the high power consumption analog-to-digital converter (ADC) sampling in the traditional decoding scheme.

Specifically including receiving antenna, Chirp despreading circuit, energy accumulation amplifier circuit, normalization circuit, zero-power synchronization and low-power decoding circuit, threshold detector and processor;

Among them, the Chirp despreading circuit is connected to the receiving antenna, which is used to mix the two broadband Chirp signals sent by the receiving antenna from the transmitter at the same time to realize the demodulation and despreading of the Chirp signal, and generate a difference frequency after despreading Signal; the energy accumulation amplifier circuit is connected with the Chirp despreading circuit, which is used to accumulate the energy of the signal to realize the amplification of the signal, and generate the blank interval required to separate the adjacent two sections of signals; the normalization circuit and the energy accumulation amplifier circuit Connected, the amplified signal is normalized through a voltage comparator, thereby converting the high level of the signal into a preset voltage value; the low-power decoding circuit is connected to the normalization circuit, and the energy integrator Integrate the entire signal to realize signal decoding; the threshold detector detects the level of the signal and sends it to the processor; the processor detects the first rising edge of the output signal of the normalization circuit to correct the clock drift and calibrate its own synchronous clock. And control the switching between the synchronization function and the decoding function in the zero-power synchronization and low-power decoding circuit.

Further, as shown in Figure 2, the present invention floats the high-frequency carrier and Down-Chirp signal generation functions to the IoT gateway to reduce receiver power consumption, and the transmitter of the gateway simultaneously sends two broadband Chirp signals. After receiving the two Chirp signals, the receiver mixes them to realize demodulation and despreading of the Chirp signals, thereby generating a despread point frequency signal. It can be understood that, among the two Chirp signals transmitted by the gateway, one of them actually functions as a high-frequency carrier and a Down-chirp signal, so there is no need for the receiver to regenerate a high-frequency carrier and a Down-chirp signal.

Specifically, the two Chirp signals in FIG. 2 may be called "Chirp 0" and "Chirp 1" respectively. They have the same frequency modulation slope (that is, the frequency increase rate, the unit is Hz/s), so there is a constant frequency difference between them. Different from narrowband signals such as amplitude shift keying (ASK) or frequency shift keying (Frequency Shift Keying, FSK) signals, these two wideband Chirp signals will not be covered by narrowband interference.

Use two RF diodes as mixers to mix the two Chirp signals. The positive and negative half-cycle RF signals received by the positive and negative electrodes of the antenna can participate in the mixing, and a high-frequency signal can be obtained. Its frequency is the sum of the frequencies of the two Chirp signals and a low-frequency beat signal (denoted as S _beat ). The LC resonant circuit is used to filter out high frequency and harmonic signals, and the only signal that can be retained after filtering is S _beat . If the receiver detects the presence of the S _beat , it can deduce that the transmitter of the gateway is sending two Chirp signals. In addition, by measuring the duration of the S _beat signal, the receiver can know the length of time for the transmitter to send the Chirp signal. Therefore, by changing the length of time the transmitter sends the Chirp signal, the symbols representing different binary values are encoded.

Theoretically, the despreading mechanism of the present invention will only be interfered by the Chirp spread spectrum signal meeting the following conditions: this Chirp signal needs to have the same frequency modulation slope as the two Chirp signals sent by the transmitter, and it has the same frequency modulation slope as the two Chirp signals sent by the transmitter. The frequency difference between Chirp signals needs to be 2n times (n=0, 1, 2, 3...) of f ₁ -f ₀ , and the possibility of this signal appearing in practical applications is also very small.

As shown in Fig. 3, the present invention utilizes LC resonant circuit to realize the accumulation of signal energy, and LC circuit is placed after despreading circuit, and it is made up of an inductance connected in series in the circuit and a grounded capacitance, the energy in the circuit Under the action of capacitance and inductance, the two forms of magnetic potential energy and electric potential energy are alternately converted. The specific principle is that the magnetic potential energy formed after the energy enters the inductor can charge the capacitor, thereby forming an electric potential energy between the two plates of the capacitor, and vice versa. The input signal of the LC circuit is S _beat , that is, the beat frequency signal generated after the Chirp signal is despread. If the frequency of the S _beat signal is equal to the resonant frequency f _res of potential energy conversion, its energy will be accumulated in the LC circuit in the form of resonance, and the resonant circuit is the amplified signal. Therefore, the resonant circuit acts as a filter and an amplifier at the same time, and only amplifies the signal at frequency f _res .

The present _invention uses the duration of the amplified S _beat signal (ie, the resonance signal) to represent a signal with a binary value "1" or a binary value "0". spaced apart by white space. The S _beat with different durations and the subsequent interval are called symbol 1 or symbol 0, and the duration of S _beat in symbol 1 is longer than that in symbol 0, and symbol 1 contains more much energy.

Furthermore, in order to generate the blank interval required to separate symbols, in the resonant circuit, before the energy of the next symbol starts to accumulate, the energy of the previous symbol should be released from the LC circuit in advance, so as to form a period of resonance before the arrival of the next symbol The period of time to stop, the blank interval.

Higher rate symbols require shorter inter-symbol intervals, thus requiring a faster discharge rate for the LC circuit. The discharge speed of the resonant circuit depends on its quality factor Q, that is to say, a smaller Q value is needed to increase the discharge speed. However, a smaller Q value also means that the signal amplification ability of the LC circuit is weaker. Therefore, the receiver needs to make a trade-off between amplification performance and communication rate.

其中P_d揨ss表示在一个谐振周期中，能量消耗在电阻上时的平均散射功率，E_store表示一个谐振周期中储存在LC中的总能量，这表明，较高的Q值意味着LC电路保存能量的能力更强，也就意味着它可以累积更多的信号能量，但同时意味着它需要更多的时间来释放电路中的能量。The definition formula of the quality factor is:

where Pd_揨ss represents the average scattered power when energy is dissipated on the resistor during a resonance cycle, and E _store represents the total energy stored in the LC during a resonance cycle, which indicates that a higher Q value means that the LC circuit The ability to conserve energy is greater, which means it can accumulate more signal energy, but it also means it takes more time to release the energy in the circuit.

In order to select the most optimal resonant circuit, the present invention uses a variety of commercially available inductors and capacitors to build a number of LC circuits suitable for different symbol rates, and actually measures their discharge time, and uses the following formula to calculate their Q values.

Among them, R_揨nner is the internal resistance of the LC resonant circuit.

Table of optional LC circuit parameters at different symbol rates

The table lists the circuit parameters, discharge time and measured amplification performance of the optional LC resonant circuit at different symbol rates. In actual implementation, a choice can be made according to the data rate requirements. In the table, “V _out /V _in ” indicates the amplification factor of the voltage when the resonant circuit amplifies the S _beat signal, and T _dis is the measured discharge time. For example, for a symbol rate of 2ksps, the resonant circuit parameters in the third row of the table can be chosen with a discharge time of 100 microseconds. This means that within a total symbol length of 500 microseconds, two adjacent symbols can be distinguished by leaving a time interval of more than 100 microseconds.

The present invention selects the third resonant circuit scheme in the table on prototypes with a symbol rate of 1ksps and 2ksps, and its resonant frequency is 43kHz; on the 5ksps prototype, selects the fifth resonant circuit scheme, whose resonant frequency is 32.8kHz.

In the present invention, the duration of the enlarged S _beat is used to represent symbols carrying different binary information. For example, the symbol "1" has a longer S _beat signal duration than the symbol "0", so the energy of the symbol "1" is higher than that of the symbol "0". If there is an integrator capable of integrating symbol energies, symbols with different energy levels will produce different integration results, which can be used to distinguish symbols. Therefore, a low-power energy integrator is designed to integrate the entire symbol to realize symbol decoding. When decoding the same symbol, compared with ADCs that need to repeat dozens of sampling, amplification, and integration operations, the energy integrator only needs to perform one integration operation, so it is expected to significantly reduce decoding power consumption.

As shown in FIG. 4 , the high level part of S _beat can charge the capacitor C1 through the resistor R. Due to the longer duration of the S _beat signal, the symbol "1" can charge the capacitor to a higher peak voltage, which can be detected by the threshold detector and converted to represent the binary value "1". On the contrary, the symbol "0" cannot raise the capacitor voltage to the detection threshold due to the short duration of the S _beat signal, so the threshold detector will output a low level representing the binary value "0". In order to reduce the power consumption of the integrator, the resistance value of R can be increased to suppress the internal current to only a few microamperes, and the power consumption of the integrator can be reduced to about 10 microwatts.

In practical applications, the peak voltage that the capacitor C1 can reach during the charging process depends not only on the duration of the S _beat , but also on the signal amplitude of the S _beat . For example, when the receiver is placed close to the transmitter of the gateway, the strength of the Chirp signal received by the receiver is stronger, which will eventually cause the amplified Sbeat signal to have a higher amplitude, so the high amplitude _Sbeat It will cause the capacitor to charge faster. In this case, although the duration of the S _beat signal in the symbol "0" is short, it is also possible to quickly charge the capacitor to the threshold voltage of the threshold detector. This will cause the symbol "0" to be incorrectly recognized as the symbol "1". Conversely, when the receiver is placed far away from the gateway transmitter, the symbol "1" may be misidentified as the symbol "0". In order to solve this problem, this design scheme normalizes the amplified Sbeat signal. Specifically, a voltage comparator is placed between the LC amplifying circuit and the RC integrating circuit, so as to convert the high level of the S _beat signal into a preset voltage value.

A threshold detector determines the binary value each symbol represents based on the peak voltage reached by the capacitor charging. Therefore, before the charging of a symbol is completed and the next symbol arrives, the capacitor needs to quickly discharge the electric energy completely, so as to avoid the residual electric energy from affecting the charging result of the next symbol. Utilizing the self-discharging effect of the capacitor is not enough to complete the power release, because the self-discharging time of the capacitor is usually calculated in seconds or even minutes, which will significantly reduce the communication rate. In order to solve this problem, this design scheme connects an NMOS switch in parallel between the two plates of the capacitor, as shown in Figure 4. At the end of each symbol, the switch will close, allowing for a rapid discharge.

In order to receive the decoded results, the processor needs to know the exact end time of each symbol and read the output of the threshold detector on time at this time. Otherwise, the processor will read the output of the threshold detector at the wrong time (for example, when the integration is not yet complete), resulting in receiving an incorrect decoded solution. That is, the processor needs to be synchronized with the symbols sent by the gateway. A commonly used symbol synchronization method is to send pre-agreed preamble symbols before communication, and the processor can identify the preamble symbols after sampling with ADC, thereby achieving synchronization. However, the decoding circuit of the present invention cannot use an ADC for sampling, and thus does not appear to be able to synchronize and decode any one symbol.

In order to solve this problem, the synchronization function is included in the design of the decoding circuit, and the synchronization function and decoding function of the circuit can be switched through the program. As shown in Figure 5 and Figure 6, two NMOS switches and two resistors are added to the circuit to realize the synchronization function. When a sync symbol is received, the switch SW2 and the switch SW3 will be closed under the control of the processor, so that the resistors R2 and R3 are connected into the circuit. At this time, the resistors R and R2 connected in parallel will form a smaller resistor, thereby speeding up the charging speed of the RC circuit. With these resistors, even a symbol "0" can charge the capacitor up to the threshold of the threshold detector, and because of R3, the energy in the capacitor can be quickly discharged below the detection threshold before the next symbol arrives, thus Triggers a high-to-low transition of the threshold comparator output signal. After detecting the transition, the processor will close SW to completely discharge the electric energy in the capacitor. From the analysis so far, when the receiver performs symbol synchronization, the receiver can completely use multiple consecutive symbols "0" as synchronization symbols. When the processor detects that the corresponding number of high levels arrives in sequence, symbol synchronization can be achieved. The reason why the symbol "1" is not used as the synchronization symbol in this article is that the duration of the S _beat signal in the symbol "1" is too long, which will cause the capacitor to be charged to an excessively high voltage. In this case, even if R3 is used for discharging, its discharge time will be longer, so the receiver has to increase the interval time between synchronization symbols, which will increase the time consumption of synchronization operations.

As shown in Figure 5, the clock of the terminal processor will continuously drift during operation, resulting in deviations in the synchronization state of the processors. With the accumulation of deviations, signal decoding errors will eventually occur. To solve this problem, the processor calibrates its own synchronous clock by detecting the first rising edge of each symbol.

The present invention requires processor participation. However, the processor only needs to be involved in the decoding during the short time between the end of each symbol and the arrival of the next symbol. Specifically, the processor only needs to read the output of the threshold detector at the end of a symbol, briefly close the switch SW to initialize the capacitor, and detect its first rising edge when the next symbol comes to calibrate the clock. Other times the processor can go to sleep. In the sleep state, the processor only turns on the timing and wake-up circuits, and the power consumption is only nanowatts.

The present invention reduces its power consumption by reducing the charging current in the RC circuit, and the charging current of the circuit can be expressed as:

Among them, V _ref represents the charging voltage applied between the two plates of the capacitor, which is equal to the reference voltage of the voltage comparator used for normalization. I _charge is suppressed by increasing the resistance R and reducing the capacitance C2. At the same time, such measures can ensure the capacitance The product of the value of RC and the value of the resistor, RC, and the charging speed of the circuit remain the same. For example, when the symbol rate is equal to 5ksps, the appropriate values of R and C should be 220kΩ and 330pF according to calculation, and the power consumption of the RC circuit at this time is 12 microwatts.

The invention can realize the receiving distance of hundreds of meters with the power consumption of microwatt level. In this scheme, the first Chirp despreading mechanism based on passive devices is proposed. This mechanism successfully despreads the Chirp signal by floating the high-power carrier and Down-chirp signal generation functions to the gateway. Power consumption is reduced from a few milliwatts to zero. Second, a novel zero-power amplification technique based on an LC resonant circuit is proposed, as well as an encoding mechanism that can be applied to this LC resonant amplifier, thereby effectively improving the receiving sensitivity. Finally, a decoding scheme based on energy accumulation is proposed to replace the high-power ADC sampling-based decoding scheme. This paper conducts extensive experimental evaluation of this design in different scenarios. Experimental test results show that μMote can support a receiving distance of up to 400 meters, and its power consumption is 62.07 microwatts at a communication bit rate of 2kbps. Compared with existing low-power receivers, μMote is able to increase the downlink communication distance by 8.65 times while consuming 63.2% less power.

The above descriptions are only preferred embodiments of the present invention, and it should be understood that the present invention is not limited to the forms disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and Modifications can be made within the scope of the ideas described herein, by virtue of the above teachings or skill or knowledge in the relevant art. However, changes and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, and should all be within the protection scope of the appended claims of the present invention.

Claims (7)

1. A low power consumption long-distance downlink receiver circuit is characterized in that: it includes receiving antenna, Chirp despreading circuit, energy accumulation amplifier circuit, normalization circuit, low power consumption decoding circuit, threshold value detector and processing device; The Chirp despreading circuit is connected with the receiving antenna, and is used to mix the two-way broadband Chirp signals simultaneously sent by the receiving antenna from the transmitter to realize demodulation and despreading of the Chirp signals, and generate a difference after despreading frequency signal; Described energy accumulating amplifying circuit is connected with Chirp despreading circuit, is used for accumulating the energy of signal to realize the amplification of signal, and generates and separates the required blank interval of adjacent two sections of signals before and after; The normalization circuit is connected to the energy accumulation amplifier circuit, and a voltage comparator is used to normalize the amplified signal, thereby converting the high level of the signal into a preset voltage value; The low-power decoding circuit is connected to the normalization circuit, and the entire signal is integrated by an energy integrator, thereby realizing signal decoding; The threshold detector detects the level of the signal and sends it to the processor; The processor detects the first rising edge of the output signal of the normalization circuit to correct the clock drift, calibrates its own synchronization clock, and controls the switching between the synchronization function and the decoding function in the zero-power synchronization and low-power decoding circuit. 2. A kind of low power consumption long-distance downlink receiver circuit according to claim 1, it is characterized in that: said Chirp despreading circuit comprises the mixer that two radio frequency diodes connected in parallel are formed, wherein one radio frequency diode The anode is connected to the receiver, and the anode of the other RF diode is grounded; the two Chirp signals are mixed by a mixer to generate a difference frequency signal S _beat , and the two Chirp signals sent by the transmitter are determined by measuring the duration of the S _beat signal The length of the time, by changing the length of time the transmitter sends the two Chirp signals, coded into different binary symbols. 3. A low-power long-distance downlink receiver circuit according to claim 2, characterized in that: said energy accumulation amplifier circuit comprises an LC composed of an inductor connected in series with the mixer and a grounded first capacitor Resonant circuit, the energy in the circuit is alternately converted between magnetic potential energy and electric potential energy under the action of the first capacitor and inductance, which is used to accumulate the energy of the signal to achieve signal amplification, and obtain the amplified S _beat signal, that is, the resonance signal . 4. A kind of low-power consumption long-distance downlink receiver circuit according to claim 3, it is characterized in that: said coding is represented as the symbol of different binary numbers and comprises: the long duration signal of the S _beat signal after amplifying Binary symbol 1 means that the signal with short duration of the amplified S _beat signal is represented by binary symbol 0; Before the energy of the next symbol in the LC resonant circuit starts to accumulate, the energy of the previous symbol is released from the LC resonant circuit in advance, thus forming a period of time when the resonance stops at one end before the arrival of the next symbol, that is, the blank time interval, and the blank time Space to separate two symbols. 5. A low-power long-distance downlink receiver circuit according to claim 2, characterized in that: said low-power decoding circuit comprises a resistor R connected in series with the normalization circuit and a second capacitor grounded A low-power energy integrator is formed, and the whole symbol is integrated by the energy integrator, so as to realize symbol decoding. 6. A low-power long-distance downlink receiver circuit according to claim 5, characterized in that: an NMOS switch SW is connected in parallel on the second capacitor, and the processor controls the switch after the previous charging is completed. The SW is closed to quickly discharge the second capacitor to realize the initialization of the second capacitor and prevent the residual electric energy from affecting the charging result of the next symbol. 7. A low-power long-distance downlink receiver circuit according to claim 5, characterized in that: a resistor R2 and an NMOS switch SW2 are connected in parallel at both ends of the resistor R, and between the resistor R and the second capacitor A resistor R2 and an NMOS switch SW3 are connected in parallel at the connection end, and the other end of the switch SW3 is grounded; When receiving a synchronous symbol, the switch SW2 and the switch SW3 are closed under the control of the processor, so that the resistors R2 and R3 are connected to the circuit, thereby reducing the resistance of the overall RC circuit, thereby speeding up the charging speed of the RC circuit. In the next symbol Before the arrival, the electric energy in the second capacitor will be quickly released below the detection threshold, thereby triggering the jump of the output signal of the threshold detector from high to low, and the processor will control the switch SW to be closed after detecting the jump to completely release the second capacitor. The electric energy in the capacitor, when performing symbol synchronization, uses multiple consecutive symbols as synchronization symbols, and when the processor sequentially detects a corresponding number of high levels, symbol synchronization can be achieved.

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