CN116386537A

CN116386537A - Pixel driving circuit, driving method thereof and display panel

Info

Publication number: CN116386537A
Application number: CN202211161717.5A
Authority: CN
Inventors: 金山川; 田雪松; 谢强; 李世明
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-09-22
Filing date: 2022-09-22
Publication date: 2023-07-04

Abstract

The application discloses a pixel driving circuit, a driving method thereof and a display panel, wherein the pixel driving circuit comprises a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit and a first threshold control sub-circuit, wherein the first reset sub-circuit is used for responding to the control of a first scanning signal to provide the voltage of a first reset signal end for the second end of the driving transistor; the second reset sub-circuit is used for responding to the control of a third scanning signal and providing the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor; the write sub-circuit is used for responding to the control of the fourth scanning signal and providing the voltage of the data signal terminal to the first terminal of the driving transistor; the first threshold control sub-circuit is used for responding to the control of the second scanning signal to conduct the connection between the control end of the driving transistor and the second end of the driving transistor; the voltage of the first reset signal end is opposite to the voltage of the second reset signal end in polarity.

Description

Pixel driving circuit, driving method thereof and display panel

Technical Field

The present disclosure relates generally to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display panel.

Background

Organic light emitting diode (Organic Light Emitting Diode, OLED) display panels have gradually gained up a vast majority of the market in recent years. OLED display panels are receiving a great deal of attention from people for their light and thin, excellent display effect, high contrast, wide color gamut, flexibility, etc., and are considered to be a next-generation display solution that is expected to replace liquid crystals.

With the increasing demand for diversified screen displays, increasing screen utilization has become a new development demand, and power consumption is currently reduced mainly by reducing the refresh frequency of the screen to meet the demand under certain displays. For example, a driving mode with higher refresh rate is adopted to drive and display dynamic pictures (such as sports events or game scenes) so as to ensure the fluency of the display pictures; the slow lens image or the static picture is driven and displayed by adopting a driving mode with low refresh rate so as to reduce the power consumption.

However, the OLED display product has the problems of low Flicker (Flicker), refresh frequency switching Flicker, first frame response Flicker, and the like while realizing low power consumption and adaptive dynamic refresh rate driving.

Disclosure of Invention

In view of the foregoing drawbacks or shortcomings in the prior art, it is desirable to provide a pixel driving circuit, a driving method thereof, and a display panel, which can improve the problems of low Flicker (Flicker), refresh frequency switching Flicker, and first frame response Flicker.

In a first aspect, the present application provides a pixel drive circuit comprising a drive transistor, a storage capacitor, a write sub-circuit, a first reset sub-circuit, a second reset sub-circuit, a first threshold control sub-circuit,

the driving transistor is used for responding to the control of the signal voltage of the control end to generate driving current on a conduction path from the first end to the second end;

the first reset sub-circuit is connected with the second end of the driving transistor and is used for responding to the control of a first scanning signal to provide the voltage of a first reset signal end for the second end of the driving transistor;

the second reset sub-circuit is connected with the control end of the driving transistor, the storage capacitor and the first end of the first threshold control sub-circuit and is used for responding to the control of the third scanning signal to provide the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor;

the writing sub-circuit is connected with the first end of the driving transistor and is used for responding to the control of a fourth scanning signal to provide the voltage of the data signal end for the first end of the driving transistor;

The second end of the first threshold control sub-circuit is connected with the second end of the driving transistor and is used for responding to the control of the second scanning signal to conduct the connection between the control end of the driving transistor and the second end of the driving transistor;

the voltage of the first reset signal end is opposite to the voltage of the second reset signal end in polarity.

Optionally, a light emitting element, a first light emitting sub-circuit, a second light emitting sub-circuit, and a third reset sub-circuit are further included, wherein,

the first light-emitting sub-circuit is connected with a first power supply end and a first end of the driving transistor and is used for responding to the control of a light-emitting signal to provide the voltage of the first power supply end for the driving transistor;

the second light-emitting subcircuit is connected with the second end of the driving transistor and the first end of the light-emitting element and used for responding to the control of the light-emitting signal to provide the driving current of the driving transistor for the light-emitting element, and the second end of the light-emitting element is connected with a second power supply end;

the third reset sub-circuit is connected with the second end of the second light-emitting sub-circuit and the first end of the light-emitting element, and is used for responding to the control of the first scanning signal and providing the voltage of the third reset signal end for the second end of the second light-emitting sub-circuit and the first end of the light-emitting element.

Optionally, the first reset sub-circuit includes a first transistor, a first end of the first transistor is connected to the first reset signal end, a second end of the first transistor is connected to the second end of the driving transistor, and a control end of the first transistor is connected to a first scan line providing the first scan signal;

the second reset sub-circuit comprises a fifth transistor, a first end of the fifth transistor is connected with the second reset signal end, a second end of the fifth transistor is connected with the control end of the driving transistor and the storage capacitor, and the control end of the fifth transistor is connected with a third scanning line for providing the third scanning signal;

the writing sub-circuit comprises a fourth transistor, wherein a first end of the fourth transistor is connected with the data signal end, a second end of the fourth transistor is connected with the first end of the driving transistor, and a control end of the fourth transistor is connected with a fourth scanning line for providing the fourth scanning signal;

the first threshold control sub-circuit comprises a second transistor, a first end of the second transistor is connected with the control end of the driving transistor and the storage capacitor, a second end of the second transistor is connected with the second end of the driving transistor, and the control end of the second transistor is connected with a second scanning line for providing the second scanning signal.

Optionally, the first light emitting sub-circuit includes a seventh transistor, a first end of the seventh transistor is connected to the first power supply end, a second end of the seventh transistor is connected to the first end of the driving transistor, and a control end of the seventh transistor is connected to a light emitting control line that provides a light emitting signal;

the second light-emitting subcircuit comprises an eighth transistor, a first end of the eighth transistor is connected with a second end of the driving transistor, a second end of the eighth transistor is connected with a first end of the light-emitting element, and a control end of the eighth transistor is connected with the light-emitting control line;

the third reset sub-circuit comprises a sixth transistor, a first end of the sixth transistor is connected with the first end of the light emitting element, a second end of the sixth transistor is connected with the third reset signal end, and a control end of the sixth transistor is connected with the first scanning line.

Optionally, the circuit further comprises a second threshold control sub-circuit, wherein a first end of the second threshold control sub-circuit is connected with the storage capacitor and the control end of the driving transistor, and a second end of the second threshold control sub-circuit is connected with the second reset sub-circuit;

The second threshold control sub-circuit is used for responding to the control of the fifth scanning signal to turn on and off the connection of the control end of the driving transistor and the first threshold control sub-circuit.

Optionally, the second threshold control sub-circuit includes a ninth transistor, a first end of the ninth transistor is connected to the control end of the driving transistor and the storage capacitor, a second end of the ninth transistor is connected to the first end of the second transistor, and a control end of the ninth transistor is connected to a fifth scan line that provides a fifth scan signal.

Optionally, the first scan signal and the third scan signal share the same scan line, and/or the second scan signal and the fourth scan signal share the same scan line.

In a second aspect, the present application provides a driving method of a pixel driving circuit, applied to a pixel driving circuit as described in any one of the above, wherein a refresh driving period of the driving method includes a first reset phase, a write phase, a first bias phase, a first light-emitting phase,

in the first reset stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal to the second terminal of the driving transistor;

In the writing stage, the writing sub-circuit responds to the control of a fourth scanning signal to provide the voltage of a data signal end for the first end of the driving transistor, and the first threshold control sub-circuit responds to a second scanning signal to conduct the connection between the control end of the driving transistor and the second end of the driving transistor;

in the first bias stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal end for the second end of the driving transistor, and the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor;

in the first light-emitting stage, the light-emitting element emits light in response to a driving current of the driving transistor.

Optionally, the hold driving period of the driving method includes a second reset phase, a hold phase, a second bias phase, a second light emitting phase,

in the second reset stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal to the second terminal of the driving transistor;

in the holding stage, the write sub-circuit disconnects the write sub-circuit from the first terminal of the driving transistor in response to control of a fourth scan signal;

In the second bias stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal to the second terminal of the driving transistor; the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor;

in the second light-emitting stage, the light-emitting element emits light in response to the drive current of the drive transistor.

Optionally, the first reset phase includes a first reset sub-phase, a second reset sub-phase, and a third reset sub-phase:

in the first reset sub-stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal for the second terminal of the driving transistor; the first threshold control sub-circuit responds to a second scanning signal to conduct connection between the control end of the driving transistor and the second end of the driving transistor;

in the second reset sub-stage, the second reset sub-circuit responds to the control of a third scanning signal to provide the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor; the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor;

In the third reset sub-stage, the second reset sub-circuit responds to the control of a third scanning signal to provide the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor; the first threshold control sub-circuit responds to a second scanning signal to conduct connection between the second end of the driving transistor and the control end of the driving transistor.

Optionally, the first reset phase further comprises a reset maintenance sub-phase located between the first reset sub-phase and the second reset sub-phase,

in the reset maintaining sub-stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal for the second terminal of the driving transistor; the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor.

Optionally, the first reset phase comprises a first reset sub-phase and a second reset sub-phase,

in the first reset sub-stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal terminal for the second terminal of the driving transistor; the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor;

In the second reset sub-stage, the second reset sub-circuit responds to the control of a third scanning signal to provide the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor; the first threshold control sub-circuit responds to a second scanning signal to disconnect the control end of the driving transistor from the second end of the driving transistor.

Optionally, the refresh driving period of the driving method further includes:

in the first reset stage, the first reset sub-circuit responds to the control of a first scanning signal to provide the voltage of a first reset signal end for the second end of the driving transistor, the second reset sub-circuit responds to the control of a third scanning signal to provide the voltage of a second reset signal end for the control end of the driving transistor and the storage capacitor, and the first threshold control sub-circuit responds to the second scanning signal to disconnect the connection between the control end of the driving transistor and the second end of the driving transistor.

In a third aspect, the present application provides a display panel comprising a pixel driving circuit as described in any one of the above.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

According to the pixel driving circuit provided by the embodiment of the application, the first reset sub-circuit and the second reset sub-circuit are used for resetting the second end and the control end of the driving transistor respectively, so that when the bias state of the driving transistor is regulated before picture switching, the bias state of the driving transistor can be regulated to be a negative bias state or a positive bias state, the driving transistor is not influenced by the picture data of the previous frame, and the picture is quickly switched to a preset switching picture, so that the flicker phenomenon in the picture switching process is improved, and the display effect is improved. Before the light-emitting stage, the first reset sub-circuit starts the drive transistor to enter the light-emitting stage from a fixed bias conduction state, so that the recovery process of the threshold voltage of the drive transistor in the drive period and the recovery process of the threshold voltage of the drive transistor in the refresh drive period tend to be consistent, the brightness difference between the refresh drive period and the drive period is reduced, and the VRR is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

fig. 1-2 are schematic structural diagrams of a pixel driving circuit according to an embodiment of the present application;

Fig. 3 is a schematic connection diagram of a pixel driving circuit according to an embodiment of the present application;

fig. 4-9 are schematic diagrams illustrating states of a pixel driving circuit according to an embodiment of the present application;

FIGS. 10-11 are timing diagrams illustrating a method of driving a pixel driving circuit according to embodiments of the present application;

fig. 12-13 are schematic diagrams illustrating states of a pixel driving circuit according to an embodiment of the present application;

FIGS. 14-15 are timing diagrams of a method for driving a pixel driving circuit according to embodiments of the present application;

fig. 16 is a schematic connection diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 17 is a schematic state diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 18-19 are timing diagrams of a driving method of a pixel driving circuit according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

The driving transistor in the pixel driving circuit can generate driving current, the light emitting element emits light in response to the driving current, wherein the driving current generated by the driving transistor is related to the potential of the grid electrode of the driving transistor, and the grid electrode of the driving transistor is connected with the storage capacitor. Due to the characteristics of the driving transistor, in the picture switching process of the display device, the driving transistor is affected by the picture data of the previous frame, so that the display picture cannot be quickly switched to the preset picture, and a flicker phenomenon occurs, which is the first frame response flicker FFR phenomenon. For example, gray images between the black and white images appear before switching from the black image to the white image, and the display effect is affected.

When the driving mode of the conventional pixel circuit switches low frequency, for example, the refresh frequency is 60HZ under the conventional driving, and the conventional pixel circuit is divided into 60 frames, and 60 refresh driving periods are provided in one second. The refresh frequency is reduced at low frequencies, for example 1HZ, and a frame is refreshed one second (one frame has only one refresh drive period).

Specifically, in the first refresh driving period, data is normally written, and in the remaining 59 sustain driving periods, data writing is not performed, and the OLED is continuously lighted by using the data written in the previous frame. In this driving mode, one frame of picture needs to be kept for a long time, and the same picture is kept for a long time, and the threshold voltage is offset to affect the characteristics of the thin film transistor, so that the brightness of the refresh frame is different from the brightness of the hold frame, and a brightness difference recognizable to human eyes is formed, which can be called as a refresh frequency switching flicker VRR phenomenon.

Referring to fig. 1 in detail, the present application provides a pixel driving circuit, which includes a driving transistor T3, a storage capacitor C, a writing sub-circuit 900, a first reset sub-circuit 100, a second reset sub-circuit 200, and a first threshold control sub-circuit 300.

The driving transistor T3 is configured to generate a driving current on a conduction path from the first terminal to the second terminal in response to control of the signal voltage of the control terminal.

The first reset sub-circuit 100 is connected to the second terminal of the driving transistor T3, and is configured to provide the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1.

The second reset sub-circuit 200 is connected to the control terminal of the driving transistor T3, the storage capacitor C, and the first terminal of the first threshold control sub-circuit 300, and is configured to provide the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3.

The writing sub-circuit 900 is connected to the first terminal of the driving transistor T3, and is configured to provide the voltage of the data signal terminal Vdata to the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4.

A second terminal of the first threshold control sub-circuit 300 is connected to the second terminal of the driving transistor T3, and is configured to turn on the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the control of the second scan signal G2.

The voltage of the first reset signal terminal Vinit1 is opposite to the voltage of the second reset signal terminal Vinit 2.

As shown in fig. 2, the pixel driving circuit further includes a light emitting element 800, a first light emitting sub-circuit 500, a second light emitting sub-circuit 600, and a third reset sub-circuit 700.

The first light emitting sub-circuit 500 is connected to a first power supply terminal VDD and a first terminal of the driving transistor T3, and is configured to supply a voltage of the first power supply terminal VDD to the driving transistor T3 in response to control of a light emitting signal EM.

The second light emitting sub-circuit 600 is connected to the second terminal of the driving transistor T3 and the first terminal of the light emitting element 800, and is configured to provide the driving current of the driving transistor T3 to the light emitting element 800 in response to the control of the light emitting signal EM, and the second terminal of the light emitting element 800 is connected to the second power terminal VSS.

The third reset sub-circuit 700 is connected to the second terminal of the second light emitting sub-circuit 600 and the first terminal of the light emitting element 800, and is configured to provide the voltage of the third reset signal terminal Vinit3 to the second terminal of the second light emitting sub-circuit 600 and the first terminal of the light emitting element 800 in response to the control of the first scan signal G1.

In the embodiment of the present application, the light emitting element 800 may be a current driven light emitting device including an LED (Light Emitting Diode ) or an OLED (Organic Light Emitting Diode, organic light emitting diode) in the prior art, and the light emitting element 800 may be a micro LED (Micro Light Emitting Diode). The micro LED is a microminiature inorganic light emitting element 800 of a size of 100 micrometers (μm) or less which emits light without a backlight and a filter. In the following examples, micro-LEDs are used as an example. It should be noted that, the light emitting element 800 may be various types of LEDs, for example, emitting red light, green light, blue light, or white light, which is not limited in the embodiments of the present application.

The "control terminal" refers specifically to the gate of the transistor, the "first terminal" refers specifically to the source of the transistor, and the "second terminal" refers specifically to the drain of the transistor. Of course, it will be appreciated by those skilled in the art that the "first end" and "second end" are interchangeable, i.e., the "first end" refers specifically to the drain of the transistor and the "second end" refers specifically to the source of the transistor.

The first power supply terminal VDD in the embodiment of the present application may be a first voltage for maintaining an input dc high level signal. The second power source terminal VSS may be configured to hold an input dc low level signal, which is referred to as a second voltage, lower than the first voltage. The following embodiments are the same as this and will not be described in detail.

In addition, transistors can be classified into N-type transistors and P-type transistors according to the semiconductor characteristics of the transistors. When the transistor is used as a switching transistor, the N-type switching transistor is controlled by a high-level switching control signal Gate to be turned on, and is controlled by a low-level switching control signal Gate to be turned off. The P-type switching transistor is controlled by a low-level switching control signal Gate to be turned on, and is controlled by a high-level switching control signal Gate to be turned off.

It is noted that the pixel circuits in the embodiments of the present application are applicable to pixel driving circuits of various structures (e.g., 8T1C, 9T1C, 12T1C, 8T2C, or the like). An exemplary description will be made below for the pixel driving circuits of 8T1C, 9T 1C. It will be appreciated that different pixel circuit configurations are selected in different application scenarios.

In the embodiment of the application, the pixel driving circuit adopts an LTPO circuit, namely, the LTPO circuit is prepared by using a low-temperature polysilicon (LTPS) technology and an oxide (IGZO), and the low-temperature polysilicon thin film transistor (Low Temperature Poly Silicon, abbreviated as LTPS) is formed into an active layer by polysilicon deposition. LTPS has the advantages of higher electron mobility, higher reaction speed, high brightness, high resolution, low power consumption and the like.

An oxide thin film transistor (oxide TFT) uses an oxide semiconductor as an active layer of the TFT, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) for example, the oxide semiconductor has higher electron mobility and good turn-off characteristics, and compared with LTPS, the oxide semiconductor has simple manufacturing process and higher compatibility with amorphous silicon manufacturing process.

Of course, the oxide thin film transistor may also be other metal oxide semiconductors, such as Indium Zinc Tin Oxide (IZTO) or Indium Gallium Zinc Tin Oxide (IGZTO), and the like. The size of the transistor can be effectively reduced and leakage current can be prevented by adopting the oxide thin film transistor, so that the resolution of the display substrate can be increased while the pixel circuit can be suitable for low-frequency driving.

In various embodiments of the present application, it is defined that the control terminal of the driving transistor T3 is connected to the storage capacitor C at the first node N1, the first terminal of the driving transistor T3 is connected to the second node N2, and the second terminal of the driving transistor T3 is connected to the third node N3. It should be noted that, in the description of the embodiment of the present application, the first node N1, the second node N2, and the third node N3 do not represent actually existing components, but represent junction points of related circuit connections in the circuit diagram.

In the embodiment of the present application, the active signal (level) refers to a signal (level) for turning on the corresponding switching element, and the inactive signal (level) refers to a signal (level) for turning off the corresponding switching element. Similarly, in other embodiments of the present application, this explanation is made. The active level and the inactive level only represent that the level of the signal has 2 state quantities, and do not represent that the active level or the inactive level has a specific value throughout.

According to the pixel driving circuit provided by the embodiment of the application, the first reset sub-circuit 100 and the second reset sub-circuit 200 are used for resetting the second end and the control end of the driving transistor T3 respectively, so that when the bias state of the driving transistor T3 is regulated before picture switching, the bias state of the driving transistor T3 can be regulated to be in a negative bias state or a positive bias state, the driving transistor T3 is not influenced by the picture data of the previous frame, and the picture is quickly switched to a preset switching picture, thereby being beneficial to improving the flicker phenomenon in the picture switching process and improving the display effect. Before the light-emitting stage, the first reset sub-circuit 100 starts the driving transistor T3 to enter the light-emitting stage from the on state of the fixed bias, so that the recovery process of the threshold voltage of the driving transistor T3 in the holding driving period T200 and the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period T100 tend to be consistent, the brightness difference between the refresh driving period T100 and the holding driving period T200 is reduced, and the VRR is improved.

In the embodiments of the present application, an exemplary description is given of adjustment for a negative bias state of a transistor. In the embodiment of the application, the exemplary 8T1C circuit comprises 8 thin film transistors (T1-T8), wherein T2 and T5 are N-type thin film transistors NMOS and adopt oxide TFTs; the rest is a P-type thin film transistor PMOS, and adopts an LTPS TFT. An exemplary 9T1C circuit includes 8 thin film transistors (T1-T9), where T9 is an N-type thin film transistor NMOS, using oxide TFTs; the rest is a P-type thin film transistor PMOS, and adopts an LTPS TFT.

Example 1

In this embodiment of the present application, the pixel driving circuit employs 8T1C, as shown in fig. 3, the first reset sub-circuit 100 includes a first transistor T1, a first end of the first transistor T1 is connected to the first reset signal end Vinit1, a second end of the first transistor T1 is electrically connected to a second end of the driving transistor T3 at a third node N3, and a control end of the first transistor T1 is connected to a first scan line that provides the first scan signal G1.

The second reset sub-circuit 200 includes a fifth transistor T5, a first end of the fifth transistor T5 is connected to the second reset signal terminal Vinit2, a second end of the fifth transistor T5 is electrically connected to the control terminal of the driving transistor T3 at the first node N1 and the storage capacitor C, and a control terminal of the fifth transistor T5 is connected to a third scan line providing the third scan signal G3.

The writing sub-circuit 900 includes a fourth transistor T4, a first end of the fourth transistor T4 is connected to the data signal terminal Vdata, a second end of the fourth transistor T4 is electrically connected to the first end of the driving transistor T3 at a second node N2, and a control end of the fourth transistor T4 is connected to a fourth scan line providing the fourth scan signal G4.

The first threshold control sub-circuit 300 includes a second transistor T2, a first end of the second transistor T2 is electrically connected to the control end of the driving transistor T3 at a first node N1 and the storage capacitor C, a second end of the second transistor T2 is electrically connected to the second end of the driving transistor T3 at a third node N3, and a control end of the second transistor T2 is connected to a second scan line providing the second scan signal G2.

The first light emitting sub-circuit 500 includes a seventh transistor T7, a first end of the seventh transistor T7 is connected to the first power supply terminal VDD, a second end of the seventh transistor T7 is electrically connected to the first end of the driving transistor T3 at a second node N2, and a control end of the seventh transistor T7 is connected to a light emitting control line that provides a light emitting signal EM.

The second light emitting sub-circuit 600 includes an eighth transistor T8, a first end of the eighth transistor T8 is electrically connected to a second end of the driving transistor T3 at a third node N3, a second end of the eighth transistor T8 is connected to the first end of the light emitting element 800, and a control end of the eighth transistor T8 is connected to the light emitting control line.

The third reset sub-circuit 700 includes a sixth transistor T6, a first end of the sixth transistor T6 is connected to the first end of the light emitting element 800, a second end of the sixth transistor T6 is connected to the third reset signal end Vinit3, and a control end of the sixth transistor T6 is connected to the first scan line.

In this embodiment, the N-type thin film transistors NMOS are T2 and T5, and the P-type thin film transistors PMOS are the rest, where the voltage of the first reset signal terminal Vinit1 is positive, the voltage of the second reset signal terminal Vinit2 is negative, the voltage of the third reset signal terminal Vinit3 is negative, the voltage value of the first reset signal terminal Vinit1 is greater than the voltage value of the second signal terminal, i.e., |vinit1| > |vinit2|, and by this arrangement, a large negative bias is formed between the first node N1 and the third node N3 in the reset process of the driving transistor T3, which accelerates the capturing of carriers on the gate of the driving transistor T3, and eliminates the influence of the previous frame of display.

The voltages of Vinit2 and Vinit3 may be the same or different. Vinit2 is responsible for resetting the control end of the driving transistor T3, vinit3 is responsible for resetting the anode of the light emitting element 800, and the advantage is that the two processes are not interfered with each other, vinit3 for resetting the anode of the light emitting element 800 can reset at a lower voltage, eliminating positive charges, and is more beneficial for prolonging the service life.

The application provides a driving method of a pixel driving circuit, as shown in fig. 4-10, which is applied to the pixel driving circuit described in any one of the above, wherein a refresh driving period t100 of the driving method includes a first reset phase t110, a write phase t120, a first bias phase t130, and a first light-emitting phase t140.

In the first reset phase T110, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1.

Specifically, the first reset phase t110 includes a first reset sub-phase t101, a second reset sub-phase t102, and a third reset sub-phase t103:

in the first reset sub-stage T101, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub-circuit 300 turns on the connection of the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 4 and 10.

In the first reset sub-stage T101, the first scan signal G1 is at a low level, the first transistor T1 is turned on, the second scan signal G2 is at a high level, and the second transistor T2 is turned on; the third scan signal G3 is low, and the fifth transistor T5 is turned off; the fourth scan signal G4 and the light emitting signal EM are at high level, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off; the control terminal of the sixth transistor T6 multiplexes the first scan signal G1, the first scan signal G1 is at a low level, and the sixth transistor T6 is turned on. At this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the control terminal of the driving transistor T3 through the first transistor T1 and the second transistor T2, and the control terminal of the driving transistor T3 is reset until the driving transistor T3 is turned off. At this stage, the voltage at the first node N1 is Vinit1, the voltage at the second node N2 is Vinit1-Vth, the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the drive transistor T3, and for the PMOS drive transistor T3, vth <0.

In the second reset sub-stage T102, the second reset sub-circuit 200 supplies the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3. The first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 5 and 10.

In the second reset sub-stage T102, the third scan signal G3 is at a high level, and the fifth transistor T5 is turned on; the second scan signal G2 is low, and the second transistor T2 is turned off; the first, fourth and emission signals G1, G4 and EM are at high level, the first, fourth, sixth, seventh and eighth transistors T1, T4, T6, T7 and T8 are turned off, and the voltage of the second reset signal terminal Vinit2 is applied to the second terminal of the driving transistor T3 through the fifth transistor T5; at this stage, the driving transistor T3 is turned on, the control terminal of the driving transistor T3 is connected to the storage capacitor C, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1.

In the second reset sub-stage T102, a large negative bias is formed between the N1-N3 nodes of the driving transistor T3, which accelerates capturing of the gate capturing carriers, so that the driving transistor T3 is not affected by the previous frame of picture data, and still generates a driving current corresponding to the preset switching picture, so that the picture is rapidly switched to the preset switching picture, thereby being beneficial to improving the FFR flicker phenomenon occurring in the picture switching process and improving the display effect. In the second reset sub-phase T102, the driving transistor T3 is turned on, the deep negative bias on the driving transistor T3 causes the release of saturated carriers within the frame, which causes the threshold shift and brightness change of the driving transistor T3, and the improvement of VRR is not obvious.

In the third reset sub-stage T103, the second reset sub-circuit 200 supplies the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3. The first threshold control sub-circuit 300 turns on the connection of the second terminal of the driving transistor T3 and the control terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 6 and 10.

In the third reset sub-stage T103, the second scan signal G2 and the third scan signal G3 are at a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the first, fourth and emission signals G1, G4 and EM are at high level, and the first, fourth, sixth, seventh and eighth transistors T1, T4, T6, T7 and T8 are turned off. At this stage, the voltage of the second reset signal terminal Vinit2 is applied to the control terminal of the driving transistor T3 through the fifth transistor T5 and the second transistor T2, the gate of the driving transistor T3 is reset, the driving transistor T3 is turned on under the control of the voltage of the second reset signal terminal Vinit2, and the voltage of the first reset signal terminal Vinit1 is applied to the first terminal and the second terminal of the driving transistor T3 through the fifth transistor T5. At this stage, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit2-Vth, and the voltage at the third node N3 is Vinit2, where Vth is the threshold voltage of the driving transistor T3.

In this stage, due to the large negative bias voltage of the driving transistor T3 between the gate and the source in the second reset sub-stage T102, the threshold voltage of the driving transistor T3 shifts to a certain extent, in this embodiment, the first reset sub-stage T101N1/N2/N3 is positive, the third reset sub-stage T103N1/N2/N3 becomes negative, and the driving transistor T3 is charged and discharged for multiple times in the first reset stage T110, so that voltage inversion is realized for three nodes of the driving transistor T3 at least once, and the light emission control line is not turned on during this process, so that the light emission is performed after the driving transistor T3 is stabilized, thereby improving the drift and hysteresis characteristics of the driving transistor T3 and improving the short-term afterimage problem.

In other embodiments of the present application, in order to increase the state of the large bias negative voltage formed between the gate and the source of the driving transistor T3 in the second reset sub-stage T102, in this embodiment, the first reset stage T110 further includes a reset maintaining sub-stage tt102 located between the first reset sub-stage T101 and the second reset sub-stage T102, as shown in fig. 7 and 10.

In the reset maintaining sub-stage tt102, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1; the first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2.

In this stage, the first scan signal G1 is at a low level, the first transistor T1 is turned on, the second scan signal G2 and the third scan signal G3 are at a low level, and the second transistor T2 and the fifth transistor T5 are turned off; the fourth scan signal G4 and the light emitting signal EM are at high level, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off; the control terminal of the sixth transistor T6 multiplexes the first scan signal G1, the first scan signal G1 is at a low level, and the sixth transistor T6 is turned on. At this stage, the driving transistor T3 is turned on, and the first and second terminals of the driving transistor T3 are reset by the first scan signal G1. The voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1.

The positive voltage charging of the first reset sub-circuit 100 to the second node N2 and the third node N3 in the reset maintaining sub-stage tt102 maintains the large bias negative voltage formed between the gate and the source by the driving transistor T3 in the second reset sub-stage T102, further eliminates the influence of the previous frame of picture data, and makes the picture rapidly switched to the preset switching picture, thereby being beneficial to improving the FFR flicker phenomenon occurring in the picture switching process and improving the display effect.

In the writing phase T120, the writing sub-circuit 900 supplies the voltage of the data signal terminal Vdata to the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub-circuit 300 turns on the connection of the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 8 and 10.

In the writing stage T120, the fourth scan signal G4 is at a low level, the fourth transistor T4 is turned on, the second scan signal G2 is at a high level, and the second transistor T2 is turned on; the third scan signal G3 is low, and the fifth transistor T5 is turned off; the first scan signal G1 and the light emitting signal EM are at a high level, and the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. At this stage, the driving transistor T3 is turned on, and the voltage of the data signal terminal Vdata is applied to the control terminal of the driving transistor T3 through the fourth transistor T4 and the second transistor T2, so that writing of the data signal is realized, and voltage compensation of the control terminal of the driving transistor T3 is realized. At this stage, the voltage at the first node N1 is vdata+vth, the voltage at the second node N2 is Vdata, and the voltage at the third node N3 is Vdata, where Vth is the threshold voltage of the driving transistor T3.

In the first bias stage T130, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 9 and 10.

In the first bias stage T130, the first scan signal G1 is at a low level, the first transistor T1 and the sixth transistor T6 are turned on, the second scan signal G2 is at a low level, and the second transistor T2 is turned off; the third scan signal G3 is low, and the fifth transistor T5 is turned off; the fourth scan signal G4 and the light emitting signal EM are at high level, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off. At this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the second and third terminals of the driving transistor T3 through the first transistor T1. At this stage, the voltage at the first node N1 is vdata+vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3.

At this stage, the first transistor T1 resets the second node N2 and the third node N3 to a high voltage, which is equivalent to applying a negative bias to the gate-source of the driving transistor T3, so that the recovery process of the threshold voltage of the driving transistor T3 is changed again during the light emitting stage.

In the first light emitting period T140, the light emitting element 800 emits light in response to the driving current of the driving transistor T3. The light emitting signal EM is low level, the seventh transistor T7 and the eighth transistor T8 are turned on at the low level, and the driving transistor T3 is turned on; the other transistors are all in an off state under the control of corresponding switch control signals.

The driving transistor T3DN is operated in a saturated state, and as can be seen from the saturated state current characteristics, the saturated current I flowing through the driving transistor T3DN for driving the light emitting element 80030 to emit light satisfies the formula:

I＝1/2*μ*Cox*W/L*(Vgs-Vth)^2

＝K(Vdata+Vth-VDD–Vth)^2

＝K(Vdata-VDD)^2

wherein K is a structural parameter, and the value is relatively stable in the same structure and can be calculated as a constant.

Where K is a structural parameter, and the value is relatively stable in the same structure and can be calculated as a constant. Thus, it can be seen that the working current of the light emitting element 800 is not affected by the threshold voltage Vth of the driving transistor T3DN, so that the problem of low Flicker (Flicker) and the like is effectively solved, and the non-uniformity of the panel display is improved.

As shown in fig. 11, the sustain drive period t200 of the driving method includes a second reset phase t210, a sustain phase t220, a second bias phase t230, and a second light emitting phase t240.

In the second reset phase T210, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1.

In the holding period T220, the write sub-circuit 900 disconnects the write sub-circuit 900 from the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4. The hold period t220 corresponds to the write period t120 in the refresh drive period t100, in which no data signal voltage is written.

It can be understood that the voltage signal is written into the control terminal of the driving transistor T3 during the light emitting phase of the refresh driving period T100; since no data signal is written in the sustain drive period T200, both before and during the light emission thereof are voltages written to the control terminal of the driving transistor T3 in the write period T120 of the refresh drive period T100, so as to realize control of the driving current in the light emission period in the sustain drive period.

In the second bias stage T230, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2.

In the second light emitting period T240, the light emitting element 800 emits light in response to the driving current of the driving transistor T3.

In the present embodiment, the driving timing of the first scan signal G1 in the sustain driving period t200 is the same as that of the first scan signal G1 in the refresh driving period t100, and the driving timings of the remaining scan signals in the sustain driving period t200 are such that the responsive transistors can be kept off at respective stages of the sustain driving period t 200.

In this embodiment of the present application, the pixel driving circuit is in a fixed bias on state by the first bias stage T130 of the refresh driving period T100 and the second bias stage T230 of the retention driving period T200, so that no matter whether the data signal of the previous frame is a black state or a white state signal, the driving transistor T3 starts to enter the light-emitting stage from the fixed bias on state, so that the recovery process of the threshold voltage of the driving transistor T3 in the retention driving period T200 and the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period T100 tend to be consistent, the brightness difference between the refresh driving period T100 and the retention driving period T200 is reduced, and the VRR is improved.

In the embodiment of the present application, the anode potential of the light emitting element 800EL is set to be reset by the third reset sub-circuit 700 multiple times in the reset stage, so as to control the light emitting element 800EL not to emit light, and avoid the influence of the charges remained on the anode of the light emitting element 800 on the light emitting brightness.

Example two

In this embodiment, the pixel driving circuit adopts 8T1C, optimizes the arrangement mode of the scanning signal lines based on the first embodiment, reduces GOAs based on driving each gate control signal by using 5 groups of GOAs (Gate Driver on Array, array substrate row driving) in the second embodiment, and uses 4 groups of GOAs to realize the control of the pixel driving circuit in this embodiment by using the second scanning signal G2 and the fourth scanning signal G4 to share the same scanning line, i.e. the driving timings of the second scanning signal G2 and the fourth scanning signal G4 are the same. Through the technical scheme in the embodiment of the application, GOA space and pixel space can be saved, power consumption of GOA can be reduced, and the method is suitable for products with narrow frames and high pixel density.

In this embodiment, as shown in fig. 12-14, the refresh driving period t100 of the driving method includes a first reset phase t110, a writing phase t120, a first bias phase t130, and a first light-emitting phase t140.

In this embodiment, the first reset phase t110 includes a first reset sub-phase t111 and a second reset sub-phase t112. Specifically:

In the first reset sub-stage T111, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 12 and 14.

In the first reset sub-stage T111, the second transistor T2 is turned off, and the second node N2 and the third node N3 of the driving transistor T3 are reset by the first reset sub-circuit 100, so that the voltages of the second node N2 and the third node N3 are reset to Vinit1.

In the second reset sub-stage T112, the second reset sub-circuit 200 supplies the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3. The first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 13 and 14.

In the second reset sub-stage T112, the second transistor T2 is turned off, and the first node N1 of the driving transistor T3 is reset by the second reset sub-circuit 200, so that the voltage of the first node N1 is reset to Vinit2. By forming a negative bias between the gate and source of the driving transistor T3 in the first reset period T110, FFR can be effectively improved. It can be understood that, in the present embodiment, since the larger negative bias voltage of the gate-source of the driving transistor T3 in the first embodiment is not formed, the effect of improving the FFR in the present embodiment is significantly weaker than that in the second embodiment, but the FFR can be greatly improved and the display effect can be improved as compared with the scheme in the prior art.

In the writing phase T120, the writing sub-circuit 900 supplies the voltage of the data signal terminal Vdata to the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub-circuit 300 turns on the connection of the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 8 and 14.

In the first bias stage T130, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 9 and 14.

In the first light emitting period T140, the light emitting element 800 emits light in response to the driving current of the driving transistor T3.

Alternatively, as shown in fig. 15, the sustain drive period t200 of the driving method includes a second reset phase t210, a sustain phase t220, a second bias phase t230, a second light emitting phase t240,

In the holding period T220, the write sub-circuit 900 disconnects the write sub-circuit 900 from the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4.

In the present embodiment, the timing of the first scan signal G1 in the retention driving period t200 is the same as the timing of the first scan signal G1 in the refresh driving period t100, and the driving timings of the remaining scan signals in the retention driving period t200 are such that the responsive transistors can be kept off at each stage of the retention driving period t 200. Through the second bias stage T230, the recovery process of the threshold voltage of the driving transistor T3 in the retention driving period T200 and the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period T100 tend to be consistent, the brightness difference between the refresh driving period T100 and the retention driving period T200 is reduced, and the VRR is improved.

It can be understood that, in this embodiment, since a large negative bias is not formed between the gate and the source of the driving transistor T3 in the refresh driving period T100, the shift of the threshold voltage in the refresh driving period T100 is mainly determined by the positive bias voltage on the N2 and N3 of the driving transistor T3, so that the N2 and N3 of the driving transistor T3 are positively biased by the first reset sub-circuit 100 in both the holding driving period T200 and the refresh driving period T100, so that the threshold voltage drift conditions of the driving transistor T3 in the holding driving period T200 and the refresh driving period T100 are substantially consistent, and the recovery process of the threshold voltage of the driving transistor T3 also tends to be consistent, so that the brightness difference between the holding driving period T200 and the holding driving period T100 is small, and the VRR improvement is obvious.

Example III

In the embodiment of the application, the pixel driving circuit adopts 9T1C. On the basis of the first embodiment, the pixel driving circuit further includes a second threshold control sub-circuit 400, as shown in fig. 16, a first end of the second threshold control sub-circuit 400 is connected to the storage capacitor C and the control end of the driving transistor T3, and a second end of the second threshold control sub-circuit 400 is connected to the second reset sub-circuit 200; the second threshold control sub-circuit 400 is configured to switch on and off the connection of the control terminal of the driving transistor T3 and the first threshold control sub-circuit 300 in response to the control of the fifth scan signal G5.

Specifically, the second threshold control sub-circuit 400 includes a ninth transistor T9, a first terminal of the ninth transistor T9 is electrically connected to the control terminal of the driving transistor T3 at a first node N1 and the storage capacitor C, a second terminal of the ninth transistor T9 is connected to the first terminal of the second transistor T2, and a control terminal of the ninth transistor T9 is connected to a fifth scan line providing a fifth scan signal G5.

In this embodiment, the T9 is an N-type thin film transistor NMOS, and the rest are P-type thin film transistors PMOS.

In this embodiment of the present application, the driving transistor T3 is a P-type transistor, and because the leakage current of the P-type transistor is relatively large, a phenomenon such as a splash screen (Flicker) is generated by using low-frequency driving, thereby restricting the use of the pixel circuit. The leakage condition of the first node N1 can be further reduced by adding the ninth transistor T9 in the pixel circuit in this embodiment. For a specific driving manner, reference may be made to a description of an 8T1C driving method, which is not repeated herein.

In the first embodiment, 5 groups of GOAs are used to drive the gate control signals, and the ninth transistor is added in the first embodiment, so that 6 groups of GOAs are normally needed to drive the pixel driving circuit. In order to optimize the arrangement manner of the scan signal lines, in this embodiment, the second scan signal G2 and the fourth scan signal G4 share the same scan line, and the first scan signal G1 and the third scan signal G3 share the same scan line, that is, the driving timings of the second scan signal G2 and the fourth scan signal G4 are the same, and the driving timings of the first scan signal G1 and the third scan signal G3 are the same. The control of the pixel driving circuit in the embodiment is realized by adopting 4 groups of GOAs, the GOA space and the pixel space can be saved by the technical scheme in the embodiment of the application, the power consumption of the GOA can be reduced, and the method is suitable for products with narrow frames and high pixel density.

In this embodiment, as shown in fig. 17-18, the refresh driving period t100 of the driving method includes a first reset phase t110, a writing phase t120, a first bias phase t130, a first light-emitting phase t140,

in the first reset phase T110, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1. The second reset sub-circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3, and the first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2.

In this embodiment, positive voltage reset is implemented on the second node N2 and the third node N3 of the driving transistor T3 by the first reset sub-circuit 100, negative voltage reset is implemented on the first node N1 of the driving transistor T3 by the second reset sub-circuit 200, and a larger negative bias voltage is formed between the gate and the source of the driving transistor T3, so that the FFR of the refresh driving period T100 can be significantly improved.

In the writing phase T120, the writing sub-circuit 900 supplies the voltage of the data signal terminal Vdata to the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub-circuit 300 turns on the connection of the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 8 and 18.

In the first bias stage T130, the first reset sub-circuit 100 supplies the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub-circuit 300 disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3 in response to the second scan signal G2, as shown in fig. 9 and 18.

Alternatively, as shown in fig. 19, the sustain drive period t200 of the driving method includes a second reset phase t210, a sustain phase t220, a second bias phase t230, a second light emitting phase t240,

In the present embodiment, the driving timing of the first scan signal G1 in the sustain driving period t200 is the same as that of the first scan signal G1 in the refresh driving period t100, and the driving timings of the remaining scan signals in the sustain driving period t200 are such that the responsive transistors can be kept off at respective stages of the sustain driving period t 200. In the second reset phase T210 of the hold driving period T200, the ninth transistor T9 remains turned off, and the N2 and N3 nodes are reset only by the first reset sub-circuit 100, and the N1 node cannot be reset by the second reset sub-circuit 200.

Through the first bias stage T130 and the second bias stage T230, positive-voltage reset is realized on the second node N2 and the third node N3 of the driving transistor T3 through the first reset sub-circuit 100, so that the recovery processes of the threshold voltages of the driving transistor T3 in the refresh driving period T100 and the holding driving period T200 tend to be consistent, the brightness difference between the refresh driving period T100 and the holding driving period T200 can be reduced, and the improvement of the VRR can be realized.

It can be appreciated that in the present embodiment, a larger negative bias is formed between the gate and the source of the driving transistor T3 in the refresh driving period T100, which effectively improves FFR, but causes a certain shift to the threshold voltage of the driving transistor T3. However, the high level is only applied to the second node N2 and the third node N3 of the driving transistor T3 in the holding driving period T200, and there is no process of resetting the N1 point in the holding driving period T200, and only the process of voltage bias Vinit1 is performed, so that the improvement effect on the VRR is weaker only through the first bias stage T130 and the second bias stage T230 compared with the scheme of the second embodiment, but the improvement effect on the VRR is stronger compared with the prior art, and meanwhile, the improvement effect on the VRR is also realized.

Based on the same inventive concept, the present application provides a display panel comprising a pixel driving circuit as described in any one of the above. The display panel can be applied to: OLED display device, AMOLED display device, cell-phone, tablet computer, TV set, display, notebook computer, digital photo frame, navigator etc. any product or part that has the display function.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the invention. Terms such as "disposed" or the like as used herein may refer to either one element being directly attached to another element or one element being attached to another element through an intermediate member. Features described herein in one embodiment may be applied to another embodiment alone or in combination with other features unless the features are not applicable or otherwise indicated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. Those skilled in the art will appreciate that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed.

Claims

1. A pixel driving circuit is characterized by comprising a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit and a first threshold control sub-circuit,

2. The pixel driving circuit according to claim 1, further comprising a light emitting element, a first light emitting sub-circuit, a second light emitting sub-circuit, and a third reset sub-circuit, wherein,

3. The pixel driving circuit according to claim 2, wherein the first reset sub-circuit comprises a first transistor, a first terminal of the first transistor is connected to the first reset signal terminal, a second terminal of the first transistor is connected to the second terminal of the driving transistor, and a control terminal of the first transistor is connected to a first scan line that supplies the first scan signal;

4. A pixel driving circuit according to claim 3, wherein the first light emitting sub-circuit comprises a seventh transistor, a first terminal of the seventh transistor being connected to the first power supply terminal, a second terminal of the seventh transistor being connected to the first terminal of the driving transistor, a control terminal of the seventh transistor being connected to a light emission control line providing a light emission signal;

5. A pixel driving circuit according to claim 3, further comprising a second threshold control sub-circuit, a first terminal of the second threshold control sub-circuit being connected to the storage capacitor, a control terminal of the driving transistor, a second terminal of the second threshold control sub-circuit being connected to the second reset sub-circuit;

6. The pixel driving circuit according to claim 5, wherein the second threshold control sub-circuit includes a ninth transistor, a first terminal of the ninth transistor being connected to the control terminal of the driving transistor and the storage capacitor, a second terminal of the ninth transistor being connected to the first terminal of the second transistor, and a control terminal of the ninth transistor being connected to a fifth scan line that supplies a fifth scan signal.

7. The pixel driving circuit according to claim 1, wherein the first scan signal and the third scan signal share the same scan line, and/or the second scan signal and the fourth scan signal share the same scan line.

8. A driving method of a pixel driving circuit, characterized in that it is applied to the pixel driving circuit according to any one of claims 1 to 7, wherein a refresh driving period of the driving method comprises a first reset phase, a writing phase, a first bias phase, a first light-emitting phase,

9. The method for driving a pixel driving circuit according to claim 8, wherein,

the hold driving period of the driving method includes a second reset phase, a hold phase, a second bias phase, a second light emitting phase,

10. The method of driving a pixel driving circuit according to claim 8, wherein the first reset phase includes a first reset sub-phase, a second reset sub-phase, and a third reset sub-phase:

11. The method for driving a pixel driving circuit according to claim 8, wherein,

the first reset phase further includes a reset maintenance sub-phase located between the first reset sub-phase and the second reset sub-phase,

12. The method of driving a pixel driving circuit according to claim 8, wherein the first reset phase comprises a first reset sub-phase, a second reset sub-phase,

13. The driving method of the pixel driving circuit according to claim 8, wherein the refresh driving period of the driving method further comprises:

14. A display panel comprising a pixel driving circuit as claimed in any one of claims 1 to 7.