CN116384496A

CN116384496A - Quantum chip structure and layout generation method thereof

Info

Publication number: CN116384496A
Application number: CN202310332600.7A
Authority: CN
Inventors: 陈俣翱; 晋力京
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-07-04

Abstract

The disclosure provides a quantum chip structure and a layout generation method of the quantum chip structure, relates to the technical field of computers, and particularly relates to the field of quantum computing. The scheme is as follows: a plurality of twisted square units are densely paved to form a topological structure; the central quantum bit of the twisted square unit is respectively coupled with the five first quantum bits; among the five first qubits: the first qubit of the first azimuth is coupled with the first qubit of the second azimuth, and the first qubit of the third azimuth is coupled with the first qubit of the fourth azimuth and the adjacent first qubit of the fifth azimuth respectively; among the two second qubits: the second qubit of the sixth azimuth is coupled with the first qubit of the first azimuth and the first qubit of the fourth azimuth, respectively, and the second qubit of the seventh azimuth is coupled with the first qubit of the second azimuth and the first qubit of the fifth azimuth, respectively. According to the technology of the present disclosure, a quantum chip with high connectivity can be obtained.

Description

Quantum chip structure and layout generation method thereof

Technical Field

The present disclosure relates to the field of computer technology, and in particular to the field of quantum computing.

Background

There are many factors for measuring the performance of the quantum chip, and connectivity is one of the key indexes. Therefore, how to design superconducting quantum chips with high connectivity from the quantum hardware level becomes a very important problem.

Disclosure of Invention

The present disclosure provides a quantum chip structure and a layout generation method of the quantum chip structure.

According to an aspect of the present disclosure, there is provided a quantum chip structure including:

a topology formed by closely laying a plurality of twisted square units; each twisted square unit comprises a central quantum bit, five first quantum bits adjacent to the central quantum bit and two second quantum bits not adjacent to the central quantum bit; the central qubit is respectively coupled with the five first qubits; wherein,,

among the five first qubits: the first qubit of the first azimuth is coupled with the first qubit of the adjacent second azimuth, and the first qubit of the third azimuth is coupled with the first qubit of the adjacent fourth azimuth and the first qubit of the adjacent fifth azimuth respectively;

among the two second qubits: the second qubit of the sixth orientation is coupled with the first qubit of the adjacent first orientation and the first qubit of the adjacent fourth orientation, respectively, and the second qubit of the seventh orientation is coupled with the first qubit of the adjacent second orientation and the first qubit of the adjacent fifth orientation, respectively.

According to another aspect of the present disclosure, there is provided a layout generation method of a quantum chip structure, including:

constructing a first topological pattern;

determining a second topological pattern from the first topological pattern according to the number of preset qubits, wherein the first topological pattern and the second topological pattern are formed by closely paving a plurality of twisted square patterns;

generating a layout according to the second topological pattern, wherein the layout is used for manufacturing the quantum chip structure of any embodiment of the disclosure; wherein,,

each twisted square pattern comprises a central quantum node identifier, five first quantum node identifiers adjacent to the central quantum node identifier and two second quantum node identifiers not adjacent to the central quantum node identifier; the central quantum node identifiers are respectively coupled with the five first quantum node identifiers;

among the five first quantum node identifications: the first quantum node identifier of the first azimuth is coupled with the first quantum node identifier of the adjacent second azimuth, and the first quantum node identifier of the third azimuth is coupled with the first quantum node identifier of the adjacent fourth azimuth and the first quantum node identifier of the adjacent fifth azimuth respectively;

among the two second quantum node identities: the second quantum node identifier of the sixth azimuth is respectively coupled with the first quantum node identifier of the adjacent first azimuth and the first quantum node identifier of the adjacent fourth azimuth, and the second quantum node identifier of the seventh azimuth is respectively coupled with the first quantum node identifier of the adjacent second azimuth and the first quantum node identifier of the adjacent fifth azimuth.

According to another aspect of the present disclosure, there is provided a method of manufacturing a quantum chip, including:

and manufacturing the quantum chip structure of any embodiment of the disclosure by using the layout generated by the layout generation method of the quantum chip structure of any embodiment of the disclosure.

According to another aspect of the present disclosure, there is provided a layout generating device of a quantum chip structure, including:

a building module for building a first topological pattern;

the determining module is used for determining a second topological pattern from the first topological pattern according to the number of preset qubits, and the first topological pattern and the second topological pattern are formed by closely paving a plurality of twisted square patterns;

the generation module is used for generating a layout according to the second topological pattern, and the layout is used for manufacturing the quantum chip structure of any embodiment of the disclosure; wherein,,

According to another aspect of the present disclosure, there is provided a manufacturing apparatus of a quantum chip, including:

and the manufacturing module is used for manufacturing the quantum chip structure of any embodiment of the disclosure by utilizing the layout generated by the layout generation method of the quantum chip structure of any embodiment of the disclosure.

According to another aspect of the present disclosure, there is provided an electronic device including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the embodiments of the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform a method according to any one of the embodiments of the present disclosure.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method according to any of the embodiments of the present disclosure.

According to the technology of the present disclosure, a quantum chip with high connectivity can be obtained.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of a quantum chip structure according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a quantum chip structure according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of twisted square cells of a quantum chip structure according to an embodiment of the present disclosure;

FIG. 4a is a schematic diagram of a structure of a qubit according to an embodiment of the disclosure;

fig. 4b is a schematic diagram of a qubit and coupler structure according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 15 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 16 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 17 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 18 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 19 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 20 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 21 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 22 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 23 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 24 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 25 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 26 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 27 is a schematic diagram of a quantum chip structure according to another embodiment of the present disclosure;

FIG. 28 is a schematic diagram of a chip topology of a 54 qubit rectangular oblique square tiling network;

FIG. 29 is a schematic diagram of a chip topology of an 80 qubit rectangular regular octagon-regular quadrilateral tiling network;

FIG. 30 is a schematic diagram of a chip topology of a 127 qubit rectangular regular hexagonal tiling network;

FIG. 31 is a schematic diagram of a layout generation method of a quantum chip structure according to an embodiment of the present disclosure;

FIG. 32 is a schematic diagram of a first topological pattern and a second topological pattern according to an embodiment of the present disclosure;

FIG. 33 is a schematic view of a twisted square pattern according to an embodiment of the present disclosure;

FIG. 34 is a schematic diagram of a layout generating device of a quantum chip structure according to an embodiment of the present disclosure;

fig. 35 is a block diagram of an electronic device used to implement the methods of embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Quantum computing has become an important direction of research and development in academia and industry in recent years. Quantum computing presents significant advantages over traditional computing in solving problems such as large-number decomposition, and is also of great significance to leading-edge research such as quantum multi-body systems, quantum chemical simulations, and the like. In hardware implementation, quantum computing has various technical schemes, such as superconducting quantum circuits, ion traps, optical quanta, and the like. Superconducting quantum circuits are considered as the most promising candidates for quantum computing hardware in the industry, benefiting from the advantages of long decoherence time, easiness in handling and reading, strong expandability and the like. Therefore, as a key part of superconducting quantum computation (i.e., quantum computation performed by using a superconducting circuit quantum chip), the design, development and preparation of a superconducting quantum chip integrating a plurality of superconducting qubits are very important.

In practical application, there are many factors for measuring performance of a quantum chip (such as a superconducting circuit quantum chip), and connectivity is one of the key indexes. Here, connectivity refers to the degree of connectivity between one qubit and the remaining other qubits in a quantum chip (such as a superconducting circuit quantum chip). Taking a superconducting quantum chip as an example, unlike ion trap quantum computation, superconducting qubits can only be coupled with adjacent superconducting qubits in a superconducting quantum circuit. With this limitation, two superconducting qubit gates are also limited to implementations between adjacent superconducting qubits. However, in practice, coupling between non-adjacent superconducting qubits is required in order to achieve quantum gate operation between any two superconducting qubits. Based on this, mapping an algorithm-level quantum circuit (i.e., a logic quantum circuit) to a physical-level physical quantum circuit satisfying physical limitations of a superconducting quantum chip becomes an important subject. Although this mapping solves the problem to some extent, it comes at the cost of requiring the additional introduction of a large number of two-bit quantum gates (i.e., two superconducting quantum bit gates), undoubtedly greatly reducing the efficiency and accuracy of the computation. Thus, how to design superconducting quantum chips with as high connectivity as possible from the quantum hardware level becomes a very important issue.

Embodiments of the present disclosure provide a quantum chip structure including a topology 200 formed by a plurality of twisted square cells 100 being densely packed.

Fig. 1 and 2 illustrate a topology 200 of an embodiment of the present disclosure. Each dot-shaped icon in fig. 1 and 2 can be understood as a qubit of a quantum chip structure, and a line between dot-shaped icons indicates that the two qubits can be directly or indirectly coupled. The twisted square unit 100 may be understood as a shape composed of a triangle structure-a quadrangle structure-a triangle structure-a quadrangle structure connected end to end, and any one of the areas satisfying the shape in fig. 1 may be regarded as the twisted square unit 100.

For ease of understanding, further explanation is based on fig. 2. The light gray shaped area outlined by the dashed box in fig. 2 can be understood as a twisted square cell 100. The respective light gray shaped areas, which are exemplarily shown in fig. 2 and have the same shape as the twisted square cells 100 in the dotted line frame, can be understood as one twisted square cell 100. The dark gray area in fig. 2 may be understood as a superposition of two twisted square units 100, for example, a superposition of a twisted square unit 100 outlined by a dashed-line frame in the upper right corner in fig. 2 and a twisted square unit 100 outlined by a dashed-line frame exists, and a non-superposition of the two is a light gray area, and a superposition of the two is a dark gray area.

As shown in fig. 3, each of the plurality of twisted square units 100 includes a central qubit Qi, five first qubits adjacent to the central qubit Qi, and two second qubits not adjacent to the central qubit Qi. The central qubit Qi is coupled to five first qubits, respectively.

The five first qubits include: a first qubit Q1 in a first orientation, a first qubit Q2 in a second orientation, a first qubit Q3 in a third orientation, a first qubit Q4 in a fourth orientation, and a first qubit Q5 in a fifth orientation. Wherein the first qubit Q1 of the first azimuth is coupled with the first qubit Q2 of the adjacent second azimuth, and the first qubit Q3 of the third azimuth is coupled with the first qubit Q4 of the adjacent fourth azimuth and the first qubit Q5 of the adjacent fifth azimuth, respectively.

The two second qubits include: a second qubit Q6 in a sixth orientation and a second qubit Q7 in a seventh orientation. Wherein the second qubit Q6 of the sixth azimuth is coupled with the first qubit Q1 of the adjacent first azimuth and the first qubit Q4 of the adjacent fourth azimuth, and the second qubit Q7 of the seventh azimuth is coupled with the first qubit Q2 of the adjacent second azimuth and the first qubit Q5 of the adjacent fifth azimuth, respectively.

According to the embodiment of the disclosure, it is to be noted that:

any one qubit in the topology 200 can be considered as one central qubit Qi as long as it satisfies the condition that there are five first qubits adjacent and two second qubits not adjacent. The twisted square structure formed by coupling any one central qubit Qi of the topology 200 with the adjacent five first qubits and the non-adjacent two second qubits can be considered as one twisted square unit 100 of the topology 200.

The arrangement order of the five first qubits and the two second qubits around the central qubit Qi is in turn: first qubit Q1 of first azimuth, first qubit Q2 of second azimuth, second qubit Q7 of seventh azimuth, first qubit Q5 of fifth azimuth, first qubit Q3 of third azimuth, first qubit Q4 of fourth azimuth, second qubit Q6 of sixth azimuth.

In each twisted square cell 100, the spacing between the center qubit Qi and the five first qubits may be the same or different; the spacing between the first qubit Q1 of the first bearing and the first qubit Q2 of the second bearing may be the same or different; the spacing between the first qubit Q3 of the third orientation and the first qubit Q4 of the fourth orientation may be the same or different; the spacing between the first qubit Q3 of the third orientation and the first qubit Q5 of the fifth orientation may be the same or different. The spacing between the second qubit Q7 of the seventh bearing and the first qubit Q2 of the second bearing may be the same or different; the spacing between the second qubit Q7 of the seventh orientation and the first qubit Q5 of the fifth orientation may be the same or different; the spacing between the second qubit Q6 of the sixth orientation and the first qubit Q1 of the first orientation may be the same or different; the spacing between the second qubit Q6 of the sixth orientation and the first qubit Q4 of the fourth orientation may be the same or different. That is, the specific form of the quadrangular structure and the triangular structure in each twisted square unit 100 can be selected and adjusted. The method can be specifically selected and adjusted according to the design requirement and connectivity requirement of the quantum chip structure.

In each twisted square cell 100, the respective qubits may be directly coupled or indirectly coupled through a coupler.

The plurality of twisted square cells 100 can be laid down in an infinite manner within the planar area planned by the quantum chip structure without leaving voids.

In practical applications, the central qubit Qi, the five first qubits and the two second qubits may be the same or different types of the qubits selected by the three, which is not limited by the scheme of the embodiments of the disclosure. The central qubit Qi, the five first qubits and the two second qubits may be disposed on the same plane, so as to facilitate implementation of the processing technique.

The quantum chip structure of the embodiments of the present disclosure may be understood as a superconducting circuit quantum chip structure.

In practical applications, there are many factors for measuring performance of a quantum chip structure (such as a superconducting circuit quantum chip), and connectivity is one of the key indexes. Here, connectivity refers to the degree of connectivity between one qubit and the remaining other qubits in a quantum chip structure (such as a superconducting circuit quantum chip structure). Through connectivity calculation, the planar configuration communication parameter of the topology structure 200 formed by closely paving the plurality of twisted square units 100 in the embodiment of the disclosure is smaller than 0.57, and in the case that a proper spacing is selected between the qubits of each twisted square unit 100 with a coupling relationship, the planar configuration communication parameter can further reach 0.5667 or 0.5657.

According to the technology of the embodiment of the disclosure, the novel topological structure 200 of the quantum chip structure formed by closely paving the plurality of twisted square units 100 can enable each quantum bit of the quantum chip structure to present strong connectivity. Through calculation, the planar configuration communication parameter of the topology structure 200 of the quantum chip structure of the embodiment of the disclosure may reach less than 0.57, compared with the design scheme of the topology structure of the quantum chip structure commonly used in industry, the quantum chip structure of the embodiment of the disclosure presents significant advantages in connectivity, which is far superior to the design scheme of other topology structures in industry, and the quantum chip structure (for example, superconducting circuit quantum chip) with the optimal connectivity in industry at present can be obtained. The quantum chip structure of the embodiment of the disclosure has the advantages of being beneficial to the strong connectivity, being capable of remarkably improving the execution efficiency of the quantum algorithm on the quantum chip structure of the high-performance superconducting circuit, having important practical value for the realization of the high-potential quantum algorithm and bringing new possibility for the structural design of the quantum chip.

According to the technology of the embodiment of the disclosure, the central qubit Qi of the embodiment of the disclosure is adjacent to at most 5 first qubits, so that compared with the case that one qubit is coupled with more than six qubits (including the number) in the industry, the number of adjacent qubits is reduced, the crosstalk among the qubits is reduced, and the fidelity of the quantum gate operation is improved. Meanwhile, the number of couplers in the whole quantum chip structure can be relatively reduced, so that the problem of difficult lead of quantum bits and couplers in the quantum chip structure can be effectively solved, more lead spaces are reserved for the quantum bits and the couplers, and the method is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. The spatial area of the quadrilateral structure of each twisted square cell 100 may be used for routing (including but not limited to read cavities, measurement and control lines).

According to the technology of the embodiment of the disclosure, the topology structure 200 is constructed by using the twisted square units 100, so that more quantum bits can be distributed in a limited space of the quantum chip structure, and the connectivity of the quantum chip structure can be improved, thereby achieving the effect of multiple purposes.

According to the technology of the embodiment of the present disclosure, the specific form of the topology structure 200 may be changed according to the number of quantum bits, so that the topology structure 200 has a stronger expansibility, and may not be limited to a specific design scheme, but a series of design schemes with similar structures. Through calculation, the quantum chip structure of the embodiment of the disclosure has excellent connectivity even if the quantum chip structure is expanded to thousands of quantum bits.

According to the technology of the embodiment of the disclosure, the quantum chip structure of the embodiment of the disclosure has good integration level. The scheme of closely laying the plurality of twisted square units 100 makes full use of the entire space of the quantum chip structure. Meanwhile, the method maintains strong consistency in all directions, and is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. When the number of qubits is scaled up, the advantages are further emphasized.

In one example, as shown in fig. 4a, a cross capacitor and an elongated in-line metal line are etched respectively in an aluminum film plated on a substrate (such as a sapphire substrate); here, a josephson junction is connected between one end of the cross-shaped capacitor (e.g. the right end of fig. 4 a) and the ground plate. The quantum device formed by the cross capacitor and the Josephson junction can be used as a quantum bit, and the linear metal wire is a quantum bit control wire, so that a quantum system of a control wire-quantum bit is formed by the cross capacitor and the Josephson junction. It will be appreciated that the most critical geometrical parameter in fig. 4a is the gap between the two quantum devices (i.e. qubit and control line) which directly affects the coupling strength of the two. Where d represents the gap between the control line of the qubit and the qubit. In order to improve the chip integration and reduce the influence of the circuit on other elements in the quantum chip, elements such as a quantum bit, a coupler and a reading resonant cavity which are responsible for operation and reading in a quantum chip structure (such as a superconducting quantum chip) are independently placed on a bit layer, a control line connected with an external control system of the chip and a reading line used for reading are placed on a wiring layer, and the bit layer and the wiring layer can be connected by utilizing indium columns. By adopting the flip chip technology, the control and reading lines of the quantum chip and the core computing unit are respectively arranged on different layers, the wiring space is greatly increased, and the wiring flexibility is improved.

In one embodiment, as shown in fig. 4b, for a single qubit, it is generally necessary to connect to an external control system, such as by connecting the qubit to the external control system via a qubit control line (flux control line and/or microwave control line), so that manipulation of the qubit is achieved. Based on this, the quantum chip structure further includes the following structure:

one end of the qubit control line 1 is connected with a control line port 2 of the target qubit, and the other end is used for being connected with an external control system. And/or

And one end of the reading resonant cavity 3 is connected with a reading cavity port 4 of the target quantum bit, the other end of the reading resonant cavity is connected with a reading line 5, and the reading line 5 is used for being connected with an external control system. In this way, reading of the qubit can be achieved.

Wherein the target qubit is at least one of the following qubits: a central qubit Qi, five first qubits or two second qubits.

The number of qubit control lines 1 may be selected and adjusted as needed. For example, each target qubit may lead out one qubit control line 1, e.g., one magnetic flux control line or one microwave control line; for another example, each target qubit may draw two qubit control lines 1, one of which is a magnetic flux control line and the other is a microwave control line; it will be appreciated that the manner in which the qubit control line 1 is routed is related to the particular structure of the target qubit and is not particularly limited herein.

In one embodiment, as shown in fig. 4b, in a quantum chip structure comprising a coupler structure, one coupler control line connected to an external control system is also required for each coupler. Based on this, the quantum chip structure further includes the following structure:

and a coupler 6 disposed between two adjacent qubits for coupling the two adjacent qubits.

And one end of the coupler control line 7 is connected with a control line port 8 of the coupler 6, and the other end of the coupler control line is used for being connected with an external control system. In this way, manipulation of the coupler can be achieved.

Wherein, two adjacent qubits are at least one of the following combinations:

the central quantum bit Qi is respectively connected with one of five first quantum bits, a first quantum bit Q1 of a first azimuth and a first quantum bit Q2 of a second azimuth, a first quantum bit Q3 of a third azimuth and a first quantum bit Q4 of a fourth azimuth, a first quantum bit Q3 of the third azimuth and a first quantum bit Q5 of a fifth azimuth, a second quantum bit Q6 of a sixth azimuth and a first quantum bit Q1 of the first azimuth, a second quantum bit Q6 of the sixth azimuth and a first quantum bit Q4 of the fourth azimuth, a second quantum bit Q7 of a seventh azimuth and a first quantum bit Q2 of the second azimuth, and a second quantum bit Q7 of the seventh azimuth and a first quantum bit Q5 of the fifth azimuth.

In one embodiment, the central qubit Qi of any twisted square cell 100 may be any one of the five first qubits or two second qubits of another twisted square cell 100.

In one embodiment, any one of the five first qubits or the two second qubits of any one twisted square cell 100 may be the center qubit Qi, any one of the five first qubits or the two second qubits of another twisted square cell 100.

In one example, the twisted square cell 100 framed by the dashed-line box in the upper right corner of fig. 2 coincides with the twisted square cell 100 framed by the dashed-line box, and the first qubit Q2 of the second orientation of the twisted square cell 100 framed by the dashed-line box is the second qubit Q7 of the seventh orientation of the twisted square cell 100 framed by the dashed-line box. The second qubit Q7 of the seventh orientation of the twisted square cell 100 framed by the dashed box is the first qubit Q5 of the fifth orientation of the twisted square cell 100 framed by the dashed box. The center qubit Qi of the twisted square cell 100 framed by the dashed box is the first qubit Q2 of the second orientation of the twisted square cell 100 framed by the dashed box. The first qubit Q5 of the fifth orientation of the twisted square cell 100, as framed by the dashed box, is the center qubit Qi of the twisted square cell 100, as framed by the dashed box. The first qubit Q3 of the third orientation of the twisted square cell 100 framed by the dashed box is the first qubit Q1 of the first orientation of the twisted square cell 100 framed by the dashed box.

In one embodiment, as shown in fig. 3, the outer side of the central qubit Qi is sequentially formed with a first triangle structure, a first quadrangle structure, a second triangle structure, a third triangle structure, and a second quadrangle structure.

The first triangle structure is composed of a central qubit Qi, a first qubit Q1 of a first azimuth and a first qubit Q2 of a second azimuth.

The second triangle structure is composed of the central qubit Qi, the first qubit Q3 of the third azimuth and the first qubit Q5 of the fifth azimuth.

The third triangle structure is composed of the central qubit Qi, the first qubit Q3 of the third azimuth and the first qubit Q4 of the fourth azimuth.

The first quadrilateral structure is composed of a central qubit Qi, a first qubit Q2 of a second azimuth, a first qubit Q5 of a fifth azimuth and a second qubit Q7 of a seventh azimuth.

The second quadrangle structure is composed of a central quantum bit Qi, a first quantum bit Q1 of a first azimuth, a first quantum bit Q4 of a fourth azimuth and a second quantum bit Q6 of a sixth azimuth.

According to the embodiment of the disclosure, it is to be noted that:

the first triangular structure may be an isosceles triangular structure, an equilateral triangular structure, or other triangular structure. The second triangular structure may be an isosceles triangular structure, an equilateral triangular structure, or other triangular structure. The third triangular structure may be an isosceles triangular structure, an equilateral triangular structure, or other triangular structure.

The first quadrilateral structure may be a square structure, a rectangular structure, a parallelogram structure, or the like.

The second quadrilateral structure may be a square structure, a rectangular structure, a parallelogram structure, or the like.

According to the technology of the embodiment of the disclosure, the central qubit Qi is only coupled with the first qubit constructing the triangle structure and is not coupled with the second qubit constructing the rectangle structure, so that the central qubit Qi is only adjacent to 5 first qubits at most, and compared with the case that one qubit is coupled with more than six qubits (including the number) in the industry, the number of adjacent qubits is reduced, the crosstalk among the qubits is reduced, and the fidelity of the quantum gate operation is further improved. Meanwhile, the number of couplers in the whole quantum chip structure can be relatively reduced, so that the problem of difficult lead of quantum bits and couplers in the quantum chip structure can be effectively solved, more lead spaces are reserved for the quantum bits and the couplers, and the method is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. The spatial area of the quadrilateral structure of each twisted square cell 100 may be used for routing (including but not limited to read cavities, measurement and control lines).

In one embodiment, the spacing between the center qubit Qi and the five first qubits is a first threshold.

The interval between the first quantum bit Q1 in the first azimuth and the first quantum bit Q2 in the second azimuth is a first threshold value, and the interval between the first quantum bit Q3 in the third azimuth and the first quantum bit Q4 in the fourth azimuth and the interval between the first quantum bit Q5 in the fifth azimuth are both first threshold values.

The second qubit Q6 in the sixth direction is separated from the first qubit Q1 in the first direction and the first qubit Q4 in the fourth direction by a first threshold. The first threshold is a distance between the second qubit Q7 in the seventh direction and the first qubit Q2 in the second direction and the first qubit Q5 in the fifth direction.

According to the embodiment of the disclosure, it is to be noted that:

the specific size of the first threshold can be selected and adjusted as required.

According to an aspect of the embodiment of the present disclosure, the twisted square unit 100 as shown in fig. 3 may be constructed, that is, the twisted square unit 100 is composed of an equilateral triangle structure-a square structure-an equilateral triangle structure-a square structure, which are sequentially connected end to end.

According to the technology of the embodiment of the disclosure, the planar configuration communication parameter of the topological structure 200 of the quantum chip structure of the embodiment of the disclosure can be less than 0.57, so that strong connectivity is presented among all the quantum bits of the quantum chip structure. Compared with the design scheme of the topological structure of the quantum chip structure common in the industry, the quantum chip structure of the embodiment of the disclosure presents remarkable advantages in connectivity, is far superior to the design schemes of other topological structures in the industry, and can obtain the quantum chip structure (for example, superconducting circuit quantum chip) with the optimal connectivity in the industry at present. The quantum chip structure of the embodiment of the disclosure has the advantages of being beneficial to the strong connectivity, being capable of remarkably improving the execution efficiency of the quantum algorithm on the quantum chip structure of the high-performance superconducting circuit, having important practical value for the realization of the high-potential quantum algorithm and bringing new possibility for the structural design of the quantum chip.

In one embodiment, the spacing between the center qubit Qi and the first qubit Q1 of the first azimuth, the first qubit Q2 of the second azimuth, the first qubit Q4 of the fourth azimuth, and the first qubit Q5 of the fifth azimuth are all the first threshold. The spacing between the central qubit Qi and the first qubit Q3 of the third bearing is a second threshold.

The spacing between the first qubit Q1 of the first azimuth and the first qubit Q2 of the second azimuth is a second threshold. The first qubit Q3 in the third direction is separated from the first qubit Q4 in the fourth direction and the first qubit Q5 in the fifth direction by a first threshold.

According to the embodiment of the disclosure, it is to be noted that:

the specific magnitudes of the first threshold and the second threshold can be selected and adjusted as needed.

According to the scheme of the embodiment of the present disclosure, the twisted square unit 100 as shown in fig. 5 may be configured, that is, the twisted square unit 100 is composed of an isosceles triangle structure-square structure-isosceles triangle structure-square structure connected end to end in sequence. On this basis, according to the twisted square unit 100 shown in fig. 7, the topology 200 shown in fig. 5, 6 and 7 can be obtained.

According to the technology of the embodiment of the disclosure, the planar configuration communication parameter of the topological structure 200 of the quantum chip structure of the embodiment of the disclosure can be less than 0.57, so that strong connectivity is presented among all the quantum bits of the quantum chip structure. Compared with the design scheme of the topological structure of the quantum chip structure common in the industry, the quantum chip structure of the embodiment of the disclosure presents remarkable advantages in connectivity, is far superior to the design schemes of other topological structures in the industry, and can obtain the quantum chip structure (for example, superconducting circuit quantum chip structure) with the optimal connectivity in the industry at present. The quantum chip structure of the embodiment of the disclosure has the advantages of being beneficial to the strong connectivity, being capable of remarkably improving the execution efficiency of the quantum algorithm on the quantum chip structure of the high-performance superconducting circuit, having important practical value for the realization of the high-potential quantum algorithm and bringing new possibility for the structural design of the quantum chip.

In one embodiment, the central qubit Qi is indirectly coupled to the five first qubits via couplers.

The first quantum bit Q1 in the first azimuth and the first quantum bit Q2 in the second azimuth are indirectly coupled through a coupler, and the first quantum bit Q3 in the third azimuth and the first quantum bit Q4 in the fourth azimuth and the first quantum bit Q5 in the fifth azimuth are indirectly coupled through a coupler.

The second qubit Q6 of the sixth orientation is indirectly coupled to both the first qubit Q1 of the first orientation and the first qubit Q4 of the fourth orientation via a coupler. The second qubit Q7 of the seventh azimuth is indirectly coupled with the first qubit Q2 of the second azimuth and the first qubit Q5 of the fifth azimuth through a coupler.

According to the technology of the embodiment of the disclosure, the central qubit Qi of the embodiment of the disclosure is only coupled with 5 first qubits at most, so that compared with the case that one qubit is coupled with more than six qubits (including the number) in the industry, the number of adjacent qubits is reduced, the crosstalk between the qubits coupled by the coupler is reduced, and the fidelity of the quantum gate operation is further improved.

In one example, the coupler may also be implemented using qubits, the core function of which is to adjust the coupling strength between two qubits of a connection. For example, the first qubit Q1 of the first azimuth is indirectly coupled with the first qubit Q2 of the second azimuth through an additional qubit, and the first qubit Q3 of the third azimuth is indirectly coupled with the first qubit Q4 of the fourth azimuth and the first qubit Q5 of the fifth azimuth through an additional qubit. The second qubit Q6 of the sixth bit is indirectly coupled with the first qubit Q1 of the first bit and the first qubit Q4 of the fourth bit through additional qubits. The second qubit Q7 of the seventh bit is indirectly coupled with the first qubit Q2 of the second bit and the first qubit Q5 of the fifth bit through additional qubits.

In one embodiment, the central qubit Qi is directly coupled to all five first qubits.

The first qubit Q1 of the first azimuth is directly coupled with the first qubit Q2 of the second azimuth, and the first qubit Q3 of the third azimuth is directly coupled with the first qubit Q4 of the fourth azimuth and the first qubit Q5 of the fifth azimuth.

The second qubit Q6 of the sixth bit is directly coupled to both the first qubit Q1 of the first bit and the first qubit Q4 of the fourth bit. The second qubit Q7 of the seventh bearing is directly coupled to both the first qubit Q2 of the second bearing and the first qubit Q5 of the fifth bearing.

According to the technology of the embodiment of the disclosure, the central qubit Qi of the embodiment of the disclosure is only coupled with 5 first qubits at most, so that compared with the case that one qubit is coupled with more than six qubits (including the number) in the industry, the number of adjacent qubits is reduced, the crosstalk between directly coupled qubits is reduced, and the fidelity of the quantum gate operation is improved.

In one embodiment, the quantum chip structure further comprises:

the topology layer 110 has a pre-shaped outer edge profile. Topology 200 is disposed in topology layer 110. The predetermined shape of the outer edge profile is one of a rectangle (as shown in fig. 1), an inclined rectangle rotated by a predetermined angle (as shown in fig. 8), a circle (as shown in fig. 9), or an ellipse.

The preset shape of the outer edge profile can be selected and adjusted according to the shape of the quantum chip structure and the number of qubits required.

According to the technology of the embodiments of the present disclosure, the preset shape of the outer edge profile of the topology layer 110 may be adapted to the shape of the quantum chip structure, thereby facilitating fabrication and installation. The plurality of twisted square units 100 are densely paved in the shape of the outer edge profile, so that the quantum chip structure of the embodiment of the disclosure has good integration level, and the whole space of the quantum chip structure is fully utilized.

In one embodiment, in the case where the preset shape of the outer edge profile is a rectangle, as shown in fig. 10 to 13, the topology 200 is a polygonal structure, and the topology 200 includes a first corner and a third corner located on a first diagonal line, and a second corner and a fourth corner located on a second diagonal line.

The first, second, third and fourth corners may be understood as four right-angled regions of the topology 200 corresponding to the outline of the outer edge of the rectangular shape. The region may be constituted by the qubits of the twisted square cell 100, or may be constituted by the qubits added to the outside of the twisted square cell 100 and the qubits of the twisted square cell 100.

The shapes of the first corner, the second corner, the third corner and the fourth corner can be triangular structures or quadrilateral structures, and the specific shapes of the four corners can be the same or different.

In one embodiment, as shown in fig. 10, in the case where the preset shape of the outer edge profile is rectangular, the first corner is formed by the quadrangular structure in the first twisted square unit 100, the second corner is formed by the quadrangular structure in the second twisted square unit 100, the third corner is formed by the quadrangular structure in the third twisted square unit 100, and the fourth corner is formed by the quadrangular structure in the fourth twisted square unit 100.

According to the technology of the embodiment of the present disclosure, flexible adjustment of the positions of the qubits at the edge positions of the topology 200 according to the required number of qubits and the shape of the outer edge profile of the topology layer 110 can be achieved. Thus, the topology structure 200 is constructed by utilizing the twisted square units 100, so that more quantum bits can be distributed in the limited space of the quantum chip structure, the connectivity of the quantum chip structure can be improved, and the effect of multiple purposes is achieved. Meanwhile, the quantum chip structure of the embodiment of the disclosure has good integration level, the twisted square units 100 are densely paved in the topological structure layer 110, and the whole space of the quantum chip structure is fully utilized. Meanwhile, the method maintains strong consistency in all directions, and is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. When the number of qubits is scaled up, the advantages are further emphasized.

In one embodiment, as shown in fig. 11, in the case where the preset shape of the outer edge profile is rectangular, the first corner is formed by the quadrangular structure in the first twisted square unit 100, the second corner is formed by the first triangular structure and the first additional triangular structure in the second twisted square unit 100, wherein the first additional triangular structure is formed by the third qubit located outside the first triangular structure and the first qubit Q1 of the first orientation and the first qubit Q2 of the second orientation in the first triangular structure, the third corner is formed by the quadrangular structure in the third twisted square unit 100, and the fourth corner is formed by the second triangular structure and the third triangular structure in the fourth twisted square unit 100.

According to the technology of the embodiment of the present disclosure, it is possible to flexibly adjust the positions of the qubits at the edge positions of the topology 200 and flexibly arrange additional qubits at the edge positions of the topology 200 according to the required number of qubits and the shape of the outer edge profile of the topology layer 110. Thus, the topology structure 200 is constructed by utilizing the twisted square units 100, so that more quantum bits can be distributed in the limited space of the quantum chip structure, the connectivity of the quantum chip structure can be improved, and the effect of multiple purposes is achieved. Meanwhile, the quantum chip structure of the embodiment of the disclosure has good integration level, the twisted square units 100 are densely paved in the topological structure layer 110, and the whole space of the quantum chip structure is fully utilized. Meanwhile, the method maintains strong consistency in all directions, and is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. When the number of qubits is scaled up, the advantages are further emphasized.

In one embodiment, as shown in fig. 12, in case that the preset shape of the outer edge profile is rectangular, a first corner is formed by a quadrangular structure in the first twisted square unit 100, a second corner is formed by a quadrangular structure in the second twisted square unit 100, a third corner is formed by a first triangular structure and a first additional triangular structure in the third twisted square unit 100, wherein the first additional triangular structure is formed by a third qubit located outside the first triangular structure and a first qubit Q1 of a first orientation and a first qubit Q2 of a second orientation in the first triangular structure, and a fourth corner is formed by a second triangular structure and a third triangular structure in the fourth twisted square unit 100.

In one embodiment, as shown in fig. 13, in the case where the preset shape of the outer edge profile is rectangular, the first corner is formed of a first triangle structure and a first additional triangle structure in the first twisted square unit 100, wherein the first additional triangle structure is formed of a third qubit located outside the first triangle structure and a first qubit Q1 of a first orientation and a first qubit Q2 of a second orientation in the first triangle structure, the second corner is formed of a second triangle structure and a third triangle structure in the second twisted square unit 100, the third corner is formed of a first triangle structure and a second additional triangle structure in the third twisted square unit 100, wherein the second additional triangle structure is formed of a fourth qubit located outside the first triangle structure and a first qubit Q1 of a first orientation and a first qubit Q2 of a second orientation in the first triangle structure, and the fourth corner is formed of a second triangle structure and a third triangle structure in the fourth twisted square unit 100.

In one example, where the preset shape of the outer edge profile is square, the topology 200 may be an n x n square topology 200 (n is a positive integer).

Wherein when n is even, the n x n square topology 200 is formed by

The 2 x 2 square topology 200 is densely paved as basic units, and the sum is (n+1) ² The 2 x 2 square topology 200 is here a concave octagon structure of 4 regular triangles and 2 squares stitched together, containing 9 vertices. As shown in fig. 14, a 2 x 2 square topology 200 is shown. As shown in fig. 15, a 4 x 4 square topology 200 is shown. As shown in fig. 16, a 6 x 6 square topology 200 is shown.

Wherein when n is an odd number, the n×n square topology 200 is obtained by removing all vertices on two adjacent outermost sides from the (n+1) × (n+1) square topology 200, and includes (n+1) in total ² And a plurality of vertices. Taking the 5×5 square topology 200 as an example, as shown in fig. 17, 13 vertices on the uppermost side and the rightmost side of the 6×6 square topology 200 can be removed, resulting in a 5×5 square topology 200 within a dashed frame. As shown in fig. 18, 13 total vertices at the uppermost side and leftmost side may also be removed, resulting in a 5×5 diamond square topology 200 within the dashed box.

In one embodiment, in the case where the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number m of preset qubits in the topology layer 110 is an even number, the topology 200 is a polygonal structure, and the topology 200 includes a first corner and a second corner located on a first diagonal line, and a third corner and a fourth corner located on a second diagonal line. Wherein,,

the first corner is formed by the second quadrangular structure in the first twisted square unit 100.

And a second corner formed by a second quadrilateral in the second twisted square unit 100.

And a third corner formed by a second quadrangular structure in the third twisted square unit 100.

And a fourth corner formed by the second quadrangular structure in the fourth twisted square unit 100.

The second quadrangle structure in the first twisted square unit 100, the second quadrangle structure in the second twisted square unit 100, the second quadrangle structure in the third twisted square unit 100, and the second quadrangle structure in the fourth twisted square unit 100 are all inclined rectangles rotated counterclockwise by the first angle, as shown in fig. 19.

According to the embodiment of the disclosure, it is to be noted that:

The preset angle by which the inclined rectangle rotates can be selected and adjusted according to the structural requirement of the quantum chip structure, and is not particularly limited herein. For example, the preset angle may be 30 °, 45 °, 60 °, and the like.

And a second corner formed by the first quadrangular structure in the second twisted square unit 100.

A fourth corner is formed by the first quadrilateral in the fourth twisted square unit 100.

The second quadrangular structure in the first twisted square unit 100 and the second quadrangular structure in the third twisted square unit 100 are both inclined rectangles rotated counterclockwise by the first angle. The first quadrangular structure in the second twisted square unit 100 and the first quadrangular structure in the fourth twisted square unit 100 are both formed as inclined rectangles rotated clockwise by a second angle, as shown in fig. 20.

According to the embodiment of the disclosure, it is to be noted that:

In one example, the pre-shaping of the outer edge profileIn the case of an inclined square having a shape rotated by 45 °, an n×n 45 ° inclined square topology 200 (n.gtoreq.2, positive integer) is formed by n sequentially connected vertices arranged in an n×n square shape ² The square and regular triangle twisted edges are formed, and the total of the square and regular triangle twisted edges comprises 2n (n+1) vertexes. Where n represents the number of square structures in a row or column of topology 200. As shown in fig. 19, a 3 x 3 45 ° slanted square topology 200 is shown. As shown in fig. 20, a 4 x 4 45 ° diagonal square topology 200 is shown.

In one embodiment, the quantum chip structure further comprises:

at least one fifth qubit is disposed at least outside of either edge of topology 200 and coupled to at least two qubits located on either edge. Wherein the at least two qubits are any two qubits among the five first qubits or the two second qubits.

According to the embodiment of the disclosure, it is to be noted that:

the number of fifth qubits depends on the number of qubits required for the quantum chip structure. The fifth qubit may be understood as a qubit that does not constitute the twisted square cell 100. That is, when the total number of the qubits of the topology 200 formed by the twisted square cells 100 does not satisfy the number of the qubits required for the quantum chip structure, the fifth qubit needs to be added to compensate for the number of the qubits required for the quantum chip structure.

The qubits (e.g., third and fourth qubits) in any of the embodiments of the present disclosure that do not constitute twisted square cells 100 can be considered fifth qubits of the embodiments of the present disclosure.

According to the technology of the embodiment of the present disclosure, by setting the fifth qubit outside any edge of the topology 200, fine tuning of the topology 200 can be achieved, so that the number of qubits of the topology 200 increases. By additionally setting the fifth qubit, the specific form of the topological structure 200 can be changed according to the number of the qubits, so that the topological structure 200 has stronger expansibility, and the topological structure is not limited to a specific design scheme, but a series of design schemes with similar structures. Through calculation, the quantum chip structure of the embodiment of the disclosure has excellent connectivity even if the quantum chip structure is expanded to thousands of quantum bits. Meanwhile, the problem of the number of quantum bits required by the quantum chip structure can be solved, and the arrangement position of the quantum bits at the edge position of the topological structure 200 can be flexibly adjusted according to the outline of the outer edge of the topological structure layer 110. The quantum chip structure of the embodiment of the disclosure has good integration level, the twisted square units 100 are densely paved in the topological structure layer 110, and the whole space of the quantum chip structure is fully utilized.

In one example, as shown in fig. 21-23, adding a fifth qubit to the 3 x 3 45 ° diagonal square topology 200 achieves topology 200 trimming.

As shown in fig. 21, on the basis of a 3×3 45 ° oblique square topological structure 200, a fifth qubit is added to the outer sides of four edges of the topological structure 200, and each fifth qubit is coupled with a twisted square unit 100 of the corresponding edge to form a gray structural region in the figure. Thus, an increase of four qubits on the basis of a 3×3 45 ° slanted square topology 200 is achieved.

As shown in fig. 22, on the basis of a 3×3 45 ° oblique square topology 200, a fifth qubit is added on the outer sides of a first edge and a second edge opposite to the topology 200, two fifth qubits are added on the outer sides of a third edge and a fourth edge opposite to the topology 200, and each fifth qubit is coupled with a twisted square unit 100 of the corresponding edge to form a gray structure region in the figure. Thus, an increase of six qubits on the basis of a 3×3 45 ° slanted square topology 200 is achieved.

As shown in fig. 23, on the basis of a 3×3 45 ° oblique square topology 200, four fifth qubits are added to the outer sides of four edges of the topology 200, and each fifth qubit is coupled with a twisted square unit 100 of a corresponding edge to form a gray structure region in the figure. Thus, an increase of 16 qubits on the basis of a 3×3 45 ° slanted square topology 200 is achieved.

In one example, the fifth qubit is increased in a manner related to the parity of n, as shown in fig. 24, and the smallest-sized dashed rectangular box contains a topology 200 of 3×3 45 ° diagonal square topology (as shown in fig. 19). The topology 200 encompassed by the medium-sized dashed rectangular box is the topology 200 of fig. 19 after adding the fifth qubit (as shown in fig. 22). The largest-sized dashed rectangular box contains topology 200 as shown in fig. 23 with the addition of the fifth qubit to topology 200 of fig. 19. Wherein, the 3×3 45 ° oblique square topology structure included in the dashed rectangle frame with the smallest size adds a fifth qubit on the outer side of the inner concave portion of each side edge, so that the fifth qubit is coupled with three qubits of the inner concave portion to form two additional triangle structures, and the topology structure 200 with the outermost inner angle of not less than 120 ° in fig. 21 can be obtained.

In one example, as shown in fig. 25 to 27, the topology 200 fine-tuning is implemented by adding a fifth qubit to the 4×4 45 ° diagonal square topology 200.

As shown in fig. 25, on the basis of a 4×4 45 ° oblique square topology 200, a fifth qubit is added on the outer sides of a first edge and a second edge opposite to the topology 200, two fifth qubits are added on the outer sides of a third edge and a fourth edge opposite to the topology 200, and each fifth qubit is coupled with a twisted square unit 100 of the corresponding edge to form a gray structure region in the figure. Thus, an increase of six qubits on the basis of a 4 x 4 45 ° diagonal square topology 200 is achieved.

As shown in fig. 26, on the basis of a 4×4 45 ° oblique square topology 200, two fifth qubits are added on the outer sides of a first edge and a second edge opposite to the topology 200, three fifth qubits are added on the outer sides of a third edge and a fourth edge opposite to the topology 200, and each fifth qubit is coupled with a twisted square unit 100 of the corresponding edge to form a gray structure region in the figure. Thus, a ten qubit addition to the 4 x 4 45 ° diagonal square topology 200 is achieved.

As shown in fig. 27, on the basis of a 4×4 45 ° oblique square topology 200, five fifth qubits are added to the outer sides of four edges of the topology 200, and each fifth qubit is coupled with a twisted square unit 100 of a corresponding edge to form a gray structure region in the figure. In this way, an increase of twenty qubits on the basis of a 4 x 4 45 ° slanted square topology 200 is achieved.

The setting positions of the fifth qubits shown in fig. 21 to 27 are only for illustration, and are not limited to the setting positions and the setting numbers of the fifth qubits.

In one example, topology 200 can be equivalently converted into a variety of deformed topologies 200 by adjusting the spacing between the center qubit Qi and five first qubits, the spacing between five first qubits, or the spacing between two second qubits and adjacent first qubits to meet the design requirements and connectivity requirements of different quantum chip structures.

For example, the topology 200 of fig. 15 can equivalently yield the topology 200 of fig. 5 by adjusting the spacing between qubits. By such fine tuning, the topology 200 can be adapted to the topology layers 110 of different outer edge profiles. As another example, the topology 200 of fig. 20 can equivalently yield the topology 200 of fig. 6 by adjusting the spacing between qubits. As another example, the topology 200 of fig. 27 can be equivalently obtained by adjusting the pitch between qubits to obtain the topology 200 of fig. 7.

It should be noted that, the equivalent topology 200 of fig. 5 to 7 is only for illustration, and is not limited to the transformation method of the equivalent topology 200, nor to the adjustment method of the spacing between qubits.

Connectivity performance description of embodiments of the present disclosure:

The following describes a specific method for efficiently calculating the planar configuration communication parameters of the configuration scheme H. The method comprises the following specific steps:

step 1: inputting a layout structure of a configuration scheme H, namely a target topology structure, wherein the target topology structure comprises a layout scale parameter n;

here, in the case of the determination of the value of n, the total number of qubit nodes, i.e., the first total number, can be determined based on the target topology of configuration scheme H.

Step 2: and when the value of N is 1,2,3 and 4, calculating the total number (namely the first total number) of the quantum bit nodes contained in the target topological structure of the configuration scheme H, and obtaining four values of the first total number N.

Step 3: using the value of N when n=1, 2,3, performing polynomial interpolation on the first total number N with respect to the layout scale parameter N to obtain a first initial association relationship between the layout scale parameter N and the first total number N, for example, obtaining a quadratic polynomial

Step 4: when n takes 1,2,3,4,5,6,7, calculating the sum of mapping distances corresponding to the target topology structure of the configuration scheme H (namely, the first target mapping distance)

Wherein Q is _j And Q _k For qubits, k is a shape parameter.

Here, when calculation is performed using the graph theory algorithm, if the qubit can be well encoded in the regular target topology, the sum of the mapping distances can be rapidly calculated.

Step 5: using the value of D when n=1, 2,3,4,5,6, performing polynomial interpolation on the sum D of mapping distances corresponding to the target topological structure of the configuration scheme H with respect to n to obtainA second initial association between the layout scale parameter n and the sum D of the mapping distances corresponding to the target topology, for example, a polynomial of at most five times is obtained

Step 6: the value of N when n=4 is used _n＝4 To validate a quadratic polynomial

I.e. using the value of N i when n=4 _n＝4 Verifying the first initial association, i.e. checking +.>

Step 7: using the value d|of N when n=7 _n＝7 To verify the fifth degree polynomial

I.e. using the value d|of D when n=7 _n＝7 Verifying the second initial association, i.e. checking +.>

Step 8: if the two verification results are correct, the first initial association relationship is used as a first target association relationship, and the second initial association relationship is used as a second target association relationship, so that the plane configuration communication parameter of the configuration scheme H is obtained:

Otherwise, returning to the step 2, the new process can be performedThe value of the first total number N and the value of the first target mapping distance D are calculated at intervals in steps and the interpolation process is repeated (the number of required values may be unchanged). For example, use N| _n＝1 ，N| _n＝4 ，N| _n＝7 Interpolation by N| _n＝10 To verify, etc. In practical applications, the interpolation process may also consider the parameter selection of the arrangement, the parity of n or other modulus properties, which is not particularly limited in the scheme of the present disclosure.

Further, it can be based on

And +.>

The following third target association relationship is obtained, and thus, the chip topology structure (i.e., the chip topology structure of the first target quantum chip) H which can be obtained by the configuration scheme H can be calculated based on the third target association relationship _n Chip connection parameter c (H) _n )：/>

It should be noted that, the chip topology structure with a large number of quantum bits may be generalized into a configuration scheme, and then, the planar configuration communication parameters of the configuration scheme are calculated by using the method, and then, the chip communication parameters of the chip topology structure are obtained.

In this way, the scheme of the present disclosure can obtain the plane configuration communication parameter c (H) of the configuration scheme H based on a given configuration scheme H, and further, can obtain the chip topology structure H of the superconducting quantum chip obtained by the configuration scheme H _n Chip connection parameter c (H) _n )。

1. The chip communication parameters of the chip topology structure are calculated by adopting the scheme, and the result is as follows, and the fact that the smaller the plane configuration communication parameter c is, the stronger the communication degree is.

(a) As shown in fig. 28, the chip topology structure is a rectangular oblique square close-packed network with 54 qubits (X-shaped nodes in the figure), and the chip communication parameter c is about 0.678;

(b) As shown in fig. 29, the chip topology is a rectangular regular octagon-regular quadrilateral tiling network of 80 qubits (circular nodes in the figure), whose chip connectivity parameter c≡0.920;

(c) As shown in fig. 30, the chip topology is a rectangular regular hexagonal close-packed network of 127 qubits (circular nodes in the figure), whose chip connectivity parameter c≡0.988.

(d) In the one-dimensional chain chip structure, 12 quantum bits are distributed in a one-dimensional chain manner. Every two adjacent qubits are coupled, and the chip communication parameter c is approximately equal to 1.251;

(e) The following demonstrates the connectivity advantages of the topology 200 of embodiments of the present disclosure. Shorthand n x n square topology is S _n Forming a twisted square configuration scheme s=s ₁ ,S ₂ ,S ₃ …; the inclined square topological structure of n multiplied by n45 degrees is simply noted as X _n Scheme x=x, constituting a 45 ° oblique twisted square configuration ₁ ,X ₂ ,X ₃ …. The planar configuration communication parameters c of the twisted square configuration scheme S and the 45-degree inclined twisted square configuration scheme X are calculated according to the method:

in particular, it was found by the above calculation that: the square or water chestnut selection in the square topological structure does not change the plane configuration communication parameters of the twisted square configuration scheme S, and the introduction of fine adjustment does not change the plane configuration communication parameters of the inclined twisted square configuration scheme X of 45 degrees.

Regarding the plane configuration communication parameters, the twisted square configuration scheme S and the 45 ° oblique twisted square configuration scheme X are compared with the schemes of fig. 28 to 30 as follows:

regarding the plane configuration communication parameters, the twisted square configuration scheme S and the 45 ° oblique twisted square configuration scheme X are compared with the industry common plane configuration scheme as follows:

as can be seen from the above description of connectivity, the novel topology 200 of the quantum chip structure formed by closely paving the plurality of twisted square units 100 can enable each qubit of the quantum chip structure to exhibit strong connectivity. Through calculation, the planar configuration communication parameter of the topology structure 200 of the quantum chip structure of the embodiment of the disclosure may reach less than 0.57, compared with the design scheme of the topology structure of the quantum chip structure commonly used in industry, the quantum chip structure of the embodiment of the disclosure presents significant advantages in connectivity, which is far superior to the design scheme of other topology structures in industry, and the quantum chip structure (for example, superconducting circuit quantum chip) with the optimal connectivity in industry at present can be obtained. The quantum chip structure of the embodiment of the disclosure has the advantages of being beneficial to the strong connectivity, being capable of remarkably improving the execution efficiency of the quantum algorithm on the quantum chip structure of the high-performance superconducting circuit, having important practical value for the realization of the high-potential quantum algorithm and bringing new possibility for the structural design of the quantum chip.

As shown in fig. 31 and 32, an embodiment of the present disclosure provides a layout generating method of a quantum chip structure, including:

step S3101: the first topology pattern 400 is constructed.

Step S3102: the second topology pattern 410 is determined from the first topology pattern 400 according to the number of preset qubits, and the first topology pattern 400 and the second topology pattern 410 are each formed by closely paving a plurality of twisted square patterns 300.

Step S3103: from the second topological pattern 410, a layout is generated, which is used to fabricate the quantum chip structure of any of the embodiments of the present disclosure.

The gray area in fig. 32 is a twisted square pattern 300, the outer solid frame in fig. 32 includes a first topology pattern 400, the broken frame in fig. 32 includes a second topology pattern 410, and any unit (including a mirror image and a unit of a rotation angle) that can form the gray area shape in the first topology pattern 400 and the second topology pattern 410 can be considered as a twisted square pattern 300.

As shown in fig. 33, each twisted square pattern 300 includes a center quantum node identification Pi, five first quantum node identifications adjacent to the center quantum node identification Pi, and two second quantum node identifications not adjacent to the center quantum node identification Pi. The central quantum node identities Pi are coupled to the five first quantum node identities, respectively.

Among the five first quantum node identifications: the first quantum node identifier P1 of the first azimuth is coupled with the first quantum node identifier P2 of the adjacent second azimuth, and the first quantum node identifier P3 of the third azimuth is coupled with the first quantum node identifier P4 of the adjacent fourth azimuth and the first quantum node identifier P5 of the adjacent fifth azimuth, respectively.

Among the two second quantum node identities: the second quantum node identifier P6 in the sixth direction is coupled to the first quantum node identifier P1 in the first direction and the first quantum node identifier P4 in the fourth direction, respectively, and the second quantum node identifier P7 in the seventh direction is coupled to the first quantum node identifier P2 in the second direction and the first quantum node identifier P5 in the fifth direction, respectively.

According to the embodiment of the disclosure, it is to be noted that:

the size of the first topological pattern 400 constructed can be selected and adjusted as required, so that the second topological pattern 410 can be planned in the first topological pattern 400.

The number of preset qubits can be understood as the number of qubits required for the quantum chip structure to be manufactured, i.e. the total number of central qubit node identifications, five first quantum node identifications and two second quantum node identifications.

The specific manner of determining the second topology pattern 410 from the first topology pattern 400 may be to define a pattern area in the first topology pattern 400, so that the number of quantum node identifiers included in the pattern area meets the requirement of the preset number of quantum bits. The number of quantum node identifications contained in the delineated pattern region may be greater than the preset number of quantum bits, and the excess quantum node identifications may be removed when the second topology pattern 410 is determined based on the delineated pattern region. The defined pattern area may be the same as or different from the outer edge contour of the contour pattern of the layout. The pattern area can be adjusted through the outline of the outline pattern preset of the layout.

Each dot-shaped icon in fig. 32 can be understood as a quantum node identifier (center quantum bit node identifier, five first quantum node identifiers, two second quantum node identifiers), and a line connecting between dot-shaped icons represents a coupler identifier. The twisted square pattern 300 can be understood as a shape consisting of a triangle structure-a quadrangle structure-a triangle structure-a quadrangle structure connected end to end in sequence.

The planar configuration communication parameter of the quantum chip structure manufactured by the layout of the quantum chip structure disclosed by the embodiment of the invention can be less than 0.57.

When the layout of the quantum chip structure in the embodiment of the disclosure is utilized to manufacture the quantum chip structure, the twisted square pattern 300 corresponds to a twisted square unit for generating the quantum chip structure, the center quantum node identifier Pi corresponds to a center quantum bit, the first quantum node identifier P1 in the first direction corresponds to a first quantum bit in the first direction, the first quantum node identifier P2 in the second direction corresponds to a first quantum bit in the second direction, the first quantum node identifier P3 in the third direction corresponds to a first quantum bit in the third direction, the first quantum node identifier P4 in the fourth direction corresponds to a first quantum bit in the fourth direction, the first quantum node identifier P5 in the fifth direction corresponds to a first quantum bit in the fifth direction, the second quantum node identifier P6 in the sixth direction corresponds to a second quantum bit in the sixth direction, and the second quantum node identifier P7 in the seventh direction corresponds to a second quantum bit in the seventh direction. In this way, the topology of the quantum chip structure described in fig. 1 can be fabricated using the layout shown within the dashed box in fig. 32.

It should be noted that, based on the correspondence between the layout of the quantum chip structure and the quantum chip structure, descriptions of specific functions and examples of the layout of the quantum chip structure in any embodiment of the disclosure may be referred to the related descriptions of the quantum chip structure in any embodiment, and are not repeated herein.

According to the technology of the embodiment of the disclosure, the quantum chip structure manufactured by the layout of the quantum chip structure of the embodiment of the disclosure can be realized: the novel topological structure of the quantum chip structure formed by closely paving a plurality of twisted square units can enable all quantum bits of the quantum chip structure to show strong connectivity. Through calculation, the planar configuration communication parameter of the topology structure of the quantum chip structure of the embodiment of the disclosure can reach less than 0.57, compared with the design scheme of the topology structure of the quantum chip structure common in the industry, the quantum chip structure of the embodiment of the disclosure presents significant advantages in connectivity, which is far superior to the design scheme of other topology structures in the industry, and the quantum chip structure (for example, superconducting circuit quantum chip) with the optimal connectivity in the industry at present can be obtained. The quantum chip structure of the embodiment of the disclosure has the advantages of being beneficial to the strong connectivity, being capable of remarkably improving the execution efficiency of the quantum algorithm on the quantum chip structure of the high-performance superconducting circuit, having important practical value for the realization of the high-potential quantum algorithm and bringing new possibility for the structural design of the quantum chip. The central qubit is adjacent to 5 first qubits at most, so that compared with the situation that one qubit is coupled with more than six qubits (including the number) in the industry, the number of the adjacent qubits is reduced, the crosstalk among the qubits is reduced, and the fidelity of the quantum gate operation is improved. Meanwhile, the number of couplers in the whole quantum chip structure can be relatively reduced, so that the problem of difficult lead of quantum bits and couplers in the quantum chip structure can be effectively solved, more lead spaces are reserved for the quantum bits and the couplers, and the method is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. The space region of the quadrilateral structure of each twisted square unit can be utilized for wiring (including but not limited to a read cavity, a measurement and control line). The twisted square units are utilized to construct a topological structure, so that more quantum bits can be distributed in a limited space of the quantum chip structure, the connectivity of the quantum chip structure can be improved, and the effect of multiple purposes is achieved. The specific form of the topological structure can be changed according to the number requirement of the quantum bits, so that the topological structure has stronger expansibility, and the topological structure is not limited to a specific design scheme, but a series of design schemes with similar structures. Through calculation, the quantum chip structure of the embodiment of the disclosure has excellent connectivity even if the quantum chip structure is expanded to thousands of quantum bits. The quantum chip structure has good integration level. The scheme of closely paving a plurality of twisted square units fully utilizes the whole space of the quantum chip structure. Meanwhile, the method maintains strong consistency in all directions, and is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. When the number of qubits is scaled up, the advantages are further emphasized.

In one embodiment, the center quantum node identifier Pi of any one twisted square pattern 300 may be any one of the five first quantum node identifiers or the two second quantum node identifiers of another twisted square pattern 300.

In one embodiment, any one of the five first quantum node identifiers or the two second quantum node identifiers of any one of the twisted square patterns 300 may be the center quantum node identifier Pi, any one of the five first quantum node identifiers or the two second quantum node identifiers of another twisted square pattern 300.

In one embodiment, the outer side of the center quantum node mark Pi is sequentially formed with a first triangle structure, a first quadrangle structure, a second triangle structure, a third triangle structure and a second quadrangle structure in a surrounding manner. Wherein,,

the first triangle structure is composed of a center quantum node mark Pi, a first quantum node mark P1 in a first azimuth and a first quantum node mark P2 in a second azimuth.

The second triangle structure is composed of a center quantum node mark Pi, a first quantum node mark P3 in a third azimuth and a first quantum node mark P5 in a fifth azimuth.

The third triangle structure is composed of a center quantum node mark Pi, a first quantum node mark P3 in a third azimuth and a first quantum node mark P4 in a fourth azimuth.

The first quadrilateral structure is composed of a center quantum node mark Pi, a first quantum node mark P2 in a second azimuth, a first quantum node mark P5 in a fifth azimuth and a second quantum node mark P7 in a seventh azimuth.

The second quadrilateral structure is composed of a center quantum node mark Pi, a first quantum node mark P1 in a first azimuth, a first quantum node mark P4 in a fourth azimuth and a second quantum node mark P6 in a sixth azimuth.

According to the embodiment of the disclosure, it is to be noted that:

According to the technology of the embodiment of the disclosure, the quantum chip manufactured by the layout of the quantum chip of the embodiment of the disclosure can be realized: the central quantum bit is only coupled with the first quantum bit constructing the triangular structure and is not coupled with the second quantum bit constructing the rectangular structure, so that the central quantum bit is only adjacent to 5 first quantum bits at most, and compared with the situation that more than six quantum bits (including the number) are coupled with one quantum bit in the industry, the number of adjacent quantum bits is reduced, the crosstalk among the quantum bits is reduced, and the fidelity of quantum gate operation is improved. Meanwhile, the number of couplers in the whole quantum chip can be relatively reduced, so that the problem of difficult lead of the quantum bit and the couplers in the quantum chip can be effectively solved, more lead spaces are reserved for the quantum bit and the couplers, and the method is very beneficial to the design of necessary devices such as a reading cavity, a measurement and control line and the like. The space region of the quadrilateral structure of each twisted square unit can be utilized for wiring (including but not limited to a read cavity, a measurement and control line).

In one embodiment, at least one of the first triangular structure, the second triangular structure, and the third triangular structure is an equilateral triangle structure. Or, at least one of the first triangular structure, the second triangular structure and the third triangular structure is an isosceles triangle structure.

At least one of the first quadrangular structure and the second quadrangular structure is a square structure.

In one embodiment, the center quantum node identifier Pi, the five first quantum node identifiers, and the two second quantum node identifiers are located on the same plane.

In one embodiment, determining the second topology pattern from the first topology pattern according to the number of preset qubits includes:

and determining a third topological pattern in the first topological pattern according to the number of preset qubits, wherein each quantum node identifier in the third topological pattern is a quantum node identifier forming a twisted square pattern.

And setting a fifth quantum node identifier outside the edge of the third topological pattern under the condition that the number of the quantum node identifiers of the third topological pattern is smaller than the number of the preset quantum bits, wherein the fifth quantum node identifier is coupled with at least two quantum node identifiers on the edge. The at least two quantum node identifiers are quantum node identifiers in the five first quantum node identifiers or the two second quantum node identifiers.

And determining a second topological pattern according to the fifth quantum node identification and the third topological pattern.

According to the embodiment of the disclosure, it is to be noted that:

Fifth quantum node identifies a fifth quantum bit used to generate a quantum chip structure of any of the embodiments of the present disclosure.

With the layout obtained by the embodiments of the present disclosure, the topology of the quantum chip structure as shown in fig. 21 to 23 can be manufactured.

In one embodiment, generating a layout from the second topological pattern includes:

and determining a contour pattern arranged outside the second topological pattern according to the second topological pattern, wherein the contour pattern has an outer edge contour with a preset shape.

And generating a layout according to the outline pattern and the second topological pattern.

According to the embodiment of the disclosure, it is to be noted that:

the preset shape of the outer edge profile can be one of a rectangle, an inclined rectangle rotated by a preset angle, a circle or an ellipse, and the specific preset shape of the outer edge profile can be selected and adjusted according to the manufactured quantum chip structure.

The outline pattern is used to generate a topology layer of the quantum chip structure of any of the embodiments of the present disclosure.

In one embodiment, generating a layout from the outline pattern and the second topology pattern includes:

and determining the shape structures of the first corner and the third corner of the second topological pattern on the first diagonal line and the shape structures of the second corner and the fourth corner of the second topological pattern on the second diagonal line according to the outline pattern.

In one embodiment, in the case that the preset shape of the outer edge contour of the contour pattern is rectangular, the shape structures of the first corner, the second corner, the third corner and the fourth corner are one of the following four combinations:

the first corner is formed by a quadrilateral in the first twisted square pattern 300, the second corner is formed by a quadrilateral in the second twisted square pattern 300, the third corner is formed by a quadrilateral in the third twisted square pattern 300, and the fourth corner is formed by a quadrilateral in the fourth twisted square pattern 300;

the first corner is formed by a quadrilateral structure in the first twisted square pattern 300, the second corner is formed by a first triangular structure and a first additional triangular structure in the second twisted square pattern 300, wherein the first additional triangular structure is formed by a third quantum node identifier located outside the first triangular structure and a first quantum node identifier P1 in a first orientation and a first quantum node identifier P2 in a second orientation in the first triangular structure, the third corner is formed by a quadrilateral structure in the third twisted square pattern 300, and the fourth corner is formed by a second triangular structure and a third triangular structure in the fourth twisted square pattern 300;

The first corner is formed by a quadrilateral in the first twisted square pattern 300, the second corner is formed by a quadrilateral in the second twisted square pattern 300, the third corner is formed by a first triangle and a first additional triangle in the third twisted square pattern 300, wherein the first additional triangle is formed by a third quantum node identification located outside the first triangle and a first quantum node identification P1 in a first orientation and a first quantum node identification P2 in a second orientation in the first triangle, and the fourth corner is formed by a second triangle and a third triangle in the fourth twisted square pattern 300;

the first corner is formed by a first triangle structure and a first additional triangle structure in the first twisted square pattern 300, wherein the first additional triangle structure is formed by a third quantum node identification located outside the first triangle structure and a first quantum node identification P1 in a first orientation and a first quantum node identification P2 in a second orientation in the first triangle structure, the second corner is formed by a second triangle structure and a third triangle structure in the second twisted square pattern 300, the third corner is formed by a first triangle structure and a second additional triangle structure in the third twisted square pattern 300, wherein the second additional triangle structure is formed by a fourth quantum node identification located outside the first triangle structure and a first quantum node identification P1 in a first orientation and a first quantum node identification P2 in a second orientation in the first triangle structure, and the fourth corner is formed by a second triangle structure and a third triangle structure in the fourth twisted square pattern 300.

In one embodiment, in the case where the preset shape of the outer edge profile of the profile pattern is an inclined rectangle rotated by a preset angle and the number n of the preset quantum node marks in the profile pattern is an even number, the first corner is formed by the second quadrangular structure in the first twisted square pattern 300. The second corner is formed by a second quadrilateral in the second twisted square pattern 300. The third corner is formed by the second quadrilateral in the third twisted square pattern 300. The fourth corner is formed by the second quadrilateral in the fourth twisted square pattern 300.

The second quadrangle structure in the first twisted square pattern 300, the second quadrangle structure in the second twisted square pattern 300, the second quadrangle structure in the third twisted square pattern 300, and the second quadrangle structure in the fourth twisted square pattern 300 are all inclined rectangles rotated counterclockwise by the first angle.

In one embodiment, in the case where the preset shape of the outer edge profile of the profile pattern is an inclined rectangle rotated by a preset angle and the number n of the preset quantum node marks in the profile pattern is an even number, the first corner is formed by the second quadrangular structure in the first twisted square pattern 300. The second corner is formed by the first quadrilateral structure in the second twisted square pattern 300. The third corner is formed by the second quadrilateral in the third twisted square pattern 300. The fourth corner is formed by the first quadrilateral in the fourth twisted square pattern 300.

The second quadrangle structure in the first twisted square pattern 300 and the second quadrangle structure in the third twisted square pattern 300 are both inclined rectangles rotated counterclockwise by the first angle.

The first quadrangle structures in the second twisted square pattern 300 and the first quadrangle structures in the fourth twisted square pattern 300 are both formed as inclined rectangles rotated clockwise by a second angle.

In one embodiment, constructing a first topological pattern includes: and constructing the first topological pattern according to the preset interval between the quantum node identifiers.

The specific size of the preset distance can be selected and adjusted according to the needs.

According to the scheme of the embodiment of the present disclosure, by adjusting the preset distance, the twisted square unit 100 shown in fig. 3 may be formed by using a layout, that is, the twisted square unit 100 is formed by an equilateral triangle structure-a square structure-an equilateral triangle structure-a square structure, which are sequentially connected end to end. It is also possible to use a layout to construct the twisted square unit 100 as shown in fig. 5, that is, the twisted square unit 100 is composed of an isosceles triangle structure-square structure-isosceles triangle structure-square structure connected end to end in sequence. On this basis, according to the twisted square unit 100 shown in fig. 7, the topology 200 shown in fig. 5, 6 and 7 can be obtained.

In one embodiment, the preset spacing between the central quantum node identifier Pi and the five first quantum node identifiers is a first threshold.

The preset distance between the first quantum node identifier P1 in the first azimuth and the first quantum node identifier P2 in the second azimuth is a first threshold value, and the preset distance between the first quantum node identifier P3 in the third azimuth and the first quantum node identifier P4 in the fourth azimuth and the preset distance between the first quantum node identifier P5 in the fifth azimuth are both first threshold values.

The preset distance between the second quantum node identifier P6 in the sixth direction and the first quantum node identifier P1 in the first direction and the preset distance between the second quantum node identifier P4 in the fourth direction are both the first threshold value. The preset distance between the second quantum node identifier P7 in the seventh azimuth, the first quantum node identifier P2 in the second azimuth and the first quantum node identifier P5 in the fifth azimuth is the first threshold value.

In one embodiment, the preset distances between the center quantum node identifier Pi and the first quantum node identifier P1 in the first azimuth, the first quantum node identifier P2 in the second azimuth, the first quantum node identifier P4 in the fourth azimuth, and the first quantum node identifier P5 in the fifth azimuth are all the first threshold value. The preset distance between the central quantum node identifier Pi and the first quantum node identifier P3 of the third azimuth is a second threshold value.

The preset distance between the first quantum node identifier P1 of the first azimuth and the first quantum node identifier P2 of the second azimuth is a second threshold. The preset distance between the first quantum node identifier P3 in the third direction, the first quantum node identifier P4 in the fourth direction and the first quantum node identifier P5 in the fifth direction is the first threshold value.

In one embodiment, constructing a first topological pattern includes: and constructing a first topological pattern according to a preset coupling mode between the quantum node identifiers.

In one embodiment, the central quantum node identity Pi is indirectly coupled to the five first quantum node identities via coupler identities.

The first quantum node identification P1 in the first azimuth and the first quantum node identification P2 in the second azimuth are indirectly coupled through the coupler identification, and the first quantum node identification P3 in the third azimuth and the first quantum node identification P4 in the fourth azimuth and the first quantum node identification P5 in the fifth azimuth are indirectly coupled through the coupler identification.

The second quantum node identifier P6 in the sixth direction is indirectly coupled with the first quantum node identifier P1 in the first direction and the first quantum node identifier P4 in the fourth direction through the coupler identifier. The second quantum node identifier P7 in the seventh azimuth is indirectly coupled with the first quantum node identifier P2 in the second azimuth and the first quantum node identifier P5 in the fifth azimuth through the coupler identifier.

In one embodiment, the central quantum node identity Pi is directly coupled to all five first quantum node identities.

The first quantum node identifier P1 in the first azimuth is directly coupled with the first quantum node identifier P2 in the second azimuth, and the first quantum node identifier P3 in the third azimuth is directly coupled with the first quantum node identifier P4 in the fourth azimuth and the first quantum node identifier P5 in the fifth azimuth.

The second quantum node identifier P6 in the sixth direction is directly coupled to both the first quantum node identifier P1 in the first direction and the first quantum node identifier P4 in the fourth direction. The second quantum node identifier P7 of the seventh orientation is directly coupled to both the first quantum node identifier P2 of the second orientation and the first quantum node identifier P5 of the fifth orientation.

The embodiment of the disclosure provides a method for manufacturing a quantum chip, which comprises the following steps:

According to the technology of the embodiment of the disclosure, the quantum chip with high connectivity can be manufactured.

As shown in fig. 34, an embodiment of the present disclosure provides a layout generating device of a quantum chip structure, including:

a construction module 3410 is configured to construct a first topology pattern.

The determining module 3420 is configured to determine, according to the number of preset qubits, a second topology pattern from the first topology patterns, where each of the first topology pattern and the second topology pattern is formed by a plurality of twisted square patterns.

A generation module 3430 for generating a layout for fabricating the quantum chip structure of any one of claims 1 to 21 from the second topology pattern. Wherein,,

each twisted square pattern comprises a central quantum node identifier, five first quantum node identifiers adjacent to the central quantum node identifier, and two second quantum node identifiers not adjacent to the central quantum node identifier. The central quantum node identifiers are respectively coupled with the five first quantum node identifiers.

Among the five first quantum node identifications: the first quantum node identifier of the first azimuth is coupled with the first quantum node identifier of the adjacent second azimuth, and the first quantum node identifier of the third azimuth is coupled with the first quantum node identifier of the adjacent fourth azimuth and the first quantum node identifier of the adjacent fifth azimuth respectively.

In one embodiment, the determining module 3420 is configured to:

In one embodiment, the generation module 3430 includes:

the first determining sub-module is used for determining a contour pattern arranged outside the second topological pattern according to the second topological pattern, wherein the contour pattern has an outer edge contour with a preset shape.

And the generation submodule is used for generating a layout according to the outline pattern and the second topological pattern.

In one embodiment, the generating submodule is to:

the first corner is formed by a quadrilateral in a first twisted square pattern, the second corner is formed by a quadrilateral in a second twisted square pattern, the third corner is formed by a quadrilateral in a third twisted square pattern, and the fourth corner is formed by a quadrilateral in a fourth twisted square pattern.

The first corner is formed by a quadrilateral structure in a first twisted square pattern, the second corner is formed by a first triangular structure and a first additional triangular structure in a second twisted square pattern, wherein the first additional triangular structure is formed by a third quantum node mark positioned outside the first triangular structure and a first quantum node mark in a first direction and a first quantum node mark in a second direction in the first triangular structure, the third corner is formed by a quadrilateral structure in a third twisted square pattern, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square pattern.

The first corner is formed by a quadrilateral in a first twisted square pattern, the second corner is formed by a quadrilateral in a second twisted square pattern, the third corner is formed by a first triangle and a first additional triangle in a third twisted square pattern, wherein the first additional triangle is formed by a third quantum node identification located outside the first triangle and a first quantum node identification in a first orientation and a first quantum node identification in a second orientation in the first triangle, and the fourth corner is formed by a second triangle and a third triangle in a fourth twisted square pattern.

The first corner is formed by a first triangle structure and a first additional triangle structure in a first twisted square pattern, wherein the first additional triangle structure is formed by a third quantum node mark positioned outside the first triangle structure and a first quantum node mark in a first direction and a first quantum node mark in a second direction in the first triangle structure, the second corner is formed by a second triangle structure and a third triangle structure in a second twisted square pattern, the third corner is formed by a first triangle structure and a second additional triangle structure in a third twisted square pattern, the second additional triangle structure is formed by a fourth quantum node mark positioned outside the first triangle structure and a first quantum node mark in the first direction and a first quantum node mark in the second direction in the first triangle structure, and the fourth corner is formed by a second triangle structure and a third triangle structure in a fourth twisted square pattern.

In one embodiment, in the case where the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number n of preset quantum node identifiers in the profile pattern is an even number, the first corner is formed by a second quadrangular structure in the first twisted square pattern. The second corner is formed by a second quadrilateral in a second twisted square pattern. The third corner is formed by a second quadrilateral in a third twisted square pattern. The fourth corner is formed by a second quadrilateral in a fourth twisted square pattern.

The second quadrangle structure in the first twisted square pattern, the second quadrangle structure in the second twisted square pattern, the second quadrangle structure in the third twisted square pattern and the second quadrangle structure in the fourth twisted square pattern are all inclined rectangles rotated anticlockwise by the first angle.

In one embodiment, in the case where the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number n of preset quantum node identifiers in the profile pattern is an even number, the first corner is formed by a second quadrangular structure in the first twisted square pattern. The second corner is formed by the first quadrilateral in the second twisted square pattern. The third corner is formed by a second quadrilateral in a third twisted square pattern. The fourth corner is formed by the first quadrilateral in the fourth twisted square pattern.

The second quadrangle structures in the first twisted square pattern and the second quadrangle structures in the third twisted square pattern are inclined rectangles rotated counterclockwise by a first angle.

The first quadrangle structures in the second twisted square pattern and the first quadrangle structures in the fourth twisted square pattern are formed as inclined rectangles rotated clockwise by a second angle.

In one embodiment, the construction module 3410 is configured to:

and constructing a first topological pattern according to the preset interval between the quantum node identifiers.

In one embodiment, the spacing between the central quantum node identifier and the five first quantum node identifiers is a first threshold.

The distance between the first quantum node mark in the first azimuth and the first quantum node mark in the second azimuth is a first threshold value, and the distance between the first quantum node mark in the third azimuth and the first quantum node mark in the fourth azimuth and the distance between the first quantum node mark in the fifth azimuth are both first threshold values.

The distance between the second quantum node identifier in the sixth direction and the first quantum node identifier in the first direction and the distance between the second quantum node identifier in the fourth direction are both the first threshold value. The distance between the second quantum node identifier in the seventh azimuth and the first quantum node identifier in the second azimuth and the distance between the second quantum node identifier in the fifth azimuth are both the first threshold value.

In one embodiment, the spacing between the central quantum node identifier and the first quantum node identifier of the first azimuth, the first quantum node identifier of the second azimuth, the first quantum node identifier of the fourth azimuth, and the first quantum node identifier of the fifth azimuth are all a first threshold. The spacing between the central quantum node identifier and the first quantum node identifier of the third orientation is a second threshold.

The spacing between the first quantum node identification of the first orientation and the first quantum node identification of the second orientation is a second threshold. The distance between the first quantum node identifier in the third direction and the first quantum node identifier in the fourth direction and the distance between the first quantum node identifier in the fifth direction are both the first threshold value.

In one embodiment, the construction module 3410 is configured to:

and constructing a first topological pattern according to a preset coupling mode between the quantum node identifiers.

In one embodiment, the central quantum node identification and the five first quantum node identifications are each indirectly coupled through a coupler identification.

The first quantum node identification in the first azimuth is indirectly coupled with the first quantum node identification in the second azimuth through the coupler identification, and the first quantum node identification in the third azimuth is indirectly coupled with the first quantum node identification in the fourth azimuth and the first quantum node identification in the fifth azimuth through the coupler identification.

The second quantum node identifier in the sixth azimuth is indirectly coupled with the first quantum node identifier in the first azimuth and the first quantum node identifier in the fourth azimuth through the coupler identifier. The second quantum node identifier in the seventh azimuth is indirectly coupled with the first quantum node identifier in the second azimuth and the first quantum node identifier in the fifth azimuth through the coupler identifier.

In one embodiment, the central quantum node identity is directly coupled to all five first quantum node identities.

The first quantum node identifier of the first azimuth is directly coupled with the first quantum node identifier of the second azimuth, and the first quantum node identifier of the third azimuth is directly coupled with the first quantum node identifier of the fourth azimuth and the first quantum node identifier of the fifth azimuth.

The second quantum node identifier of the sixth orientation is directly coupled to both the first quantum node identifier of the first orientation and the first quantum node identifier of the fourth orientation. The second quantum node identifier of the seventh azimuth is directly coupled to both the first quantum node identifier of the second azimuth and the first quantum node identifier of the fifth azimuth.

For descriptions of specific functions and examples of each module and sub-module of the apparatus in the embodiments of the present disclosure, reference may be made to the related descriptions of corresponding steps in the foregoing method embodiments, which are not repeated herein.

The embodiment of the disclosure provides a manufacturing device of a quantum chip, which comprises:

and the manufacturing module is used for manufacturing the quantum chip structure according to any embodiment of the disclosure according to the layout generated by the layout generating method of the quantum chip structure according to any embodiment of the disclosure.

In the technical scheme of the disclosure, the acquisition, storage, application and the like of the related user personal information all conform to the regulations of related laws and regulations, and the public sequence is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 35 shows a schematic block diagram of an example electronic device 3500 that can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile apparatuses, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing apparatuses. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 35, the apparatus 3500 includes a computing unit 3501 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 3502 or a computer program loaded from a storage unit 3508 into a Random Access Memory (RAM) 3503. In the RAM 3503, various programs and data required for the operation of the apparatus 3500 can also be stored. The computing unit 3501, the ROM 3502, and the RAM 3503 are connected to each other via a bus 3504. An input/output (I/O) interface 3505 is also connected to bus 3504.

Various components in device 3500 connect to I/O interface 3505, including: an input unit 3506 such as a keyboard, a mouse, or the like; an output unit 3507 such as various types of displays, speakers, and the like; a storage unit 3508 such as a magnetic disk, an optical disk, or the like; and a communication unit 3509 such as a network card, a modem, a wireless communication transceiver, or the like. Communication unit 3509 allows device 3500 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

The computing unit 3501 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 3501 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 3501 performs the various methods and processes described above, e.g., the fabrication method of quantum chips and/or the layout design method of quantum chips. For example, in some embodiments, the method of manufacturing a quantum chip and/or the method of layout design of a quantum chip may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 3508. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 3500 via ROM 3502 and/or communication unit 3509. When the computer program is loaded into the RAM 3503 and executed by the computing unit 3501, one or more steps of the method of manufacturing a quantum chip and/or the method of layout design of a quantum chip described above can be performed. Alternatively, in other embodiments, the computing unit 3501 may be configured to perform the method of manufacturing the quantum chip and/or the method of layout design of the quantum chip in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

In the description of the present disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In this disclosure, unless explicitly stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed. Either mechanical or electrical or communication. Can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions, improvements, etc. that are within the principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A quantum chip structure comprising:

among the two second qubits: the second qubit of the sixth azimuth is coupled with the adjacent first qubit of the first azimuth and the adjacent first qubit of the fourth azimuth, respectively, and the second qubit of the seventh azimuth is coupled with the adjacent first qubit of the second azimuth and the adjacent first qubit of the fifth azimuth, respectively.

2. The quantum chip structure of claim 1, further comprising:

one end of the quantum bit control line is connected with a control line port of the target quantum bit, and the other end of the quantum bit control line is used for being connected with an external control system; and/or

One end of the reading resonant cavity is connected with a reading cavity port of the target quantum bit, the other end of the reading resonant cavity is connected with a reading line, and the reading line is used for being connected with the external control system;

wherein the target qubit is at least one of the following qubits:

The central qubit, the five first qubits, or the two second qubits.

3. The quantum chip structure of claim 1, further comprising:

the coupler is arranged between two adjacent qubits and is used for coupling the two adjacent qubits;

one end of the coupler control line is connected with a control line port of the coupler, and the other end of the coupler control line is used for being connected with an external control system;

wherein the adjacent two qubits are at least one of the following combinations:

one of the central qubit and the five first qubits, the first qubit of the first azimuth and the first qubit of the second azimuth, the first qubit of the third azimuth and the first qubit of the fourth azimuth, the first qubit of the third azimuth and the first qubit of the fifth azimuth, the second qubit of the sixth azimuth and the first qubit of the first azimuth, the second qubit of the sixth azimuth and the first qubit of the fourth azimuth, the second qubit of the seventh azimuth and the first qubit of the second azimuth, and the second qubit of the seventh azimuth and the first qubit of the fifth azimuth.

4. The quantum chip structure of claim 1, wherein the central qubit of any one twisted square cell may be any one of five first qubits or two second qubits of another twisted square cell.

5. The quantum chip structure of claim 1, wherein any one of the five first qubits or the two second qubits of any one twisted square cell may be the central qubit, any one of the five first qubits or the two second qubits of another twisted square cell.

6. The quantum chip structure of claim 1, wherein the outer side of the central qubit is sequentially formed with a first triangle structure, a first quadrangle structure, a second triangle structure, a third triangle structure, and a second quadrangle structure in a surrounding manner; wherein,,

the first triangle structure is composed of the central quantum bit, the first quantum bit of the first azimuth and the first quantum bit of the second azimuth;

the second triangle structure is composed of the central quantum bit, the first quantum bit of the third azimuth and the first quantum bit of the fifth azimuth;

The third triangle structure is composed of the central quantum bit, the first quantum bit of the third azimuth and the first quantum bit of the fourth azimuth;

the first quadrilateral structure is composed of the central qubit, the first qubit of the second azimuth, the first qubit of the fifth azimuth and the second qubit of the seventh azimuth;

the second quadrangle structure is composed of the central qubit, the first qubit of the first azimuth, the first qubit of the fourth azimuth and the second qubit of the sixth azimuth.

7. The quantum chip structure of claim 6, wherein at least one of the first, second, and third triangular structures is an equilateral triangle structure; or alternatively, the first and second heat exchangers may be,

at least one of the first triangular structure, the second triangular structure and the third triangular structure is an isosceles triangular structure.

8. The quantum chip structure of claim 6, wherein at least one of the first and second quadrilateral structures is a square structure.

9. The quantum chip structure of any one of claims 1 to 8, wherein the central qubit, the five first qubits, and the two second qubits lie in the same plane.

10. The quantum chip structure of any one of claims 1 to 8, wherein a spacing between the central qubit and the five first qubits is a first threshold;

the interval between the first quantum bit in the first azimuth and the first quantum bit in the second azimuth is a first threshold value, and the interval between the first quantum bit in the third azimuth and the first quantum bit in the fourth azimuth and the interval between the first quantum bit in the fifth azimuth are both first threshold values;

the interval between the second qubit in the sixth direction and the first qubit in the first direction and the interval between the second qubit in the fourth direction are both first thresholds; and the spacing between the second qubit in the seventh azimuth and the first qubit in the second azimuth and the first qubit in the fifth azimuth are both a first threshold value.

11. The quantum chip structure of any one of claims 1 to 8, wherein the spacing between the central qubit and the first qubit of the first orientation, the first qubit of the second orientation, the first qubit of the fourth orientation, and the first qubit of the fifth orientation are all a first threshold; the distance between the central qubit and the first qubit in the third direction is a second threshold;

The interval between the first qubit of the first azimuth and the first qubit of the second azimuth is a second threshold; the first qubit in the third direction and the first qubit in the fourth direction are separated from the first qubit in the fifth direction by a first threshold;

12. The quantum chip structure of any one of claims 1 to 8, wherein the central qubit and the five first qubits are each indirectly coupled by a coupler;

the first qubit in the first azimuth and the first qubit in the second azimuth are indirectly coupled through a coupler, and the first qubit in the third azimuth, the first qubit in the fourth azimuth and the first qubit in the fifth azimuth are indirectly coupled through a coupler;

The second qubit in the sixth direction is indirectly coupled with the first qubit in the first direction and the first qubit in the fourth direction through a coupler; and the second qubit in the seventh azimuth is indirectly coupled with the first qubit in the second azimuth and the first qubit in the fifth azimuth through a coupler.

13. The quantum chip structure of any one of claims 1 to 8, wherein the central qubit is directly coupled to the five first qubits;

the first qubit of the first azimuth is directly coupled with the first qubit of the second azimuth, and the first qubit of the third azimuth is directly coupled with the first qubit of the fourth azimuth and the first qubit of the fifth azimuth;

the second qubit of the sixth azimuth is directly coupled with both the first qubit of the first azimuth and the first qubit of the fourth azimuth; the second qubit of the seventh orientation is directly coupled to both the first qubit of the second orientation and the first qubit of the fifth orientation.

14. The quantum chip structure of any one of claims 1 to 13, further comprising:

A topological structure layer having an outer edge profile of a predetermined shape; the topology is disposed in the topology layer.

15. The quantum chip structure of claim 14, wherein the predetermined shape of the outer edge profile is one of rectangular, slanted rectangular rotated by a predetermined angle, circular or elliptical.

16. The quantum chip structure of claim 14, wherein in case the preset shape of the outer edge profile is a rectangle, the topology is a polygonal structure including first and third corners located on a first diagonal, and second and fourth corners located on a second diagonal.

17. The quantum chip structure of claim 16, wherein the shape structures of the first, second, third and fourth corners are one of four combinations:

the first corners are formed by quadrilateral structures in first twisted square units, the second corners are formed by quadrilateral structures in second twisted square units, the third corners are formed by quadrilateral structures in third twisted square units, and the fourth corners are formed by quadrilateral structures in fourth twisted square units;

The first corner is formed by a quadrilateral structure in a first twisted square unit, the second corner is formed by a first triangular structure and a first additional triangular structure in a second twisted square unit, wherein the first additional triangular structure is formed by a third qubit positioned outside the first triangular structure and a first qubit in a first direction and a first qubit in a second direction in the first triangular structure, the third corner is formed by a quadrilateral structure in a third twisted square unit, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square unit;

the first corner is formed by a quadrilateral structure in a first twisted square unit, the second corner is formed by a quadrilateral structure in a second twisted square unit, the third corner is formed by a first triangular structure and a first additional triangular structure in a third twisted square unit, wherein the first additional triangular structure is formed by a third qubit positioned outside the first triangular structure and a first qubit in a first direction and a first qubit in a second direction in the first triangular structure, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square unit;

The first corner is formed by a first triangle structure and a first additional triangle structure in a first twisted square unit, wherein the first additional triangle structure is formed by a third qubit positioned outside the first triangle structure and a first qubit in a first direction and a first qubit in a second direction in the first triangle structure, the second corner is formed by a second triangle structure and a third triangle structure in a second twisted square unit, the third corner is formed by a first triangle structure and a second additional triangle structure in a third twisted square unit, wherein the second additional triangle structure is formed by a fourth qubit positioned outside the first triangle structure and a first qubit in the first direction and a first qubit in the second direction in the first triangle structure, and the fourth corner is formed by a second triangle structure and a third triangle structure in a fourth twisted square unit.

18. The quantum chip structure of claim 14, wherein, in case that the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number m of preset qubits in the topology layer is an even number, the topology is a polygonal structure including a first corner and a second corner located on a first diagonal, and a third corner and a fourth corner located on a second diagonal; wherein,,

The first corner is formed by a second quadrilateral structure in the first twisted square unit;

the second corner is formed by a second quadrilateral structure in a second twisted square unit;

the third corner is formed by a second quadrilateral structure in a third twisted square unit;

the fourth corner is formed by a second quadrilateral structure in a fourth twisted square unit;

the second quadrilateral structure in the first twisted square unit, the second quadrilateral structure in the second twisted square unit, the second quadrilateral structure in the third twisted square unit and the second quadrilateral structure in the fourth twisted square unit are all inclined rectangles rotating anticlockwise by a first angle.

19. The quantum chip structure of claim 14, wherein, in case that the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number m of preset qubits in the topology layer is an even number, the topology is a polygonal structure including a first corner and a second corner located on a first diagonal, and a third corner and a fourth corner located on a second diagonal; wherein,,

the second corners are formed by first quadrilateral structures in the second twisted square units;

the fourth corner is formed by a first quadrilateral structure in a fourth twisted square unit;

the second quadrilateral structure in the first twisted square unit and the second quadrilateral structure in the third twisted square unit are both inclined rectangles rotated anticlockwise by a first angle;

the first quadrangle structure in the second twisted square unit and the first quadrangle structure in the fourth twisted square unit are both inclined rectangles rotated clockwise by a second angle.

20. The quantum chip structure of any one of claims 1 to 19, further comprising:

at least one fifth qubit disposed at least outside of any edge of the topology and coupled with at least two qubits located on the any edge; wherein the at least two qubits are any two qubits among the five first qubits or the two second qubits.

21. The quantum chip structure of any one of claims 1 to 20, wherein the planar configuration connectivity parameter of the topology is less than 0.57.

22. A layout generation method of a quantum chip structure comprises the following steps:

constructing a first topological pattern;

generating a layout for manufacturing the quantum chip structure of any one of claims 1 to 21 from the second topological pattern; wherein,,

each twisted square pattern comprises a central quantum node identifier, five first quantum node identifiers adjacent to the central quantum node identifier, and two second quantum node identifiers not adjacent to the central quantum node identifier; the central quantum node identifiers are respectively coupled with the five first quantum node identifiers;

Among the two second quantum node identifications: the second quantum node identifier of the sixth azimuth is respectively coupled with the first quantum node identifier of the adjacent first azimuth and the first quantum node identifier of the adjacent fourth azimuth, and the second quantum node identifier of the seventh azimuth is respectively coupled with the first quantum node identifier of the adjacent second azimuth and the first quantum node identifier of the adjacent fifth azimuth.

23. The method of claim 22, wherein determining a second topology pattern from the first topology patterns according to a preset number of qubits comprises:

determining a third topological pattern in the first topological pattern according to the number of preset quantum bits, wherein each quantum node identifier in the third topological pattern is a quantum node identifier forming a twisted square pattern;

setting a fifth quantum node identifier outside the edge of the third topological pattern under the condition that the number of quantum node identifiers of the third topological pattern is smaller than the number of preset quantum bits, wherein the fifth quantum node identifier is coupled with at least two quantum node identifiers on the edge; wherein the at least two quantum node identifiers are quantum node identifiers among the five first quantum node identifiers or the two second quantum node identifiers;

24. The method of claim 22, wherein generating a layout from the second topological pattern comprises:

determining a contour pattern arranged outside the second topological pattern according to the second topological pattern, wherein the contour pattern has an outer edge contour with a preset shape;

25. The method of claim 24, wherein the predetermined shape of the outer edge profile is one of rectangular, sloped rectangular rotated by a predetermined angle, circular, or elliptical.

26. The method of claim 24, wherein generating a layout from the outline pattern and the second topology pattern comprises:

and determining the shape structures of the first corner and the third corner of the second topological pattern on the first diagonal line and the shape structures of the second corner and the fourth corner of the second diagonal line according to the outline pattern.

27. The method of claim 26, wherein, in the case where the preset shape of the outer edge contour of the contour pattern is rectangular, the shape structures of the first, second, third and fourth corners are one of four combinations:

The first corners are formed by quadrilateral structures in a first twisted square pattern, the second corners are formed by quadrilateral structures in a second twisted square pattern, the third corners are formed by quadrilateral structures in a third twisted square pattern, and the fourth corners are formed by quadrilateral structures in a fourth twisted square pattern;

the first corner is formed by a quadrilateral structure in a first twisted square pattern, the second corner is formed by a first triangular structure and a first additional triangular structure in a second twisted square pattern, wherein the first additional triangular structure is formed by a third quantum node identifier positioned outside the first triangular structure and a first quantum node identifier in a first direction and a first quantum node identifier in a second direction in the first triangular structure, the third corner is formed by a quadrilateral structure in a third twisted square pattern, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square pattern;

the first corner is formed by a quadrilateral structure in a first twisted square pattern, the second corner is formed by a quadrilateral structure in a second twisted square pattern, the third corner is formed by a first triangular structure and a first additional triangular structure in a third twisted square pattern, wherein the first additional triangular structure is formed by a third quantum node identifier positioned outside the first triangular structure and a first quantum node identifier in a first direction and a first quantum node identifier in a second direction in the first triangular structure, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square pattern;

The first corner is formed by a first triangular structure and a first additional triangular structure in a first twisted square pattern, wherein the first additional triangular structure is formed by a third quantum node identifier located outside the first triangular structure and a first quantum node identifier in a first direction and a first quantum node identifier in a second direction in the first triangular structure, the second corner is formed by a second triangular structure and a third triangular structure in a second twisted square pattern, the third corner is formed by a first triangular structure and a second additional triangular structure in a third twisted square pattern, wherein the second additional triangular structure is formed by a fourth quantum node identifier located outside the first triangular structure and a first quantum node identifier in the first direction and a first quantum node identifier in the second direction in the first triangular structure, and the fourth corner is formed by a second triangular structure and a third triangular structure in a fourth twisted square pattern.

28. The method of claim 26, wherein the first side angle is formed by a second tetragonal structure in a first twisted square pattern in a case where a preset shape of an outer edge contour of the contour pattern is an inclined rectangle rotated by a preset angle and a number n of preset quantum node identifications in the contour pattern is an even number; the second corner is formed by a second quadrilateral in a second twisted square pattern; the third corner is formed by a second quadrilateral in a third twisted square pattern; the fourth corner is formed by a second quadrilateral in a fourth twisted square pattern;

The second quadrangle structure in the first twisted square pattern, the second quadrangle structure in the second twisted square pattern, the second quadrangle structure in the third twisted square pattern and the second quadrangle structure in the fourth twisted square pattern are all inclined rectangles rotated anticlockwise by a first angle.

29. The method of claim 26, wherein the first side angle is formed by a second quadrilateral in a first twisted square pattern in the case where a preset shape of an outer edge profile of the profile pattern is an inclined rectangle rotated by a preset angle and a number n of preset quantum node identifications in the profile pattern is an even number; the second corners are formed by first quadrilateral structures in a second twisted square pattern; the third corner is formed by a second quadrilateral in a third twisted square pattern; the fourth corner is formed by a first quadrilateral in a fourth twisted square pattern;

the second quadrangle structures in the first twisted square patterns and the second quadrangle structures in the third twisted square patterns are inclined rectangles rotated anticlockwise by a first angle;

the first quadrangle structures in the second twisted square patterns and the first quadrangle structures in the fourth twisted square patterns are formed by inclined rectangles which rotate clockwise by a second angle.

30. A method according to any one of claims 22 to 29, wherein the central quantum node identity of any one twisted square pattern may be any one of the five first quantum node identities or the two second quantum node identities of another twisted square pattern.

31. A method according to any of claims 22 to 29, wherein any one of the five first quantum node identities or the two second quantum node identities of any one twisted square pattern may be the central quantum node identity, the five first quantum node identities or the two second quantum node identities of another twisted square pattern.

32. The method of any one of claims 22 to 29, wherein the outer side of the central quantum node identifier is sequentially encircled with a first triangular structure, a first quadrilateral structure, a second triangular structure, a third triangular structure, and a second quadrilateral structure; wherein,,

the first triangle structure is composed of the central quantum node identifier, the first quantum node identifier of the first azimuth and the first quantum node identifier of the second azimuth;

The second triangle structure is composed of the central quantum node identifier, the first quantum node identifier in the third direction and the first quantum node identifier in the fifth direction;

the third triangle structure is composed of the central quantum node identifier, the first quantum node identifier in the third direction and the first quantum node identifier in the fourth direction;

the first quadrilateral structure is composed of the center quantum node identifier, the first quantum node identifier of the second azimuth, the first quantum node identifier of the fifth azimuth and the second quantum node identifier of the seventh azimuth;

the second quadrilateral structure is composed of the center quantum node identifier, the first quantum node identifier of the first azimuth, the first quantum node identifier of the fourth azimuth and the second quantum node identifier of the sixth azimuth.

33. The method of any one of claims 22 to 29, wherein constructing a first topological pattern comprises:

and constructing the first topological pattern according to the preset interval between the quantum node identifiers.

34. The method of claim 33, wherein a preset spacing between the central quantum node identification and the five first quantum node identifications is a first threshold;

The preset distance between the first quantum node identifier in the first azimuth and the first quantum node identifier in the second azimuth is a first threshold value, and the preset distance between the first quantum node identifier in the third azimuth and the first quantum node identifier in the fourth azimuth and the preset distance between the first quantum node identifier in the fifth azimuth are both first threshold values;

the preset distance between the second quantum node identifier in the sixth direction and the first quantum node identifier in the first direction and the preset distance between the second quantum node identifier in the fourth direction are both a first threshold value; and the preset distance between the second quantum node identifier in the seventh azimuth and the first quantum node identifier in the second azimuth and the preset distance between the second quantum node identifier in the fifth azimuth and the preset distance between the second quantum node identifier in the seventh azimuth and the first quantum node identifier in the second azimuth are both a first threshold value.

35. The method of claim 33, wherein the preset spacing between the central quantum node identifier and the first quantum node identifier of the first azimuth, the first quantum node identifier of the second azimuth, the first quantum node identifier of the fourth azimuth, and the first quantum node identifier of the fifth azimuth are all a first threshold; the preset distance between the central quantum node mark and the first quantum node mark in the third direction is a second threshold value;

The preset distance between the first quantum node mark in the first azimuth and the first quantum node mark in the second azimuth is a second threshold; the preset distance between the first quantum node identifier in the third direction and the first quantum node identifier in the fourth direction and the preset distance between the first quantum node identifier in the fifth direction are both a first threshold value;

36. The method of any one of claims 22 to 29, wherein constructing a first topological pattern comprises:

37. The method of claim 36, wherein the central quantum node identification and the five first quantum node identifications are each indirectly coupled by a coupler identification;

The first quantum node identifier in the first azimuth is indirectly coupled with the first quantum node identifier in the second azimuth through a coupler identifier, and the first quantum node identifier in the third azimuth is indirectly coupled with the first quantum node identifier in the fourth azimuth and the first quantum node identifier in the fifth azimuth through the coupler identifier;

the second quantum node identifier in the sixth azimuth is indirectly coupled with the first quantum node identifier in the first azimuth and the first quantum node identifier in the fourth azimuth through the coupler identifier; and the second quantum node identifier in the seventh azimuth is indirectly coupled with the first quantum node identifier in the second azimuth and the first quantum node identifier in the fifth azimuth through coupler identifiers.

38. The method of claim 36, wherein the central quantum node identity is directly coupled to each of the five first quantum node identities;

the first quantum node identifier of the first azimuth is directly coupled with the first quantum node identifier of the second azimuth, and the first quantum node identifier of the third azimuth is directly coupled with the first quantum node identifier of the fourth azimuth and the first quantum node identifier of the fifth azimuth;

The second quantum node identifier in the sixth azimuth is directly coupled with the first quantum node identifier in the first azimuth and the first quantum node identifier in the fourth azimuth; the second quantum node identifier of the seventh azimuth is directly coupled with both the first quantum node identifier of the second azimuth and the first quantum node identifier of the fifth azimuth.

39. A method of manufacturing a quantum chip, comprising:

a quantum chip structure according to any one of claims 1 to 21 is manufactured using a layout generated by the layout generation method of the quantum chip structure according to any one of claims 22 to 38.

40. A layout generation device of a quantum chip structure, comprising:

a building module for building a first topological pattern;

the determining module is used for determining a second topological pattern from the first topological patterns according to the number of preset qubits, and the first topological pattern and the second topological pattern are formed by a plurality of twisted square patterns in a closely-packed mode;

a generation module for generating a layout for fabricating the quantum chip structure of any one of claims 1 to 21 from the second topological pattern; wherein,,

41. The apparatus of claim 40, wherein the means for determining is configured to:

42. The apparatus of claim 40, wherein the means for generating comprises:

the first determining submodule is used for determining a contour pattern arranged outside the second topological pattern according to the second topological pattern, and the contour pattern is provided with an outer edge contour with a preset shape;

43. The apparatus of claim 42, wherein the generating sub-module is configured to:

44. The apparatus of claim 43, wherein, in the case where the preset shape of the outer edge contour of the contour pattern is rectangular, the shape structures of the first, second, third and fourth corners are one of four combinations:

45. The apparatus of claim 43, wherein the first side angle is formed by a second quadrilateral in a first twisted square pattern in the case where the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number n of preset quantum node identifications in the profile pattern is an even number; the second corner is formed by a second quadrilateral in a second twisted square pattern; the third corner is formed by a second quadrilateral in a third twisted square pattern; the fourth corner is formed by a second quadrilateral in a fourth twisted square pattern;

46. The apparatus of claim 43, wherein the first side angle is formed by a second quadrilateral in a first twisted square pattern in the case where the preset shape of the outer edge profile is an inclined rectangle rotated by a preset angle and the number n of preset quantum node identifications in the profile pattern is an even number; the second corners are formed by first quadrilateral structures in a second twisted square pattern; the third corner is formed by a second quadrilateral in a third twisted square pattern; the fourth corner is formed by a first quadrilateral in a fourth twisted square pattern;

47. The apparatus of any one of claims 40 to 46, wherein the build module is to:

48. The apparatus of claim 47, wherein a spacing between the central quantum node identifier and the five first quantum node identifiers is a first threshold;

the distance between the first quantum node mark in the first azimuth and the first quantum node mark in the second azimuth is a first threshold value, and the distance between the first quantum node mark in the third azimuth and the first quantum node mark in the fourth azimuth and the distance between the first quantum node mark in the fifth azimuth are both first threshold values;

the distance between the second quantum node mark in the sixth direction and the first quantum node mark in the first direction and the distance between the second quantum node mark in the fourth direction are both a first threshold value; and the distance between the second quantum node identifier in the seventh azimuth and the first quantum node identifier in the second azimuth and the distance between the second quantum node identifier in the fifth azimuth and the distance between the second quantum node identifier in the seventh azimuth and the first quantum node identifier in the second azimuth are both a first threshold value.

49. The apparatus of claim 47, wherein the spacing between the central quantum node identity and the first quantum node identity of the first bearing, the first quantum node identity of the second bearing, the first quantum node identity of the fourth bearing, and the first quantum node identity of the fifth bearing is a first threshold; the distance between the central quantum node mark and the first quantum node mark in the third azimuth is a second threshold value;

The distance between the first quantum node mark in the first azimuth and the first quantum node mark in the second azimuth is a second threshold value; the distance between the first quantum node mark in the third azimuth and the first quantum node mark in the fourth azimuth and the distance between the first quantum node mark in the fifth azimuth are both first thresholds;

50. The apparatus of any one of claims 40 to 46, wherein the build module is to:

51. The apparatus of claim 50, wherein the central quantum node identity and the five first quantum node identities are each indirectly coupled through a coupler identity;

52. The apparatus of claim 50, wherein the central quantum node identity is directly coupled to each of the five first quantum node identities;

53. An apparatus for manufacturing a quantum chip, comprising:

a manufacturing module for manufacturing the quantum chip structure of any one of claims 1 to 21 according to the layout generated by the layout generating method of the quantum chip structure of any one of claims 22 to 38.

54. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 22 to 39.

55. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 22 to 39.

56. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 22 to 39.