CN116384323A - Method, device, equipment and storage medium for compensating parasitic parameter cascade error - Google Patents

Method, device, equipment and storage medium for compensating parasitic parameter cascade error Download PDF

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CN116384323A
CN116384323A CN202310406933.XA CN202310406933A CN116384323A CN 116384323 A CN116384323 A CN 116384323A CN 202310406933 A CN202310406933 A CN 202310406933A CN 116384323 A CN116384323 A CN 116384323A
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parasitic
circuit
port
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曹小华
陈清华
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Hangzhou Clounix Technology Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a method, a device, equipment and a storage medium for compensating parasitic parameter cascade errors, which comprise the following steps: obtaining port circuits of all ports and parasitic parameters of all circuit elements in the port circuits by using a high-speed serial cascade link to be simulated; adding a compensation circuit corresponding to the port circuit at each port to eliminate errors caused by parasitic parameters of the port; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative. According to the embodiment of the invention, the compensation circuit is added at the port, so that the influence of parasitic parameters of each cascade port on the cascade result can be eliminated, and the accuracy of the cascade result is improved.

Description

Method, device, equipment and storage medium for compensating parasitic parameter cascade error
Technical Field
The invention belongs to the technical field of chips, and particularly relates to a method, a device, equipment and a storage medium for compensating parasitic parameter cascade errors.
Background
The data transmission rate of the current communication system reaches 10Gbps or more, fig. 1 is a block diagram of a typical high-speed backboard system, a SERDES chip sends signals, a FANOUT is packaged to a layer-changing via hole through a BGA, wires are routed through a daughter card, a backboard channel is arranged on a connector, the signals pass through a backboard channel and then pass through the connector to another daughter card, and the signals reach a chip receiving end through an AC coupling capacitor. In such a system, a high-speed serial link with a length of up to one meter is visible everywhere in the system, and when the system is subjected to simulation analysis, a frequency sweep of 20GHz or more is generally required, and the requirement of high bandwidth and high accuracy makes it necessary to solve the system link by adopting 3D electromagnetic simulation software during simulation. In order to obtain the long and complex link frequency response characteristics, the 3D electromagnetic simulation software is adopted to extract the channel parameters once, so that time and labor are wasted, a large amount of solving time is required, and engineering application is not facilitated.
Aiming at the problem that the S parameter of the whole link cannot be extracted at one time during high-speed serial link simulation, the current solution is to divide the link into a plurality of parts according to the structural characteristics of the link, as shown in fig. 2. Assuming that the S parameter of the link is that the link is divided into fifteen parts according to the characteristic of the link structure, and the S parameter of the link is that: chip-BGA through Kong daughter card wiring-AC coupling capacitance-daughter card wiring-daughter card connector via-connector-back board connector via-back board wiring-back board connector via-connector-daughter card connector through Kong daughter card wiring-BGA via-chip, assuming that their S parameters are respectively in sequence, the S parameter flow of each part extracted by adopting 3D electromagnetic software is shown in FIG. 3.
This can be achieved by 3D electromagnetic software
Figure SMS_1
、/>
Figure SMS_2
、…、/>
Figure SMS_3
S parameter of the whole system, thus S parameter +.>
Figure SMS_4
By the method, the S parameter of the whole system can be conveniently obtained,thereby achieving the purpose of evaluating the performance of the whole link.
In order to acquire S parameters of a link, the link is divided into a plurality of parts according to the structural characteristics of the link, S parameters of the parts are extracted by using simulation software, and then the S parameters are cascaded to acquire the S parameters of the whole link. However, this cascading method brings another problem at the same time, according to the extraction flow of the S parameters of each part described in fig. 3, in the process of solving the S parameters, excitation signals need to be added at two ends of each part model to solve, and the excitation signals are called as feed ports in 3D electromagnetic simulation software. The most commonly used 3D electromagnetic simulation software in the industry today are HFSS and CST MWS, whether HFSS or CST MWS, with similar feed ports. Taking HFSS as an example, there are two feed ports: when the HFSS is used to extract the S parameters of each part of the link, both the Lumped Port feed and the Wave Port feed are used, due to the non-ideal nature of the feed ports, the ports themselves have parasitic inductances and parasitic capacitances to ground, which will ultimately be incorporated into the extracted S parameter model. If parasitic parameters of the feed port are considered, the cascade link structure of fig. 2 will be changed to the structure form shown in fig. 4, and the need for the link is eliminated
Figure SMS_5
、/>
Figure SMS_6
、…、/>
Figure SMS_7
Besides, parasitic parameter information of the feed port is carried, and S parameters of the whole system are changed into: />
Figure SMS_8
Due to the existence of the parasitic parameters of the ports, the S parameters of the system link obtained by cascading and the actual S parameters are deviated, so that the performance of the system is accurately evaluated.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a method, apparatus, device and storage medium for compensating parasitic parameter cascade error, so as to improve the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a method of compensating for parasitic parameter cascading errors, comprising:
obtaining port circuits of all ports and parasitic parameters of all circuit elements in the port circuits by using a high-speed serial cascade link to be simulated;
adding a compensation circuit corresponding to the port circuit at each port to eliminate errors caused by parasitic parameters of the port; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
Preferably, the parasitic parameter includes parasitic inductance and parasitic capacitance, and the parameter of each circuit element of the compensation circuit includes negative inductance corresponding to the parasitic inductance and negative capacitance corresponding to the parasitic capacitance.
Preferably, the high-speed serial cascade link is formed by connecting a plurality of modules in a chip, a connector via, a BGA via and a wire according to a preset connection sequence.
Preferably, adjacent modules are connected through the ports.
The embodiment of the invention also provides a device for compensating the parasitic parameter cascade error, which comprises:
the parameter acquisition module is used for acquiring the port circuit of each port and the parasitic parameters of each circuit element in the port circuit;
the compensation module is used for adding a compensation circuit corresponding to the port circuit at each port so as to eliminate errors caused by parasitic parameters of the ports; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
Preferably, the parasitic parameter includes parasitic inductance and parasitic capacitance, and the parameter of each circuit element of the compensation circuit includes negative inductance corresponding to the parasitic inductance and negative capacitance corresponding to the parasitic capacitance.
Preferably, the high-speed serial cascade link is formed by connecting a plurality of modules in a chip, a connector via, a BGA via and a wire according to a preset connection sequence.
Preferably, adjacent modules are connected through the ports.
The embodiment of the invention also provides equipment for compensating the parasitic parameter cascade error, which comprises a memory and a processor, wherein the memory stores a computer program which can be executed by the processor to realize the method for compensating the parasitic parameter cascade error.
Embodiments of the present invention also provide a computer readable storage medium storing a computer program executable by the processor to implement a method of compensating for parasitic parameter cascade errors as described above.
According to the embodiment of the invention, the compensation circuit is added at the port, so that the influence of parasitic parameters of each cascade port on the cascade result can be eliminated, and the accuracy of the cascade result is improved.
Drawings
Fig. 1 is a block diagram of a conventional high-speed backplane system.
Fig. 2 is a diagram of a conventional high-speed serial cascade link.
Fig. 3 is a flow chart of the S-parameter extraction of the conventional 3D electromagnetic software.
Fig. 4 is a diagram of a prior art high-speed serial concatenated link with port parasitic parameters.
Fig. 5 is a flowchart of a method for compensating a parasitic parameter cascade error according to a first embodiment of the present invention.
Fig. 6 is a circuit diagram of a microstrip transmission line model.
Fig. 7 is a schematic diagram of the compensation circuit added to the circuit of fig. 6.
Fig. 8 is a diagram of a high-speed serial concatenated link with port parasitics of the compensation circuit.
Fig. 9 is a diagram of a full link model structure including two pairs of vias and a pair of differential striplines.
Fig. 10 is a schematic diagram of the compensation circuit added to fig. 9.
Fig. 11 (a) - (b) are graphs of insertion loss and reflection loss versus a full model structure, uncompensated port parasitic parameters, and compensated port parasitic parameters.
Fig. 12 is a schematic structural diagram of an apparatus for compensating a parasitic parameter cascade error according to a second embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to specific examples and drawings.
Referring to fig. 5, a first embodiment of the present invention provides a method for compensating a parasitic parameter cascade error, which may be performed by an apparatus for compensating a parasitic parameter cascade error (hereinafter referred to as a compensating apparatus), and in particular, by one or more processors in the compensating apparatus, so as to implement the following method:
s101, obtaining port circuits of all ports and parasitic parameters of all circuit elements in the port circuits by the high-speed serial cascade link to be simulated.
In this embodiment, the compensation device may be a terminal having data processing capability, such as a personal computer, workstation, server, or the like. The compensation device may be provided with a corresponding operating system and an application program, such as simulation software, and the processor may implement the steps of this embodiment by executing the simulation software.
In this embodiment, a high-speed serial cascade link to be emulated needs to be first constructed. The high-speed serial cascade link is typically formed by connecting a plurality of modules in a chip, a connector via, a BGA via, a trace (typically a strip line) in a predetermined connection order. For example, as shown in fig. 2, fig. 2 shows a circuit diagram of a possible high-speed serial cascade link, but it should be understood that, in other embodiments of the present invention, the modules included in the high-speed serial cascade link and the connection relationships between the modules may be set according to actual needs, and these solutions are all within the scope of the present invention.
In this embodiment, the modules of the high-speed serial cascade link are connected through ports. Therefore, after the high-speed serial cascade link is built, the port circuit of each port and the parasitic parameters of each circuit element in the port circuit need to be obtained.
As shown in fig. 6, fig. 6 shows a microstrip transmission line model including a port A, C and a microstrip line B, assuming that the parasitic parameters of the port a are
Figure SMS_9
The parasitic parameter of port C is +.>
Figure SMS_10
Microstrip line parameter +.>
Figure SMS_11
. It can be seen that the port circuits of port a and port C include one parasitic capacitance and one parasitic inductance. Of course, other circuit elements or more than one parasitic capacitor or parasitic inductance may be included in other port circuits, which are within the scope of the present invention.
S102, adding a compensation circuit corresponding to the port circuit at each port to eliminate errors caused by parasitic parameters of the ports; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
In the present embodiment, in FIG. 6, parasitic parameters of ports additionally introduced by cascading
Figure SMS_12
，/>
Figure SMS_13
Will cause cascade errors, in order to solve this problem, the present embodiment is directed to portsCascade errors due to parasitic parameters propose a compensation method by extracting the parasitic parameter matrix of the port +.>
Figure SMS_14
，/>
Figure SMS_15
The inverse matrix of them is obtained by means of a correlation mathematical operation>
Figure SMS_16
，/>
Figure SMS_17
Thereby obtaining accurate microstrip line S parameter without parasitic parameter of feed port:
Figure SMS_18
for the model shown in fig. 6, the ports have only their own parasitic inductance L and parasitic capacitance C to ground, so when the circuit simulation software is cascaded, in order to compensate the parasitic inductance L and the parasitic capacitance C of the ports, in this embodiment, a compensation circuit is connected to each port, and the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit, and the positive and negative are opposite, so that the errors caused by the parasitic parameters of the ports can be eliminated, thereby improving the accuracy of the cascade of the parameters of the system S, as shown in fig. 7.
According to the expansion of the thought, a compensation circuit is introduced into each port of the high-speed serial cascade link with the port parasitic parameters of the circuit structure shown in the figure 8, so that the high-speed serial cascade link with the compensation circuit is obtained.
In order to verify the feasibility of the present embodiment, the application of the present embodiment will be described below in practical examples.
For convenience of analysis, the present embodiment takes the model structure of fig. 9 as a link structure to be analyzed, and the structure includes two pairs of differential vias and a pair of differential striplines.
According to the structural characteristics of the link, the link is divided into three parts: the differential via hole, the differential strip line and the other pair of differential via holes have the same port size due to the symmetry of the structure, so that the parasitic parameters of the ports are also the same, and the parasitic inductance of the ports at the cascade position is extracted by using the parasitic parameter extraction software
Figure SMS_19
And parasitic capacitance->
Figure SMS_20
The negative values of the parasitic inductance and parasitic capacitance are added to the cascade circuit, and the cascade circuit with the port parasitic parameter compensation circuit is obtained as shown in fig. 10.
Fig. 11 (a) and 11 (b) are respectively full model structures, uncompensated port parasitic parameters and insertion loss and reflection loss comparison cases of the compensated port parasitic parameters, and as can be seen from fig. 11 (a) and 11 (b), the results obtained by compensating the cascade port parasitic parameters and the results obtained by full model consistency simulation are relatively close to each other in both insertion loss and reflection loss, while the structures obtained by uncompensated cascade port parasitic parameters have larger differences. By introducing the cascade port compensation circuit, cascade errors caused by parasitic parameters of the ports are eliminated, and the accuracy of cascade results is improved.
Referring to fig. 12, an embodiment of the present invention further provides an apparatus for compensating a parasitic parameter cascade error, which includes:
the parameter obtaining module 210 is configured to obtain the port circuit of each port and the parasitic parameters of each circuit element in the port circuit, for the high-speed serial cascade link to be simulated;
a compensation module 220, configured to add a compensation circuit corresponding to the port circuit at each port, so as to eliminate errors caused by parasitic parameters of the port; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
Preferably, the parasitic parameter includes parasitic inductance and parasitic capacitance, and the parameter of each circuit element of the compensation circuit includes negative inductance corresponding to the parasitic inductance and negative capacitance corresponding to the parasitic capacitance.
Preferably, the high-speed serial cascade link is formed by connecting a plurality of modules in a chip, a connector via, a BGA via and a wire according to a preset connection sequence.
Preferably, adjacent modules are connected through the ports.
The third embodiment of the present invention also provides an apparatus for compensating a parasitic parameter cascade error, which includes a memory and a processor, where the memory stores a computer program, and the computer program is capable of being executed by the processor to implement a method for compensating a parasitic parameter cascade error as described above.
The fourth embodiment of the present invention also provides a computer readable storage medium storing a computer program executable by the processor to implement a method of compensating for parasitic parameter cascade errors as described above.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus and method embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, an electronic device, a network device, or the like) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of compensating for parasitic parameter cascading errors, comprising:
obtaining port circuits of all ports and parasitic parameters of all circuit elements in the port circuits by using a high-speed serial cascade link to be simulated;
adding a compensation circuit corresponding to the port circuit at each port to eliminate errors caused by parasitic parameters of the port; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
2. The method of compensating for a cascading error of parasitic parameters of claim 1, wherein the parasitic parameters include parasitic inductance and parasitic capacitance, and the parameters of each circuit element of the compensation circuit include negative inductance corresponding to the parasitic inductance and negative capacitance corresponding to the parasitic capacitance.
3. The method of compensating for parasitic parameter cascading errors of claim 1, wherein the high-speed serial cascading links are formed by connecting a plurality of modules in a chip, a connector via, a BGA via, a trace in a predetermined connection order.
4. A method of compensating for parasitic parameter cascading errors in accordance with claim 3, wherein adjacent modules are connected through said ports.
5. An apparatus for compensating for parasitic parameter cascading errors, comprising:
the parameter acquisition module is used for acquiring the port circuit of each port and the parasitic parameters of each circuit element in the port circuit;
the compensation module is used for adding a compensation circuit corresponding to the port circuit at each port so as to eliminate errors caused by parasitic parameters of the ports; the compensation circuit is connected with the port circuit, the circuit structure of the compensation circuit is the same as that of the port circuit, and the parameters of each circuit element are equal to the parasitic parameters of the port circuit in size and opposite in positive and negative.
6. The apparatus for compensating for a cascading error of parasitic parameters of claim 5, wherein said parasitic parameters include parasitic inductance and parasitic capacitance, and wherein said parameters of each circuit element of said compensation circuit include a negative inductance corresponding to said parasitic inductance and a negative capacitance corresponding to said parasitic capacitance.
7. The apparatus for compensating for parasitic parameter cascading errors of claim 5, wherein the high-speed serial cascading links are formed by connecting a plurality of modules in a chip, a connector via, a BGA via, a trace in a predetermined connection order.
8. The apparatus for compensating for parasitic parameter cascading errors of claim 7, wherein adjacent modules are connected through the ports.
9. An apparatus for compensating for spurious parametric cascade errors, comprising a memory and a processor, the memory having stored therein a computer program executable by the processor to implement the method of compensating for spurious parametric cascade errors as claimed in any of claims 1 to 4.
10. A computer readable storage medium storing a computer program executable by the processor to implement the method of compensating for parasitic parameter cascading errors of any of claims 1-4.
CN202310406933.XA 2023-04-17 2023-04-17 Method, device, equipment and storage medium for compensating parasitic parameter cascade error Pending CN116384323A (en)

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