CN116384307A - Test analysis method of flash memory device - Google Patents
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Abstract
The invention provides a test analysis method of a flash memory device, which comprises the following steps: determining and manufacturing a flash memory device and an equivalent structure derived from the flash memory device; acquiring a coupling coefficient expression of the flash memory device and a relation expression of floating gate voltage and floating gate current in the erasing process; testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a coupling coefficient; and testing the relation between the floating gate voltage and the floating gate current in the erasing process according to the relation between the floating gate voltage and the floating gate current in the erasing process and the equivalent structure to obtain the relation between the floating gate voltage and the floating gate current in the erasing process. In the test analysis method of the flash memory device, the coupling coefficient expression and the relation between the floating gate voltage and the floating gate current in the erasing process are obtained first, the flash memory device and the equivalent structure are tested through the relation, and the accurate coupling coefficient and the relation between the floating gate voltage and the floating gate current in the erasing process can be obtained, so that quantized data support is provided for electrical debugging of the flash memory device, and the efficiency and the accuracy of the electrical debugging are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test analysis method of a flash memory device.
Background
Flash memory devices are currently the most popular nonvolatile memory devices, and are widely used in various electronic devices, and the storage principle is to distinguish data 0 and 1 by using different current levels caused by two states of presence or absence of electrons in a floating gate. The Erase (Erase) and write (Program) of electrons in the floating gate utilize the physical mechanisms of FN (Fowler-Nordheim) tunneling and hot carrier injection, respectively. However, in an actual device, the voltage, current and charge on the floating gate during erasing cannot be directly measured, so a test method is required to indirectly obtain the relationship between these physical quantities.
In the conventional method, the tunneling current under different floating gate voltages is generally measured by a floating gate connection method. Or by means of TCAD (Technology Computer Aided Design, semiconductor process simulation and device simulation tool) simulation, the actual change of the floating gate voltage in the erasing process is simulated after the calibration is carried out according to the actual test data. The first way, while effective, has inaccuracy in the test results due to the fact that the floating gate is connected out, which has a structure different from that of a normal flash memory device. While the second method, the results will depend on the accuracy of the physical model in TCAD simulation, the devices produced by each manufacturer may have different physical parameters, and thus the results will also be inaccurate.
Disclosure of Invention
The invention aims to provide a test analysis method of a flash memory device, which is used for testing and analyzing to obtain the accurate relation between the coupling coefficient of the flash memory device and the voltage and current of a floating gate in the erasing process.
In order to solve the above technical problems, the present invention provides a method for testing and analyzing a flash memory device, including:
determining and manufacturing a flash memory device and an equivalent structure derived from the flash memory device;
acquiring a coupling coefficient expression of the flash memory device and a relation expression of floating gate voltage and floating gate current in the erasing process;
testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a coupling coefficient; and
and testing the flash memory device and the equivalent structure according to the relation between the floating gate voltage and the floating gate current in the erasing process to obtain the relation between the floating gate voltage and the floating gate current in the erasing process.
Optionally, the flash memory device includes a single transistor structure flash memory device and a dual transistor structure flash memory device.
Optionally, the control gate in the dual transistor structure flash memory device comprises two layers of polysilicon, wherein the polysilicon of the top layer is connected out as a control gate port, and the polysilicon of the bottom layer is used as a floating gate; the control gate in the equivalent structure derived from the dual transistor structure flash memory device comprises two layers of polysilicon, and the bottom polysilicon is connected out as a floating gate port.
Optionally, the method for obtaining the coupling coefficient expression of the flash memory device includes:
obtaining a floating gate charge quantity expression according to the relation among the capacitance, the charge and the voltage;
obtaining a floating gate voltage expression according to the floating gate charge quantity expression; and
and obtaining a coupling coefficient expression according to the floating gate voltage expression.
Optionally, the coupling coefficient expression of the flash memory device is:
wherein FG is a floating gate, CG is a control gate, BL is a bit line, SL is a source line, sub is a substrate, SG is a select gate, K is a coupling coefficient, K CG Is the coupling coefficient of the control gate, V is the voltage, V FG Is the floating gate voltage, V CG Is the control gate voltage, Q FG Is the charge quantity of the floating gate C tot ＝C CG +C BL +C SL +C sub +C SG ，C CG Refers to the capacitance between the floating gate and the control gate, C BL Refers to the capacitance between the floating gate and the bit line, C SL Refers to the capacitance between the floating gate and the source line, C sub Refers to the capacitance between the floating gate and the substrate, C SG Refers to the capacitance between the floating gate and the select gate.
Optionally, the method for obtaining the relation between the floating gate voltage and the floating gate current in the erasing process comprises the following steps:
according to the coupling coefficient expression, reading the threshold voltage after the programming time t or the erasing time t of the flash memory device to obtain a relation between the floating gate voltage and the time;
deriving the relation between the floating gate voltage and time from time t to obtain a relation between the floating gate current and time;
and obtaining the relation between the floating gate voltage and the floating gate current according to the relation between the floating gate voltage and the time and the relation between the floating gate current and the time.
Optionally, the relation between the floating gate voltage and time in the erasing process is:
V FG (t)＝V TH,FG +k CG [V CG -V TH (t)]+∑k i (V i,P -V i,R ) (i=bl, SL, sub or SG);
the relation between the floating gate current and time in the erasing process is as follows:
wherein V is TH (t) is the threshold voltage, V, of the flash memory device measured after the programming time t or the erasing time t i,P Is the programming voltage of the i port, V i,R Is the erase voltage of the i port, V TH,FG Is the threshold voltage of the equivalent structure.
Optionally, the coupling coefficients include a control gate coupling coefficient, a bit line coupling coefficient, a source line coupling coefficient, a substrate coupling coefficient, and a select gate coupling coefficient.
Optionally, the method for testing the coupling coefficient of the control gate obtained by the flash memory device and the equivalent structure according to the coupling coefficient expression includes:
respectively testing the flash memory device and the equivalent structure under test conditions to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is a relation curve 1 of bit line current and control gate voltage, and the transfer characteristic curve of the equivalent structure is a relation curve 2 of bit line current and floating gate voltage;
selecting a plurality of bit line currents on the transfer characteristic curve to obtain a plurality of groups of control gate voltages and floating gate voltages, and drawing a relation curve of the floating gate voltages and the control gate voltages; and
and obtaining the control gate coupling coefficient from the slope of the relation curve of the floating gate voltage and the control gate voltage.
Optionally, the method for testing the flash memory device and the equivalent structure to obtain the bit line coupling coefficient according to the coupling coefficient expression includes:
respectively testing the flash memory device and the equivalent structure under a second test condition to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is a relation curve 3 of bit line current and control gate voltage, and the transfer characteristic curve of the equivalent structure is a relation curve 4 of bit line current and floating gate voltage;
selecting a control gate voltage, respectively obtaining two bit line currents from the curve 1 and the curve 3, obtaining two floating gate voltages from the curve 2 and the curve 4 corresponding to the two bit line currents, and calculating to obtain the difference value of the two floating gate voltages;
obtaining a relation between the floating gate voltage difference and the bit line coupling coefficient according to the coupling coefficient expression;
respectively selecting different control gate voltages to obtain a relation curve of the bit line coupling coefficient and the control gate voltage; and
and determining the selection range of the control gate voltage, and obtaining the average value of the bit line coupling coefficient.
Optionally, under a third test condition, obtaining a source line coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient, under a fourth test condition, obtaining a substrate coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient, and under a fifth test condition, obtaining a select gate coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient;
compared with the first test condition, the bit line voltage of the second test condition is different, the source line voltage of the third test condition is different, the substrate voltage of the fourth test condition is different, and the select gate voltage of the fifth test condition is different.
Optionally, the method for testing the relationship between the floating gate voltage and the floating gate current in the erasing process according to the relationship between the floating gate voltage and the floating gate current in the erasing process of the flash memory device and the equivalent structure includes:
obtaining the relation between the threshold voltage and time in the erasing process by adopting a stepping pulse test method;
and obtaining the relation between the floating gate voltage and the floating gate current in the erasing process according to the relation between the threshold voltage and the time, and the relation between the floating gate voltage and the time and the relation between the floating gate current and the time.
Optionally, the method for obtaining the relationship between the threshold voltage and time in the erasing process by adopting the step pulse test method comprises the following steps:
changing programming pulse time t, and testing threshold voltage of the flash memory device after programming pulses with different time t are applied to obtain a relation between the threshold voltage and time during programming; or, the erasing pulse time t is changed, and the threshold voltage of the flash memory device after the erasing pulses with different time t are applied is tested, so that the relation between the threshold voltage and time during erasing is obtained.
In summary, in the test analysis method of a flash memory device provided by the invention, the flash memory device and an equivalent structure derived from the flash memory device are first determined and manufactured, then a coupling coefficient expression of the flash memory device and a relation between a floating gate voltage and a floating gate current in a erasing process are obtained, then the flash memory device and the equivalent structure are tested according to the coupling coefficient expression to obtain a coupling coefficient, and the relation between the floating gate voltage and the floating gate current in the erasing process is tested according to the relation between the floating gate voltage and the floating gate current in the erasing process. According to the invention, the coupling coefficient expression and the relation between the floating gate voltage and the floating gate current in the erasing process are obtained, and the flash memory device and the equivalent structure are tested through the expression and the relation, so that the accurate coupling coefficient and the relation between the floating gate voltage and the floating gate current in the erasing process can be obtained, quantized data support is provided for the electrical debugging of the flash memory device, and the efficiency and the accuracy of the electrical debugging are improved.
Drawings
Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:
fig. 1 is a flowchart of a method for testing and analyzing a flash memory device according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a 1T-structure flash memory device according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a 2T structure flash memory device according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a 2T structure derived equivalent structure flash memory device according to an embodiment of the present invention.
Fig. 5 is a characteristic transfer curve of a 2T structure flash memory device and an equivalent structure flash memory device according to an embodiment of the present invention.
FIG. 6 is a graph of floating gate voltage versus control gate voltage according to one embodiment of the present invention.
FIG. 7 is a graph showing characteristic transfer curves of a 2T structure flash memory device and an equivalent structure flash memory device under different bit line voltages according to an embodiment of the present invention.
FIG. 8 is a graph of bit line coupling coefficient versus control gate voltage according to one embodiment of the present invention.
FIG. 9 is a graph of bit line coupling coefficient, source line coupling coefficient, substrate coupling coefficient, select gate coupling coefficient versus control gate voltage provided by an embodiment of the present invention.
FIG. 10 is a graph of threshold voltage versus time during programming according to one embodiment of the present invention.
FIG. 11 is a graph of floating gate current versus floating gate voltage during programming provided by an embodiment of the present invention.
FIG. 12 is a graph of threshold voltage versus time during an erase process according to one embodiment of the present invention.
FIG. 13 is a graph of floating gate current versus floating gate voltage during an erase process according to one embodiment of the present invention.
FIG. 14 is a graph of floating gate current versus floating gate voltage for different bit line voltages during programming according to one embodiment of the present invention.
FIG. 15 is a graph of floating gate current versus floating gate voltage for different control gate voltages during programming according to one embodiment of the present invention.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "first," "second," "third," or "third" may explicitly or implicitly include one or at least two such features, the term "proximal" typically being one end proximal to the operator, the term "distal" typically being one end proximal to the patient, "one end" and "other" and "proximal" and "distal" typically referring to corresponding two portions, including not only the endpoints, the terms "mounted," "connected," "coupled," or "coupled" are to be construed broadly, e.g., as either a fixed connection, a removable connection, or as one piece; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements.
Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In order to solve the technical problems, the invention provides a test analysis method of a flash memory device. Fig. 1 is a flowchart of a method for testing and analyzing a flash memory device according to an embodiment of the present invention, please refer to fig. 1, wherein the method for testing and analyzing a flash memory device includes:
step S1: determining and manufacturing the flash memory device and an equivalent structure derived from the flash memory device;
step S2: acquiring a coupling coefficient expression of the flash memory device and a relation expression of floating gate voltage and floating gate current in the erasing process;
step S3: testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a coupling coefficient; and
step S4: and testing the flash memory device and the equivalent structure according to the relation between the floating gate voltage and the floating gate current in the erasing process to obtain the relation between the floating gate voltage and the floating gate current in the erasing process.
In the test analysis method of the flash memory device, the coupling coefficient expression and the relation between the floating gate voltage and the floating gate current in the erasing process are obtained first, the flash memory device and the equivalent structure are tested through the expression and the relation, and the accurate coupling coefficient and the relation between the floating gate voltage and the floating gate current in the erasing process can be obtained, so that quantized data support is provided for electrical debugging of the flash memory device, and the efficiency and the accuracy of the electrical debugging are improved.
In step S1, the flash memory device and equivalent structures derived from the flash memory device are determined and fabricated.
First, the flash memory device and equivalent structures derived from the flash memory device are determined. In the present embodiment, determining the flash memory device and the equivalent structure refers to determining the theoretical flash memory device structure and the equivalent structure of the flash memory device, as shown in fig. 2 to 4.
The test analysis method provided by the invention is suitable for flash memory devices with different structures, such as a 1T (1-Transistor) structure flash memory device and a 2T (2-Transistor) structure flash memory device. Fig. 2 is a schematic structural diagram of a 1T-structure flash memory device according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of a 2T-structure flash memory device according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of an equivalent structural flash memory device derived from a 2T-structure according to an embodiment of the present invention.
Referring to fig. 2, the 1T structure flash memory device includes a substrate (sub), a Control Gate (CG) on the substrate, and Source Lines (SL) and Bit Lines (BL) in the substrate on both sides of the Control Gate. The control Gate comprises two layers of polysilicon, wherein the upper layer of polysilicon is used as a control Gate to be connected out and used as a control Gate port, the lower layer of polysilicon is called a Floating Gate (FG), the Floating Gate is a region for storing electrons, a dielectric layer is further formed between the two layers of polysilicon, the dielectric layer is an Oxide-Nitride-Oxide (ONO) stacking layer, and an Oxide layer is further formed between the Floating Gate and the substrate. The 1T structure flash memory device comprises a source line port, a control gate port, a bit line port and a substrate port.
Referring to fig. 3, the 2T structure flash memory device includes a substrate, a control Gate CG and a Select Gate (SG) on the substrate, a source line SL in the substrate on one side of the control Gate CG, a bit line BL in the substrate on one side of the select Gate SG, and a CSD (Cell Source Drain, source-drain unit) in the substrate between the control Gate CG and the select Gate SG. The control gate comprises two layers of polysilicon, wherein the upper layer of polysilicon is used as a control gate to be connected out and used as a control gate port, the lower layer of polysilicon is used as a floating gate, a dielectric layer is further formed between the two layers of polysilicon, the dielectric layer is an Oxide-Nitride-Oxide (ONO) stacked layer, and an Oxide layer is further formed between the floating gate and the substrate. The select gate also comprises two layers of polysilicon, but in practice only the lower polysilicon layer is connected out as the select gate, the upper polysilicon layer being inactive.
Referring to fig. 4, in the equivalent structure flash memory device derived from the 2T structure, the control gate transistor is formed by connecting the underlying polysilicon layer, i.e. the floating gate is connected as the floating gate port, and the rest is the same as the 2T structure flash memory device shown in fig. 3.
In this embodiment, a more complex 2T structure flash memory device is taken as an example for illustration, and the 1T structure may be the same method, which is not described in detail in this embodiment. In fig. 3, the 2T structure flash memory device includes a source line port, a select gate port, a bit line port, and a substrate port in addition to the control gate port. In fig. 4, the equivalent structure flash memory device includes a source line port, a select gate port, a bit line port, and a substrate port in addition to the floating gate port.
Next, the flash memory device and equivalent structures derived from the flash memory device are fabricated. In this embodiment, manufacturing the flash memory device and the equivalent structure means manufacturing the actual flash memory device and the equivalent structure of the flash memory device. It will be appreciated that the steps of manufacturing the flash memory device and the equivalent structures derived from the flash memory device may be performed before step S2, or may be performed after step S2, i.e. the actual product may be manufactured before testing.
In step S2, a coupling coefficient expression of the flash memory device and a relation between the floating gate voltage and the floating gate current in the erasing process are obtained.
Firstly, acquiring a coupling coefficient expression of the flash memory device, and in this embodiment, the method for acquiring the coupling coefficient expression of the flash memory device includes: firstly, obtaining a floating gate charge quantity expression according to the relation among capacitance, charge and voltage; and then obtaining a floating gate voltage expression according to the floating gate charge amount expression, and obtaining a coupling coefficient expression according to the floating gate voltage expression.
The floating gate in a flash memory device is where electrons are stored, and the amount of charge is related to the number of electrons stored. Because the floating gate potential is floating, its voltage can be influenced by other port voltages of the device. According to the relation of capacitance, charge and voltage, the charge quantity Q of the floating gate FG The following relationship is satisfied:
Q FG ＝C CG (V FG -V CG )+C BL (V FG -V BL )+C SL (V FG -V SL )+C Sub (V FG -V Sub )+C SG (V FG -V SG ) (1)
Wherein capacitance refers to the capacitance between floating gate FG and the remaining ports, e.g. C CG Refers to the capacitance between the floating gate FG and the control gate CG, C BL Refers to the capacitance between the floating gate FG and the bit line BL, C SL Refers to the capacitance between the floating gate FG and the source line SL, C sub Refers to the capacitance between the floating gate FG and the substrate sub, C SG Refers to the capacitance between floating gate FG and select gate SG. V (V) FG Refers to floating gate voltage, V CG Refers to control of gate voltage, V BL Refers to bit line voltage, V SL Refers to the source line voltage, V sub Refers to the substrate voltage, V SG Refers to the select gate voltage.
By varying the formula 1, it is possible to obtain:
wherein C is tot Is the sum of the capacitances of each end, namely C tot ＝C CG +C BL +C SL +C sub +C SG As can be seen from equation 2, a change in voltage at one end of the flash memory device causes a corresponding change in the floating gate voltage, which is affected by the voltages at each end and the amount of floating gate charge. The ratio of the capacitance at each end to the total capacitance is expressed as a coupling coefficient k, and equation 2 is rewritable as:
since the ratio of the capacitance of each end to the total capacitance is expressed as a coupling coefficient k, the sum of the coupling coefficients of each end is 1. As a preferred embodiment, the gate coupling coefficient K is controlled CG (i.e. V CG /C tot ) It is preferably designed above 0.6 so that the control gate voltage is the main influencing factor for the floating gate voltage, which is also the reason for the term "control gate".
And then obtaining a relation between the floating gate voltage and the floating gate current in the erasing and writing process. In this embodiment, the method for obtaining the relation between the floating gate voltage and the floating gate current in the erasing process includes: firstly, according to the coupling coefficient expression, reading threshold voltage after programming time t or erasing time t of the flash memory device to obtain a relation between floating gate voltage and time; then deriving the relation between the floating gate voltage and time from the time t to obtain a relation between the floating gate current and time; and then obtaining the relation between the floating gate voltage and the floating gate current according to the relation between the floating gate voltage and the time and the relation between the floating gate current and the time.
Threshold voltage V of 2T structure flash memory device TH The test method of (2) is generally as follows: v (V) BL ＝Vcc，V SL ＝0V，V SG ＝-Vcc，V Sub =vcc, scan V CG Taking the bit line current I BL V when=2.5 μa CG Threshold voltage V of flash memory device TH . In this example, vcc is 1.5V.
When the flash memory device is turned on, V CG ＝V TH The threshold voltage V TH The size of (2) and the amount of charge Q stored in the floating gate FG Related to the following. But no matter Q FG When the device is opened, the floating gate voltage is a fixed value, which is called V FG ＝V TH,FG 。V TH,FG The threshold voltage of the equivalent structure can be measured by the equivalent structure shown in fig. 4.
According to equation 3, after the programming time t or the erasing time t, the flash memory device performs the threshold voltage reading, and the reading process accords with the following relation:
wherein V is TH (t) means the threshold voltage, Q, measured after the programming time t or the erasing time t of the flash memory device FG (t) means the charge amount on the floating gate after the programming pulse time t or the erasing pulse time t of the flash memory device, V i,R Refers to the read voltage of the i port, i refers to the bit line port, the source line port, the substrate port, or the select gate port.
In the programming and erasing process (the programming is taken as an example in this embodiment, the erasing process is similar), the voltage on the floating gate accords with the following relation according to the formula 3 when the programming is performed for time t:
wherein V is i,R Refers to the read voltage of the i-port. Equation 5 minus equation 4 can be used to obtain the relationship between floating gate voltage and time during programming:
V FG (t)＝V TH,FG +k CG [V CG -V TH (t)]+∑k i (V i,P -V i,R ) (i=bl, SL, sub or SG) (formula 6)
Deriving equation 5 for time t, the floating gate current versus time relationship in the programming process can be obtained:
wherein, control gate capacitance C CG Can be obtained by combining the actually designed device size with a capacitance calculation formula of C=epsilon S/d.
If the threshold voltage V is obtained according to the formulas 6 and 7 TH Relation V with time t TH (t) obtaining the floating gate voltage V during programming FG (t) and floating gate current I FG And (t) a relationship.
Similarly, the floating gate voltage V during erasing can be obtained by the same method FG (t) and floating gate current I FG And (t) a relationship.
In step S3, the coupling coefficient is obtained by testing the flash memory device and the equivalent structure according to the coupling coefficient expression.
In this embodiment, the coupling coefficient includes a control gate coupling coefficient k CG Bit line coupling coefficient k BL Coupling coefficient k of source line SL Substrate coupling coefficient k sub Select gate coupling coefficient k SG 。
Testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a control gate coupling coefficient k CG The method of (1) comprises: firstly, under the test condition, the flash memory device and the equivalent structure are respectively tested to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is bit line current I BL And control gate voltage V CG The transfer characteristic of the equivalent structure is the bit line current I BL With floating gate voltage V FG Is a relationship 2 of (2); then selecting a plurality of bit line currents I on the transfer characteristic curve BL Obtaining a plurality of groups of control gate voltages V CG With floating gate voltage V FG Drawing a relation curve of floating gate voltage and control gate voltage; and deriving the control gate coupling coefficient k from the slope of the floating gate voltage versus control gate voltage curve CG 。
Exemplary, for control gate CG coupling coefficient k CG The test method of (2) is as follows:
the transfer characteristic curves of the 2T structure and the equivalent structure were respectively tested, and the test conditions are shown in table 1.
TABLE 1
| 2T structure | V BL ＝Vcc，V SL ＝0V，V Sub ＝Vcc，V SG = -Vcc, scan V CG | Obtaining curve 1 |
| Equivalent structure | V BL ＝Vcc，V SL ＝0V，V Sub ＝Vcc，V SG = -Vcc, scan V FG | Obtaining curve 2 |
FIG. 5 can be obtained according to the above test conditions, and FIG. 5 is a characteristic transfer curve of a 2T structure flash memory device and an equivalent structure flash memory device according to an embodiment of the present invention, as shown in FIG. 5, the abscissa is the control gate voltage V CG Or floating gate voltage V FG Wherein the abscissa of curve 1 is the control gate voltage V CG The abscissa of curve 2 is the floating gate voltage V FG The ordinate is the bit line current I BL . Then, a certain bit line current I is selected BL To obtain a group of voltages (V) CG ，V FG ) The method comprises the steps of carrying out a first treatment on the surface of the Then, the bit line current I is changed BL Another set of voltages (V CG ，V FG ) The method comprises the steps of carrying out a first treatment on the surface of the Thus reciprocating to obtain several groups of voltage values (V CG ，V FG ) Drawing the floating gate voltage on a coordinate axis to obtain a relation curve of the floating gate voltage and the control voltage, namely V FG -V CG The relationship curve is obtained as shown in FIG. 6. FIG. 6 is a graph showing the relationship between the floating gate voltage and the control gate voltage according to one embodiment of the present invention, please refer to FIG. 6, it can be seen from equation 3 that the slope of the graph in FIG. 6 is the control gate coupling coefficient k CG K in the present embodiment CG ＝0.653。
The method for testing the flash memory device and the equivalent structure to obtain the bit line coupling coefficient according to the coupling coefficient expression comprises the following steps: firstly, under the second test condition, the flash memory device and the equivalent structure are respectively tested to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is bit line current I BL And control gate voltage V CG The transfer characteristic of the equivalent structure is the bit line current I BL With floating gate voltage V FG Is a relationship 4; selecting a control gate voltage V CG Two bit line currents are obtained from curves 1 and 3, respectively, which correspond to two floating gate voltages V obtained from curves 2 and 4 FG And calculate the difference DeltaV of the two floating gate voltage values FG The method comprises the steps of carrying out a first treatment on the surface of the Obtaining a floating gate voltage difference DeltaV according to the coupling coefficient expression (i.e. expression 3) FG Coefficient of coupling k to bit line BL Is a relation of (2); respectively select different control gate voltages V CG Obtaining the bit line coupling coefficient k BL With the control gate voltage V CG Is a relationship of (2); determining the control gate voltage V CG Obtain the bit line coupling coefficient k BL Average value of (2).
The bit line voltage Vcc of the test condition two is different from the bit line voltage Vcc of the test condition one, and preferably the bit line voltage Vcc of the test condition two is increased, for example by 0.5V.
Exemplary, the bit line BL coupling coefficient k BL The test method of (2) is as follows:
testing transfer characteristic curves of 2T structure and equivalent structure respectively, but V BL Instead of Vcc+0.5V, test condition two is shown in Table 2.
TABLE 2
| 2T structure | V BL ＝Vcc+0.5V，V SL ＝0V，V Sub ＝Vcc，V SG = -Vcc, scan V CG | Obtaining curve 3 |
| Equivalent structure | V BL ＝Vcc+0.5V，V SL ＝0V，V Sub ＝Vcc，V SG = -Vcc, scan V FG | Obtaining curve 4 |
From the above test conditions, curves 3 and 4 can be obtained, and fig. 7 can be obtained by combining the curves 1 and 2 obtained heretofore. FIG. 7 is a graph showing characteristic transfer curves of a 2T structure flash memory device and an equivalent structure flash memory device under different bit line voltages according to an embodiment of the present invention, and referring to FIG. 7, a certain control gate voltage V in FIG. 7 is selected CG Two bit line currents I are obtained in curves 1 and 3, respectively BL1 And I BL2 ，I BL1 Corresponding to curve 2 to obtain floating gate voltage V FG1 ，I BL2 Corresponding to curve 4 to obtain floating gate voltage V FG2 . Calculate V FG1 And V is equal to FG2 Is DeltaV FG . As can be seen from equation 3, the difference DeltaV FG By bit line voltage V only BL The variation of (c) results in:
△V FG ＝k BL △V BL (8)
In one embodiment, deltaV is selected during testing BL =0.5v, the control gate voltage V CG Coupling coefficient k of lower bit line BL BL Can be derived from equation 8. Selecting different control gate voltages V CG Obtaining a relation curve between the bit line coupling coefficient and the control gate voltage, namely k BL -V CG The curve is shown in fig. 8. Selecting the control gate voltage V in the curve CG K in the range of-1.5V to 0V BL As the average value of the bit line coupling coefficient k BL . In the present embodiment, k BL ＝0.167。
And under the test condition III, obtaining a source line coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient, under the test condition IV, obtaining a substrate coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient, and under the test condition V, obtaining a select gate coupling coefficient by adopting the same method as that for obtaining the bit line coupling coefficient. Compared with the first test condition, the source line voltage of the third test condition is different, the substrate voltage of the fourth test condition is different, and the selection gate voltage of the fifth test condition is different. Preferably, the source line voltage of the test condition three is increased, the substrate voltage of the test condition four is increased, and the absolute value of the select gate voltage of the test condition five is increased, for example, the source line voltage is increased by 0.5V, the substrate voltage is increased by 0.5V, and the absolute value of the select gate voltage is increased by 0.5V, as compared with the test condition one, but not limited thereto.
Exemplary, source line coupling coefficient k SL Substrate coupling coefficient k sub Select gate coupling coefficient k SG Test method of (c) and bit line coupling coefficient k BL The test method is similar, namely, the voltages of the source line, the substrate and the selection gate port are sequentially changed to test the transfer characteristic curves of the 2T structure and the equivalent structure. The test conditions are shown in Table 3.
TABLE 3 Table 3
Using the coefficient k coupled to the bit line BL The same analysis method can obtain the source line coupling coefficient k SL Substrate coupling coefficient k sub Coupling coefficient k of select gate SG . Specifically, the source line coupling coefficient k is obtained by using the curve 1, the curve 2, the curve 5 and the curve 6 SL Obtaining a substrate coupling coefficient k by using the curve 1, the curve 2, the curve 7 and the curve 8 sub Obtaining a selection gate coupling coefficient k by using the curve 1, the curve 2, the curve 9 and the curve 10 SG . Finally get k SL 、k sub 、k SG And V is equal to CG As shown in fig. 9. In one embodiment, the control gate voltage V is selected CG Average value of each coupling coefficient in the range of-1.5V to 0V as the obtained coupling coefficient, k in this embodiment BL ＝0.167、k SL ＝0.129、k Sub ＝0.065、k SG ＝0.012。
In step S4, the relationship between the floating gate voltage and the floating gate current in the erasing process is obtained by testing the relationship between the flash memory device and the equivalent structure according to the relationship between the floating gate voltage and the floating gate current in the erasing process.
Specifically, a stepping pulse test method is adopted to obtain the relation between threshold voltage and time in the erasing process; and then, according to the relation between the threshold voltage and the time, the relation between the floating gate voltage and the time and the relation between the floating gate current and the time, obtaining the relation between the floating gate voltage and the floating gate current in the erasing process.
The method for obtaining the relation between the threshold voltage and time in the erasing process by adopting the stepping pulse test method comprises the following steps: changing programming pulse time t, and testing threshold voltage of the flash memory device after programming pulses with different time t are applied to obtain a relation between the threshold voltage and time in the programming process; or, changing the erasing pulse time t, and testing the threshold voltage of the flash memory device after the erasing pulses with different time t are applied to obtain the relation between the threshold voltage and time in the erasing process.
Exemplary, it is known from the above analysis of the relationship between the floating gate voltage and the floating gate current in the erasing process that only the threshold voltage V of the equivalent structure needs to be obtained TH,FG And threshold voltage V of flash memory device after programming time t or erasing time t TH (t) each ofThe floating gate voltage V in the erasing and writing process can be obtained by the end coupling coefficient FG (t) and floating gate current I FG And (t) a relationship. The coupling coefficient can be obtained by the test method, and the bit line current I in curve 2 BL Corresponding floating gate voltage V when=2.5 uA FG Namely V TH,FG 。V TH (t) can be obtained by the following method:
by adopting a stepping pulse test method, the relation between the threshold voltage and time can be obtained by changing the programming pulse time T and testing the threshold voltage of the flash memory device with the 2T structure after programming pulses with different time T are applied, and V is obtained TH -t, as shown in fig. 10.
Then according to the formulas 6 and 7, the floating gate voltage V in the programming process can be obtained FG (t) and Floating Gate Current I FG (t) and further obtain I FG -V FG As shown in fig. 11. The curve shows the voltage-current relation of hot carrier injection in the programming process, and has profound significance for understanding the mechanism of the device and debugging the parameters of the device.
The analysis method at the time of erasing is the same as that at the time of programming, and will not be described here again. Fig. 12 shows the relationship between the threshold voltage and time during the erase process, and fig. 13 shows the relationship between the floating gate current and the floating gate voltage during the erase process, i.e., the relationship between the voltage and the current during FN tunneling.
In the test analysis method of the flash memory device, the flash memory device and an equivalent structure derived from the flash memory device are firstly determined and manufactured, then a coupling coefficient expression of the flash memory device and a relation between floating gate voltage and floating gate current in the erasing process are obtained, then the flash memory device and the equivalent structure are tested according to the coupling coefficient expression to obtain the coupling coefficient, and the relation between the floating gate voltage and the floating gate current in the erasing process is tested according to the relation between the floating gate voltage and the floating gate current in the erasing process. According to the invention, the coupling coefficient expression and the relation between the floating gate voltage and the floating gate current in the erasing process are obtained, and the flash memory device and the equivalent structure are tested through the expression and the relation, so that the accurate coupling coefficient and the relation between the floating gate voltage and the floating gate current in the erasing process can be obtained, quantized data support is provided for the electrical debugging of the flash memory device, and the efficiency and the accuracy of the electrical debugging are improved.
In the embodiment of the application, specific factors influencing the floating gate voltage are obtained through theoretical analysis, a coupling coefficient expression of the flash memory device is obtained, a relation between the floating gate voltage and the floating gate current and time is established, coupling coefficients of all ends of the flash memory device are obtained through testing, and a quantitative relation curve between tunneling current and time and between floating gate voltage on the floating gate in the programming and erasing processes of the flash memory device is obtained through a stepping pulse testing method, so that the essence of the erasing and writing process is revealed. The test may provide quantized data support for electrical debugging of flash memory devices.
According to the test result of the coupling coefficient, the control gate coupling coefficient is the highest and is about 0.65, which indicates that the control gate voltage is a main influencing factor of the floating gate voltage. The step pulse test results show that the erasing threshold voltage and the logarithm of the erasing time are approximately in a linear relation, which shows that the erasing speed gradually becomes slow as the time increases. The obtained floating gate current-voltage relationship shows that the logarithm of the floating gate current and the floating gate voltage are approximately in a linear relationship, which shows that the floating gate voltage has an exponential effect on the tunneling current, and also shows that the erasing speed is gradually slowed down along with the gradual change of charges in the floating gate in the erasing process.
Based on the above test, some pull-bias tests may also be performed. For example, the bit line voltage and the control gate voltage are changed during programming, respectively, and the change in the floating gate current-voltage relationship is analyzed. Fig. 14 shows the effect of different bit line voltages on the floating gate current-voltage relationship. The results indicate that increasing the bit line voltage (i.e., increasing the horizontal electric field) can improve programming efficiency (i.e., tunneling current at the same floating gate voltage). Fig. 15 shows the effect of different control gate voltages on the floating gate current-voltage relationship, which shows that increasing the control gate voltage (i.e., increasing the vertical electric field) does not change the programming efficiency (the tunneling current is unchanged at the same floating gate voltage), but that increasing the control gate voltage, coupling to the floating gate, increases the floating gate voltage, increases the tunneling current, and thus increases the programming threshold.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (13)
1. A method for testing and analyzing a flash memory device, comprising:
determining and manufacturing a flash memory device and an equivalent structure derived from the flash memory device;
acquiring a coupling coefficient expression of the flash memory device and a relation expression of floating gate voltage and floating gate current in the erasing process;
testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a coupling coefficient; and
and testing the flash memory device and the equivalent structure according to the relation between the floating gate voltage and the floating gate current in the erasing process to obtain the relation between the floating gate voltage and the floating gate current in the erasing process.
2. The method of claim 1, wherein the flash memory device comprises a single transistor flash memory device and a dual transistor flash memory device.
3. The method of claim 2, wherein the control gate of the dual transistor flash memory device comprises two layers of polysilicon, wherein the top layer of polysilicon is connected out as a control gate port and the bottom layer of polysilicon is used as a floating gate; the control gate in the equivalent structure derived from the dual transistor structure flash memory device comprises two layers of polysilicon, and the bottom polysilicon is connected out as a floating gate port.
4. The method of claim 1, wherein the method of obtaining the coupling coefficient expression of the flash memory device comprises:
obtaining a floating gate charge quantity expression according to the relation among the capacitance, the charge and the voltage;
obtaining a floating gate voltage expression according to the floating gate charge quantity expression; and
and obtaining a coupling coefficient expression according to the floating gate voltage expression.
5. The method of claim 4, wherein the coupling coefficient expression of the flash memory device is:
wherein FG is a floating gate, CG is a control gate, BL is a bit line, SL is a source line, sub is a substrate, SG is a select gate, K is a coupling coefficient, K CG Is the coupling coefficient of the control gate, V is the voltage, V FG Is the floating gate voltage, V CG Is the control gate voltage, Q FG Is the charge quantity of the floating gate C tot ＝C CG +C BL +C SL +C sub +C SG ，C CG Refers to the capacitance between the floating gate and the control gate, C BL Refers to the capacitance between the floating gate and the bit line, C SL Refers to the capacitance between the floating gate and the source line, C sub Refers to the capacitance between the floating gate and the substrate, C SG Refers to the capacitance between the floating gate and the select gate.
6. The method for testing and analyzing a flash memory device according to claim 5, wherein the method for obtaining the relation between the floating gate voltage and the floating gate current during the erasing process comprises:
according to the coupling coefficient expression, reading the threshold voltage after the programming time t or the erasing time t of the flash memory device to obtain a relation between the floating gate voltage and the time;
deriving the relation between the floating gate voltage and time from time t to obtain a relation between the floating gate current and time;
and obtaining the relation between the floating gate voltage and the floating gate current according to the relation between the floating gate voltage and the time and the relation between the floating gate current and the time.
7. The method of claim 6, wherein the floating gate voltage versus time during erasing is as follows:
the relation between the floating gate current and time in the erasing process is as follows:
wherein V is TH (t) is the threshold voltage, V, of the flash memory device measured after the programming time t or the erasing time t i,P Is the programming voltage of the i port, V i,R Is the erase voltage of the i port, V TH,FG Is the threshold voltage of the equivalent structure.
8. The method of claim 1, wherein the coupling coefficients comprise a control gate coupling coefficient, a bit line coupling coefficient, a source line coupling coefficient, a substrate coupling coefficient, and a select gate coupling coefficient.
9. The method of claim 8, wherein the method of testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a control gate coupling coefficient comprises:
respectively testing the flash memory device and the equivalent structure under test conditions to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is a relation curve 1 of bit line current and control gate voltage, and the transfer characteristic curve of the equivalent structure is a relation curve 2 of bit line current and floating gate voltage;
selecting a plurality of bit line currents on the transfer characteristic curve to obtain a plurality of groups of control gate voltages and floating gate voltages, and drawing a relation curve of the floating gate voltages and the control gate voltages; and
and obtaining the control gate coupling coefficient from the slope of the relation curve of the floating gate voltage and the control gate voltage.
10. The method of claim 9, wherein the method of testing the flash memory device and the equivalent structure according to the coupling coefficient expression to obtain a bit line coupling coefficient comprises:
respectively testing the flash memory device and the equivalent structure under a second test condition to obtain a transfer characteristic curve, wherein the transfer characteristic curve of the flash memory device is a relation curve 3 of bit line current and control gate voltage, and the transfer characteristic curve of the equivalent structure is a relation curve 4 of bit line current and floating gate voltage;
selecting a control gate voltage, respectively obtaining two bit line currents from the curve 1 and the curve 3, obtaining two floating gate voltages from the curve 2 and the curve 4 corresponding to the two bit line currents, and calculating to obtain the difference value of the two floating gate voltages;
obtaining a relation between the floating gate voltage difference and the bit line coupling coefficient according to the coupling coefficient expression;
respectively selecting different control gate voltages to obtain a relation curve of the bit line coupling coefficient and the control gate voltage; and
and determining the selection range of the control gate voltage, and obtaining the average value of the bit line coupling coefficient.
11. The method for testing and analyzing a flash memory device according to claim 10, wherein a source line coupling coefficient is obtained by the same method as the bit line coupling coefficient under test condition three, a substrate coupling coefficient is obtained by the same method as the bit line coupling coefficient under test condition four, and a select gate coupling coefficient is obtained by the same method as the bit line coupling coefficient under test condition five;
compared with the first test condition, the bit line voltage of the second test condition is different, the source line voltage of the third test condition is different, the substrate voltage of the fourth test condition is different, and the select gate voltage of the fifth test condition is different.
12. The method of claim 6, wherein the step of testing the relationship between the floating gate voltage and the floating gate current in the process of erasing the flash memory device and the equivalent structure according to the relationship between the floating gate voltage and the floating gate current in the process of erasing the flash memory device comprises:
obtaining the relation between the threshold voltage and time in the erasing process by adopting a stepping pulse test method;
and obtaining the relation between the floating gate voltage and the floating gate current in the erasing process according to the relation between the threshold voltage and the time, and the relation between the floating gate voltage and the time and the relation between the floating gate current and the time.
13. The method for testing and analyzing a flash memory device according to claim 12, wherein the step pulse testing method is used to obtain the relationship between the threshold voltage and time during the erasing process, and the method comprises:
changing programming pulse time t, and testing threshold voltage of the flash memory device after programming pulses with different time t are applied to obtain a relation between the threshold voltage and time during programming; or, the erasing pulse time t is changed, and the threshold voltage of the flash memory device after the erasing pulses with different time t are applied is tested, so that the relation between the threshold voltage and time during erasing is obtained.
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