CN116384297A - Method for generating chip clock constraint file - Google Patents

Abstract

The invention discloses a method for generating a chip clock constraint file, which comprises the following steps: reading an original data file; performing register transmission level code expansion on the original data file; replacing the complex logic structure with a predefined simplified logic structure by replacing the module; analyzing a clock structure from the complete design logic structure through an analysis module, and storing the clock structure as a clock structure description file; and reading in the clock structure description file and a clock constraint template corresponding to the predefined simplified logic structure through a clock constraint generation module to generate a clock constraint file. According to the invention, the logic structure of the whole chip design is read in, the clock derivative relation and the topological structure are extracted from the logic structure, and the clock constraint file is generated. The method is applicable to any chip design without depending on a clock structure diagram and a clock structure table, can greatly reduce analysis and inspection time of clock structures and iteration time, accelerates the writing process of clock constraint files, and improves the accuracy of the constraint files.

Description

Method for generating chip clock constraint file

Technical Field

The invention discloses a method for generating a chip clock constraint file, and relates to the technical field of chip design and static time sequence analysis.

Background

With the continuous increase of the whole scale and complexity of the chip, the clock structure of the chip is also increasingly complex. In the design implementation of the chip, the clock constraint file describes the derivative relationship, period, waveform and phase relationship of all clocks. The more clocks, the more complex the derivative, and the more complex the clock constraint file. For the writing of clock constraint documents, there are two general approaches in the prior art: 1. the writing is done manually according to the clock architecture diagram and the register transfer level code. 2. And automatically generating a clock constraint file according to the clock architecture table.

The disadvantage of the method 1 is that the designer writes constraint commands one by one against the clock architecture diagram and the design code at the same time, which consumes a lot of time; and it is difficult to ensure correctness; when the clock architecture is changed along with the design change, the clock constraint file is also modified, so that the workload is high and the error is easy to occur.

The advantage of approach 2 is that new clock constraint files can be quickly generated as the clock architecture design changes. The disadvantage is that the clock architecture table is required to fully describe the entire clock structure, and that structures not described require manual writing, which is especially common within third party IP.

The clock constraint file is needed to be used first in the chip comprehensive implementation stage. The existing comprehensive tool needs to read in design codes, unit libraries, clock constraint files, low-power consumption description files and the like before starting the synthesis; under the condition of lacking a clock constraint file, although the comprehensive tool can analyze the logic structure of the whole design, the comprehensive tool can not generate the description of the clock structure, and can not generate the clock constraint file corresponding to the clock structure for a user.

Disclosure of Invention

The invention aims to solve the problems that the clock structure is automatically analyzed from any chip design and the clock constraint file is generated, so that the writing workload is reduced and the error risk is reduced.

The invention discloses a method for generating a chip clock constraint file, which comprises the following steps:

step 1, reading an original data file;

step 2, carrying out register transmission level code expansion on the original data file;

step 3, replacing the complex logic structure with a predefined simplified logic structure by replacing the module;

step 4, analyzing the clock structure from the design logic structure through an analysis module, and storing the clock structure as a clock structure description file;

and 5, reading in the clock structure description file and a clock constraint template corresponding to the predefined simplified logic structure through a clock constraint generation module to generate a clock constraint file.

Preferably, the raw data file includes a register transfer level code and a standard cell library.

As a preferred solution, the step 2 specifically includes:

and according to the original data file, performing code expansion by using a comprehensive tool, wherein the code expansion refers to the conversion of codes from logic description to the topological structure of a circuit, and the logic relationship, nodes, pins and the attributes of the circuit structure can be inquired in the comprehensive tool.

As a preferred solution, the step 3 specifically includes:

tracking the fan-in logic structure of the register from the clock pin of the register until the output and pins of the register of the previous stage;

and tracking the fan-in logic structure of the previous stage register from the clock pin of the previous stage register again, traversing the whole design logic in a recursion mode, and replacing the original complex logic structure with the simplified logic structure when the register output pin level obtained in the tracking process accords with the replacement condition of the predefined simplified logic structure. And storing the design logic structure level of the register and the port acquired in the tracking process as a clock structure description file.

As a preferred solution, the step 4 specifically includes:

using an analysis_clock_structure function, obtaining all registers in the design from the synthesis tool, and storing the registers as a register list as input of the function;

defining a result_list variable for storing temporary tracking results;

traversing the register list and each pin thereof, storing pin_hier, if the pin has clock attribute, acquiring starting points of all fan-ins and putting the starting points into a result variable, and if the starting points do not exist in the result_list, putting the starting points into the result variable;

if the type attribute of the result variable is a port, the input port which has been traced to the design logic structure is described as a definition point of the master clock, and the node information is recorded at this time and stored into a port_name in the format of:

ROOT：<port_name> LEAF: <pin_hier>；

if the type attribute of the result variable is a pin, the node is indicated to be in the design logic structure, and meanwhile, the pin is also indicated to be an output pin of a register at the upper stage, the hierarchy of the design logic structure where the pin is located is obtained, and the hierarchy is stored in the node reg;

the output pins of the register need to define derived clocks, so that the hierarchy of the pins is recorded, stored in pin_hier, and the format is as follows:

NODE: <node_reg > LEAF: <pin_hier>；

node_reg is used as a register and becomes the input of an analysis_clock_structure function to form a recursion algorithm, so that the whole design logic structure is traversed, and the acquired ROOT, NODE and LEAF information are continuously output in the traversing process to form a complete clock structure description file.

Preferably, the step 5 specifically includes:

traversing the clock structure description file, generating a create_generated_clock constraint command for each register output pin, generating a create_clock constraint command for each port, and calling a corresponding clock constraint template and saving as a clock constraint file if the register output pin hierarchy is a predefined simplified logic structure.

According to the method for generating the chip clock constraint file, the clock relation and the structure are extracted from the whole chip design logic through reading in the whole chip design logic, and the clock constraint file is generated. The method is applicable to any chip design without depending on a clock structure diagram and a clock structure table, can greatly reduce the time for analyzing and checking the clock structure and modifying iteration thereof, accelerates the writing process of the clock constraint file, and improves the accuracy of the constraint file.

Drawings

FIG. 1 is a flow chart of a method for generating a chip clock constraint file according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an analysis module algorithm according to an embodiment of the invention.

Fig. 3 is an analysis diagram of a clock dividing structure according to an embodiment of the invention.

FIG. 4 is a substitute command for a substitute module according to an embodiment of the invention.

Fig. 5 is an alternate schematic diagram of a single clock input predefined module in accordance with an embodiment of the present invention.

Fig. 6 is an alternative schematic diagram of the multi-clock input predefined module 1 according to an embodiment of the invention.

Fig. 7 is an alternative schematic diagram of the multi-clock input predefined module 2 of an embodiment of the present invention.

FIG. 8 is a flowchart of an algorithm for parsing a clock structure from a design logic structure in accordance with one embodiment of the present invention.

FIG. 9 is a flowchart of an algorithm for generating a clock constraint file in accordance with an embodiment of the present invention.

Detailed Description

The invention discloses a method for generating a chip clock constraint file, as shown in fig. 1, which comprises the following steps:

s1: the original data file is read. The original data file includes: the registers transmit level codes, cell libraries.

S2: and according to the original data file, utilizing a comprehensive tool to conduct code expansion. Expansion refers to the conversion of code from a logical description to a topology of a circuit and enables querying of the integrated tool for the logical relationships, nodes, pins, and their attributes of the circuit structure.

S3: and traversing all sub-module names and layers of the circuit topology structure in the comprehensive tool through replacing the module, and replacing the complex logic structure with a simplified logic structure.

The complex logic structure is characterized in that the structure has a clock loop, such as an OCC (optical code) on-chip clock, a frequency divider and the like, is fixed in structure and is often multiplexed multiple times in the same design. There are several common alternatives and corresponding clock constraint templates.

Taking fig. 5 as an example, after the CKIN signal enters the predefined logic structure in the dashed box, it passes through some logic circuits, which may be multiple different frequency division circuit structures, and finally passes through the gate to select one clock to propagate to CKOUT. This form may be replaced by a register.

Taking fig. 6 as an example, fast_clk and slow_clk enter the predefined logic structure in the dashed box at the same time, and are output to CKOUT through some logic circuits. SLOW CLK may be ignored if it is a clock that is not of interest to the current clock constraint file. This form may be replaced by a register.

Taking fig. 7 as an example, two or more clocks clk_1 and clk_2 enter the predefined logic structure within the dashed box at the same time, and are output to CKOUT through a certain logic circuit. If these input clocks are all the clocks required by the current clock constraint file, then the same number of gates and one register of input ports as the input clocks can be used instead.

The replacement module may simplify the algorithm of the analysis module. Taking fig. 2 as an example, the core idea of the analysis algorithm is to trace the clock pin of the current register to the previous stage register in the fan-in direction. The previous stage register is cycled through as a new current register with its clock pins tracking fan-in logic.

However, in the case of some complex circuits, as shown in fig. 3, the current register clock pin is fanned in from the output of the gate, the gate input is fanned in, one from the output of the register, and the other is fanned in from the two-input or gate, which is also fanned in from the outputs of two different registers. Analysis algorithms have difficulty resolving the function of these structures. The logical structure in the dashed box is thus taken as a predefined logical structure and replaced by a register as a simplified logical structure. In the synthesis tool, the structural replacement is done using the commands shown in fig. 4. After replacement, the analysis algorithm will continue to analyze the clock pins of the previous stage registers, avoiding complex logic, which will simplify the analysis algorithm. When the clock constraint file is generated, the clock constraint template corresponding to the predefined logic structure can be directly called, and the generation flow is simplified.

S4: and extracting a clock structure in the circuit topology structure through an analysis module, and storing the clock structure as a file in a self-defined format.

The method comprises the following specific steps: the core algorithm is an analysis_clock_structure function, the operation flow is shown in fig. 8, all registers in the design are obtained from the synthesis tool, and the registers are stored as a register list as inputs of the function. And defining a result_list for storing temporary tracking results.

Traversing the register list and each pin thereof, storing pin_hier, if the pin has clock attribute, acquiring starting points of all fan-ins and putting the starting points into a result variable, and if the starting points do not exist in the result_list, putting the starting points into the result variable;

if the type attribute of the result variable is a port, the input port which has been traced to the design logic structure is described as a definition point of the master clock, and the node information is recorded at this time and stored into a port_name in the format of:

ROOT：<port_name> LEAF: <pin_hier>；

if the type attribute of the result variable is a pin, the node is indicated to be in the design logic structure, and meanwhile, the pin is also indicated to be an output pin of a register at the upper stage, the hierarchy of the design logic structure where the pin is located is obtained, and the hierarchy is stored in the node reg;

the output pins of the register need to define derived clocks, so that the hierarchy of the pins is recorded, stored in pin_hier, and the format is as follows:

NODE: <node_reg > LEAF: <pin_hier>；

node_reg is used as a register and becomes the input of an analysis_clock_structure function to form a recursion algorithm, so that the whole design logic structure is traversed, and the acquired ROOT, NODE and LEAF information are continuously output in the traversing process to form a complete clock structure description file.

Where ROOT refers to the designed port, NODE refers to the output pin of the previous stage register, and LEAF refers to the output pin of the current register.

S5: and the clock constraint file generation module is used for generating a clock constraint file by analyzing the clock structure description file and reading in a clock constraint template corresponding to the predefined logic structure.

Clock structure description file:

proc_analyze_clock_after_elaborate.node.rpt；

the specific steps are as shown in fig. 9, traversing the clock structure description file, and restoring the true hierarchy of the predefined modules: the traversed result is put into a clk_bridges list.

The clock name prefix is defined in order to avoid renaming to the clock in other designs. From clk_branches, a key-value pair dictionary data structure is created: the key is the clock name clk_name and the value is the clock number clk_id.

Traversing clk_branches, for each clk_branch: if the branch has only one element, indicating that there is no previous element, the design input port is represented, so the output creates a master clock command:

create_clock -name $clk_name_{clk_id} -period ${freq} -add [get_ports {clk_pin}]；

if clk_branch has multiple elements, then clk_branch is traversed, from which the clock context is parsed: master_clock and generated_clock, and master_clock and generated_clock and clock_id information are applied to clock constraint templates corresponding to predefined logical structures.

When traversing the full clk_bridges list, all clock constraint commands have been written to the clock constraint file. On the basis of the generated clock constraint file, the user defines necessary variables, such as design_name, frequency division and frequency multiplication coefficients of each derived clock and the like, so as to form a final complete clock constraint file.

Claims (6)

1. The method for generating the chip clock constraint file is characterized by comprising the following steps:

step 1, reading an original data file;

step 2, carrying out register transmission level code expansion on the original data file;

step 3, replacing the complex logic structure with a predefined simplified logic structure by replacing the module;

step 4, analyzing the clock structure from the complete design logic structure through an analysis module, and storing the clock structure as a clock structure description file;

and 5, reading in the clock structure description file and a clock constraint template corresponding to the predefined simplified logic structure through a clock constraint generation module to generate a clock constraint file.

2. The method of claim 1, wherein the raw data file includes a register transfer level code and a standard cell library.

3. The method for generating a chip clock constraint file according to claim 1, wherein the step 2 specifically includes:

and performing code expansion on the original data file by using a comprehensive tool, wherein the code expansion refers to the conversion of codes from logic description to the topological structure of a circuit, and the logic relationship, nodes, pins and the attributes of the circuit structure can be inquired in the comprehensive tool.

4. The method for generating a chip clock constraint file according to claim 1, wherein the step 3 specifically includes:

tracking the fan-in logic structure of the register from the clock pin of the register until the output end of the former stage register;

tracking the fan-in logic structure of the previous stage register from the clock pin of the previous stage register again, traversing the whole design logic structure in a recursion mode, and replacing the original complex logic structure by the simplified logic structure when the register output pin level obtained in the tracking process accords with the predefined replacement condition of the simplified logic structure;

and storing the output pin hierarchy and port information of the register acquired in the tracking process as a clock structure description file.

5. The method for generating a chip clock constraint file according to claim 1, wherein the step 5 specifically includes:

traversing the clock structure description file, generating a create_generated_clock constraint command for each register output pin, generating a create_clock constraint command for each port, and calling a corresponding clock constraint template and saving as a clock constraint file if the register output pin hierarchy conforms to a predefined simplified logic structure.

6. The method for generating a chip clock constraint file according to claim 1, wherein the step 4 specifically includes:

using an analysis_clock_structure function, obtaining all registers in the design from the synthesis tool, and storing the registers as a register list as input of the function;

defining a result_list variable for storing temporary tracking results;

traversing the register list and each pin thereof, storing pin_hier, if the pin has clock attribute, acquiring starting points of all fan-ins and putting the starting points into a result variable, and if the starting points do not exist in the result_list, putting the starting points into the result variable;

if the type attribute of the result variable is a port, the input port which has been traced to the design logic structure is described as a definition point of the master clock, and the node information is recorded at this time and stored into a port_name in the format of:

ROOT：<port_name> LEAF: <pin_hier>；

if the type attribute of the result variable is a pin, the node is indicated to be in the design logic structure, and meanwhile, the pin is also indicated to be an output pin of a register at the upper stage, the hierarchy of the design logic structure where the pin is located is obtained, and the hierarchy is stored in the node reg;

the output pins of the register need to define derived clocks, so that the hierarchy of the pins is recorded, stored in pin_hier, and the format is as follows:

NODE: <node_reg > LEAF: <pin_hier>；

node_reg is used as a register and becomes the input of an analysis_clock_structure function to form a recursion algorithm, so that the whole design logic structure is traversed, and the acquired ROOT, NODE and LEAF information are continuously output in the traversing process to form a complete clock structure description file.

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