CN116382977B - Reset detection method and system applied to data communication and electronic equipment - Google Patents
Reset detection method and system applied to data communication and electronic equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a reset detection method, a system and electronic equipment applied to data communication, comprising the following steps: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module. The reset module transmits the generated hard reset signal and soft reset signal to the high-speed driving module. The high-speed driving module initializes the system, and the judging module determines an initialization result and sends initialization result abnormal information to the self-adaptive adjusting module; the self-adaptive adjusting module counts abnormal times when receiving the information, adjusts the clock period of the adjustable duration parameter and outputs the clock period to the resetting module, so that the resetting module generates a hard resetting signal and a soft resetting signal according to the adjusted adjustable duration parameter interval, and the system is initialized again. According to the application, the self-adaptive adjustment module can automatically circulate and control the reset module to send out the hard reset signals and the soft reset signals of the adjustable duration parameters with different intervals according to the initialization result, so that the system restarting efficiency is effectively improved when the system fails.
Description
Technical Field
The present application relates to the field of data communications technologies, and in particular, to a reset detection method and system applied to data communications, and an electronic device.
Background
In high-speed data communication, two types of reset, namely hardware reset and software reset exist, and a certain time sequence relation T is formed between the two types of reset. However, in practical circuit applications, the timing relationship T of hardware reset and software reset cannot be matched due to the influence of external environmental factors, so that channel reset transmission corresponding to the hardware reset and the software reset cannot be successful.
Disclosure of Invention
In order to solve the existing technical problems, the embodiment of the application provides a reset detection method, a system and electronic equipment applied to data communication.
In a first aspect, an embodiment of the present application provides a reset detection system applied to data communication, including: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module;
the reset module is used for generating a hard reset signal and a soft reset signal at intervals and sending the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles;
the high-speed driving module is used for initializing the system to be reset after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals;
the judging module is used for determining initialization results of the hard reset signal and the soft reset signal, and sending initialization result abnormality information to the self-adaptive adjusting module when the initialization results are abnormal;
the self-adaptive adjusting module is used for counting the number of abnormal results when the initialization result sent by the judging module is abnormal information, adjusting the clock cycle of the adjustable duration parameter according to the number of abnormal results, outputting the adjusted adjustable duration parameter to the resetting module, enabling the resetting module to generate a hard resetting signal and a soft resetting signal according to the adjusted adjustable duration parameter interval, and initializing the system to be reset again.
In a second aspect, an embodiment of the present application further provides a reset detection method applied to data communication, where the method is applied to a reset detection system, and includes: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module, wherein the method comprises the following steps:
starting the reset module, generating a hard reset signal and a soft reset signal at intervals, and transmitting the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles;
after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals, initializing the system to be reset by using the high-speed driving module;
determining initialization results of the hard reset signal and the soft reset signal through the judging module, and sending initialization result abnormality information to the self-adaptive adjusting module when the initialization results are abnormal;
when the self-adaptive adjustment module receives the abnormal information of the initialization result sent by the judgment module, counting the abnormal result times of the abnormal initialization result, adjusting the clock period of the adjustable duration parameter according to the abnormal result times, and outputting the adjusted adjustable duration parameter to the reset module, so that the reset module generates a hard reset signal and a soft reset signal according to the adjusted adjustable duration parameter interval, and initializing the system to be reset again.
In a third aspect, an embodiment of the present application provides an electronic device, including a bus, a transceiver, a memory, a processor, and a computer program stored in the memory and executable on the processor, where the transceiver, the memory, and the processor are connected by the bus, and where the computer program when executed by the processor implements the steps in any one of the above reset detection methods.
In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium having stored thereon a computer program, which when executed by a processor, implements the steps of the reset detection method described in any one of the above.
In the solutions provided in the first to fourth aspects of the present application, the reset module sends a hard reset signal and a soft reset signal to the high-speed driving module at intervals of the adjustable duration parameter, the high-speed driving module initializes the system after receiving the hard reset signal and the soft reset signal sent by the reset module, the judging module judges the initialization result of the system, when the initialization result is abnormal, the adaptive adjustment module counts the number of abnormal results of the initialization result as abnormal, adjusts the clock period of the adjustable duration parameter according to the number of abnormal results, the adaptive adjustment module returns the adjusted adjustable duration parameter to the bit module, and the reset module generates the hard reset signal and the soft reset signal at intervals of the adjusted adjustable duration parameter, so as to initialize the system again until the initialization result is non-abnormal, and stops the cycle. Compared with the prior art that the initialization result is required to be detected manually and repeatedly, the initialization result can be automatically fed back without frequently detecting the whole system manually, so that the labor intensity and the labor cost of manpower can be effectively reduced; meanwhile, the self-adaptive adjusting module can automatically circulate and control the resetting module to send out hard resetting signals and soft resetting signals of different intervals and adjustable duration parameters according to the initialization result, and the restarting efficiency of the system when the system fails is effectively improved.
Drawings
In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.
FIG. 1 shows a flow chart of a reset detection system for data communication according to an embodiment of the present application;
FIG. 2 is a flowchart of a reset detection method applied to data communication according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the method is applied to a reset detection method for data communication.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The present application will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present application.
There are typically two resets in high speed data communications, namely a hardware reset (hard_rst) and a software reset (soft_rst), which have a timing relationship (i.e., the adjustable duration parameter in the present application). Such timing relationships often result in mismatch of the timing relationships of the hardware reset and the software reset due to some external environmental factors in the actual circuit, thereby making the corresponding channel reset unsuccessful. In the normal state, the timing relationship is equal to the preset value T 0 However, in actual operation, time deviation and system interference (difference in wiring length between two reset signals and the controlled module) caused by random interference are encountered, resulting in a difference from a preset value T 0 There is a difference that requires changing the timing relationship between the two.
The application feeds back the reset system through detecting the channel link enabling signal, and circularly and adaptively adjusts the reset module until the channel transmission is normal.
Example 1
The reset detection system proposed in the present embodiment may be a computing device such as a server capable of executing the reset operation proposed in the present embodiment.
The embodiment provides a reset detection system applied to data communication, referring to a flowchart of the reset detection system shown in fig. 1, the system includes: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module.
And a reset module: the method comprises the steps of generating a hard reset signal and a soft reset signal at intervals, and sending the hard reset signal and the soft reset signal generated at intervals to a high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles.
The reset module is used for generating a hard reset signal and a soft reset signal at intervals and transmitting the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module so as to perform system initialization operation for the first time.
Specifically, the reset module may obtain, through a reset stability schedule, an initial adjustable duration parameter used when the system initialization operation is performed for the first time. The reset stability time table is a hardware reset and hardware stability time relation comparison table which is artificially manufactured in advance. The required data to reset the stability schedule includes, but is not limited to, experimental measurements, network disclosure, and personal experience of those skilled in the art.
And resetting the stable schedule, and caching the stable schedule in the resetting module.
The initial adjustable duration parameter is used for representing the time interval of generating a hard reset signal and a soft reset signal when the reset module performs the system initialization operation for the first time.
In one embodiment, the initial adjustable duration parameter may include 128 clock cycles.
And a high-speed driving module: the system is used for initializing the system to be reset after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals.
An operation of initializing a system, comprising: hardware initialization operations based on the hard reset signal and software initialization operations based on the soft reset signal.
The specific process of the hardware initialization operation and the specific process of the software initialization operation are all in the prior art, and are not described herein.
And a judging module: and the initialization result is used for determining the initialization results of the hard reset signal and the soft reset signal, and when the initialization result is abnormal, the initialization result abnormal information is sent to the self-adaptive adjustment module.
Specifically, the judging module determines whether the initialization of the system is successful by judging whether the output port level in the system is pulled up or not, specifically, the judging module may perform the following steps (1) to (2):
(1) When the initialization result is normal, the system initialization is successful;
(2) And when the initialization result is abnormal, sending initialization result abnormal information to the self-adaptive adjustment module.
In the steps (1) to (2), the output ports refer to channel ports and Lane ports set on the system, and the channel ports and Lane ports are respectively connected with the judging module.
When the judging module obtains the high-level signal sent by the channel port and the high-level signal sent by the Lane port, the output port level is determined to be high, the initializing operation of the system is completed, a normal initializing result is obtained, and the reset detection method applied to data communication provided by the embodiment is ended.
When the judging module determines that the channel port and the Lane port do not send out high-level signals, the output port level is not pulled up, the initialization operation performed on the system is not completed, an abnormal initialization result is obtained, initialization result abnormal information is generated according to the abnormal initialization result, and the initialization result abnormal information is sent to the self-adaptive adjusting module, so that the self-adaptive adjusting module adjusts the clock period of the adjustable duration parameter.
After the self-adaptive adjustment module receives the initialization result abnormal information, the clock period of the adjustable duration parameter can be adjusted. Specifically, when the initialization result sent by the judging module is abnormal information, the self-adaptive adjusting module is used for counting the abnormal result times that the initialization result is abnormal, adjusting the clock period of the adjustable duration parameter according to the abnormal result times, and outputting the adjusted adjustable duration parameter to the resetting module, so that the resetting module generates a hard resetting signal and a soft resetting signal according to the adjusted adjustable duration parameter interval, and the system to be reset is initialized again.
The specific process for counting the number of abnormal results with the initialization result being abnormal comprises the following steps: and performing increment operation on the number of abnormal results stored in the self-adaptive adjustment module, so as to obtain the number of abnormal results after increment operation, wherein the number of abnormal results is used as the number of abnormal results of which the statistical initialization result is abnormal.
Specifically, the self-adaptive adjustment module is configured to adjust a clock period of the adjustable duration parameter according to the number of abnormal results, and includes the following specific processes:
the clock period of the adjustable duration parameter is adjusted by the following formula:
T 1 ＝T+(n-1)*t
wherein t represents the duration of a unit clock period; t represents an adjustable duration parameter before adjustment; t (T) 1 Representing the adjusted adjustable duration parameter; n represents the number of statistically abnormal results.
Here, the counted number of abnormal results is the number of abnormal results in which the above-described statistical initialization result is abnormal.
The time length of the unit clock period is pre-cached in the self-adaptive adjustment module.
Specifically, the adaptive adjustment module, configured to output the adjusted adjustable duration parameter to the reset module, may include the following steps (1) to (3):
(1) Counting the number of clock cycles in the adjusted adjustable duration parameter;
(2) Stopping the reset flow of the system when the number of clock cycles in the adjusted adjustable duration parameter reaches the threshold value of the number of clock cycles;
(3) And outputting the adjusted adjustable duration parameter to a reset module when the number of clock cycles in the adjusted adjustable duration parameter is determined to be smaller than the threshold value of the number of clock cycles. In the step (1), the number of clock cycles in the adjusted adjustable duration parameter may be counted by dividing the adjusted adjustable duration parameter by the duration of a unit clock cycle.
In the step (2), the threshold value of the clock cycle number is pre-cached in the adaptive adjustment module.
The threshold number of clock cycles may take any integer between 130 and 150.
In one embodiment, the number of clock cycles threshold may be 140.
After the system initialization operation fails for the first time, the reset detection system provided in this embodiment may execute the following procedure:
when the system fails to initialize for the first time (initialization is abnormal), the counted abnormal result number of times is 1 and is substituted into the formula, the adjusted adjustable duration parameter is equal to the adjustable duration parameter before adjustment, and the fact that the self-adaptive adjustment module does not change the value of the adjusted adjustable duration parameter when the initial fails is indicated, and the self-adaptive adjustment module still sends the value of the adjusted adjustable duration parameter to the reset module according to the clock cycle number of the adjustable duration parameter before adjustment.
And when the second initialization fails, the self-adaptive adjustment module increases the adjusted adjustable duration parameter by one clock cycle. And when the system fails to initialize for the third time, the adjusted adjustable duration parameter is increased by two clock cycles, and the like until the clock cycles of the adjustable duration parameter reach the threshold value of the number of clock cycles. The clock cycle number threshold is set manually, and the clock cycle number threshold and the clock cycle value of the initial adjustable duration parameter are different according to different scenes of system application. For example, if the system adopts a vivado platform, the initial adjustable duration parameter is 128 clock cycles, and the threshold number of clock cycles is 140. The system finishes the circulation, and one is that the clock period of the adjustable duration parameter reaches the threshold value of the number of clock periods or the initialization is successful, and the self-adaptive module terminates sending the adjusted adjustable duration parameter to the reset module.
In summary, the reset module sends a hard reset signal and a soft reset signal to the high-speed driving module with the adjustable duration parameter as an interval, the high-speed driving module initializes the system after receiving the hard reset signal and the soft reset signal sent by the reset module, the judging module judges the initialization result of the system, when the initialization result is abnormal, the self-adaptive adjustment module counts the abnormal result times of the initialization result being abnormal, adjusts the clock period of the adjustable duration parameter according to the abnormal result times, the self-adaptive adjustment module transmits the adjusted adjustable duration parameter to the reset module, the reset module generates the hard reset signal and the soft reset signal with the adjusted adjustable duration parameter as an interval, and further initializes the system again until the initialization result is non-abnormal, and the cycle is stopped; compared with the prior art that the initialization result is required to be detected manually and repeatedly, the initialization result can be automatically fed back without frequently detecting the whole system manually, so that the labor intensity and the labor cost of manpower can be effectively reduced; meanwhile, the self-adaptive adjusting module can automatically circulate and control the resetting module to send out hard resetting signals and soft resetting signals of different intervals and adjustable duration parameters according to the initialization result, and the restarting efficiency of the system is effectively improved when the system fails.
Example 2
The embodiment of the application also provides a reset detection method applied to data communication, referring to a flowchart of the reset detection method shown in fig. 2, the method is applied to the reset detection system provided in embodiment 1, and the method comprises the following steps:
step 100: and starting the reset module, generating a hard reset signal and a soft reset signal at intervals, and transmitting the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles.
Step 101: and after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals, initializing the system to be reset by using the high-speed driving module.
Step 102: and determining initialization results of the hard reset signal and the soft reset signal through the judging module, and sending initialization result abnormality information to the self-adaptive adjusting module when the initialization results are abnormal.
Step 103: when the self-adaptive adjusting module receives the abnormal information of the initialization result sent by the judging module, counting the abnormal result times of the abnormal initialization result, adjusting the clock period of the adjustable duration parameter according to the abnormal result times, and outputting the adjusted adjustable duration parameter to the resetting module, so that the resetting module generates a hard resetting signal and a soft resetting signal according to the adjusted adjustable duration parameter interval, and initializing the system to be reset again.
Specifically, the flow of the above reset detection has been described in detail in embodiment 1, and thus, will not be repeated.
Further, the adaptive adjustment module is configured to adjust a clock period of the adjustable duration parameter according to the number of abnormal results, and includes:
the clock period of the adjustable duration parameter is adjusted by the following formula:
T 1 ＝T+(n-1)*t
wherein t represents the duration of a unit clock period; t represents an adjustable duration parameter before adjustment; t (T) 1 Representing the adjusted adjustable duration parameter; n represents the number of statistically abnormal results.
Still further, the adaptive adjustment module is configured to output the adjusted adjustable duration parameter to the reset module, and includes:
counting the number of clock cycles in the adjusted adjustable duration parameter;
stopping the reset flow of the equipment when the number of clock cycles in the adjusted adjustable duration parameter reaches the threshold value of the number of clock cycles;
and outputting the adjusted adjustable duration parameter to a reset module when the number of clock cycles in the adjusted adjustable duration parameter is determined to be smaller than the threshold value of the number of clock cycles.
In summary, the reset module sends a hard reset signal and a soft reset signal to the high-speed driving module with the adjustable duration parameter as an interval, the high-speed driving module initializes the system after receiving the hard reset signal and the soft reset signal sent by the reset module, the judging module judges the initialization result of the system, when the initialization result is abnormal, the self-adaptive adjustment module counts the abnormal result times of the initialization result being abnormal, adjusts the clock period of the adjustable duration parameter according to the abnormal result times, the self-adaptive adjustment module transmits the adjusted adjustable duration parameter to the reset module, the reset module generates the hard reset signal and the soft reset signal with the adjusted adjustable duration parameter as an interval, and further initializes the system again until the initialization result is non-abnormal, and the cycle is stopped; compared with the prior art that the initialization result is required to be detected manually and repeatedly, the initialization result can be automatically fed back without frequently detecting the whole system manually, so that the labor intensity and the labor cost of manpower can be effectively reduced; meanwhile, the self-adaptive adjusting module can automatically circulate and control the resetting module to send out hard resetting signals and soft resetting signals of different intervals and adjustable duration parameters according to the initialization result, and the restarting efficiency of the system is effectively improved when the system fails.
Example 3
The embodiment of the application also provides an electronic device, which comprises a bus, a transceiver 1130, a memory, a processor and a computer program running on the processor, wherein the transceiver, the memory and the processor are respectively connected through the bus, and the computer program realizes the processes of the embodiment 2 when being executed by the processor, and can achieve the same technical effects, so that the repetition is avoided and the description is omitted.
Specifically, the electronic device participating in the reset detection method shown in fig. 3 is a schematic structural diagram, and the electronic device further includes: computer programs stored on the memory 1150 and executable on the processor 1120, which when executed by the processor 1120, implement the various processes of the reset detection method embodiments described above.
A transceiver 1130 for receiving and transmitting data under the control of the processor 1120.
In an embodiment of the application, represented by bus 1110, bus 1110 may include any number of interconnected buses and bridges, with bus 1110 connecting various circuits, including one or more processors, represented by processor 1120, and memory, represented by memory 1150.
Bus 1110 represents one or more of any of several types of bus structures, including a memory bus and a memory controller, a peripheral bus, an accelerated graphics port (Accelerate Graphical Port, AGP), a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such an architecture includes: industry standard architecture (Industry Standard Architecture, ISA) bus, micro channel architecture (Micro Channel Architecture, MCA) bus, enhanced ISA (EISA) bus, video electronics standards association (VideoElectronics Standards Association, VESA) bus, peripheral component interconnect (Peripheral Component Interconnect, PCI) bus.
Processor 1120 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments may be implemented by instructions in the form of integrated logic circuits in hardware or software in a processor. The processor includes: general purpose processors, central processing units (Central Processing Unit, CPU), network processors (Network Processor, NP), digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA), complex programmable logic devices (Complex Programmable Logic Device, CPLD), programmable logic arrays (Programmable Logic Array, PLA), micro control units (Microcontroller Unit, MCU) or other programmable logic devices, discrete gates, transistor logic devices, discrete hardware components. The methods, steps and logic blocks disclosed in the embodiments of the present application may be implemented or performed. For example, the processor may be a single-core processor or a multi-core processor, and the processor may be integrated on a single chip or located on multiple different chips.
The processor 1120 may be a microprocessor or any conventional processor. The steps of the method disclosed in connection with the embodiments of the present application may be performed directly by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules may be located in a random access Memory (Random Access Memory, RAM), flash Memory (Flash Memory), read-Only Memory (ROM), programmable ROM (PROM), erasable Programmable ROM (EPROM), registers, and so forth, as are known in the art. The readable storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
Bus 1110 may also connect together various other circuits such as peripheral devices, voltage regulators, or power management circuits, bus interface 1140 providing an interface between bus 1110 and transceiver 1130, all of which are well known in the art. Accordingly, the embodiments of the present application will not be further described.
The transceiver 1130 may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. For example: the transceiver 1130 receives external data from other devices, and the transceiver 1130 is configured to transmit the data processed by the processor 1120 to the other devices. Depending on the nature of the computer system, a user interface 1160 may also be provided, for example: touch screen, physical keyboard, display, mouse, speaker, microphone, trackball, joystick, stylus.
It should be appreciated that in embodiments of the present application, the memory 1150 may further comprise memory located remotely from the processor 1120, such remotely located memory being connectable to a server through a network. One or more portions of the above-described networks may be an ad hoc network (ad hoc network), an intranet, an extranet (extranet), a Virtual Private Network (VPN), a Local Area Network (LAN), a Wireless Local Area Network (WLAN), a Wide Area Network (WAN), a Wireless Wide Area Network (WWAN), a Metropolitan Area Network (MAN), the Internet (Internet), a Public Switched Telephone Network (PSTN), a plain old telephone service network (POTS), a cellular telephone network, a wireless fidelity (Wi-Fi) network, and a combination of two or more of the above-described networks. For example, the cellular telephone network and wireless network may be a global system for mobile communications (GSM) system, a Code Division Multiple Access (CDMA) system, a Worldwide Interoperability for Microwave Access (WiMAX) system, a General Packet Radio Service (GPRS) system, a Wideband Code Division Multiple Access (WCDMA) system, a Long Term Evolution (LTE) system, an LTE Frequency Division Duplex (FDD) system, an LTE Time Division Duplex (TDD) system, a long term evolution-advanced (LTE-a) system, a Universal Mobile Telecommunications (UMTS) system, an enhanced mobile broadband (Enhance Mobile Broadband, embbb) system, a mass machine type communication (massive Machine Type of Communication, mctc) system, an ultra reliable low latency communication (Ultra Reliable Low Latency Communications, uirllc) system, and the like.
It should be appreciated that the memory 1150 in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Wherein the nonvolatile memory includes: read-Only Memory (ROM), programmable ROM (PROM), erasable Programmable EPROM (EPROM), electrically Erasable EPROM (EEPROM), or Flash Memory (Flash Memory).
The volatile memory includes: random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as: static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SynchronousDRAM, SDRAM), double data rate synchronous DRAM (DoubleDataRateSDRAM, DDRSDRAM), enhanced synchronous DRAM (EnhancedSDRAM, ESDRAM), synchronous link DRAM (SynchlinkDRAM, SLDRAM), and Direct memory bus RAM (Direct RambusRAM, DRRAM). The memory 1150 of the electronic device described in embodiments of the present application includes, but is not limited to, the above and any other suitable types of memory.
In an embodiment of the application, memory 1150 stores the following elements of operating system 1151 and application programs 1152: an executable module, a data structure, or a subset thereof, or an extended set thereof.
Specifically, the operating system 1151 includes various system programs, such as: a framework layer, a core library layer, a driving layer and the like, which are used for realizing various basic services and processing tasks based on hardware. The applications 1152 include various applications such as: a media player (MediaPlayer), a Browser (Browser) for implementing various application services. A program for implementing the method of the embodiment of the present application may be included in the application 1152. The application 1152 includes: applets, objects, components, logic, data structures, and other computer system executable instructions that perform particular tasks or implement particular abstract data types.
In addition, the embodiment of the present application further provides a computer readable storage medium, on which a computer program is stored, where the computer program when executed by a processor implements each process of the above embodiment of the reset detection method, and the same technical effects can be achieved, so that repetition is avoided, and no further description is given here.
The computer-readable storage medium includes: persistent and non-persistent, removable and non-removable media are tangible devices that may retain and store instructions for use by an instruction execution device. The computer-readable storage medium includes: electronic storage, magnetic storage, optical storage, electromagnetic storage, semiconductor storage, and any suitable combination of the foregoing. The computer-readable storage medium includes: phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), non-volatile random access memory (NVRAM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital Versatile Disks (DVD) or other optical storage, magnetic cassette storage, magnetic tape disk storage or other magnetic storage devices, memory sticks, mechanical coding (e.g., punch cards or bump structures in grooves with instructions recorded thereon), or any other non-transmission medium that may be used to store information that may be accessed by a computing device. In accordance with the definition in the present embodiments, the computer-readable storage medium does not include a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a pulse of light passing through a fiber optic cable), or an electrical signal transmitted through a wire.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus, electronic device, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one position, or may be distributed over a plurality of network units. Some or all of the units can be selected according to actual needs to solve the problem to be solved by the scheme of the embodiment of the application.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application is essentially or partly contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (including: a personal computer, a server, a data center or other network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the storage medium includes various media as exemplified above that can store program codes.
In the description of the embodiments of the present application, those skilled in the art will appreciate that the embodiments of the present application may be implemented as a method, an apparatus, an electronic device, and a computer-readable storage medium. Thus, embodiments of the present application may be embodied in the following forms: complete hardware, complete software (including firmware, resident software, micro-code, etc.), a combination of hardware and software. Furthermore, in some embodiments, embodiments of the application may also be implemented in the form of a computer program product in one or more computer-readable storage media having computer program code embodied therein.
Any combination of one or more computer-readable storage media may be employed by the computer-readable storage media described above. The computer-readable storage medium includes: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer readable storage medium include the following: portable computer diskette, hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory (FlashMemory), optical fiber, compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any combination thereof. In embodiments of the present application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, device.
The computer program code embodied in the computer readable storage medium may be transmitted using any appropriate medium, including: wireless, wire, fiber optic cable, radio frequency (RadioFrequency, RF), or any suitable combination thereof.
Computer program code for carrying out operations of embodiments of the present application may be written in assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or in one or more programming languages, including an object oriented programming language such as: java, smalltalk, C ++, also include conventional procedural programming languages, such as: c language or similar programming language. The computer program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of remote computers, the remote computers may be connected via any sort of network, including: a Local Area Network (LAN) or a Wide Area Network (WAN), which may be connected to the user's computer or to an external computer.
The embodiment of the application describes a method, a device and electronic equipment through flowcharts and/or block diagrams.
It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer readable program instructions may also be stored in a computer readable storage medium that can cause a computer or other programmable data processing apparatus to function in a particular manner. Thus, instructions stored in a computer-readable storage medium produce an instruction means which implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The foregoing is merely a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the embodiment of the present application, and the changes or substitutions are covered by the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (6)
1. A reset detection system for use in data communications, comprising: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module;
the reset module is used for generating a hard reset signal and a soft reset signal at intervals and sending the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles;
the high-speed driving module is used for initializing the system to be reset after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals;
the judging module is used for determining initialization results of the hard reset signal and the soft reset signal, and sending initialization result abnormality information to the self-adaptive adjusting module when the initialization results are abnormal;
the self-adaptive adjustment module is used for counting the number of abnormal results when the initialization result sent by the judgment module is abnormal information, adjusting the clock cycle of the adjustable duration parameter according to the number of abnormal results, and outputting the adjusted adjustable duration parameter to the reset module, so that the reset module generates a hard reset signal and a soft reset signal according to the adjusted adjustable duration parameter interval, and initializing the system to be reset again;
the self-adaptive adjustment module is configured to adjust a clock period of the adjustable duration parameter according to the number of abnormal results, and includes:
the clock period of the adjustable duration parameter is adjusted by the following formula:
T 1 ＝T+(n-1)*t
wherein t represents the duration of a unit clock period; t represents an adjustable duration parameter before adjustment; t (T) 1 Representing the adjusted adjustable duration parameter; n represents the number of statistically abnormal results.
2. The reset detection system of claim 1 wherein the adaptive adjustment module for outputting the adjusted adjustable duration parameter to the reset module comprises:
counting the number of clock cycles in the adjusted adjustable duration parameter;
stopping the reset flow of the system when the number of clock cycles in the adjusted adjustable duration parameter reaches the threshold value of the number of clock cycles;
and outputting the adjusted adjustable duration parameter to the reset module when the number of clock cycles in the adjusted adjustable duration parameter is smaller than the threshold value of the number of clock cycles.
3. A reset detection method applied to data communication, the method being applied to a reset detection system, comprising: the device comprises a reset module, a high-speed driving module, a judging module and a self-adaptive adjusting module, and is characterized in that the method comprises the following steps:
starting the reset module, generating a hard reset signal and a soft reset signal at intervals, and transmitting the hard reset signal and the soft reset signal generated at intervals to the high-speed driving module, wherein the time interval between the hard reset signal and the soft reset signal is an adjustable duration parameter, and the adjustable duration parameter comprises a plurality of clock cycles;
after receiving the hard reset signal and the soft reset signal sent by the reset module at intervals, initializing the system to be reset by using the high-speed driving module;
determining initialization results of the hard reset signal and the soft reset signal through the judging module, and sending initialization result abnormality information to the self-adaptive adjusting module when the initialization results are abnormal;
when the self-adaptive adjustment module receives the abnormal information of the initialization result sent by the judgment module, counting the abnormal result times of the abnormal initialization result, adjusting the clock cycle of the adjustable duration parameter according to the abnormal result times, and outputting the adjusted adjustable duration parameter to the reset module, so that the reset module generates a hard reset signal and a soft reset signal according to the adjusted adjustable duration parameter interval, and re-initializes the system to be reset, wherein the self-adaptive adjustment module is used for adjusting the clock cycle of the adjustable duration parameter according to the abnormal result times, and comprises the following steps:
the clock period of the adjustable duration parameter is adjusted by the following formula:
T 1 ＝T+(n-1)*t
wherein t represents the duration of a unit clock period; t represents an adjustable duration parameter before adjustment; t (T) 1 Representing the adjusted adjustable duration parameter; n represents the number of statistically abnormal results.
4. The reset detection method of claim 3, wherein the adaptive adjustment module configured to output the adjusted adjustable duration parameter to the reset module comprises:
counting the number of clock cycles in the adjusted adjustable duration parameter;
stopping the reset flow of the system when the number of clock cycles in the adjusted adjustable duration parameter reaches the threshold value of the number of clock cycles;
and outputting the adjusted adjustable duration parameter to the reset module when the number of clock cycles in the adjusted adjustable duration parameter is smaller than the threshold value of the number of clock cycles.
5. An electronic device comprising a bus, a transceiver, a memory, a processor and a computer program stored on the memory and executable on the processor, the transceiver, the memory and the processor being connected by the bus, characterized in that the computer program when executed by the processor implements the steps of the reset detection method according to any of claims 3 to 4.
6. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the reset detection method according to any one of claims 3 to 4.
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