CN116368730A

CN116368730A - Apparatus and method for power sensitive circuit compensating for power supply voltage variations

Info

Publication number: CN116368730A
Application number: CN202180068828.9A
Authority: CN
Inventors: M·埃尔-诺扎伊; A·埃尔加马尔
Original assignee: Analog Devices International ULC
Current assignee: Analog Devices International ULC
Priority date: 2020-10-21
Filing date: 2021-10-18
Publication date: 2023-06-30
Also published as: WO2022084260A1; US20230376064A1; US11755047B2; EP4233172A1; US20220121234A1

Abstract

Apparatus and methods for a power sensitive circuit for compensating for supply voltage variations are provided. In some embodiments, an electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a set of Integrated Circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a power supply sensing circuit that generates a sense signal based on a local voltage level of a power supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between a nominal voltage level of the power supply voltage and the local voltage level, and a signal processing circuit that is biased by the bias signal.

Description

Apparatus and method for power sensitive circuit compensating for power supply voltage variations

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly, to powering sensitive circuits.

Background

An Integrated Circuit (IC) includes at least one power pin for receiving a supply voltage from a power supply. The supply voltage received by the IC is used to provide power to circuitry formed on the IC.

When connected to the circuit board, the IC receives a supply voltage through the circuit board traces. For example, the circuit board may correspond to a Printed Circuit Board (PCB) that has been patterned to form a power bus for delivering a power supply voltage to the IC.

Disclosure of Invention

Apparatus and methods for a power sensitive circuit for compensating for supply voltage variations are provided. In some embodiments, an electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a set of Integrated Circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a power supply sensing circuit that generates a sense signal based on a local voltage level of a power supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between a nominal voltage level and the local voltage level of the power supply voltage, and a signal processing circuit that is biased by the bias signal. By implementing an IC with supply voltage compensation in this manner, the signal processing circuit exhibits power-invariant performance.

In one aspect, an electronic system is provided. An electronic system includes a supply conductor configured to route a supply voltage having a nominal voltage level, and a plurality of semiconductor die, each semiconductor die configured to receive the supply voltage from the supply conductor. Each of the plurality of semiconductor die includes a power supply sensing circuit configured to generate a sensing signal based on a local voltage level of the power supply voltage, a bias control circuit configured to adjust a bias signal based on the sensing signal to account for differences between the nominal voltage level and the local voltage level of the power supply voltage, and a signal processing circuit biased by the bias signal.

In another aspect, a method of compensating for supply voltage variations in an electronic system is provided that includes providing a supply voltage to a plurality of semiconductor dies using a supply conductor, the supply voltage having a nominal voltage level. The method further comprises the steps of: sensing a local voltage level of a supply voltage for each of the plurality of semiconductor die, adjusting a bias signal on each of the plurality of semiconductor die to account for a difference between the nominal voltage level and the local voltage level of the supply voltage, and biasing a signal processing circuit on each of the plurality of semiconductor die with the bias signal.

In another aspect, a semiconductor die for a multi-chip signal processing system is provided. The semiconductor die includes a power supply pin configured to receive a power supply voltage, a power supply sensing circuit configured to generate a sense signal based on a local voltage level of the power supply voltage at the power supply pin, a bias control circuit configured to adjust a bias signal based on the sense signal to account for a difference between a nominal voltage level of the power supply voltage and the local voltage level of the power supply voltage, and a signal processing circuit biased by the bias signal.

Drawings

FIG. 1A is a schematic diagram of one embodiment of an electronic system with supply voltage variation compensation.

FIG. 1B is a schematic diagram of another embodiment of an electronic system with supply voltage variation compensation.

Fig. 2A is a schematic diagram of an Integrated Circuit (IC) with supply voltage variation compensation according to another embodiment.

FIG. 2B is a graph of one example of supply current versus supply voltage for one embodiment of the IC of FIG. 2A.

Fig. 3 is a schematic diagram of a power supply insensitive amplifier in accordance with one embodiment.

Fig. 4A is a schematic diagram of a power insensitive amplifier in accordance with another embodiment.

Fig. 4B is a schematic diagram of a power insensitive amplifier in accordance with another embodiment.

Fig. 4C is a schematic diagram of a power insensitive amplifier according to another embodiment.

Fig. 4D is a schematic diagram of a power insensitive amplifier according to another embodiment.

Fig. 5A is an example plot of gain versus frequency for three different supply voltage levels.

Fig. 5B is a graph of another example of gain versus frequency curves for three different supply voltage levels.

Fig. 6 is a schematic diagram of a multi-chip beamforming system according to one embodiment.

Fig. 7 is a schematic diagram of a phased array antenna system according to one embodiment.

Detailed Description

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be implemented in numerous different manners. In this specification, reference is made to the drawings, wherein like reference numerals may refer to identical or functionally similar elements. It will be appreciated that the elements illustrated in the drawings figures are not necessarily drawn to scale. Furthermore, it should be understood that certain embodiments may include more elements than shown in the figures and/or subsets of elements illustrated in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more drawings.

Apparatus and methods for a power sensitive circuit for compensating for supply voltage variations are provided. In some embodiments, an electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a set of Integrated Circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a power supply sensing circuit that generates a sense signal based on a local voltage level of a power supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between a nominal voltage level and the local voltage level of the power supply voltage, and a signal processing circuit that is biased by the bias signal.

By implementing an IC with supply voltage compensation in this manner, the signal processing circuit exhibits power-invariant performance. Without such compensation, the performance of the signal processing circuit is affected by variations in the voltage level of the supply voltage relative to the nominal voltage level. For example, the signal processing circuitry may perform various analog and/or RF signaling functions including, but not limited to, amplification, phase shifting, and/or frequency dependent processing, and the performance of such functions may be affected by a particular voltage level of the supply voltage.

Thus, the signal processing circuit has a dynamically adjusted bias to account for supply voltage variations. For example, each signal processing circuit may include an amplifier having a DC operating point set by a bias signal, and the bias control circuit of each IC adjusts the local bias signal to keep the gain of the amplifier substantially constant.

In some implementations, each signal processing circuit corresponds to a signal processing channel of an electronic system, and the outputs of each signal processing unit are combined to generate a combined signal. For example, the electronic system may correspond to a phased array antenna system, and the signal processing circuitry may be used for gain control and/or phase control when forming the signal beam.

In such applications, the overall performance of the electronic system is enhanced by reducing or eliminating the effects of supply voltage drops on inter-channel variations. For example, in a beamforming application, the output of the signal processing circuitry may be used to generate a signal beam having a precise scan angle.

FIG. 1A is a schematic diagram of one embodiment of an electronic system 10 with supply voltage variation compensation. The electronic system 10 comprises an IC 1, a power supply 4 and a supply conductor 5. An integrated circuit, such as IC 1 of fig. 1A, is also referred to herein as a semiconductor die or semiconductor chip.

As shown in fig. 1A, power supply 4 generates a supply voltage VSUP that is provided to one or more power pins of IC 1 via supply conductor 5. In some embodiments, the electronic system 10 is implemented on a circuit board, and the power supply conductors 5 correspond to conductive traces of the circuit board. In some embodiments, the power supply 4 may correspond to another IC, such as a power management IC comprising at least one switch mode power supply and/or at least one DC-DC converter.

Due to the non-zero impedance of the supply conductor 5, the losses result in the local voltage level of the supply voltage VSUP' received at the IC 1 being lower than the nominal voltage level of the supply voltage VUP directly at the output of the power supply 4. For example, the supply conductor 5 may have a resistance that causes a current resistor (i×r) voltage drop and a corresponding difference between the nominal voltage level and the local voltage level. Furthermore, even when the supply conductor 5 is very wide and thick for low resistivity, voltage drops may occur in applications where the IC 1 draws a relatively large amount of current.

In the illustrated embodiment, the IC 1 includes a signal processing circuit 11, a power supply sensing circuit 12, and a bias control circuit 13.

The signal processing circuit 11 receives an input signal IN and generates an output signal OUT. The signal processing circuit 11 also receives a BIAS signal BIAS for biasing the signal processing circuit 11. For example, the signal processing circuit 11 may comprise analog and/or RF circuits operating with a DC BIAS point set by the BIAS signal BIAS. Although shown as outputting an output signal and receiving an input signal and a bias signal, the signal processing circuit 11 may be adapted to include any number of inputs and/or outputs.

Without compensation, the performance of the signal processing circuit 11 is affected by the voltage level variation of the power supply voltage VSUP'. For example, the signal processing circuit 11 may perform various analog and/or RF signaling functions, such as amplification, phase shifting, and/or frequency dependent processing, and the performance of such functions may be affected by the particular voltage level of the supply voltage VSUP'.

To take account of the supply voltage variation, the supply sensing circuit 12 SENSEs the voltage level of the supply voltage VSUP' and generates a SENSE signal SENSE that is provided to the bias control circuit 13. The BIAS control circuit 13 processes the SENSE signal SENSE to provide an adjustment to the BIAS signal BIAS such that the performance of the signal processing circuit 11 is substantially the same in the event of a change in the supply voltage VSUP'. Thus, even if the local voltage level is 10mV, 50mV or 100mV below the nominal voltage level, the adjustment of the BIAS signal BIAS keeps the operation of the signal processing circuit 11 constant at all such supply voltages.

Therefore, by realizing the IC 1 with power supply voltage compensation, the signal processing circuit 11 exhibits power supply invariant performance.

Fig. IB is a schematic diagram of another embodiment of an electronic system 20 with supply voltage variation compensation. The electronic system 20 includes an IC la, lb.

In contrast to the electronic system 10 of fig. 1A, the electronic system 20 of fig. 1B includes a plurality of ICs powered by a supply voltage VSUP provided by the power supply 4. Although an example with three ICs is shown, more or fewer ICs may be included as indicated by the ellipses.

As shown In fig. 1B, supply voltage VSUP is routed from the output of power supply 4 through supply conductor 5' to pins of IC la, lb. In some embodiments, the electronic system 20 is implemented on a circuit board, and the power supply conductors 5' correspond to conductive traces of the circuit board.

Conductor length varies between power supply 4 and each IC la, lb. Furthermore, even In the case where the conductor lengths match between the power supply 4 and each IC la, lb.

In the illustrated example, the IC la includes one or more power pins that receive a power supply voltage VSUP'. In addition, the IC lb includes one or more power pins receiving a supply voltage VSUP ", and the IC In includes one or more power pins receiving a supply voltage VSUP'". Thus, the local voltage level of the In supply voltage for each IC la, lb.) the received supply voltage level may vary from IC to IC.

To account for supply voltage variations, each IC la, lb. For example, the IC 1a includes a power supply sensing circuit 12a generating a sensing signal SENSE ', a BIAS control circuit 13a generating a BIAS signal BIAS' regulated by the sensing signal SENSE ', and a signal processing circuit 11a biased by the BIAS signal BIAS' and processing an input signal INa to generate an output signal OUTa.

Likewise, IC 1b includes a power supply SENSE circuit 12b that generates a SENSE signal SENSE ", a BIAS control circuit 13b that generates a BIAS signal BIAS" that is conditioned by SENSE signal SENSE ", and a signal processing circuit 11b that biases and processes input signal INb to generate an output signal OUTb by BIAS signal BIAS". Further, the IC In includes a power supply sensing circuit 12n generating a sensing signal SENSE '", a BIAS control circuit 13n generating a BIAS signal BIAS'" adjusted by the sensing signal SENSE '", and a signal processing circuit 11n biasing and processing the input signal INn by the BIAS signal BIAS'" to generate an output signal OUTn.

In certain embodiments, the

signal processing circuits

11a,11b, & 11n correspond to signal processing channels that operate in combination with one another to produce a combined signal. In one example, the

signal processing circuits

11a,11b,..1 ln corresponds to an RF signal channel of a beamformed communication system, also referred to herein as a phased array antenna system. In applications where the signal processing channel operates in combination with another channel, variations in the performance of a given channel can reduce the accuracy of the overall system. For example, in a beamforming context, when power supply variation decreases performance of each channel, a scan angle of beamforming may decrease.

To compensate for power supply variations, each IC la, lb. Thus, even when the voltage levels of VSUP ", and VSUP'" are different from each other, the internal IC bias adjustment may result In the performance of IC la, lb.

Fig. 2A is a schematic diagram of an IC 30 with supply voltage variation compensation according to another embodiment. IC 30 includes at least one pin 21 for receiving a supply voltage VSUP. In addition, the IC 30 includes a power supply sensing circuit 12, a DC operating point adjustment circuit 23, and a signal processing circuit 24 including at least one amplifier 25.

As shown in fig. 2A, the power supply sensing circuit 12 receives a local power supply voltage VSUP and generates a SENSE signal SENSE that varies in relation to the power supply voltage level. Further, the DC operating point adjusting circuit 23 generates the BIAS signal BIAS based on the SENSE signal SENSE. In particular, the DC operating point adjustment circuit 23 generates a BIAS signal BIAS to BIAS the DC operating point of the amplifier 25 such that the gain of the amplifier 25 is substantially constant in the variation of the supply voltage VSUP.

Fig. 2B is a graph of supply current ISUP versus one example of supply voltage VSUP for one embodiment of IC 30 of fig. 2A.

In certain embodiments herein, an IC implemented with supply voltage variation compensation exhibits a decrease in supply current ISUP as supply voltage VSUP increases. Thus, the IC may exhibit the profile of fig. 2B, rather than having a flat profile of supply current versus supply voltage or a supply current profile that increases with supply voltage.

Although examples in which the curve of the supply current ISUP and the supply voltage VSUP is substantially linear, other curves are possible.

Fig. 3 is a schematic diagram of a power insensitive amplifier 60 according to one embodiment. The power insensitive amplifier 60 includes a power sense circuit 12, a controllable bias current source 41, a first biased p-type field effect transistor (PFET) 43, a second biased PFET 44, a first biased n-type field effect transistor (NFET) 51, a second biased NFET 53, an amplifier common source NFET 52, an amplifier cascode NFET 54, a bias resistor 57, and a choke inductor 58. The supply insensitive amplifier 60 is powered by the supply voltage VSUP and is used to amplify the input signal received at the input IN to produce an output signal at the output OUT.

Although one embodiment of a circuit to compensate for supply voltage variations is shown, the teachings herein are applicable to a wide variety of signal processing circuits.

In the illustrated embodiment, the controllable bias current source 41 includes a first terminal electrically connected to ground voltage and a second terminal electrically connected to the gate and drain of the first bias PFET 43 and the gate of the second bias PFET 44. Further, the first bias PFET 43 and the second bias PFET 44 each include a source electrically connected to the supply voltage VSUP. Second bias PFET 44 also includes a drain electrically connected to the drain of second bias NFET 53, the gate of first bias NFET 51, and the first end of bias resistor 57. First bias NFET 53 also includes a source electrically connected to ground voltage and a drain electrically connected to the source of second bias NFET 52. The cascode bias voltage VCAS is used to bias the gate of the second bias NFET 53 and the gate of the amplifier cascode NFET 54. Any suitable bias circuit may be used to generate the cascode bias voltage VCAS.

With continued reference to fig. 3, input terminal IN is connected to a second end of bias resistor 57 and to the gate of amplifier common source NFET 52. The amplifier common source NFET 52 includes a source electrically connected to ground voltage and a drain electrically connected to the source of the amplifier cascode NFET 54. The amplifier cascode NFET 54 also includes a drain electrically connected to the output terminal OUT. The choke inductor 58 includes a first end electrically connected to the supply voltage VSUP and a second end electrically connected to the output terminal OUT.

As shown in fig. 3, the power supply sensing circuit 12 adjusts the amount of bias current IBIAS from the controllable bias current source 41 based on the sensed voltage difference between the power supply voltage VSUP and the ground voltage. In addition, first bias PFET 43 and second bias PFET 44 act as current mirrors that mirror the adjusted bias current IBIAS to produce a mirrored current that flows through the series combination of second bias NFET 53 and first bias NFET 51 to produce bias voltage VBIAS. In addition, bias voltage VBIAS is provided to the gate of amplifier common source NFET 52 through bias resistor 57.

In the illustrated embodiment, the amplifier is implemented using a cascode amplifier topology, wherein an amplifier cascode NFET 54 is included between the drain of the amplifier common source NFET 52 and a choke inductor 58. In this example, one cascode device is included, but additional cascode devices may be included, or the cascode devices may be omitted. Furthermore, although FET implementations are depicted, implementations using bipolar transistors or using a combination of FETs and bipolar transistors are also possible.

Although the use of a cascode topology mitigates the effect of supply variations on gain, a cascode amplifier may still have gain that varies with supply voltage level if not compensated.

By adjusting the bias current IBIAS to account for variations in the supply voltage VSUP, the amplifier 60 operates in a manner that is insensitive to supply voltage variations.

Fig. 4A is a schematic diagram of a power insensitive amplifier 70 according to another embodiment. The power insensitive amplifier 70 includes a first bias PFET 43, a second bias PFET 44, a first bias NFET 51, a second bias NFET 53, an amplifier common source NFET 52, an amplifier cascode NFET 54, a bias resistor 57, and a choke inductor 58, which may be as described above with respect to fig. 3. The power insensitive amplifier 70 also includes a first sense NFET63, a second sense NFET64, a third bias NFET 65, a fourth bias NFET 66, and a bias current source 67.

In the illustrated embodiment, first sense NFET63 includes a source electrically connected to a ground voltage, a drain electrically connected to a supply voltage VSUP, and a gate electrically connected to supply voltage VSUP and to the gate of second sense NFET 64. Bias current source 67 includes a first terminal electrically connected to supply voltage VSUP and a second terminal electrically connected to the drain of second sense NFET64, the gate of fourth bias NFET 66, and the gate and drain of third bias NFET 65. The second sense NFET64, the third bias NFET 65 and the fourth bias NFET 66 each include a source connected to a ground voltage.

First sense NFET63 and second sense NFET64 are used to generate a sense current ISENSE that varies with respect to supply voltage VSUP. The sense current ISENSE is subtracted from the bias current IBIAS of the bias current source 67 to generate the amplifier current IAMP. The amplifier current IAMP is mirrored by the third bias NFET 65 and the fourth bias NFET 66 and is then processed by the depicted bias circuit to produce the amplifier bias voltage VBIAS.

Fig. 4B is a schematic diagram of a power insensitive amplifier 80 according to another embodiment. The power insensitive amplifier 80 of fig. 4B is similar to the power insensitive amplifier 70 of fig. 4A, except that the power insensitive amplifier 80 further includes a resistor calibration circuit 61 and a calibrated sense resistor 62.

As shown in fig. 4B, the calibrated sense resistor 62 includes a first terminal electrically connected to the supply voltage VSUP and a second terminal electrically connected to the gate of the second sense NFET64 and the gate and drain of the first sense NFET 63. The calibrated sense resistor 62 is calibrated by the resistor calibration circuit 61 to operate at a fixed resistance RSENSE.

By including a calibrated sense resistor 62, enhanced control of the sense current IRSENSE subtracted from the bias current IBIAS is achieved. Thus, an improvement in the accuracy of compensation for the power supply voltage variation is achieved.

Fig. 4C is a schematic diagram of a power insensitive amplifier 90 according to another embodiment. In contrast to the power insensitive amplifier 60 of FIG. 4A, the power insensitive amplifier 90 of FIG. 4C omits the first and second sense NFETs 63 and 64 of FIG. 4A and includes a first voltage dividing resistor 81, a second voltage dividing resistor 82, a differential amplifier 83, a regulation NFET 84, a resistor calibration circuit 61, and a calibrated sense resistor 62.

As shown in fig. 4C, the first voltage dividing resistor 81 includes a first terminal electrically connected to the power supply voltage VSUP and a second terminal electrically connected to the first input of the differential amplifier 83 and the first terminal of the second voltage dividing resistor 82. In addition, differential amplifier 83 includes an output electrically connected to the gate of regulation NFET 84 and a second input electrically connected to the source of regulation NFET 84 and the first end of calibrated sense resistor 84. The calibrated sense resistor 62 and the second voltage divider resistor 82 each also include a second terminal electrically connected to ground voltage. The calibrated sense resistor 62 is calibrated by the resistor calibration circuit 61 to operate at a fixed resistance RSENSE.

In the illustrated embodiment, the drain of regulated NFET 84 draws a sense current IV2ISENSE, which is subtracted from bias current IBIAS to produce amplifier current IAMP. The depicted sensing circuit operates as a voltage-to-current (V2I) loop that converts a sensed supply voltage level (as detected by a resistive divider) to a corresponding sense current IV2ISENSE.

Fig. 4D is a schematic diagram of a power insensitive amplifier 100 according to another embodiment. In contrast to the power insensitive amplifier 90 of fig. 4C, the power insensitive amplifier 100 of fig. 4D also includes PVT calibration circuitry 91 for providing calibration to account for process, voltage and/or temperature variations, thereby providing another layer of enhancement of the ability to account for supply voltage variations in the amplifier.

In this example, the PVT calibration circuit 91 adjusts at least one of the resistance of the first voltage dividing resistor 81', the resistance of the second voltage dividing resistor 82', or the current of the bias current source 67 '. However, other components may be adjusted to provide such PVT compensation. In some configurations, PVT compensation is tailored for a particular IC and may be based on storing data in a non-volatile memory, such as flash memory, magnetic memory, or fuses.

Fig. 5A is an example plot of gain versus frequency for three different supply voltage levels. These figures correspond to examples of power sensitive amplifiers that do not use supply voltage compensation. In the graph of fig. 5A, gain versus frequency plots are provided for supply voltage levels of 1.15V, 1.25V, and 1.35V.

As shown in fig. 5A, the gain may vary significantly (as shown by the vertical offset from one plot to another) due to variations in the supply voltage.

Fig. 5B is a graph of another example of gain versus frequency curves for three different supply voltage levels. These figures correspond to one embodiment of the power sensitive amplifier 80 of fig. 4B.

As shown in a comparison of fig. 5A and 5B, providing supply voltage compensation may reduce variations in amplifier gain.

Although one example of a simulation result is described, other simulation results are possible. For example, simulation results may vary depending on circuit topology, simulation model, simulation parameters, and/or simulation tools. Thus, other results are also possible.

Fig. 6 is a schematic diagram of a multi-chip beamforming system 160 according to one embodiment. The multi-chip beamforming system 160 includes a circuit board 150, a voltage regulator 151, a beamforming IC array 152, and a power supply conductor 153.

In the illustrated embodiment, the array of beam forming ICs 152 includes a total of 25 ICs (indexed with indices 1 through 25) attached to the circuit board 152. However, other implementations are possible, such as an array of ICs including more or fewer ICs. In some embodiments, each IC 152 controls RF signals transmitted to and/or received from one or more corresponding antennas of the antenna array.

The voltage regulator 151 outputs a supply voltage VSUP to the supply conductor 153. The voltage regulator 151 may be implemented in a variety of ways, for example using a switched mode power supply or a DC-DC converter. Although shown separate from the circuit board 150, the voltage regulator 151 may alternatively be attached to the circuit board 150.

When a common voltage regulator is used to power a large number of ICs, a large DC current (IDC) may flow from the voltage regulator 151. Since supply conductor 153 has a finite resistivity (in this example, a segment of resistance R), the flow of current can cause i×r of ICs in array 152 to drop and the local supply voltage level to change, as shown in fig. 6. For example, without compensation, the upper left-most IC of array 152 (with index 1) may have the highest supply voltage level and highest gain, while the lower right-most IC of array 152 (with index 25) may have the lowest supply voltage level and lowest gain.

By implementing an array of ICs 152 in accordance with the teachings herein, the gain of the ICs in the array 152 remains substantially constant and variations in supply voltage caused by the i×r drop are compensated for.

Fig. 7 is a schematic diagram of a phased array antenna system 220 according to one embodiment. Phased array antenna system 220 includes voltage regulator 200, digital processing circuit 201, data conversion circuit 202, channel processing circuit 203, RF

front end ICs

205a,205b,..205 n, and antennas 206a,206b,..206 n. Although an example having three RF front-end ICs and three antennas is shown, phased array antenna system 220 may include more or fewer RF front-end ICs and/or more or fewer antennas, as shown by the ellipses. Furthermore, in some implementations, phased array antenna system 220 is implemented with separate antennas for transmitting and receiving signals.

Phased array antenna system 220 illustrates one embodiment of an electronic system that may include one or more ICs implemented according to the teachings herein. However, the circuits herein may be used in a wide variety of electronic devices. Phased array antenna systems are also referred to herein as active scanning electron steering arrays.

As shown in fig. 7, the channel processing circuit 203 is coupled to the antennas 206a,206b through the RF

front end ICs

205a,205 b. In the present embodiment, the channel processing circuit 203 includes a separation/combination circuit 207, a frequency up/down conversion circuit 208, and a phase and amplitude control circuit 209. The channel processing circuit 203 provides RF signal processing of RF signals transmitted by and received from each communication channel. In the illustrated embodiment, each communication channel is associated with a corresponding RF front-end IC and antenna.

With continued reference to fig. 7, digital processing circuit 201 generates digital transmit data for controlling the transmit beams transmitted from antennas 206a,206 b. The digital processing circuit 201 also processes digital receive data representing the receive beam. In some implementations, the digital processing circuit 201 includes one or more baseband processors.

As shown in fig. 7, digital processing circuit 201 is coupled to data conversion circuit 202, which includes digital-to-analog converter (DAC) circuitry for converting digital transmit data to one or more baseband transmit signals and analog-to-digital converter (ADC) circuitry for converting one or more baseband receive signals to digital receive data.

In the present embodiment, the frequency up/down conversion circuit 208 provides frequency up-shifting from baseband to RF and frequency down-shifting from RF to baseband. However, other implementations are possible, such as a configuration in which phased array antenna system 220 operates, in part, at an Intermediate Frequency (IF). In some implementations, the separation/combination circuit 207 provides separation of the transmit signals of one or more frequency upshifts to generate RF signals suitable for processing by the RF front-

end ICs

205a,205b, 205n and subsequent transmission on the antennas 206a,206b, 206n. Further, the separation/combination circuit 207 combines RF signals received via the antennas 206a,206b,..206 n and the RF front-

end ICs

205a,205b,..205 n to generate one or more baseband received signals for the data conversion circuit 202.

The channel processing circuitry 203 further includes phase and amplitude control circuitry 209 for controlling the beamforming operation. For example, the phase and amplitude control circuit 209 controls the amplitude and phase of RF signals transmitted or received via antennas 206a,206b, 206n to provide beamforming. Regarding signal transmission, slave antennas 206a,206b, 206n aggregate by constructive and destructive interference to collectively produce a transmit beam having a particular direction. With respect to signal reception, after amplitude scaling and phase shifting, channel processing circuitry 203 generates a receive beam by combining the RF signals received from antennas 206a,206 b.

Phased array antenna systems are used in a variety of applications including, but not limited to, mobile communications, military and defense systems, and/or radar technology.

As shown in fig. 7, the RF front ends 205a,205b, 205n each include one or more

controllable gain amplifiers

211a,211b, 211n for scaling the amplitude of the RF signals transmitted or received by the antennas 206a,206b, 206n. Further, the RF front-

end ICs

205a,205b, 205n each include one or more

controllable phase shifters

212a,212b, 212n for phase shifting the RF signals. For example, in some embodiments, the phase and amplitude control circuit 209 generates a gain control signal for controlling the amount of gain provided by the

controllable amplifiers

211a,211b, 211n, and a phase control signal for controlling the amount of phase shift provided by the

phase shifters

212a,212b, 212 n.

The phased array antenna system 220 operates to produce a transmit beam or a receive beam that includes a main lobe pointing in the desired communication direction. Phased array antenna system 220 achieves an increased signal-to-noise ratio (SNR) in the main lobe direction. The transmit or receive beam also includes one or more side lobes that point in a different direction than the main lobe and are undesirable.

The accuracy of the beam direction of phased array antenna system 220 is based on the accuracy of controlling the phase of RF signals communicated via antennas 206a,206 b. For example, when one or more RF signals have a large phase error, the beam may be interrupted and/or directed in the wrong direction. In addition, the magnitude or amplitude of the beam sidelobe levels is based on the accuracy of the amplitude of the control RF signal.

Thus, it is desirable to tightly control the phase and amplitude of the RF signals communicated by antennas 206a,206 b.

As shown in fig. 7, voltage regulator 200 provides a supply voltage to front-

end ICs

205a,205 b. By implementing front-

end ICs

205a,205b, 205n, the beamforming operation of phased array antenna system 220 is enhanced by providing insensitivity to power supply variations in accordance with the teachings herein.

Application of

The device adopting the above scheme can be implemented as various electronic devices. Examples of electronic devices include, but are not limited to, RF communication systems, consumer electronics, electronic test devices, communication infrastructure, and the like. For example, the circuitry herein may be included in a wide range of RF communication systems including, but not limited to, radar systems, base stations, mobile devices (e.g., phased array antenna systems, notebook computers, tablet computers, and/or wearable electronics.

The teachings herein are applicable to RF communication systems operating over a wide range of frequencies, including not only RF signals between 100MHz and 7GHz, but also to higher frequencies, such as the X-band (about 7GHz to 12 GHz), the Ku-band (about 12GHz to 18 GHz), the K-band (about 18GHz to 27 GHz), the Ka-band (about 27GHz to 40 GHz), the V-band (about 40GHz to 75 GHz), and/or the W-band (about 75GHz to 110 GHz). Accordingly, the teachings herein are applicable to a variety of RF communication systems, including microwave communication systems.

The signals amplified by the signal processing circuitry herein may be associated with a variety of communication standards including, but not limited to, global system for mobile communications (GSM), enhanced data rates for GSM evolution (EDGE), code Division Multiple Access (CDMA), wideband CDMA (W-CDMA), 3G, long Term Evolution (LTE), 4G, and/or 5G, as well as other proprietary and non-proprietary communication standards.

Conclusion(s)

The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Also, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element or feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuitry is not adversely affected).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may use different components and/or circuit topologies to perform similar functions, and some elements may be deleted, moved, added, subdivided, combined, and/or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the invention is to be limited only by reference to the following claims.

Claims

1. An electronic system, comprising:

a supply conductor configured to route a supply voltage having a nominal voltage level; and

a plurality of semiconductor die, each semiconductor die configured to receive the supply voltage from the supply conductor, wherein each of the plurality of semiconductor die comprises:

a power supply sensing circuit configured to generate a sensing signal based on a local voltage level of the power supply voltage;

a bias control circuit configured to adjust a bias signal based on the sense signal to account for a difference between the nominal voltage level and a local voltage level of the supply voltage; and

and a signal processing circuit biased by the bias signal.

2. The electronic system of claim 1, wherein the signal processing circuit comprises an amplifier having a DC operating point set by the bias signal.

3. The electronic system of claim 2, wherein the bias control circuit is configured to adjust the bias signal to maintain a gain of the amplifier substantially constant.

4. The electronic system of any preceding claim, wherein the bias control circuit comprises a bias current source configured to output a bias current, wherein the power supply sensing circuit is configured to generate a sense current operable to regulate the bias current.

5. An electronic system according to any preceding claim, wherein the outputs of each signal processing circuit are combined to produce a combined signal.

6. The electronic system of claim 5, wherein the combined signal is a signal beam and the electronic system is a beam forming system.

7. The electronic system of any of the preceding claims, further comprising a voltage regulator configured to generate the supply voltage.

8. The electronic system of any preceding claim, wherein the power supply sensing circuit comprises a voltage-to-current loop configured to convert a detected voltage difference between the local voltage level and a ground voltage to a sensing current and adjust the bias signal based on the sensing current.

9. A method of compensating for supply voltage variations in an electronic system, the method comprising:

providing a supply voltage to the plurality of semiconductor die using a supply conductor, the supply voltage having a nominal voltage level;

sensing a local voltage level of a supply voltage of each of the plurality of semiconductor die;

adjusting a bias signal on each of the plurality of semiconductor die to account for a difference between the nominal voltage level and a local voltage level of the supply voltage; and

the bias signal is used to bias signal processing circuitry on each of the plurality of semiconductor die.

10. The method of claim 9, wherein biasing the signal processing circuit comprises setting a DC operating point of an amplifier using the bias signal.

11. The method of claim 10, further comprising adjusting the bias signal to maintain a gain of the amplifier substantially constant.

12. The method of any of claims 9 to 11, wherein adjusting the bias signal comprises generating a sense current based on a voltage difference between a local voltage level of the supply voltage and a ground voltage, and adjusting a bias current of the amplifier using the sense current.

13. The method of any of claims 9 to 12, further comprising combining output signals from the signal processing circuits of each of the plurality of semiconductor die to generate a combined signal.

14. The method of claim 13, wherein the combined signal is a signal beam.

15. The method of any of claims 9 to 14, further comprising generating the supply voltage using a voltage regulator.

16. A semiconductor die for a multi-chip signal processing system, the semiconductor die comprising:

a power pin configured to receive a power supply voltage;

a power supply sensing circuit configured to generate a sensing signal based on a local voltage level of a power supply voltage at the power supply pin;

a bias control circuit configured to adjust a bias signal based on the sense signal to account for a difference between a nominal voltage level of the supply voltage and a local voltage level of the supply voltage; and

and a signal processing circuit biased by the bias signal.

17. The semiconductor chip of claim 16, wherein the signal processing circuit comprises an amplifier having a DC operating point set by the bias signal.

18. The semiconductor chip of claim 17, wherein the bias control circuit is configured to adjust the bias signal to keep a gain of the amplifier substantially constant.

19. The semiconductor chip of any one of claims 16 to 18, wherein the bias control circuit comprises a bias current source configured to output a bias current, wherein the power supply sensing circuit is configured to generate a sense current operable to regulate the bias current.

20. The semiconductor chip of any one of claims 16 to 19, wherein the power supply sensing circuit comprises a voltage-to-current loop configured to convert a detected voltage difference between the local voltage level and a ground voltage to a sensing current and adjust the bias signal based on the sensing current.