CN116368607A

CN116368607A - Hybrid fabrication for integrated circuit devices and components

Info

Publication number: CN116368607A
Application number: CN202180075331.XA
Authority: CN
Inventors: W·戈梅斯; A·A·夏尔马; M·J·科布林斯基; D·B·因格利
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2020-12-08
Filing date: 2021-09-24
Publication date: 2023-06-30
Also published as: TW202240844A; WO2022125166A1

Abstract

Microelectronic assemblies fabricated using hybrid fabrication and related devices and methods are disclosed herein. As used herein, "hybrid fabrication" refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers using different materials or different fabrication techniques. For example, a microelectronic assembly can include: a first IC structure comprising a first interconnect and a second IC structure comprising a second interconnect, wherein at least some of the first and second interconnects may comprise a liner and a conductive filler material, and wherein a material composition of the liner/conductive filler material of the first interconnect may be different from a material composition of the liner/conductive filler material of the second interconnect.

Description

Hybrid fabrication for integrated circuit devices and components

Cross Reference to Related Applications

The present application claims the benefits and priorities of U.S. non-provisional patent application Ser. No.17/114,537 entitled "HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES (hybrid manufacturing for Integrated Circuit devices and components)", U.S. non-provisional patent application Ser. No.17/114,537 and U.S. non-provisional patent application Ser. No. HYBRID MANUFACTURING FOR INTEGRATED CIRCUIT DEVICES AND ASSEMBLIES (hybrid manufacturing for Integrated Circuit devices and components) ", U.S. non-provisional patent application Ser. No.17/114,700, filed on 8 of 2020, and hereby incorporated by reference in their entirety.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and more particularly, to microelectronic assemblies fabricated using hybrid fabrication and related devices and methods.

Background

Scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry for the last few decades. Scaling to smaller and smaller features enables increased densities of functional units over a limited footprint of the semiconductor chip. For example, shrinking transistor size allows for a greater number of memory or logic devices to be incorporated on a chip, resulting in greater capacity for product manufacturing. However, the push to ever increasing capacity is not without problems. The necessity of optimizing the performance of each Integrated Circuit (IC) die and each IC package including one or more dies is becoming increasingly important.

Drawings

The embodiments can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. The embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

1A-1D illustrate cross-sectional side views of a microelectronic assembly having first and second IC structures bonded using front-to-front (f 2 f) bonding, in accordance with some embodiments.

Fig. 2A-2C illustrate cross-sectional side views of a microelectronic assembly having first and second IC structures bonded using front-to-back (f 2 b) bonding, in accordance with some embodiments.

Fig. 3A-3K illustrate cross-sectional side views of a microelectronic assembly having first and second IC structures bonded using back-to-back (b 2 b) bonding, in accordance with some embodiments.

Figure 4 illustrates a cross-sectional side view of a microelectronic assembly having different etch stop materials in first and second IC structures, in accordance with some embodiments.

Fig. 5A-5D illustrate cross-sectional side views of a microelectronic assembly, which is an f2f bond assembly having a post-bond via formed from the top, in accordance with some embodiments.

Fig. 6A-6D illustrate cross-sectional side views of a microelectronic assembly, which is an f2b bonding assembly having a post-bonding via formed from the top, in accordance with some embodiments.

Figures 7A-7E illustrate cross-sectional side views of a microelectronic assembly, which is a b2b bonding assembly having post-bonding vias formed from the top, according to some embodiments.

Figures 8A-8D illustrate cross-sectional side views of a microelectronic assembly that is an f2f bonding assembly having post-bonding vias formed from the bottom, according to some embodiments.

Fig. 9A-9D illustrate cross-sectional side views of a microelectronic assembly, which is an f2b bonding assembly having post-bonding vias formed from the bottom, in accordance with some embodiments.

10A-10E illustrate cross-sectional side views of a microelectronic assembly, which is a b2b bonding assembly having post-bonding vias formed from the bottom, according to some embodiments.

11A-11C illustrate cross-sectional side views of microelectronic assemblies having post-bond vias extending through pairs of bonded IC structures, in accordance with some embodiments.

Fig. 12A-12H illustrate an IC package that may include one or more microelectronic assemblies fabricated using hybrid fabrication, in accordance with some embodiments.

Fig. 13A and 13B are top views of a wafer and die, respectively, that may include one or more microelectronic assemblies fabricated using hybrid fabrication, in accordance with various embodiments.

Fig. 14 is a cross-sectional side view of an IC device that may be included in a microelectronic assembly fabricated using hybrid fabrication, according to any of the embodiments disclosed herein.

Fig. 15 is a cross-sectional side view of an IC device assembly that may include one or more microelectronic assemblies fabricated using hybrid fabrication, in accordance with various embodiments.

Fig. 16 is a block diagram of an exemplary computing device that may include one or more microelectronic assemblies fabricated using hybrid manufacturing, or an IC device or package having such microelectronic assemblies, in accordance with various embodiments.

Detailed Description

SUMMARY

The systems, methods, and apparatus of the present disclosure each have several inventive aspects, no single one of which is solely responsible for the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

To illustrate hybrid fabrication for IC devices and components as described herein, it may be useful to first understand that phenomena that may occur during IC fabrication. The following basic information can be regarded as the basis on which the present disclosure can be properly interpreted. Such information is provided for illustrative purposes only and, accordingly, should not be construed in any way as limiting the broad scope of the present disclosure and its potential applications.

Conventionally, an IC die is coupled to a package substrate to achieve mechanical stability and facilitate connection with other components (e.g., a circuit board). The performance that such conventional IC packages can achieve is constrained by die performance, manufacturing, material and thermal considerations, and the like. Furthermore, transferring a large number of signals between two or more dies in a multi-die IC package is challenging due to the increasingly smaller size of such dies, thermal and power delivery constraints, and other constraints.

Microelectronic assemblies fabricated using hybrid fabrication and related devices and methods are disclosed herein. As used herein, "hybrid fabrication" refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers using different materials or different fabrication techniques. For example, in some embodiments, a microelectronic assembly can include: a first IC structure comprising a first interconnect and a second IC structure comprising a second interconnect, wherein at least some of the first and second interconnects may comprise a liner layer and a conductive filler material, and wherein a material composition of the liner/conductive filler material of the first interconnect may be different from a material composition of the liner/conductive filler material of the second interconnect. In another example, in some embodiments, an IC package can include a package substrate having a first side and an opposing second side, and further include a microelectronic assembly coupled to the package substrate through a package interconnect. Such an IC packaged microelectronic assembly can include a first IC structure having a first face and an opposing second face, wherein the first face of the first IC structure is at least partially between the second face of the package substrate and the second face of the first IC structure, and the first face of the first IC structure is coupled to the second face of the package substrate through a package interconnect. The microelectronic assembly can also include a second IC structure having a first face and an opposing second face, wherein the first face of the second IC structure is at least partially between the second face of the first IC structure and the second face of the second IC structure. The microelectronic assembly can also include a bonding material bonding the second face of the first IC structure to the first face of the second IC structure, and a conductive via having at least a portion in the first IC structure and at least a portion in the second IC structure and extending through the bonding material.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without these specific details, or/and with the aid of only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Furthermore, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration embodiments which may be practiced. It is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense. For convenience, if there are sets of drawings designated with different letters, e.g., fig. 1A-1D, such sets may be referred to herein without letters, e.g., as "fig. 1".

In the drawings, some schematic views of exemplary structures of the various devices and components described herein may be shown with precise right angles and straight lines for ease of illustration only, and embodiments of the components may be curved, rounded or otherwise irregularly shaped, as determined by and sometimes unavoidable due to the manufacturing process used to manufacture the semiconductor device components. Thus, it is to be understood that such schematic diagrams may not reflect realistic process limitations that may result in features that appear less "ideal" when any of the structures described herein are inspected, for example, using Scanning Electron Microscope (SEM) images or Transmission Electron Microscope (TEM) images. In such images of real structures, possible processing defects may also be visible, such as straight edges of imperfect material, inclined vias or other openings, accidental rounding of corners or thickness variations of different material layers, occasional threading, edge or combination dislocations within the crystal region, and/or occasional dislocation defects of individual atoms or clusters of atoms. There may be other drawbacks not listed here but common to the field of device fabrication. Furthermore, while a certain number of given elements may be illustrated in some of the figures (e.g., a certain number and type of interconnects in the first and second IC structures of the microelectronic assembly illustrated in some of the figures, a certain number of dies in the IC package illustrated in other figures, etc.), this is for ease of illustration only, and more or less of the number of given elements may be included in the microelectronic assembly and related devices in accordance with various embodiments of the present disclosure. Furthermore, the various views shown in some of the drawings are intended to show the relative arrangement of the various elements therein. In other embodiments, the various microelectronic assemblies or portions thereof fabricated using hybrid fabrication may include other elements or components not shown (e.g., transistor portions, various components that may be in electrical contact with any of the illustrated components of the microelectronic assemblies fabricated using hybrid fabrication, etc.). For example, inspection of layout and mask data using optical microscopy, TEM or SEM and reverse engineering of portions of the device for the purpose of reconstructing the circuit, and/or inspection of device cross-sections using, for example, physical Failure Analysis (PFA) for the purpose of detecting the shape and position of various device elements described herein, would allow for the determination of the presence of one or more microelectronic assemblies fabricated using hybrid fabrication as described herein.

Various operations may be described as multiple discrete acts or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. The order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may be performed out of the order of presentation. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed, and/or the described operations may be omitted.

For the purposes of this disclosure, the phrase "a and/or B" refers to (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). The term "between" when used with reference to a measurement range includes the ends of the measurement range. Although certain elements may be referred to herein in the singular, such elements may comprise a plurality of sub-elements. For example, a "conductive material" may include one or more conductive materials.

The description uses the phrase "in an embodiment," which may refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The present disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side" to explain various features of the drawings, but these terms are merely for ease of discussion and do not imply desired or required orientations. The figures are not necessarily drawn to scale. Unless otherwise indicated, the use of the ordinal adjectives "first," "second," "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

For example, the term "interconnect" may be used to describe any element formed of a conductive material to provide electrical connection to one or more components associated with an IC or/and to provide electrical connection between various such components. In general, "interconnect" may refer to both an electrical trace (sometimes referred to as a "wire" or "trench contact") and an electrical via. In general, in the context of interconnects, the term "conductive trace" may be used to describe a conductive element that is isolated by an insulator material (e.g., a low-k dielectric material) provided in the plane of the IC die. Such traces are typically stacked into several levels or layers of a metallization stack. On the other hand, the term "via" may be used to describe a conductive element that interconnects two or more traces of different levels. To this end, the vias may be provided substantially perpendicular to the plane of the IC die and may interconnect two traces in adjacent levels or two traces in non-adjacent levels. The term "metallization stack" may be used to denote a stack of one or more interconnects for providing connections to different circuit components of an IC chip. Sometimes, the traces and vias may be referred to as "conductive traces" and "conductive vias," respectively, thereby emphasizing the fact that these elements comprise conductive materials (e.g., metals).

The interconnects described herein, and in particular, the interconnects of the IC structures of microelectronic assemblies fabricated using hybrid fabrication described herein, may be used to provide electrical connections to one or more components associated with an IC or/and between various such components, wherein, in various embodiments, components associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. The components associated with an IC may include those mounted on the IC or those connected to the IC. An IC may be analog or digital and may be used in many applications such as microprocessors, optoelectronic components, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. An IC may be employed as part of a chipset for performing one or more related functions in a computer.

In another example, the terms "package" and "IC package" are synonymous, the terms "die" and "IC die" are synonymous, the term "insulating" means "electrically insulating," the term "electrically conductive," unless otherwise indicated. Furthermore, the term "coupled" may be used to describe a direct electrical or magnetic connection between the connected objects without any intervening devices, while the term "coupled" may be used to describe a direct electrical or magnetic connection between the connected objects, or an indirect connection through one or more passive or active intervening devices. The term "circuit" may be used to describe one or more passive and/or active components arranged to cooperate to provide a desired function.

In yet another example, the terms "oxide", "carbide", "nitride", and the like refer to a compound containing oxygen, carbon, nitrogen, and the like, respectively, the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, and the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide, if used.

The terms "substantially," "near," "approximately," "near," and "approximately" are generally meant to be within +/-20% of a target value, based on the context of the particular values described herein or as known in the art. Similarly, terms indicating the orientation of elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, based on the context of particular values described herein or as known in the art, generally refer to within +/-5-20% of a target value.

Exemplary microelectronic assemblies fabricated using hybrid fabrication

In general, hybrid fabrication will be described herein with reference to a first IC structure 110 and a second IC structure 120 being bonded to each other using a bonding material 130.

IC structures

110 and 120 may be fabricated by different manufacturers using different materials or different fabrication techniques. Various examples of microelectronic assemblies including

IC structures

110 and 120 will now be described with reference to fig. 1-11.

Several elements referred to by reference numerals in the description of fig. 1-11 are shown in different patterns in these figures, and a legend is provided at the bottom of each of the drawing pages containing fig. 1-11, the figures illustrating the correspondence between the reference numerals and the patterns. For example, the figures illustrate that fig. 1-11 use different patterns to illustrate the first interconnect 112, the second interconnect 122, the bonding material 130, and the like.

Several of these elements are illustrated in fig. 1-11 as being included in various embodiments of the microelectronic assembly 100, but may not be present in other embodiments of the microelectronic assembly 100. For example, although fig. 1 and 2 illustrate the substrate 132 of the first IC structure 110, in other embodiments, the substrate 132 may not be included. Furthermore, any feature of any embodiment of a microelectronic assembly described with reference to one of fig. 1-11 may be combined with any feature of any embodiment of a microelectronic assembly described with reference to one or more of fig. 1-11, unless otherwise indicated. In some embodiments, each of the microelectronic assemblies 100 disclosed herein can function as a System In Package (SiP) including

multiple IC structures

110, 120 or pairs of such IC structures having different functions. In such an embodiment, the microelectronic assembly 100 may be referred to as a SiP.

Fig. 1A-1D illustrate cross-sectional side views of a microelectronic assembly 100 having a first IC structure 110 and a second IC structure 120 bonded using an f2f bond, in accordance with some embodiments.

Fig. 1A illustrates a cross-sectional side view of a microelectronic assembly 100, according to some embodiments of the present disclosure. Many of the elements of the microelectronic assembly 100 of fig. 1A are included in other figures; the discussion of these elements will not be repeated in discussing these figures, and any of these elements may take any of the forms disclosed herein.

As shown in fig. 1A, IC structure 110 may include one or more (typically a plurality of) interconnects 112, while IC structure 120 may include one or more (typically a plurality of) interconnects 122. In IC structure 110, interconnects 112 may be arranged in one or more (typically multiple) layers of the metallization stack, wherein each layer may comprise an insulating material 114 (e.g., a dielectric material formed as multiple layers, as is known in the art). The interconnect 112 may include one or more conductive traces and one or more conductive vias to provide one or more conductive paths through the insulating material 114. Similarly, in IC structure 120, interconnect 122 may be disposed in one or more (typically multiple) layers of the metallization stack, where each layer may include an insulating material 124 (e.g., a dielectric material formed as multiple layers, as is known in the art). Interconnect 122 may include one or more conductive traces and one or more conductive vias to provide one or more conductive paths through insulating material 124. Any of the conductive vias (e.g., conductive traces and/or conductive vias) disclosed herein may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys.

In some embodiments, at least one of insulating material 114 and insulating material 124 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric, and/or benzocyclobutene-based polymer). In some embodiments, at least one of insulating material 114 and insulating material 124 may include a semiconductor material, such as silicon, germanium, or a group III-V material (e.g., gallium nitride), and one or more additional materials. For example, at least one of insulating material 114 and insulating material 124 may include silicon oxide or silicon nitride. The conductive paths formed by the interconnects 112 may include conductive traces and/or conductive vias and may be connected to one another by any suitable means. Similarly, the conductive paths formed by interconnect 122 may include conductive traces and/or conductive vias and may be connected to each other by any suitable means. Although fig. 1-11 illustrate a particular number and arrangement of conductive vias formed by interconnect 112 and by interconnect 122, these are merely illustrative and any suitable number and arrangement may be used.

In some embodiments, any of

interconnects

112 and 122 may include conductive vias to route power, ground, and/or signals to/from various components of

IC structures

110 and 120. For example, any of the

IC structures

110 and 120 may include through-substrate vias (TSVs, including conductive material vias, such as conductive vias, that are isolated from surrounding silicon or other semiconductor material by a barrier oxide) or other conductive paths through which power, ground, and/or signals may be transferred between a package substrate (e.g., package substrate 202 shown in fig. 12) to which the microelectronic assembly 100 may be coupled and one or more dies or IC structures located at the "top" or "bottom" of the microelectronic assembly 100. For example, if the IC package is such that the IC structure 110 is on the bottom and coupled to the package substrate, and the IC package 120 is on the top, the IC structure 110 may include conductive vias to route power, ground, and/or signals between the package substrate and the IC structure 120 and/or between the package substrate and a different die or IC structure in the die or IC structure that may be "on top" of the IC structure 120. In another example, if the IC package is such that the IC structure 120 is at the bottom and coupled to the package substrate, and the IC package 110 is at the top (i.e., the microelectronic assembly 100 is turned upside down as compared to that shown in fig. 1A), the IC structure 120 may include conductive vias to route power, ground, and/or signals between the package substrate and the IC structure 110 and/or between the package substrate and a different die or IC structure in the die or IC structure that may be "on top" of the IC structure 110. In some embodiments, IC structure 110 or IC structure 120 may be a source and/or destination of signals communicated between a package substrate and another IC structure and/or other die or IC structure included in an IC package. In some embodiments, IC structure 110 may not route power and/or ground to IC structure 120; instead, the IC structure 120 may be directly coupled to power and/or ground lines in the package substrate of the IC package. By allowing the IC structure 120 to be directly coupled to power and/or ground lines in the package substrate, such power and/or ground lines need not be routed through the IC structure 110, allowing the IC structure 110 to be made smaller or include more active circuitry or signal paths.

In some embodiments, either of the

IC structures

110 and 120 may include only conductive vias formed by the

interconnects

112, 114, respectively, and may not include active or passive circuitry. In other embodiments, either of IC structure 110 and IC structure 120 may include active or passive circuitry (e.g., transistors, diodes, resistors, inductors, capacitors, etc.), which are schematically illustrated in the example of fig. 1A as device circuitry 116 that may be included in IC structure 110 and device circuitry 126 that may be included in IC structure 120. For example, if the IC package is such that IC structure 110 is located at the bottom and coupled to the package substrate, and IC structure 120 is located at the top and includes device circuitry 126, then power and/or ground signals may be routed from/through the package substrate, and to device circuitry 126 of IC structure 120 via interconnect 112 and interconnect 122. In various such embodiments, IC structure 110 may or may not include device circuitry 116. In another example, if the IC package is such that IC structure 120 is located at the bottom and coupled to the package substrate, and IC structure 110 is located at the top and includes device circuitry 116, power and/or ground signals may be routed from/through the package substrate, and to device circuitry 116 of IC structure 110 through interconnect 122 and interconnect 112. In various such embodiments, IC structure 120 may or may not include device circuitry 126. In general, in some embodiments, the microelectronic assembly 100 may include device circuitry 116, while in other embodiments the device circuitry 116 is excluded, and similarly, the microelectronic assembly 100 may include device circuitry 126 in some embodiments, while in other embodiments the device circuitry 126 is excluded.

The

device circuitry

116 and 126 may include semiconductor material systems as active materials (e.g., as channel materials for transistors), including, for example, N-type or P-type material systems.

In some embodiments, the active material of device circuitry 116 and/or 126 may comprise a substantially monocrystalline semiconductor, such as silicon or germanium.

In some embodiments, the active material of device circuitry 116 and/or 126 may include a compound semiconductor, for example, a compound semiconductor having a first sub-lattice of at least one element from group III of the periodic table (e.g., al, ga, in) and a second sub-lattice of at least one element from group V of the periodic table (e.g., P, as, sb). In some embodiments, the active material of device circuitry 116 and/or 126 may include binary, ternary, or quaternary III-V compound semiconductors that are alloys of two, three, or even four elements from groups III and V of the periodic table, including boron, aluminum, indium, gallium, nitrogen, arsenic, phosphorus, antimony, and bismuth.

In some embodiments, the active material of device circuitry 116 and/or 126 may be/include an intrinsic group IV or group III-V semiconductor that is not intentionally doped with any electroactive impurities Bulk material or alloy. In alternative embodiments, nominal impurity dopant levels may be present within the active material of device circuitry 116 and/or 126, for example, to set a threshold voltage Vt or to provide halo pocket implants, etc. However, in such impurity doped embodiments, the impurity dopant level within the active material may also be relatively low, e.g., below about 10 ¹⁵ cm ^-3 And advantageously below 10 ¹³ cm ^-3 。

For the exemplary P-type transistor embodiment, the active material of device circuitry 116 and/or 126 may advantageously be a group IV material with high hole mobility, such as, but not limited to, ge or a Ge-rich SiGe alloy. For some exemplary embodiments, such active materials may have a Ge content of between 0.6 and 0.9, and advantageously at least 0.7.

For the exemplary N-type transistor embodiment, the active material of device circuitry 116 and/or 126 may advantageously be a III-V material with high electron mobility, such as, but not limited to InGaAs, inP, inSb and InAs. For some such embodiments, the active material may be a ternary III-V alloy, such as InGaAs or GaAsSb. For some In _x Ga _1- _x For As fin embodiments, the In content In such active materials may be between 0.6 and 0.9, and advantageously at least 0.7 (e.g., in _0.7 Ga _0.3 As)。

In some embodiments, the active material of device circuitry 116 and/or 126 may be a thin film material, and in such embodiments, device 116 and/or 126 may be a Thin Film Transistor (TFT). TFTs are a special type of Field Effect Transistor (FET) fabricated by depositing a thin film of active semiconductor material and dielectric layers and metal contacts over a support structure, which may be a non-conductive (and non-semiconductive) support structure. During operation of the TFT, at least a portion of the active semiconductor material forms the channel of the TFT, and thus, thin films of such active semiconductor material are referred to herein as "TFT channel materials. This is in contrast to conventional non-TFT transistors, in which the active semiconductor channel material is typically part of a semiconductor substrate, for example, part of a silicon wafer. In various such embodiments, the active material of device circuitry 116 and/or 126 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium indium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.

In general, the active materials of device circuitry 116 and/or 126 may include one or more of the following materials: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, gallium arsenide indium, silicon germanium, gallium nitride, gallium aluminum nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, magnesium, and the like.

Although fig. 1A illustrates the

device circuitry

116 and 126 as front end of line (FEOL, or simply "front end") devices in the

IC structures

110, 120, respectively, in general the device circuitry 116 and/or 126 may include any combination of FEOL devices, back end of line (BEOL, or simply "back end") devices, TFTs, etc. Furthermore, although fig. 1A shows

interconnects

112 and 122 provided over the top surfaces of

IC structures

110 and 120, respectively, in other embodiments, IC structure 110 and/or IC structure 120 may also include backside interconnects, e.g., as described below with reference to fig. 2C.

Fig. 1A illustrates that device circuitry 116 may be provided over support structure 132 such that device circuitry 116 is interposed between support structure 132 and at least some of interconnects 112. In general, support structure 132 may comprise any material that may serve as a foundation upon which the IC structures described herein may be formed. In some embodiments, the support structure 132 may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system. In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or silicon-on-insulator substructure. In other embodiments, the semiconductor substrate may be formed using alternative materials that may or may not be bonded to silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials.

Although not shown in fig. 1A, device circuitry 126 may also be provided over support structures similar to support structure 132 such that device circuitry 126 is located between such support structures and at least some of interconnects 122. The support structure of IC structure 120 is not shown in fig. 1A, thereby illustrating that in some embodiments, after bonding IC structure 120 to IC structure 130 in f2f bonding, the support structure of IC structure 120 may no longer be needed (e.g., because support structure 132 may provide sufficient mechanical stability for microelectronic assembly 100) and may be removed, for example, using an appropriate thinning/polishing process. Such an embodiment may advantageously reduce the overall height of the microelectronic assembly 100 (i.e., the dimension measured along the vertical axis for the example shown in the present figures). In other embodiments, the IC structure 120 may be provided over the IC structure 110 using layer transfer, in which case the support structure of the IC structure 120 has been substantially removed as it is placed over the IC structure 110 for bonding.

Although not specifically shown in these figures, in some embodiments, one or both of the

IC structures

110, 120 may include or be part of one or more of the following options: a central processing unit, a memory device (e.g., a high bandwidth memory device), logic circuitry, input/output circuitry, a transceiver (e.g., a field programmable gate array transceiver), gate array logic of power delivery circuitry (e.g., a field programmable gate array logic), a III-V or III-N device (e.g., a III-V or III-N amplifier (e.g., a GaN amplifier)), peripheral component interconnect express circuitry, or double data rate transmission circuitry.

The microelectronic assembly 100 may be fabricated as described below. First, the

IC structures

110 and 120 may be fabricated separately, e.g., at different manufacturing facilities, by different companies, etc. Thereafter, the faces of the

IC structures

110 and 120 may be bonded. In some embodiments, bonding of the faces of

IC structures

110 and 120 may be performed using an insulator-insulator bond (e.g., an oxide-oxide bond), wherein insulating material 114 is bonded to insulating material 124. In some embodiments, bonding material 130 may be present between the faces of

IC structures

110 and 120 that are bonded together. To this end, the bonding material 130 may be applied to one or both sides of the

IC structures

110 and 120 that should be bonded, after which the

IC structures

110 and 120 are brought together, possibly with the application of appropriate pressure and heating of the assembly to an appropriate temperature (e.g., moderately high temperature, e.g., between about 50 and 200 degrees celsius) for a certain period of time. In some embodiments, the bonding material 130 may be an adhesive material that ensures that the

IC structures

110 and 120 attach to each other. In some embodiments, the bonding material 130 may be an etch stop material. In some embodiments, the bonding material may be both an etch stop material and have suitable adhesive properties to ensure that the

IC structures

110 and 120 are attached to one another. In some embodiments, bonding material 130 may not be used, in which case the layer labeled "130" in fig. 1A represents the bonding interface resulting from the inter-bonding of

IC structures

110 and 120. Such a bonding interface may be identified as a seam or lamina in the microelectronic assembly 100 using, for example, selective area diffraction (SED), even though the specific materials of the insulators of the

IC structures

110 and 120 bonded together may be the same, in which case the bonding interface would still be identifiable as a seam or lamina in portions that would otherwise appear as bulk insulator (e.g., bulk oxide) layers. As used herein, reference to "bonding material 130" applies to "bonding interface" for embodiments that do not use an artificially added adhesive material to

bond IC structures

110 and 120, unless otherwise indicated.

For each IC structure, the term "bottom" or "back" of the structure may refer to the back of the IC structure, e.g., the bottom of the support structure 132 of the IC structure 110, while the term "top" or "front" of the structure may refer to the opposite side. FIG. 1A shows the back side 134-1 and the front side 134-2 of each of the

IC structures

110 and 120. As can be seen in fig. 1A, the microelectronic assembly 100 is an f2f bond assembly in that the front face 134-2 of the IC structure 120 is bonded to the front face 134-2 of the IC structure 110. Thus, in the f2f bonding assembly, one of the

IC structures

110, 120 is flipped up and down for bonding such that the top surface of the flipped IC structure faces and is bonded to the top surface of the non-flipped IC structure.

Fig. 1A illustrates an embodiment of a microelectronic assembly 100 in which portions of at least some of the interconnects 112 located on the top surface of the IC structure 110 may contact portions of at least some of the interconnects 122 located on the top surface of the IC structure 120, thereby providing electrical continuity/connection between the interconnects 112 and the interconnects 122. A dashed oval outline is provided in fig. 1A to indicate two examples of such electrical connections between

interconnects

112 and 122. In some embodiments, the overlap between the conductive fill material of

interconnects

112 and 122 may be substantially 100% of the surface area (at the junction interface) of the smallest of

interconnects

112 and 122, as shown in fig. 1A for an example of an electrical connection between

interconnects

112 and 122 within the right-hand dashed oval outline. In some embodiments, the overlap between the conductive fill material of the

interconnects

112 and 122 may be substantially a portion (i.e., less than 100%) of the surface area (at the bonding interface) of the smallest one of the

interconnects

112 and 122, as shown in fig. 1A for an example of an electrical connection between the

interconnects

112 and 122 within the left-hand dashed oval outline. Thus, in some embodiments,

IC structures

110 and 120 may be joined such that an electrical connection may be formed between at least one of interconnects 112 and at least one of interconnects 122 by contacting at least a portion of conductive fill material 118 of at least one of interconnects 112 with at least a portion of conductive fill material 128 of at least one of interconnects 122.

It is noted that fig. 1A and similar subsequent figures of the microelectronic assembly 100 illustrate that when an electrical connection is made between one of the interconnects 112 and one of the interconnects 122, either the

interconnect

112 or 122 extends through the bonding material/interface 130. For example, inspection of electrical connections within the dashed oval outline in FIG. 1A reveals that interconnect 122 appears to intersect bonding material/interface 130 to contact corresponding interconnect 112. This illustrates that the conductive material of the

interconnects

112, 122 is able to penetrate the bonding material/interface 130 to form an electrical connection, as the bonding material/interface 130 may be relatively thin (e.g., on the order of a few nanometers). Although in a given figure one of the interconnects may be shown as penetrating the bonding material/interface 130 (e.g., in fig. 1a—only interconnect 122), in other embodiments the other of the interconnects (for fig. 1a—interconnect 112) may penetrate the bonding material/interface 130, or both of the interconnects of the bonded IC structure may penetrate the bonding material/interface 130 (for fig. 1a—both interconnects 112 and 122).

As a result of the hybrid bonding of

IC structures

110 and 120, microelectronic assembly 100 may exhibit several characteristic features.

One such feature is that for the f2f bond shown in fig. 1A, the cross-sectional shape of interconnect 112 may be inverted relative to the cross-sectional shape of interconnect 122, as can be seen in fig. 1A. The cross-section of fig. 1A is a cross-section in a plane that is substantially perpendicular to the bonding interface (e.g., a plane of bonding material 130 that is substantially perpendicular to a plane that also serves as the bonding interface). For some fabrication processes, the cross-sectional shape of the interconnect in this plane (e.g., the plane of fig. 1A) may be trapezoidal, i.e., the cross-section of the interconnect may have two parallel sides, one of which is a short side and the other is a long side, and the long side is closer to the top surface of the IC structure than the short side (i.e., the long side faces the front surface of the IC structure and the short side faces the back surface of the IC structure). For example, dual damascene or single damascene processes for fabricating interconnects may achieve such trapezoidal cross sections. This is illustrated in fig. 1A, and the long side of the trapezoidal cross section of interconnect 112 is closer to the front side of IC structure 110 than the short side thereof, and thus closer to the bonding interface with IC structure 120. Such a fabrication process used in fabricating IC structure 120 would similarly result in the long sides of the trapezoidal cross section of interconnect 122 being closer to the front side of IC structure 120 than the short sides thereof. Since the IC structure 120 is flipped in the f2f bond arrangement, this means that the long side of the trapezoidal cross section of the interconnect 122 is closer to the bond interface with the IC structure 110 than the short side, as shown in fig. 1A.

Another characteristic feature of the hybrid bond of

IC structures

110 and 120 may be revealed by examining the material composition of

interconnects

112 and 122. In general, each of the

interconnects

112 and 122 may include a liner and a conductive fill material. The liner, if included, may be an adhesive liner and/or a barrier liner. Fig. 1A illustrates an embodiment in which at least some of the interconnects 112 may include a conductive fill material 118 and a liner 119, while at least some of the interconnects 122 may include a conductive fill material 128 and a liner 129 (the inset within the dashed outline on the left side of fig. 1A illustrates such an example of one of the interconnects 112 and one of the interconnects 122). In some such embodiments, the material composition of

liners

119 and 129 may be different. For example, liner 119 of interconnect 112 may be a liner with one or more of tantalum, tantalum nitride, titanium nitride, and tungsten carbide, while liner 129 of interconnect 122 may be a liner with one or more of tantalum, tantalum nitride, and cobalt, or vice versa. Any of the materials (e.g., any of the examples listed above) may be included in

liners

119 and 129 in an amount between about 1% and 75%, for example, between about 5% and 50%, indicating that the materials are included by intentional alloying of the materials, in contrast to the case that may include accidental doping or impurities for which any of the metals may be less than about 0.1%. Thus, any difference in the material composition of

liners

119 and 129 that exceeds about 0.1% of the intended doping and/or impurity level of a given material may be indicative of the hybrid bond used to provide microelectronic assembly 100. Similarly, in some embodiments, the material composition of

conductive fill materials

118 and 128 may be different. For example, the conductive fill material 118 of the interconnect 112 may include copper (Cu), while the conductive fill material 128 of the interconnect 122 may include tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), or AlCu (e.g., in a ratio between 1:1 and 1:100), or vice versa. Any of the materials (e.g., any of the examples listed above) may be included in the

conductive fill materials

118 and 128 in an amount between about 1% and 75%, for example, between about 5% and 50%, indicating that the materials are included by intentional alloying of the materials, in contrast to the inclusion of potentially unexpected doping or impurities for which any of the metals may be less than about 0.1%. Thus, any difference in material composition of the

conductive fill materials

118 and 128 that exceeds about 0.1% of the unintentional doping/impurity level of a given material may be indicative of a hybrid bond for providing the microelectronic assembly 100.

In some embodiments, the liners 119 and/or 129 may be eliminated, and the

interconnects

112, 122 may include only the

conductive materials

118, 128. While fig. 1A shows an embodiment of the microelectronic assembly 100 in which both the liner 119 and the liner 129 are present in some or all of the

interconnects

112, 122, respectively, fig. 1B shows an embodiment of the microelectronic assembly 100 without the liner 119 but with the liner 129 present (as shown in the inset within the dashed outline on the left side of fig. 1B), fig. 1C shows an embodiment of the microelectronic assembly 100 without the liner 129 but with the liner 119 present (as shown in the inset within the dashed outline on the left side of fig. 1C), and fig. 1D shows an embodiment of the microelectronic assembly 100 without both the liner 119 and the liner 129 (as shown in the inset within the dashed outline on the left side of fig. 1D). The remainder of the description provided with respect to fig. 1A for microelectronic assembly 100 applies to fig. 1B-1D.

Yet another characteristic feature of the hybrid bond of

IC structures

110 and 120 may be revealed by examining the geometry of the cross-sections of

interconnects

112 and 122. For example, in some embodiments, the thickness of the liner 119 may be different from the thickness of the liner 129, e.g., at least about 5% different, at least about 10% different, or at least about 5-50% different. For example, liner 119 may have a thickness between about 1 nanometer and 6 nanometers (including all values and ranges therein), while liner 129 may have a thickness between about 4 nanometers and 10 nanometers (including all values and ranges therein), or vice versa.

In some embodiments, there may be other differences in the cross-sectional geometries of

interconnects

112 and 122. For example, in some embodiments, the heights of the trapezoids of the conductive traces of

interconnects

112 and 122 may be different, e.g., at least about 5% different, at least about 10% different, or at least 5-50% different, when comparing the conductive traces of

interconnects

112 and 122. In some embodiments, the corners of the trapezoidal cross sections of

interconnects

112 and 122 may be different (e.g., the angle between the long side and one of the sides of the trapezoid), for example, at least about 5% different, at least about 10% different, or at least 5-50% different. In some embodiments, the pitch of at least some of the interconnects 112 may be different from the pitch of at least some of the interconnects 122, e.g., at least about 5% different, or at least about 10% different.

Yet another characteristic feature of the hybrid bond of

IC structures

110 and 120 may be revealed by examining the material composition of insulating

materials

114 and 124, as in some such embodiments, the material composition of insulating

materials

114 and 124 may be different. For example, any of the materials of insulating

materials

114 and 124 may be included in an amount between about 1% and 75%, for example, between about 5% and 50%, indicating that these materials are intentionally included, as opposed to including possible accidental doping or impurities, for which any of these materials may be less than about 0.1%. Thus, any difference in the material composition of the insulating

materials

114 and 124 that exceeds about 0.1% of the unintentional doping/impurity level of a given material may be indicative of a hybrid bond for providing the microelectronic assembly 100.

Fig. 2A-2C illustrate cross-sectional side views of a microelectronic assembly 100 having first and

second IC structures

110, 120 bonded using f2b bonding, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 2A-2C is similar to that described above, except that none of the

IC structures

110, 120 is flipped upside down for bonding such that the bottom surface of the IC structure 120 faces and is bonded to the top surface of the IC structure 110. Similar to fig. 1A-1D, fig. 2A-2C indicate a back side 134-1 and a front side 134-2 of each of the

IC structures

110 and 120. In contrast to fig. 1A-1D, since the microelectronic assembly 100 shown in fig. 2A-2C is an f2b bonding assembly, it is bonding the back side 134-1 of the IC structure 120 to the front side 134-2 of the IC structure 110.

A dashed oval outline is provided in fig. 2A-2C to indicate examples of electrical connections that may be made in f2b bonded microelectronic assemblies. Specifically, fig. 2A illustrates an embodiment of the microelectronic assembly 100 wherein the f2b bond enables a direct electrical connection between one or more of the interconnects 112 of the IC structure 110 and the device circuitry 126 of the IC structure 120. In various embodiments, the overlap between the conductive fill material of interconnect 112 and the portion of device circuitry 126 that should be contacted may be substantially 100% of the surface area (at the bonding interface) or may be a partial overlap. On the other hand, fig. 2B illustrates an embodiment of the microelectronic assembly 100, wherein the f2B bond enables an electrical connection between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, similar to the electrical connection between the

interconnects

112 and 122 described above with reference to fig. 1. Similar to fig. 2B, fig. 2C also illustrates an embodiment of the microelectronic assembly 100, wherein f2B bonding enables electrical connection between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, except that fig. 2C illustrates an embodiment in which the interconnects 122 included in the backside portion 121 of the IC structure 120 are backside interconnects. In some embodiments, the backside interconnect may be formed by flipping the IC structure 120 upside down and forming the backside interconnect from the backside of the IC structure 120. Thus, as can be seen from fig. 2C, in such an embodiment, the trapezoids of the cross-sectional side view of interconnect 122 as backside interconnects (i.e., those in portion 121) are inverted relative to the trapezoids of interconnect 122 as non-backside interconnects (i.e., front side interconnect 122, those of interconnect 122 that are located outside of portion 121). Otherwise, the electrical connection between one or more of the interconnects 112 of the IC structure 110 and one or more of the backside interconnects 122 of the IC structure 120 is similar to the electrical connection between the

interconnects

112 and 122 described above with reference to fig. 1. In various other embodiments, the f2b bonded microelectronic assembly 100 can include any combination of the electrical connections shown in fig. 2A-2C.

It should be noted that although fig. 2C shows the backside interconnect 122 to be included in a layer of insulating material 124, in other embodiments the backside interconnect 122 may be included in a layer of insulating material having a different material composition than the insulating material 124 used to surround the frontside interconnect 122, and in still other embodiments the backside interconnect 122 may be provided within a substrate or support structure of the IC structure 120 (e.g., a support structure similar to support structure 132 described above).

One characteristic feature that is particular to the f2b bond shown in fig. 2A-2C is that the cross-sectional trapezoidal shape of interconnect 112 and front side interconnect 122 may be oriented in the same manner (i.e., not inverted relative to each other). This is illustrated in fig. 2A-2C, where the long side of the trapezoidal cross section of interconnect 112 is closer to the front side of IC structure 110 than the short side thereof, and thus closer to the bonding interface with IC structure 120, and the short side of the trapezoidal cross section of front side interconnect 122 is closer to the bonding interface with IC structure 110 than the long side thereof. For backside interconnect 122, the cross-sectional trapezoidal shape of interconnect 112 may be inverted relative to the cross-sectional trapezoidal shape of backside interconnect 122, as can be seen in fig. 2C. As shown in fig. 2C, the long side of the trapezoidal cross section of interconnect 112 is closer to the front side of IC structure 110 than the short side thereof, and thus closer to the bonding interface with IC structure 120, and the long side of the trapezoidal cross section of backside interconnect 122 is closer to the bonding interface with IC structure 110 than the short side thereof.

In addition to the features characteristic of the f2f bond of fig. 1, the features characteristic of the hybrid bond described with reference to fig. 1 are also applicable to the various embodiments of the microelectronic assembly of fig. 2, and are therefore not repeated for fig. 2 for the sake of brevity.

Fig. 3A-3K illustrate cross-sectional side views of a microelectronic assembly 100 having first and

second IC structures

110, 120 bonded using b2b bonding, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 3A-3K is similar to that of fig. 2 except that the IC structure 110 is flipped upside down for bonding so that the bottom surface of the IC structure 120 faces and is bonded to the bottom surface of the IC structure 110. Similar to fig. 1 and 2, fig. 3A-3K indicate a back side 134-1 and a front side 134-2 of each of the

IC structures

110 and 120. In contrast to the f2b bonding embodiment of fig. 2, since the microelectronic assembly 100 shown in fig. 3A-3K is a b2b bonding assembly, it is bonding the back side 134-1 of the IC structure 110 to the back side 134-1 of the IC structure 120.

A dashed oval outline is provided in fig. 3A-3K to indicate examples of electrical connections that may be made in b2b bonded microelectronic assemblies.

Fig. 3A illustrates an embodiment of b2b bonded microelectronic assembly 100 wherein IC structure 110 may include support structure 132 as described above, and the support structure of IC structure 120 may be removed prior to bonding. In such an embodiment, a bonding interface (e.g., bonding material 130) may be located between the back side 134-1 of the support structure 132 of the IC structure 110 and the back side 134-1 of the IC structure 120. The dashed oval outline shown in fig. 3A indicates that such an embodiment may include electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, similar to the electrical connections between the

interconnects

112 and 122 described above with reference to fig. 1.

Fig. 3B illustrates an embodiment of a B2B bonded microelectronic assembly 100 similar to that illustrated in fig. 3A, except that the dashed oval outline illustrated in fig. 3B indicates that such an embodiment may include one or more direct electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more devices of the device circuitry 126 of the IC structure 120, which are similar to the electrical connections described above with reference to fig. 2A.

Fig. 3C illustrates an embodiment of b2b bonded microelectronic assembly 100, wherein IC structure 120 may include support structure 132 as described above, and the support structure of IC structure 110 may be removed prior to bonding. In such an embodiment, a bonding interface (e.g., bonding material 130) may be located between the back side 134-1 of the support structure 132 of the IC structure 120 and the back side 134-1 of the IC structure 110. The dashed oval outline shown in fig. 3C indicates that such an embodiment may include electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, similar to the electrical connections between the

interconnects

112 and 122 described above with reference to fig. 1.

Fig. 3D illustrates an embodiment of a b2b bonded microelectronic assembly 100 similar to that illustrated in fig. 3C, except that the dashed oval outline illustrated in fig. 3D indicates that such an embodiment may include one or more direct electrical connections between one or more of the interconnects 122 of the IC structure 120 and one or more devices of the device circuitry 116 of the IC structure 110, which are similar to the electrical connections described above with reference to fig. 2A.

Fig. 3E illustrates an embodiment of a b2b bonded microelectronic assembly 100, wherein each of the

IC structures

110 and 120 may include a respective support structure 132 as described above. In such an embodiment, a bonding interface (e.g., bonding material 130) may be located between the back side 134-1 of the support structure 132 of the IC structure 120 and the back side 134-1 of the support structure 132 of the IC structure 110. The dashed oval outline shown in fig. 3E indicates that such an embodiment may include electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, similar to the electrical connections between the

interconnects

112 and 122 described above with reference to fig. 1.

Fig. 3F shows an embodiment of b2b bonded microelectronic assembly 100 in which neither IC structure 120 nor IC structure 110 includes support structure 132 (i.e., both support structures may be removed prior to bonding), but carrier support structure 136 may be attached to IC structure 110, thereby providing mechanical stability to microelectronic assembly 100. In other embodiments, carrier support structures 136 may be attached to IC structure 120, and/or one carrier support structure 136 may be attached to IC structure 110 and another carrier support structure 136 may be attached to IC structure 120. The dashed oval outline shown in fig. 3F indicates that such an embodiment may include electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more of the interconnects 122 of the IC structure 120, similar to the electrical connections between the

interconnects

112 and 122 described above with reference to fig. 1.

Fig. 3G illustrates an embodiment of a b2b bonded microelectronic assembly 100 similar to that shown in fig. 3F, except that the dashed oval outline shown in fig. 3G indicates that such an embodiment may include one or more direct electrical connections between one or more devices of the device circuitry 126 of the IC structure 120 and one or more devices of the device circuitry 116 of the IC structure 110. In various embodiments, the overlap between the portion of device circuitry 116 that should be contacted and the portion of device circuitry 126 that should be contacted may be substantially 100% of the surface area (at the bonding interface) or may be a partial overlap.

Fig. 3H illustrates an embodiment of a b2b bonded microelectronic assembly 100 similar to that illustrated in fig. 3F or 3G, except that the dashed oval outline illustrated in fig. 3H indicates that such an embodiment may include one or more direct electrical connections between one or more of the interconnects 112 of the IC structure 110 and one or more devices of the device circuitry 126 of the IC structure 120, which are similar to the electrical connections described above with reference to fig. 2A. Although not specifically shown, other embodiments of b2 b-bonded microelectronic assemblies 100 similar to those shown in fig. 3F or 3G may include one or more direct electrical connections between one or more of the interconnects 122 of the IC structure 120 and one or more devices of the device circuitry 116 of the IC structure 110, which are similar to the electrical connections described above with reference to fig. 2A.

Fig. 3I-3K illustrate an embodiment of a b2b bonded microelectronic assembly 100, wherein one or both of the

IC structures

110 and 120 include backside interconnects.

Specifically, fig. 3I shows an embodiment of a b2b bonded microelectronic assembly 100, wherein the IC structure 120 includes a backside interconnect 122 in a portion 121, which is similar to the backside interconnect 122 described with reference to fig. 2C. The dashed oval outline shown in fig. 3I indicates an exemplary electrical connection between one of the front side interconnects 112 of the IC structure 110 and one of the back side interconnects 122 of the IC structure 120. Although not specifically shown, in other embodiments of the b2b bonded microelectronic assembly 100 similar to that shown in fig. 3I, one or more of the backside interconnects 122 of the IC structure 120 may be electrically coupled to one or more devices of the device circuitry 116 of the IC structure 110 at a bonding interface.

Fig. 3J illustrates an embodiment of a b2b bonded microelectronic assembly 100, wherein the IC structure 110 includes a backside interconnect 112 in a portion 111, similar to backside interconnect 122 described with reference to fig. 2C. As can be seen from fig. 3J, in such an embodiment, the trapezoids of the cross-sectional side views of interconnects 112 that are backside interconnects (i.e., those in portion 111) are inverted relative to the trapezoids of interconnects 112 that are non-backside interconnects (i.e., front side interconnects 112, those of interconnects 112 that are located outside of portion 111). It should be noted that although fig. 3J illustrates the backside interconnect 112 to be included in a layer of insulating material 114, in other embodiments the backside interconnect 112 may be included in a layer of insulating material having a different material composition than the insulating material 114 used to surround the frontside interconnect 112, and in still other embodiments the backside interconnect 112 may be provided within a substrate or support structure of the IC structure 110 (e.g., a support structure similar to support structure 132 described above). The dashed oval outline shown in fig. 3J indicates an exemplary electrical connection between one of the front-side interconnects 122 of the IC structure 120 and one of the back-side interconnects 112 of the IC structure 110. Although not specifically shown, in other embodiments of the b2b bonded microelectronic assembly 100 similar to that shown in fig. 3J, one or more of the backside interconnects 112 of the IC structure 120 may be electrically coupled to one or more devices of the device circuitry 126 of the IC structure 120 at a bonding interface.

Fig. 3K shows an embodiment of b2b bonded microelectronic assembly 100, which may be a combination of the embodiments shown in fig. 3I and 3J, in that IC structure 110 includes backside interconnect 112 in portion 111 and IC structure 120 includes backside interconnect 122 in portion 121. The dashed oval outline shown in fig. 3K indicates an exemplary electrical connection between one of the backside interconnects 112 of the IC structure 110 and one of the backside interconnects 122 of the IC structure 120.

One characteristic feature that is characteristic of the b2b bond shown in fig. 3A-3K is that the cross-sectional trapezoidal shape of the front side interconnect 112 may be inverted relative to the cross-sectional trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 3A-3K, where the shorter side of the trapezoidal cross section of front side interconnect 112 is closer to back side 134-1 of IC structure 110 than its longer side, and thus closer to the bonding interface with IC structure 120, and the shorter side of the trapezoidal cross section of front side interconnect 122 is closer to the bonding interface with IC structure 110 than its longer side. One characteristic feature that is particular to the b2b bonding of the microelectronic assembly when implementing the backside interconnect 122 is that the cross-sectional trapezoidal shape of the front side interconnect 112 can be oriented in the same manner as the cross-sectional trapezoidal shape of the backside interconnect 122 (i.e., not inverted relative to each other), as can be seen in fig. 3I and 3K. As shown in fig. 3I and 3K, the shorter sides of the trapezoidal cross section of the front side interconnect 112 are closer to the front side of the IC structure 110 than the longer sides thereof, and thus closer to the bonding interface with the IC structure 120, and the longer sides of the trapezoidal cross section of the back side interconnect 122 are closer to the bonding interface with the IC structure 110 than the shorter sides thereof. One characteristic feature that is particular to the b2b bonding of the microelectronic assembly when implementing the backside interconnect 112 is that the cross-sectional trapezoidal shape of the front side interconnect 122 can be oriented in the same manner as the cross-sectional trapezoidal shape of the backside interconnect 112 (i.e., not inverted relative to each other), as can be seen in fig. 3J and 3K. As shown in fig. 3J and 3K, the shorter sides of the trapezoidal cross section of the front side interconnect 122 are closer to the front side 134-1 of the IC structure 120 than the longer sides thereof, and thus closer to the bonding interface with the IC structure 110, and the longer sides of the trapezoidal cross section of the back side interconnect 112 are closer to the bonding interface with the IC structure 120 than the shorter sides thereof.

In addition to the features characteristic of the f2f bond of fig. 1, the characteristic features of the hybrid bond described with reference to fig. 1 are applicable to the various embodiments of the microelectronic assembly of fig. 3, and thus are not repeated for fig. 3 for the sake of brevity.

Although fig. 1-3 illustrate an embodiment in which two IC structures (i.e., a pair of IC structures 110 and 120) are bonded together, any of the embodiments described with reference to fig. 1-3 can be extended to a microelectronic assembly 100 that includes three or more IC structures bonded together in any combination as described herein. For example, in some embodiments, the microelectronic assembly 100 can include two IC structures joined in an f2b joining configuration, e.g., as shown in fig. 2, and can further include a third IC structure joined to the IC structure 120, such that the IC structure 120 and the third IC structure are joined in an f2f joining configuration according to any of the embodiments described herein (i.e., the back side 134-1 of the IC structure 120 will be joined to the IC structure 110 according to any of the embodiments described herein, while the front side 134-2 of the IC structure will be joined to the front side of the third IC structure according to the f2f joining configuration embodiments described herein). In another example, in some embodiments, the microelectronic assembly 100 can include two IC structures joined in an f2f joining configuration, e.g., as shown in fig. 1, and can further include a third IC structure joined to the IC structure 120, such that the IC structure 120 and the third IC structure are joined in a b2b joining configuration according to any of the embodiments described herein (i.e., the front side 134-2 of the IC structure 120 will be joined to the IC structure 110 according to any of the embodiments described herein, while the back side 134-1 of the IC structure will be joined to the back side of the third IC structure according to the b2b joining configuration embodiments described herein). All such embodiments having three or more IC structures bonded together are within the scope of the present disclosure and may be included in other embodiments of microelectronic assemblies 100 as shown in fig. 1-3.

Fig. 4 illustrates a cross-sectional side view of a microelectronic assembly 100 having different etch stop materials in the first and

second IC structures

110, 120, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 4 is similar to that shown in fig. 1, except that fig. 4 further illustrates a layer of etch stop material 113 that may be included in the IC structure 110 (e.g., between some or all of the metal layer pairs of the metallization stack of the IC structure 110) and a layer of etch stop material 123 that may be included in the IC structure 120 (e.g., between some or all of the metal layer pairs of the metallization stack of the IC structure 120). Such a layer of etch stop material is common in the semiconductor fabrication art and may be provided at a different location of the

IC structures

110, 120 than shown in fig. 4, depending on, for example, the particular processing technique used to fabricate portions of these IC structures. Any location of the

etch stop materials

113, 123 within the

IC structures

110, 120 known in the art is possible and within the scope of the present disclosure. A particular feature with respect to etch stop materials in the context of hybrid manufacturing is that the material composition of their etch stop materials may be different, as the

IC structures

110, 120 may be manufactured by different manufacturers using different materials or different manufacturing techniques. For example, the etch stop material 113 may include a material having silicon and nitrogen (e.g., silicon nitride), while the etch stop material 123 may include a material having silicon and carbon (e.g., silicon carbide), or one of the

etch stop materials

113, 123 may include a material having aluminum and oxygen (e.g., aluminum oxide). Further, the bonding material 130 at the interface between the

IC structures

110 and 120 may have a material composition different from one or both of the etch stop material 113 and the etch stop material 123. For example, in some embodiments, the bonding material 130 may include silicon, nitrogen, and carbon, wherein the atomic percent of any of these materials may be at least 1%, e.g., between about 1% and 50%, indicating that these elements are intentionally added, as opposed to unexpected impurities, which are typically less than about 0.1%. Having both nitrogen and carbon in addition to silicon in these concentrations is not typically used in conventional semiconductor fabrication processes where either nitrogen is typically used in combination with silicon or carbon is used in combination with silicon, and therefore this would be a characteristic feature of the hybrid fabrication described herein. The use of an etch stop material comprising silicon, nitrogen, and carbon at the interface between IC structures 110 and 120 (where the atomic percent of any of these materials may be at least 1%, e.g., siOCN) may be advantageous in: such a material may serve as both an etch stop material and have sufficient adhesive properties to bond the

IC structures

110 and 120 together. Furthermore, an etch stop material comprising silicon, nitrogen, and carbon at the interface between IC structures 110 and 120 (where the atomic percent of any of these materials may be at least 1%) may be advantageous in improving the etch selectivity of such material relative to etch

stop materials

113, 123.

Although the

etch stop materials

113, 123 of fig. 4 are not shown in fig. 1-3, any of the embodiments of the microelectronic assembly 100 described with reference to fig. 1-3 may include any of the

etch stop materials

113, 123 at any suitable location, as described with reference to fig. 4. Similarly, although some of the figures following fig. 4 show

etch stop materials

113, 123, any of the embodiments of the microelectronic assembly 100 described with reference to these figures may not include one or both of the

etch stop materials

113, 123.

Fig. 1-4 illustrate interconnections that may be included in the

IC structures

110, 120 prior to bonding the IC structures together. In some embodiments of hybrid fabrication, the microelectronic assembly 100 may also include interconnects, such as conductive vias or conductive traces, provided in one or both of the

IC structures

110, 120 after the IC structures are bonded together. Such interconnects are referred to as "post-bond interconnects" in this disclosure, and may include any combination of one or more post-bond vias and/or one or more post-bond traces. Providing one or more post-bond interconnects may provide significant advantages in its ability to provide electrical connections between various components of the microelectronic assembly 100 and/or provide reduced resistance. The post-bond interconnects may be particularly suitable for routing power to various components of the microelectronic assembly 100 due to reduced resistance, although they may also be used to route ground and/or signals to various components of the microelectronic assembly 100. Also for reasons of reduced resistance, the post-bond interconnects may be referred to as "quick interconnects" (e.g., quick vias) because they may allow for faster routing of power, ground, and/or signals to various components of the microelectronic assembly 100 than can be achieved by the

interconnects

112 and 122 located in the

respective IC structures

110, 120 prior to bonding the

IC structures

110, 120 together.

Some embodiments of microelectronic assemblies 100 with post-bond interconnections are shown in fig. 5-11. In particular, fig. 5-7 illustrate some embodiments of a microelectronic assembly 100 having post-bond vias 140 formed from a top of the microelectronic assembly 100, fig. 8-10 illustrate some embodiments of a microelectronic assembly 100 having post-bond vias 140 formed from a bottom of the microelectronic assembly 100, and fig. 11 illustrates some embodiments of a microelectronic assembly 100 in which the post-bond vias 140 extend through pairs of

IC structures

110 and 120 bonded together. Although fig. 5-11 illustrate a particular arrangement of the various components of

IC structures

110 and 120, one or more of the post-bond interconnects described with reference to post-bond vias 140 of fig. 5-11 may be provided in any of the embodiments of microelectronic assembly 100 described with reference to fig. 1-4. In other words, any of the embodiments described with reference to fig. 5-11 may be combined with any of the embodiments described with reference to fig. 1-4.

In various embodiments (e.g., for any of the embodiments of the microelectronic assembly 100 described with reference to fig. 5-11), such post-bond interconnects may include at least a conductive filler material, and optionally, a liner material. In some embodiments, one characteristic feature of the hybrid bond of

IC structures

110 and 120 may be that the material composition of the conductive fill material of the post-bond interconnect may be different than the material composition of conductive fill material 118 and/or the material composition of conductive fill material 128. The differences in material composition of the

conductive fill materials

118 and 128 described above apply to differences in material composition of the conductive fill material and the conductive fill material 118 and/or 128 of the post-bond interconnect and, therefore, are not repeated here for brevity. In some embodiments, another characteristic feature of the hybrid bond of

IC structures

110 and 120 may be that the material composition of the liner of the post-bond interconnect may be different than the material composition of liner 119 and/or the material composition of liner 129. The differences in material composition of the

liners

119 and 129 described above apply to differences in material composition of the liners and the liners 119 and/or 129 of the post-bond interconnect and, therefore, are not repeated here for the sake of brevity.

Fig. 5-11 illustrate some embodiments of a microelectronic assembly 100 having post-bond vias 140 formed from the top of, from the bottom of, or extending through a plurality of bond pairs of the microelectronic assembly 100 for different bond configurations. For any of the embodiments of fig. 5-11 (e.g., whether f2f is used, f2b is used, or b2b is used), the post-bond via 140 extending from the top or bottom of the microelectronic assembly 100 may stop at any of the following options (i.e., the bottom may be interfaced therewith): 1) insulating material (e.g., insulating material 114 or insulating material 124), 2) any of the etch stop materials that may be present in the microelectronic assembly 100 (e.g., any of the etch stop materials 113, 123), 3) bonding material 130 or bonding interface between different IC structures bonded together, and/or 4) any portion of the

interconnects

112, 122 or other components (e.g., device circuitry 116, 126) of the

IC structures

110, 120. In some embodiments, the location/depth of the bottom of the post-bond via 140 extending from the top or bottom of the microelectronic assembly 100 can be based on the particular etching process used to form the post-bond via 140. For example, if an opening for post-bond via 140 is formed using a selective etching process with an etchant that removes insulating

materials

114, 124 and etch stop material 123 but does not remove, for example, etch stop material 113, then post-bond via 140 may have a bottom aligned with a top of etch stop material 113. In another example, if a selective etching process is used to form openings for post-bond vias 140 with an etchant that removes insulating

materials

114, 124 and etch stop material 123 but does not remove bonding material 130, then post-bond vias 140 may have bottoms aligned with the tops of bonding material 130. To ensure this, the respective materials will be selected to have sufficient etch selectivity, wherein, as is known in the art, if the etchant used to etch one material does not substantially etch the other material, or possibly vice versa, the two materials are described as "having sufficient etch selectivity". In other embodiments, some materials of the microelectronic assembly 100 may have sufficient etch selectivity relative to each other, and the post-bond vias 140 may still extend through these materials, which may be accomplished through the use of different etchants, such that openings for the post-bond vias 140 are formed through the different materials of the microelectronic assembly 100. In other embodiments, the location/depth of the bottom of the post-bond via 140 may be based on the time of etching, wherein generally the longer the etching time, the deeper the opening for the post-bond via 140. In the context of the embodiments of fig. 8-10 in which the post-bond via 140 is formed from the bottom of the microelectronic assembly 100, the bottom of the post-bond via 140 refers to the end of the post-bond via 140 opposite the bottom of the microelectronic assembly 100 shown in fig. 8-10.

Fig. 5-7 illustrate some embodiments of the microelectronic assembly 100 having post-bond vias 140 formed from the top of the microelectronic assembly 100 for f2f, f2b, and b2b bond configurations, respectively.

Fig. 5A-5D illustrate cross-sectional side views of a microelectronic assembly 100, which is an f2f bonding assembly having a post-bond via 140 formed from the top, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 5A-5D is similar to that shown in fig. 1, except that it further includes post-bond vias 140 formed from the top of the microelectronic assembly 100. For the embodiment of fig. 5A-5D, post-bond via 140 may be referred to as "top f2f post-bond via 140".

For the f2f embodiment shown in FIG. 5, the "top" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 110. Fig. 5A-5D are different views of an embodiment of a microelectronic assembly 100 having top f2f post-bond vias 140 of different depths.

Fig. 5A illustrates an embodiment in which the top f2f post-bond via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 and stops before reaching the bonding material 130. Thus, fig. 5A shows that the top f2f post-bond via 140 may be such that it is a blind via in a top IC structure (e.g., IC structure 120). Although not specifically shown in the cross-section of fig. 5A, the top f2f post-bond via 140 may be electrically coupled to one or more components of the IC structure 120 (e.g., to one or more of the interconnects 122, devices of the device circuitry 126, etc.) to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 5A, in some embodiments, the top f2f post-bond via 140, which is a blind via in the IC structure 120 (e.g., as shown in fig. 5A), may be electrically coupled to one or more components of the IC structure 110 (e.g., to one or more of the interconnects 112, devices of the device circuitry 116, etc.) to provide power, ground, and/or signals to those components of the IC structure 110, which may be accomplished, for example, by electrically coupling the top f2f post-bond via 140 to one or more of the interconnects 122 and electrically coupling one or more of those interconnects 122 to one or more components of the IC structure 110.

Fig. 5B illustrates an embodiment in which the post-bond top f2f via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 and stops when the interconnect 112 is encountered. Such top f2f post-bond via 140 may be formed, for example, by: an opening for the via is formed using an etch that is selective to the material of interconnect 112 such that the bottom of via 140 is self-aligned to interconnect 112 after top f2f bonding. In this way, the top f2f post-bond via 140 may be electrically coupled to the interconnect 112. Although not specifically shown in the cross-section of fig. 5B, such top f2f post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120. The top f2f post-bond via 140, which extends all the way through the IC structure 120 and is electrically connected to the interconnect 112 of the IC structure 110, may be further electrically coupled to one or more components of the IC structure 110 coupled to the interconnect 112 to provide power, ground, and/or signals to those components of the IC structure 110.

Fig. 5C illustrates an embodiment in which the top f2f post-bond via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100, extends through all of the top IC structure (e.g., IC structure 120) of the microelectronic assembly 100, bonds material 130, and extends into the bottom IC structure (e.g., IC structure 110) of the microelectronic assembly 100, and stops before reaching the bottom of the microelectronic assembly 100. Thus, fig. 5C shows that the top f2f post-bond via 140 may be such that it is a blind via extending through the top IC structure and into the bottom IC structure (e.g., from IC structure 120 into IC structure 110). Although not specifically shown in the cross-section of fig. 5C, such top f2f post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 5C, the post-bond top f2f via 140, which extends all the way through the IC structure 120 and forms a blind via in the IC structure 110 as shown in fig. 5C, may be further electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

Fig. 5D illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 to the bottom of the microelectronic assembly 100 after the top f2f is bonded. In this manner, the top f2f post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the top f2f post-bonded vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 5D, the post-bond via 140, which is a TSV, top f2f in the microelectronic assembly 100 can be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120, and/or can be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

In some embodiments, one characteristic feature that is characteristic of the top f2f post-bond via 140 extending from the top of the f2f bonded microelectronic assembly as shown in fig. 5A-5D may be that the cross-sectional trapezoidal shape of the top f2f post-bond via 140 is inverted relative to the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 5A-5D, where the shorter side of the trapezoidal cross-section of the via 140 after the top f2f bond is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross-section of the front side interconnect 122 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof. In some embodiments, another characteristic feature that is characteristic of the top f2f post-bond via 140 extending from the top of the f2f bonded microelectronic assembly as shown in fig. 5A-5D may be that the cross-sectional trapezoidal shape of the top f2f post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of the front side interconnect 112. This is illustrated in fig. 5A-5D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2f bond is closer to the bottom of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the front side interconnect 112 is closer to the bottom of the microelectronic assembly 100 than its longer side. Although not specifically shown in fig. 5A-5D, if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of top f2f post-bond via 140 extending from the top of the f2f bonded microelectronic assembly, as shown in fig. 5A-5D, may be that the cross-sectional trapezoidal shape of top f2f post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of backside interconnect 122. This will be shown in fig. 5A-5D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2f bond is closer to the bottom of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the backside interconnect 122 is closer to the bottom of the microelectronic assembly 100 than its longer side. Further, although not specifically shown in fig. 5A-5D, if IC structure 110 includes backside interconnect 112, then in some embodiments, a characteristic feature characteristic of top f2f post-bond via 140 extending from the top of the f2f bonded microelectronic assembly, as shown in fig. 5A-5D, may be that the cross-sectional trapezoidal shape of top f2f post-bond via 140 is inverted relative to the trapezoidal shape of backside interconnect 112. This will be shown in fig. 5A-5D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2f bond is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the backside interconnect 112 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof.

Fig. 6A-6D illustrate cross-sectional side views of a microelectronic assembly 100, which is an f2b bonding assembly having a post-bonding via 140 formed from the top, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 6A-6D is similar to that shown in fig. 2, except that post-bond vias 140 are also included that are formed from the top of the microelectronic assembly 100. For the embodiment of fig. 6A-6D, the post-bond via 140 may be referred to as a "top f2b post-bond via 140".

For the f2b embodiment shown in FIG. 6, the "top" of the microelectronic assembly 100 is considered the front 134-2 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 110. Fig. 6A-6D are different views of an embodiment of a microelectronic assembly 100 having top f2b post-bond vias 140 of different depths.

Fig. 6A illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 after the top f2b bond and stops before reaching the bonding material 130 (i.e., fig. 6A is similar to fig. 5A except that fig. 6A illustrates the f2b bond configuration). Thus, fig. 6A shows that the top f2b post-bond via 140 may be such that it is a blind via in a top IC structure (e.g., IC structure 120). Although not specifically shown in the cross-section of fig. 6A, the top f2b post-bond via 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 6A, in some embodiments, the top f2b post-bond via 140, which is a blind via in the IC structure 120 (e.g., as shown in fig. 6A), may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110, which may be accomplished, for example, by electrically coupling the top f2b post-bond via 140 to one or more interconnects 122 and electrically coupling one or more of those interconnects 122 to one or more components of the IC structure 110.

Fig. 6B illustrates an embodiment in which the post-bond top f2B via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 and stops when the interconnect 112 is encountered (i.e., fig. 6B is similar to fig. 5B except that fig. 6B illustrates an f2B bond configuration). Such top f2b post-bond via 140 may be formed, for example, by: an opening for the via is formed using an etch that is selective to the material of interconnect 112 such that the bottom of via 140 is self-aligned to interconnect 112 after top f2b is bonded. In this way, the top f2b post-bond via 140 may be electrically coupled to the interconnect 112. Although not specifically shown in the cross-section of fig. 6B, such top f2B post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120. The top f2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 110 coupled with the interconnect 112 by means of the top f2b post-bond via 140 extending all the way through the IC structure 120 and electrically connected with the interconnect 112 of the IC structure 110 to provide power, ground, and/or signals to these components of the IC structure 110.

Fig. 6C illustrates an embodiment in which the top f2b post-bond via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100, extends through all of the top IC structure (e.g., IC structure 120) of the microelectronic assembly 100, bonds material 130 and into the bottom IC structure (e.g., IC structure 110) of the microelectronic assembly 100, and stops before reaching the bottom of the microelectronic assembly 100 (i.e., fig. 6C is similar to fig. 5C except that fig. 6C illustrates the f2b bonding configuration). Thus, fig. 6C shows that the top f2b post-bond via 140 may be such that it is a blind via that extends through the top IC structure and into the bottom IC structure (e.g., from IC structure 120 into IC structure 110). Although not specifically shown in the cross-section of fig. 6C, such top f2b post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 6C, the post-bond via 140, which extends all the way through the IC structure 120 and forms a blind via in the IC structure 110 as shown in fig. 6C, may be further electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

Fig. 6D illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 all the way to the bottom of the microelectronic assembly 100 after the top f2b bond (i.e., fig. 6D is similar to fig. 5D except that fig. 6D illustrates the f2b bond configuration). In this manner, the top f2b post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the top f2b post-bonded vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 6D, the post-bond via 140, which is a TSV, top f2b in the microelectronic assembly 100 can be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120, and/or can be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

In some embodiments, one characteristic feature that is unique to the top f2b post-bond via 140 extending from the top of the f2 b-bonded microelectronic assembly as shown in fig. 6A-6D may be that the cross-sectional trapezoidal shape of the top f2b post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 6A-6D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2b is bonded is closer to the bottom of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the front side interconnect 122 is closer to the bottom of the microelectronic assembly 100 than its longer side. In some embodiments, another characteristic feature that is characteristic of the top f2b post-bond via 140 extending from the top of the f2 f-bond microelectronic assembly as shown in fig. 6A-6D may be that the cross-sectional trapezoidal shape of the top f2b post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of the front side interconnect 112. This is illustrated in fig. 6A-6D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2b is bonded is closer to the bottom of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the front side interconnect 112 is closer to the bottom of the microelectronic assembly 100 than its longer side. Although not specifically shown in fig. 6A-6D, if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of top f2b post-bond via 140 extending from the top of the f2 f-bonded microelectronic assembly, as shown in fig. 6A-6D, may be that the cross-sectional trapezoidal shape of top f2b post-bond via 140 is inverted relative to the trapezoidal shape of backside interconnect 122. This will be shown in fig. 6A-6D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2b is bonded is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the backside interconnect 122 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof. Further, although not specifically shown in fig. 6A-6D, if the IC structure 110 includes a backside interconnect 112, then in some embodiments, a characteristic feature characteristic of the top f2f post-bond via 140 extending from the top of the f2b bonded microelectronic assembly, as shown in fig. 6A-6D, may be that the cross-sectional trapezoidal shape of the top f2b post-bond via 140 is also inverted relative to the trapezoidal shape of the backside interconnect 112. This will be shown in fig. 6A-6D, where the shorter side of the trapezoidal cross section of the via 140 after the top f2b is bonded is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the backside interconnect 112 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof.

Fig. 7A-7E illustrate cross-sectional side views of a microelectronic assembly 100, which is a b2b bonding assembly having a post-bonding via 140 formed from the top, according to some embodiments. The microelectronic assembly 100 shown in fig. 7A-7E is similar to that shown in fig. 3, except that it further includes post-bond vias 140 formed from the top of the microelectronic assembly 100. For the embodiment of fig. 7A-7E, post-bond via 140 may be referred to as "top b2b post-bond via 140".

For the b2b embodiment shown in fig. 7, the "top" of the microelectronic assembly 100 is considered the front 134-2 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the front 134-1 of the IC structure 110. Fig. 7A-7E are different views of an embodiment of a microelectronic assembly 100 having top b2b post-bond vias 140 of different depths.

Fig. 7A illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 after the top b2b bond and stops before reaching the bonding material 130 (i.e., fig. 7A is similar to fig. 5A and 6A, except that fig. 7A illustrates a b2b bond configuration). Thus, fig. 7A shows that the top b2b post-bond via 140 may be such that it is a blind via in a top IC structure (e.g., IC structure 120). Although not specifically shown in the cross-section of fig. 7A, the top b2b post-bond via 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 7A, in some embodiments, the top b2b post-bond via 140, which is a blind via in the IC structure 120 (e.g., as shown in fig. 7A), may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110, which may be accomplished, for example, by electrically coupling the top b2b post-bond via 140 to one or more interconnects 122 and electrically coupling one or more of those interconnects 122 to one or more components of the IC structure 110.

Fig. 7B illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 after the top B2B bond and stops when the backside interconnect 112 is encountered (i.e., fig. 7B is similar to fig. 5B and 6B, except that fig. 7B illustrates a B2B bond configuration, and thus, in fig. 7B, the interconnect 112 is a backside interconnect and in fig. 5B and 6B, the interconnect is a front side interconnect). Such top b2b post-bond via 140 may be formed, for example, by: the openings for the vias are formed using an etch that is selective to the material of the backside interconnect 112 such that the bottom of the via 140 is self-aligned with the backside interconnect 112 after the top b2b is bonded. In this way, the top b2b post-bond via 140 may be electrically coupled to the backside interconnect 112. Although not specifically shown in the cross-section of fig. 7B, such top B2B post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120. The top b2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 110 coupled with the backside interconnect 112 by means of a top b2b post-bond via 140 extending all the way through the IC structure 120 and electrically connected with the backside interconnect 112 of the IC structure 110 to provide power, ground, and/or signals to these components of the IC structure 110.

Fig. 7C illustrates an embodiment in which the top B2B post-bond via 140 extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100 and stops when the front side interconnect 112 is encountered (i.e., fig. 7C is similar to fig. 7B except that the bond interface is in a different location and the interconnect 112 that the top B2B post-bond via 140 contacts is the front side interconnect). Such top b2b post-bond via 140 may be formed, for example, by: an opening for the via is formed using an etch that is selective to the material of the front side interconnect 112 such that the bottom of the via 140 is self-aligned with the front side interconnect 112 after the top b2b is bonded. In this way, the top b2b post-bond via 140 may be electrically coupled to the front side interconnect 112. Although not specifically shown in the cross-section of fig. 7C, such top b2b post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120. The top b2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 110 coupled with the front side interconnect 112 by means of the top b2b post-bond via 140 extending all the way through the IC structure 120 and electrically connected with the front side interconnect 112 of the IC structure 110 to provide power, ground, and/or signals to these components of the IC structure 110.

Fig. 7D illustrates an embodiment in which the post-bond via 140 at the top b2b extends from the top of the microelectronic assembly 100 toward the bottom of the microelectronic assembly 100, extends through all of the top IC structures of the microelectronic assembly 100 (e.g., IC structure 120), bonds material 130 and into the bottom IC structures of the microelectronic assembly 100 (e.g., IC structure 110), and stops before reaching the bottom of the microelectronic assembly 100 (i.e., fig. 7D is similar to fig. 5C and 6C, except that fig. 7D illustrates a b2b bonding configuration). Thus, fig. 7D shows that the top b2b post-bond via 140 may be such that it is a blind via that extends through the top IC structure and into the bottom IC structure (e.g., from IC structure 120 into IC structure 110). Although not specifically shown in the cross-section of fig. 7D, such top b2b post-bond vias 140 may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 7D, the b2b post-bond via 140, which extends all the way through the IC structure 120 and forms a blind via in the IC structure 110 as shown in fig. 7D, may be further electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

Fig. 7E illustrates an embodiment in which the via 140 extends from the top of the microelectronic assembly 100 all the way to the bottom of the microelectronic assembly 100 after the top b2b bond (i.e., fig. 7E is similar to fig. 5D and 6D, except that fig. 7E illustrates a b2b bond configuration). In this manner, the top b2b post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the top b2b post-bonded vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 7E, the post-bond via 140, which is a TSV, top b2b in the microelectronic assembly 100 can be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120, and/or can be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110.

In some embodiments, one characteristic feature that is characteristic of the top b2b post-bond via 140 extending from the top of the b2 b-bond microelectronic assembly as shown in fig. 7A-7E may be that the cross-sectional trapezoidal shape of the top b2b post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 7A-7E, where the shorter side of the trapezoidal cross section of the via 140 after the top b2b is bonded is closer to the bottom of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the front side interconnect 122 is closer to the bottom of the microelectronic assembly 100 than its longer side. In some embodiments, another characteristic feature that is characteristic of the top b2b post-bond via 140 extending from the top of the b2 b-bond microelectronic assembly as shown in fig. 7A-7E may be that the cross-sectional trapezoidal shape of the top b2b post-bond via 140 is inverted relative to the trapezoidal shape of the front side interconnect 112. This is illustrated in fig. 7A-7E, where the shorter side of the trapezoidal cross section of the via 140 after the top b2b is bonded is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the front side interconnect 112 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof. Although not specifically shown in fig. 7A-7E, if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of top b2b post-bond via 140 extending from the top of the b2 b-bonded microelectronic assembly, as shown in fig. 7A-7E, may be that the cross-sectional trapezoidal shape of top b2b post-bond via 140 is inverted relative to the trapezoidal shape of backside interconnect 122. This will be shown in fig. 7A-7E, where the shorter side of the trapezoidal cross section of the via 140 after the top b2b is bonded is closer to the bottom of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the backside interconnect 122 is closer to the bottom of the microelectronic assembly 100 than the shorter side thereof. Further, although not specifically shown in fig. 7A, 7C, 7D, and 7E (i.e., only shown in fig. 7B), if IC structure 110 includes backside interconnect 112, then in some embodiments, a characteristic feature characteristic of top portion B2B post-bond via 140 extending from the top of the B2B-bonded microelectronic assembly, as shown in fig. 7A-7E, may be that the cross-sectional trapezoidal shape of top portion B2B post-bond via 140 is oriented in the same manner as the trapezoidal shape of backside interconnect 112 (i.e., not inverted). This will be shown in fig. 7A, 7C, 7D, and 7E, where the shorter side of the trapezoidal cross section of the via 140 is closer to the bottom of the microelectronic assembly 100 than the longer side thereof after the top b2b is bonded, and the shorter side of the trapezoidal cross section of the backside interconnect 112 is closer to the bottom of the microelectronic assembly 100 than the longer side thereof.

While fig. 7A-7E illustrate the top b2b post-bond via 140 for some specific examples of b2b bond configurations, the description provided herein of the top b2b post-bond via 140 is equally applicable to other embodiments of the b2b bond configuration of the microelectronic assembly 100, e.g., to any of those embodiments described with reference to fig. 3.

Although each of fig. 5-7 shows a single top post-bond via 140 extending from the top of the microelectronic assembly 100, in other embodiments, the microelectronic assembly 100 may include any number of two or more top post-bond vias 140, which may have the same or different depths.

Fig. 8-10 illustrate some embodiments of a microelectronic assembly 100 having post-bond vias 140 formed from the bottom of the microelectronic assembly 100 for f2f, f2b, and b2b bond configurations, respectively. In some embodiments, the post-bond via 140 extending from the bottom of the microelectronic assembly 100 may be fabricated as follows: the microelectronic assembly is flipped upside down (i.e., such that the back side of the microelectronic assembly is facing up), the flipped back side of the microelectronic assembly is processed to form bonded vias 140 extending from the back side of the microelectronic assembly, and then the microelectronic assembly is flipped upside down again (i.e., such that the back side of the microelectronic assembly is facing down and the front side is facing up, and such that the bonded vias 140 extend upwardly from the bottom of the microelectronic assembly, as shown in fig. 8-10).

Fig. 8A-8D illustrate cross-sectional side views of a microelectronic assembly 100, which is an f2f bonding assembly having a post-bond via 140 formed from the bottom, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 8A-8D is similar to that shown in fig. 1, except that it further includes post-bond vias 140 formed from the bottom of the microelectronic assembly 100. For the embodiment of fig. 8A-8D, post-bond via 140 may be referred to as "bottom f2f post-bond via 140".

For the f2f embodiment shown in FIG. 8, the "top" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 110. Fig. 8A-8D are different views of an embodiment of a microelectronic assembly 100 having bottom f2f bonded vias 140 of different depths.

Fig. 8A illustrates an embodiment in which the bottom f2f post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops before reaching the bonding material 130. Thus, fig. 8A shows that the bottom f2f post-bond via 140 can be such that it is a blind via in the bottom IC structure (e.g., in IC structure 110). Although not specifically shown in the cross-section of fig. 8A, the bottom f2f post-bond via 140 may be electrically coupled to one or more components of the IC structure 110 (e.g., to one or more of the interconnects 112, devices of the device circuitry 116, etc.) to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 8A, in some embodiments, bottom f2f post-bond via 140, which is a blind via in IC structure 110 (e.g., as shown in fig. 8A), may be electrically coupled to one or more components of IC structure 120 (e.g., to one or more of interconnects 122, devices of device circuitry 126, etc.) to provide power, ground, and/or signals to these components of IC structure 120, which may be accomplished, for example, by electrically coupling bottom f2f post-bond via 140 to one or more of interconnects 112 and electrically coupling one or more of these interconnects 112 to one or more components of IC structure 110.

Fig. 8B illustrates an embodiment in which the bottom f2f post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops when the interconnect 122 is encountered. Such bottom f2f post-bond via 140 may be formed, for example, by: an opening for the via is formed using an etch that is selective to the material of interconnect 122 such that the bottom of via 140 is self-aligned with interconnect 122 after bottom f2f bonding. In this way, the bottom f2f post-bond via 140 may be electrically coupled to the interconnect 122. Although not specifically shown in the cross-section of fig. 8B, such bottom f2f post-bond vias 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110. The bottom f2f post-bond via 140, with the bottom f2f post-bond via 140 extending all the way through the IC structure 110 and electrically connected to the interconnect 122 of the IC structure 120, may be further electrically coupled to one or more components of the IC structure 120 coupled to the interconnect 122 to provide power, ground, and/or signals to these components of the IC structure 120.

Fig. 8C illustrates an embodiment in which the bottom f2f post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100, extends through all of the bottom IC structure of the microelectronic assembly 100 (e.g., IC structure 110), bonds material 130, and into the top IC structure of the microelectronic assembly 100 (e.g., IC structure 120), and stops before reaching the top of the microelectronic assembly 100. Thus, fig. 8C shows that bottom f2f post-bond via 140 may be such that it is a blind via that extends through the bottom IC structure and into the top IC structure (e.g., from IC structure 110 into IC structure 120). Although not specifically shown in the cross-section of fig. 8C, such bottom f2f post-bond vias 140 may be electrically coupled to one or more components of IC structure 110 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 8C, the post-bond bottom f2f via 140, which extends all the way through the IC structure 110 and forms a blind via in the IC structure 120 as shown in fig. 8C, may be further electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

Fig. 8D illustrates an embodiment in which the via 140 extends from the bottom of the microelectronic assembly 100 to the top of the microelectronic assembly 100 after the bottom f2f is bonded. In this manner, the bottom f2f post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the bottom f2f post-bonded vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 8D, the bottom f2f post-bond vias 140 in the microelectronic assembly 100 as TSVs may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110, and/or may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

In some embodiments, one characteristic feature that is unique to the bottom f2f post-bond via 140 extending from the bottom of the f2f bonded microelectronic assembly as shown in fig. 8A-8D may be that the cross-sectional trapezoidal shape of the bottom f2f post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 8A-8D, where the shorter side of the trapezoidal cross-section of the via 140 after bottom f2f bonding is closer to the top of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross-section of the front side interconnect 122 is closer to the top of the microelectronic assembly 100 than its longer side. In some embodiments, as shown in fig. 8A-8D, another characteristic feature that bottom f2f post-bond via 140, extending from the bottom of the f2f bonded microelectronic assembly, may be that the cross-sectional trapezoidal shape of bottom f2f post-bond via 140 is inverted relative to the trapezoidal shape of front side interconnect 112. This is illustrated in fig. 8A-8D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2f bonding is closer to the top of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the front side interconnect 112 is closer to the top of the microelectronic assembly 100 than the shorter side thereof. Although not specifically shown in fig. 8A-8D, if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of bottom f2f post-bond via 140 extending from the bottom of the f2f bonded microelectronic assembly, as shown in fig. 8A-8D, may be that the cross-sectional trapezoidal shape of bottom f2f post-bond via 140 is inverted relative to the trapezoidal shape of backside interconnect 122. This will be shown in fig. 8A-8D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2f bonding is closer to the top of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the backside interconnect 122 is closer to the top of the microelectronic assembly 100 than the shorter side thereof. Further, although not specifically shown in fig. 8A-8D, if IC structure 110 includes backside interconnect 112, then in some embodiments, a characteristic feature characteristic of bottom f2f post-bond via 140 extending from the bottom of the f2f bonded microelectronic assembly, as shown in fig. 8A-8D, may be that the cross-sectional trapezoidal shape of bottom f2f post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of backside interconnect 112. This will be shown in fig. 8A-8D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2f bonding is closer to the top of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the backside interconnect 112 is closer to the top of the microelectronic assembly 100 than its longer side.

Fig. 9A-9D illustrate cross-sectional side views of a microelectronic assembly 100, which is an f2b bonding assembly having a post-bonding via 140 formed from the bottom, in accordance with some embodiments. The microelectronic assembly 100 shown in fig. 9A-9D is similar to that shown in fig. 2, except that post-bond vias 140 are also included that are formed from the bottom of the microelectronic assembly 100. For the embodiment of fig. 9A-9D, post-bond via 140 may be referred to as "bottom f2b post-bond via 140".

For the f2b embodiment shown in FIG. 9, the "top" of the microelectronic assembly 100 is considered the front 134-2 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the back 134-1 of the IC structure 110. Fig. 9A-9D illustrate embodiments of the microelectronic assembly 100 having bottom f2b post-bond vias 140 of different depths.

Fig. 9A illustrates an embodiment in which the bottom f2b post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops before reaching the bonding material 130 (i.e., fig. 9A is similar to fig. 8A except that fig. 9A illustrates an f2b bonding configuration). Thus, fig. 9A shows that the bottom f2b post-bond via 140 may be such that it is a blind via in the bottom IC structure (e.g., in IC structure 110). Although not specifically shown in the cross-section of fig. 9A, the bottom f2b post-bond via 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 9A, in some embodiments, the bottom f2b post-bond via 140 in the IC structure 110 as a blind via (e.g., as shown in fig. 9A) may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120, which may be accomplished, for example, by electrically coupling the bottom f2b post-bond via 140 to one or more interconnects 112 and electrically coupling one or more of those interconnects 112 to one or more components of the IC structure 120.

Fig. 9B illustrates an embodiment in which the bottom f2B post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops when the interconnect 122 is encountered (i.e., fig. 9B is similar to fig. 8B except that fig. 9B illustrates an f2B bond configuration). Such bottom f2b post-bond via 140 may be formed, for example, by: an opening for the via is formed using an etch that is selective to the material of interconnect 122 such that the bottom of via 140 is self-aligned with interconnect 122 after bottom f2b is bonded. In this way, the bottom f2b post-bond via 140 may be electrically coupled to the interconnect 122. Although not specifically shown in the cross-section of fig. 9B, such bottom f2B post-bond vias 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110. The bottom f2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 120 coupled with the interconnect 122 by means of the bottom f2b post-bond via 140 extending all the way through the IC structure 110 and electrically connected with the interconnect 122 of the IC structure 120 to provide power, ground, and/or signals to these components of the IC structure 120.

Fig. 9C illustrates an embodiment in which the bottom f2b post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100, extends through all of the bottom IC structure of the microelectronic assembly 100 (e.g., IC structure 110), bonds material 130, and into the top IC structure of the microelectronic assembly 100 (e.g., IC structure 120), and stops before reaching the top of the microelectronic assembly 100 (i.e., fig. 9C is similar to fig. 8C except that fig. 9C illustrates an f2b bonding configuration). Thus, fig. 9C shows that bottom f2b post-bond via 140 may be such that it is a blind via that extends through the bottom IC structure and into the top IC structure (e.g., from IC structure 110 into IC structure 120). Although not specifically shown in the cross-section of fig. 9C, such bottom f2b post-bond vias 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 9C, the post-bond bottom f2b that extends all the way through the IC structure 110 and forms a blind via in the IC structure 120, as shown in fig. 9C, via 140 may be further electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

Fig. 9D illustrates an embodiment in which the via 140 extends from the bottom of the microelectronic assembly 100 all the way to the top of the microelectronic assembly 100 after the bottom f2b is bonded (i.e., fig. 9D is similar to fig. 8D except that fig. 9D illustrates the f2b bonding configuration). In this manner, the bottom f2b post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the bottom f2b post-bond vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 9D, the post-bond via 140, which is a TSV, bottom f2b in the microelectronic assembly 100 can be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110, and/or can be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

In some embodiments, one characteristic feature that is characteristic of the bottom f2b post-bond via 140 extending from the bottom of the f2 b-bonded microelectronic assembly as shown in fig. 9A-9D may be that the cross-sectional trapezoidal shape of the bottom f2b post-bond via 140 is inverted relative to the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 9A-9D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2b bonding is closer to the top of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the front side interconnect 122 is closer to the top of the microelectronic assembly 100 than the shorter side thereof. In some embodiments, another characteristic feature that is characteristic of the bottom f2b post-bond via 140 extending from the bottom of the f2 f-bonded microelectronic assembly as shown in fig. 9A-9D may be that the cross-sectional trapezoidal shape of the bottom f2b post-bond via 140 is also inverted relative to the trapezoidal shape of the front side interconnect 112. This is illustrated in fig. 9A-9D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2b bonding is closer to the top of the microelectronic assembly 100 than the longer side thereof, and the longer side of the trapezoidal cross section of the front side interconnect 112 is closer to the top of the microelectronic assembly 100 than the shorter side thereof. Although not specifically shown in fig. 9A-9D, if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of bottom f2b post-bond via 140 extending from the bottom of the f2 f-bonded microelectronic assembly, as shown in fig. 9A-9D, may be that the cross-sectional trapezoidal shape of bottom f2b post-bond via 140 is oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of backside interconnect 122. This will be shown in fig. 9A-9D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2b bonding is closer to the top of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the backside interconnect 122 is closer to the top of the microelectronic assembly 100 than its longer side. Further, although not specifically shown in fig. 9A-9D, if IC structure 110 includes backside interconnect 112, then in some embodiments, a characteristic feature that is characteristic of bottom f2b post-bond via 140 extending from the bottom of the f2 f-bonded microelectronic assembly, as shown in fig. 9A-9D, may be that the cross-sectional trapezoidal shape of bottom f2b post-bond via 140 is also oriented in the same manner as (i.e., not inverted from) the trapezoidal shape of backside interconnect 112. This will be shown in fig. 9A-9D, where the shorter side of the trapezoidal cross section of the via 140 after bottom f2b bonding is closer to the top of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the backside interconnect 112 is closer to the top of the microelectronic assembly 100 than its longer side.

Fig. 10A-10E illustrate cross-sectional side views of a microelectronic assembly 100, which is a b2b bonding assembly having a post-bonding via 140 formed from the bottom, according to some embodiments. The microelectronic assembly 100 shown in fig. 10A-10E is similar to that shown in fig. 3, except that post-bond vias 140 are also included that are formed from the bottom of the microelectronic assembly 100. For the embodiment of fig. 10A-10E, post-bond via 140 may be referred to as "bottom b2b post-bond via 140".

For the b2b embodiment shown in fig. 7, the "top" of the microelectronic assembly 100 is considered the front 134-2 of the IC structure 120, and the "bottom" of the microelectronic assembly 100 is considered the back 134-2 of the IC structure 110. Fig. 10A-10E illustrate embodiments of the microelectronic assembly 100 having bottom b2b post-bond vias 140 of different depths.

Fig. 10A illustrates an embodiment in which the via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 after bottom b2b bonding and stops before reaching the bonding material 130 (i.e., fig. 10A is similar to fig. 8A and 9A, except that fig. 10A illustrates a b2b bonding configuration). Thus, fig. 10A shows that the bottom b2b post-bond via 140 can be such that it is a blind via in the bottom IC structure (e.g., in IC structure 110). Although not specifically shown in the cross-section of fig. 10A, the bottom b2b post-bond via 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 10A, in some embodiments, the bottom b2b post-bond via 140 in the IC structure 110 as a blind via (e.g., as shown in fig. 10A) may be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120, which may be accomplished, for example, by electrically coupling the bottom b2b post-bond via 140 to one or more interconnects 112 and electrically coupling one or more of those interconnects 112 to one or more components of the IC structure 120.

Fig. 10B illustrates an embodiment in which the bottom B2B post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops when the backside interconnect 122 is encountered (i.e., fig. 10B is similar to fig. 10C except that the bond interface is in a different location and the interconnect 122 that the bottom B2B post-bond via 140 contacts is the backside interconnect). Such bottom b2b post-bond via 140 may be formed, for example, by: the openings for the vias are formed using an etch that is selective to the material of the backside interconnect 122 such that the bottom of the via 140 is self-aligned with the backside interconnect 122 after the bottom b2b is bonded. In this way, the bottom b2b post-bond via 140 may be electrically coupled to the backside interconnect 122. Although not specifically shown in the cross-section of fig. 10B, such bottom B2B post-bond vias 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110. The bottom b2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 120 coupled with the backside interconnect 122 by means of the bottom b2b post-bond via 140 extending all the way through the IC structure 110 and electrically connected with the backside interconnect 122 of the IC structure 120 to provide power, ground, and/or signals to these components of the IC structure 120.

Fig. 10C illustrates an embodiment in which the bottom b2b post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100 and stops when the front side interconnect 122 is encountered. Such bottom b2b post-bond via 140 may be formed, for example, by: the openings for the vias are formed using an etch that is selective to the material of the front side interconnect 122 such that the bottom of the via 140 is self-aligned with the front side interconnect 122 after the bottom b2b is bonded. In this way, the bottom b2b post-bond via 140 may be electrically coupled to the front side interconnect 122. Although not specifically shown in the cross-section of fig. 10C, such bottom b2b post-bond vias 140 may be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110. The bottom b2b post-bond via 140 may be further electrically coupled to one or more components of the IC structure 120 coupled with the front side interconnect 122 by means of the bottom b2b post-bond via 140 extending all the way through the IC structure 110 and electrically connected with the front side interconnect 122 of the IC structure 120 to provide power, ground, and/or signals to these components of the IC structure 120.

Fig. 10D illustrates an embodiment in which the bottom b2b post-bond via 140 extends from the bottom of the microelectronic assembly 100 toward the top of the microelectronic assembly 100, extends through all of the bottom IC structure of the microelectronic assembly 100 (e.g., IC structure 110), bonds material 130 and into the top IC structure of the microelectronic assembly 100 (e.g., IC structure 120), and stops before reaching the top of the microelectronic assembly 100 (i.e., fig. 10D is similar to fig. 8C and 9C, except that fig. 10D illustrates an f2b bonding configuration). Thus, fig. 10D shows that bottom b2b post-bond via 140 may be such that it is a blind via that extends through the bottom IC structure and into the top IC structure (e.g., from IC structure 110 into IC structure 120). Although not specifically shown in the cross-section of fig. 10D, such bottom b2b post-bond vias 140 may be electrically coupled to one or more components of IC structure 110 to provide power, ground, and/or signals to those components. Further, although not specifically shown in the cross-section of fig. 10D, the post-bond via 140, which extends all the way through the IC structure 110 and forms a blind via in the IC structure 120, as shown in fig. 10D, may be further electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

Fig. 10E illustrates an embodiment in which the via 140 extends from the bottom of the microelectronic assembly 100 all the way to the top of the microelectronic assembly 100 after bottom b2b bonding (i.e., fig. 10E is similar to fig. 8D and 9D, except that fig. 10E illustrates a b2b bonding configuration). In this manner, the bottom b2b post-bond via 140 is a TSV that extends between opposite sides of the microelectronic assembly 100. Thereafter, electrical connections to the bottom b2b post-bonded vias 140 can be made from one or both of the top and bottom of the microelectronic assembly 100. Although not specifically shown in the cross-section of fig. 10E, the post-bond via 140, which is a TSV, bottom b2b in the microelectronic assembly 100 can be electrically coupled to one or more components of the IC structure 110 to provide power, ground, and/or signals to those components of the IC structure 110, and/or can be electrically coupled to one or more components of the IC structure 120 to provide power, ground, and/or signals to those components of the IC structure 120.

In some embodiments, another characteristic feature that is characteristic of the bottom b2b post-bond via 140 extending from the bottom of the b2 b-bonded microelectronic assembly as shown in fig. 10A-10E may be that the cross-sectional trapezoidal shape of the bottom b2b post-bond via 140 is inverted relative to the trapezoidal shape of the front side interconnect 122. This is illustrated in fig. 10A-10E, where the bottom b2b has joined the trapezoidal cross-section of the via 140 with its shorter side closer to the top of the microelectronic assembly 100 than its longer side, and the front interconnect 122 with its longer side closer to the top of the microelectronic assembly 100 than its shorter side. In some embodiments, as shown in fig. 10A-10E, another characteristic feature that bottom b2b extending from the bottom of the f2f bonded microelectronic assembly, after bonding, of the via 140 may be that the cross-sectional trapezoidal shape of the via 140 after bonding of the bottom b2b is oriented in the same manner as the trapezoidal shape of the front side interconnect 112 (i.e., not inverted). This is illustrated in fig. 10A-10E, where the bottom b2b has joined the shorter side of the trapezoidal cross section of the via 140 closer to the top of the microelectronic assembly 100 than its longer side, and the shorter side of the trapezoidal cross section of the front side interconnect 112 closer to the top of the microelectronic assembly 100 than its longer side. Although not specifically shown in fig. 10A, 10C, 10D, and 10E (i.e., only in fig. 10B), if IC structure 120 includes backside interconnect 122, then in some embodiments, a characteristic feature characteristic of bottom B2B post-bond via 140 extending from the bottom of the f2f bonded microelectronic assembly, as shown in fig. 10A-10E, may be that the cross-sectional trapezoidal shape of bottom B2B post-bond via 140 is oriented in the same manner as the trapezoidal shape of backside interconnect 122 (i.e., not inverted). This will be shown in fig. 10A, 10C, 10D, and 10E, where the shorter side of the trapezoidal cross section of the via 140 is closer to the top of the microelectronic assembly 100 than the longer side thereof after the bottom b2b is bonded, and the shorter side of the trapezoidal cross section of the backside interconnect 122 is closer to the top of the microelectronic assembly 100 than the longer side thereof. Further, although not specifically shown in fig. 10A-10E, if IC structure 110 includes backside interconnect 112, then in some embodiments, a characteristic feature characteristic of bottom b2b post-bond via 140 extending from the bottom of the f2f bonded microelectronic assembly, as shown in fig. 10A-10E, may be that the cross-sectional trapezoidal shape of bottom b2b post-bond via 140 is inverted relative to the trapezoidal shape of backside interconnect 112. This will be shown in fig. 10A-10E, where the bottom b2b has joined the trapezoidal cross-section of the via 140 with its shorter side closer to the top of the microelectronic assembly 100 than its longer side, and the trapezoidal cross-section of the backside interconnect 112 with its longer side closer to the top of the microelectronic assembly 100 than its shorter side.

While fig. 10A-10E illustrate the bottom b2b post-bond via 140 for some specific examples of b2b bond configurations, the description provided herein of the bottom b2b post-bond via 140 is equally applicable to other embodiments of the b2b bond configuration of the microelectronic assembly 100, e.g., to any of those embodiments described with reference to fig. 3.

Although each of fig. 8-10 shows a single bottom post-bond via 140 extending from the bottom of the microelectronic assembly 100, in other embodiments, the microelectronic assembly 100 may include any number of two or more bottom post-bond vias 140, which may have the same or different depths. Further, various embodiments of the microelectronic assembly 100 as described herein can include any number and any combination of top and bottom

post-bond vias

140, 140 having any depth, depending on the design. For example, any of the embodiments of the microelectronic assembly 100 described with reference to fig. 8-10 may further include one or more top post-bond vias 140 extending from the top of the microelectronic assembly 100 according to any of the embodiments of the microelectronic assembly 100 described with reference to fig. 5-7. Further, while fig. 5-10 illustrate embodiments in which the post-bond via 140 extends through at most two IC structures bonded together (i.e., through a pair of IC structures 110 and 120), any of the embodiments described with reference to fig. 5-10 may be extended to a microelectronic assembly 100 that includes multiple pairs of such bonded together IC structures, wherein one or more post-bond vias 140, which may extend from the top, from the bottom, or from both the top and the bottom, may extend through three or more IC structures. Some non-limiting examples of such embodiments are shown in fig. 11A-11C.

Fig. 11A-11C illustrate cross-sectional side views of a microelectronic assembly 100 having post-bond vias 140 extending through pairs of bonded IC structures, in accordance with some embodiments.

As described above with reference to fig. 1-3, in some embodiments, the microelectronic assembly 100 can include three or more IC structures bonded together according to any of the bonding configurations described herein. Fig. 11A-11C illustrate some examples of such embodiments in which three pairs of

IC structures

110, 120 are bonded together (i.e., in which four IC structures are bonded together, forming three pairs). However, the description provided with respect to fig. 11A-11C is equally applicable to embodiments of the microelectronic assembly 100 in which only three IC structures are bonded together (e.g., such embodiments may be contemplated by eliminating the top or bottom IC structures in the example shown in fig. 11A-11C) or in which more than four IC structures are bonded together. Furthermore, while fig. 11A-11C illustrate embodiments in which the post-bond via 140 extends from the top of the microelectronic assembly 100, other embodiments of the microelectronic assembly 100 described with reference to fig. 11A-11C may include embodiments in which the post-bond via 140 extends from the bottom of the microelectronic assembly 100 instead of from the top, and any combination of two or more post-bond vias 140 extending from the top and/or from the bottom to different depths. The back 134-1 and front 134-2 sides of each of the IC structures shown in fig. 11A-11C are labeled according to the convention used in the previous figures.

Fig. 11A illustrates a cross-sectional side view of a microelectronic assembly 100 including two pairs of f2f bonded IC structures bonded together to form a total of three pairs of IC structures, and further including a post-bond via 140 formed from the top, in accordance with some embodiments. The first pair is formed by bonding the IC structures 110-1 and 120-1 with a bonding material/interface 130-1 in an f2f bonding configuration similar to that shown, for example, in fig. 1 (i.e., the IC structures 110-1 and 120-1 of fig. 11A are examples of the

IC structures

110 and 120 of fig. 1, and the bonding material 130-1 of fig. 11A is an example of the bonding material 130 of fig. 1). The second pair is formed by bonding the IC structures 110-2 and 120-2 with a bonding material/interface 130-2 also in an f2f bonding configuration similar to that shown, for example, in fig. 1 (i.e., the IC structures 110-2 and 120-2 of fig. 11A are other examples of the

IC structures

110 and 120 of fig. 1, and the bonding material 130-2 of fig. 11A is another example of the bonding material 130 of fig. 1). Further, as shown in fig. 11A, the first pair of IC structures 120-1 and the second pair of IC structures 110-2 may be bonded with a bonding material/interface 130-3 in a b2b bonding configuration (i.e., bonding material 130-3 of fig. 11A is one example of bonding material 130 of the b2b bonding configuration embodiment of fig. 3), thereby forming a third pair of bonded together IC structures. All embodiments of the f2f and b2b bonding arrangements described above are applicable to the corresponding pair of IC structures shown in fig. 11A and are therefore not repeated here for the sake of brevity. For example, although FIG. 11A shows the IC structure 110-2 as including the support structure 132 as part of its back side 134-1 bonded to the back side 134-1 of the IC structure 120-1, in other embodiments the support structure 132 may not be included in the IC structure 110-2, or it may be included in the IC structure 120-1.

Fig. 11B illustrates a cross-sectional side view of a microelectronic assembly 100 including two pairs of f2B bonded IC structures bonded together to form a total of three pairs of IC structures, and further including a post-bond via 140 formed from the top, in accordance with some embodiments. The first pair is formed by bonding the IC structures 110-1 and 120-1 with a bonding material/interface 130-1 in an f2B bonding configuration similar to that shown, for example, in fig. 2 (i.e., the IC structures 110-1 and 120-1 of fig. 11B are examples of the

IC structures

110 and 120 of fig. 2, and the bonding material 130-1 of fig. 11B is an example of the bonding material 130 of fig. 2). The second pair is formed by bonding the IC structures 110-2 and 120-2 with a bonding material/interface 130-2 also in an f2B bonding configuration similar to that shown, for example, in fig. 2 (i.e., the IC structures 110-2 and 120-2 of fig. 11B are other examples of the

IC structures

110 and 120 of fig. 2, and the bonding material 130-2 of fig. 11B is another example of the bonding material 130 of fig. 2). Further, as shown in FIG. 11B, the first pair of IC structures 120-1 and the second pair of IC structures 110-2 may also be bonded with a bonding material/interface 130-3 in an f2B bonding configuration (i.e., bonding material 130-3 of FIG. 11B is yet another example of bonding material 130 of the f2B bonding configuration embodiment of FIG. 2), thereby forming a third pair of bonded together IC structures. All embodiments of the f2B bonding arrangement described above are applicable to the corresponding pair of IC structures shown in fig. 11B and are therefore not repeated here for the sake of brevity.

Fig. 11C illustrates a cross-sectional side view of a microelectronic assembly 100 including two pairs b2b of bonded IC structures bonded together to form a total of three pairs of IC structures, and further including a post-bond via 140 formed from the top, in accordance with some embodiments. The first pair is formed by bonding the IC structures 110-1 and 120-1 with a bonding material/interface 130-1 in a b2b bonding configuration similar to that shown, for example, in fig. 3 (i.e., the IC structures 110-1 and 120-1 of fig. 11C are examples of the

IC structures

110 and 120 of fig. 3, and the bonding material 130-1 of fig. 11C is an example of the bonding material 130 of fig. 3). The second pair is formed by bonding the IC structures 110-2 and 120-2 with a bonding material/interface 130-2 also in a b2b bonding configuration similar to that shown, for example, in fig. 3 (i.e., the IC structures 110-2 and 120-2 of fig. 11C are other examples of the

IC structures

110 and 120 of fig. 3, and the bonding material 130-2 of fig. 11C is another example of the bonding material 130 of fig. 3). Further, as shown in fig. 11C, the first pair of IC structures 120-1 and the second pair of IC structures 110-2 may be bonded with a bonding material/interface 130-3 in an f2f bonding configuration (i.e., bonding material 130-3 of fig. 11C is one example of bonding material 130 of the f2f bonding configuration embodiment of fig. 1), thereby forming a third pair of bonded together IC structures. All embodiments of the f2f and b2b bonding arrangements described above are applicable to the corresponding pair of IC structures shown in fig. 11C and are therefore not repeated here for the sake of brevity.

Although the post-bond via 140 is shown in fig. 11A-11C as a TSV extending between the top and bottom of the microelectronic assembly 100, in other embodiments of fig. 11A-11C, the post-bond via 140 may be a blind via having a bottom that terminates on any material in any IC structure of the microelectronic assembly 100, as described with reference to fig. 5-10. Further, post-bond via 140 may be electrically coupled to any component of one or more of the IC structures shown in fig. 11A-11C. Moreover, other arrangements of multiple IC structures having one or more post-bond vias 140 than those shown in FIGS. 11A-11C are possible and are within the scope of the present disclosure.

Exemplary Package with microelectronic Assembly fabricated Using hybrid manufacturing

Any embodiment of one or more microelectronic assemblies 100 as described herein may be included in an IC package. Fig. 12A-12H illustrate some examples of such IC packages, which illustrate IC packages that may include one or more microelectronic assemblies 100 fabricated using hybrid fabrication according to some embodiments.

Fig. 12A illustrates an IC package 200 including a package substrate 202, a die 204-1, and a die 204-2, according to some embodiments.

The package substrate 202 may include an insulating material (e.g., a dielectric material formed in multiple layers, as is known in the art) and one or more conductive vias (e.g., including conductive traces and/or conductive vias, as shown) through the dielectric material. In some embodiments, the insulating material of the package substrate 202 may be a dielectric material, such as an organic dielectric material, a flame retardant 4-grade material (FR-4), a Bismaleimide Triazine (BT) resin, a polyimide material, a glass reinforced epoxy matrix material, or low-k and ultra-low-k dielectrics (e.g., carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, and organic polymer dielectrics). Specifically, when the package substrate 202 is formed using a standard Printed Circuit Board (PCB) process, the package substrate 202 may include FR-4, and the conductive vias in the package substrate 202 may be formed from patterned copper sheets separated by build-up layers of FR-4. The conductive vias in the package substrate 202 may be suitably adjacent to liner materials such as an adhesive liner and/or a barrier liner.

In some embodiments, the package substrate 202 may be a lower density medium and any of the die 204 may be a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms that indicate that conductive vias (e.g., including conductive lines and conductive vias) in a lower density medium are larger and/or have a larger pitch than conductive vias in a higher density medium. In some embodiments, the higher density medium may be fabricated using a modified semi-additive process or a semi-additive build-up process by means of advanced lithography (employing small vertical interconnect features formed by advanced laser or photolithographic processes), while the lower density medium may be a PCB fabricated using standard PCB processes (e.g., standard subtractive processes using etching chemistries to remove unwanted copper regions and employing rough vertical interconnect features formed by standard laser processes).

In some embodiments, die 204-1 may include any of the IC structures disclosed herein, and die 204-2 may include any of the other IC structures disclosed herein, such that the IC structure of die 204-1 is bonded to the IC structure of die 204-2 using the bonding material/interface 130 as described herein, shown in the illustration of fig. 12A, using hybrid bonding as described herein. For example, in some embodiments, die 204-1 may include IC structure 110 and die 204-2 may include IC structure 120, or vice versa,

IC structures

110 and 120 of these dies being bonded to form microelectronic assembly 100 according to any embodiment of the present disclosure. In other embodiments, any of the dies 204-1 and 204-2 may include a stack of two or more IC structures bonded together as described herein, the IC structures of the dies being bonded to form the microelectronic assembly 100 according to any embodiment of the present disclosure. For example, in some embodiments, die 204-1 may include a stack of IC structures 110-1 bonded to IC structure 120-1, while die 204-2 may include a stack of IC structures 110-2 bonded to IC structure 120-2, and IC structure 120-1 of the stack of die 204-1 may be bonded to IC structure 110-2 of the stack of die 204-2 using bonding material/interface 130 shown in FIG. 12A. For example, such dies 204-1 and 204-2 may include the IC structure of the microelectronic assembly 100 according to any of the embodiments of fig. 11A-11C. In general, any of the dies 204-1 and 204-2 can include any number of one or more IC structures bonded with other IC structures within the same die or with IC structures of other dies to form the microelectronic assembly 100 according to any of the hybrid bonding embodiments described herein. An exemplary structure that may be included in die 204 disclosed herein is discussed below with reference to fig. 14.

In various embodiments of the IC package 200, the different die 204 (as shown in any of fig. 12A-12H) may include any suitable circuitry. For example, in some embodiments, die 204-1 may be an active or passive die, and die 204-2 may include input/output circuitry, high bandwidth memory, and/or Enhanced Dynamic Random Access Memory (EDRAM). Since the dies 204-1 and 204-2 include the IC structures 110 and/or 120 described herein, the description of the circuits and devices that the

IC structures

110, 120 provided above may include or be part of applies to the dies 204-1 and 204-2. For example, in some embodiments, die 204-1 may include power delivery circuitry and die 204-2 may include a memory device, e.g., a high bandwidth memory device, or in other embodiments, die 204-1 may include input/output circuitry and die 204-2 may include field programmable gate array logic. In some embodiments, any of the dies 204 may include one or more device layers including transistors (e.g., as described below with reference to fig. 14).

In some embodiments, one of the dies 204-1 and 204-2 may have a smaller footprint than the other, e.g., as shown in the example of fig. 12A, die 204-2 is narrower than die 204-1. For example, in some embodiments, the width of die 204-1 may be greater than the width of die 204-2 by distance 206. In some embodiments, the distance 206 may be between about 0.5 millimeters and 5 millimeters (e.g., between about 0.75 millimeters and 2 millimeters, or about 1 millimeter). Although die 204-2 is shown as being aligned on the right side with die 204-1, as

IC structures

110 and 120 are shown as being aligned in the various figures of fig. 1-11, such alignment is not necessary in the various embodiments of IC package 200 and in the various embodiments of microelectronic assembly 100 described herein.

As shown in fig. 12A, the package substrate 202 may be coupled to the die 204-1 by a die-to-package substrate (DTPS) interconnect 210. Specifically, the top surface of the package substrate 202 may include a set of conductive contacts 212, and the bottom surface of the die 204-1 may include a set of conductive contacts 214; the conductive contacts 214 at the bottom surface of the die 204-1 may be electrically or mechanically coupled to the conductive contacts 212 at the top surface of the package substrate 202 through the DTPS interconnect 210. For example, any of the conductive contacts disclosed herein (e.g.,

conductive contacts

212, 214, 222, 224, 232, 234, etc.) may include bond pads, posts, or any other suitable conductive contact.

In the embodiment of fig. 12A, die 204-1 is not disposed in a recess in package substrate 202, but in other embodiments of IC package 200, the top surface of package substrate 202 may include a recess 208 in which die 204-1 is at least partially disposed, and conductive contacts 212 to which die 204-1 is coupled may be located at the bottom of recess 208, as shown in fig. 12B. For example, in some embodiments, the recess 208 may be drilled down to a planar metal stop by laser drilling in the package substrate 202 (not shown); once the metal stop is reached, it may be removed to expose the conductive contact 212 at the bottom of the recess 208. In some embodiments, the recess 208 may be formed by mechanical drilling. In some embodiments, the depth 216 of the recess 208 may be between about 10 microns and 200 microns (e.g., between about 10 microns and 30 microns, between about 30 microns and 100 microns, between about 60 microns and 80 microns, or about 75 microns). In some embodiments, the depth 216 may be equal to a particular number of layers of dielectric material in the package substrate 202. For example, the depth 216 may be approximately equal to between one and five layers of dielectric material (e.g., two or three layers of dielectric material) in the package substrate 202. In some embodiments, depth 216 may be equal to a thickness of a solder resist material (not shown) on a top surface of package substrate 202. In some embodiments, the top surface of die 204-1 may extend higher than the top surface of package substrate 202, as shown in fig. 12B. In other embodiments, the top surface of die 204-1 may be substantially coplanar with the top surface of package substrate 202, or may be recessed below the top surface of package substrate 202.

The remainder of the description provided in connection with fig. 12A applies to and may be combined with the embodiment of fig. 12B (or vice versa) and is therefore not repeated for the sake of brevity.

The DTPS interconnect 210 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 210 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the DTPS interconnects 210). The DTPS interconnect 210, including solder, may comprise any suitable solder material, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. In some embodiments, the set of DTPS interconnects 210 may comprise an anisotropically conductive material, such as an anisotropically conductive film or an anisotropically conductive paste. The anisotropic conductive material may comprise a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include tiny conductive particles embedded in a glue or a thermosetting adhesive film (e.g., a thermosetting biphenyl epoxy or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and/or one or more metals (e.g., nickel or gold). For example, the conductive particles may comprise nickel coated gold or silver coated copper, which in turn will be coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is sufficiently compressed (e.g., by conductive contacts on both sides of the anisotropic conductive material), the conductive materials in the vicinity of the compressed region may contact each other, thereby forming a conductive path from one side of the film to the other side in the compressed region.

Fig. 12C illustrates that in some embodiments, the IC package 200 may further include a circuit board 218. The package substrate 202 may be coupled to the circuit board 218 by second level interconnects 220 located at a bottom surface of the package substrate 202. Specifically, the package substrate 202 may include conductive contacts 222 at a bottom surface thereof, and the circuit board 218 may include conductive contacts 224 at a top surface thereof. The second level interconnect 220 may electrically and mechanically couple the conductive contact 224 and the conductive contact 222. The second level interconnect 220 shown in fig. 12C is a solder ball (e.g., for a ball grid array arrangement), but any suitable second level interconnect 220 (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement) may be used in other embodiments of the IC package 200. The circuit board 218 may be, for example, a motherboard, and may have other components (not shown) attached thereto. The circuit board 218 may include conductive vias and other conductive contacts (not shown) for routing power, ground, and signals through the circuit board 218, as is known in the art. In some embodiments, the second level interconnect 220 may not couple the package substrate 202 to the circuit board 218, but may instead couple the package substrate 202 to another IC package, interposer, or any other suitable component.

In some embodiments, one or more of the conductive vias in the package substrate 202 may extend between one or more conductive contacts 212 at the top surface of the package substrate 202 and one or more conductive contacts 222 at the bottom surface of the package substrate 202, as shown in fig. 12C. In some embodiments, one or more of the conductive vias in the package substrate 202 may extend between one or more conductive contacts 212 at the bottom of the recess 208 and one or more conductive contacts 222 at the bottom surface of the package substrate 202 as shown in fig. 12B. In some embodiments, one or more of the conductive vias in the package substrate 202 may extend between different conductive contacts 212 located at the top surface of the package substrate 202. In some embodiments, one or more of the conductive vias in the package substrate 202 may extend between different conductive contacts 222 at the bottom surface of the package substrate 202. The remainder of the description provided in connection with fig. 12A and 12B applies to and may be combined with the embodiment of fig. 12C (or vice versa) and is therefore not repeated for the sake of brevity.

In some embodiments, the die 204-1 of the IC package 200 described herein may be a single-sided die (in the sense that the die 204-1 has conductive contacts 214 on only a single surface), for example, as shown in fig. 12A-12C. In other embodiments, die 204-1 of IC package 200 described herein may be a dual-sided (or "multi-level" or "omni-directional") die (in the sense that die 204-1 has conductive contacts 214 on one surface and other conductive contacts on the opposite surface). An example of such an implementation is shown in fig. 12D.

Fig. 12D illustrates that in some embodiments, IC package 200 may also include die 204-3. In some embodiments, die 204-3 may be electrically and mechanically coupled to die 204-1 through a die-to-die (DTD) interconnect 230. Specifically, the top surface of die 204-1 may include a set of conductive contacts 232 and the bottom surface of die 204-3 may include a set of conductive contacts 234. One or more of the conductive contacts 234 at the bottom surface of die 204-3 may be electrically and mechanically coupled to some of the conductive contacts 232 at the top surface of die 204-1 through DTD interconnect 230. Fig. 12D illustrates that in some embodiments, the pitch of DTD interconnect 230 may be different from the pitch of DTPS interconnect 210 (in other embodiments, these pitches may be substantially the same). In some embodiments, die 204-3 of IC package 200 may be a single sided die (in the sense that die 204-3 has conductive contacts 234 on only a single surface), as shown in fig. 12D. In other embodiments (not specifically shown), die 204-3 of IC package 200 described herein may be a dual sided die (the latter configured to couple die 204-3 to other components in the sense that die 204-3 has conductive contacts 234 on one surface and other conductive contacts on the opposite surface). Although not specifically shown in fig. 12D, in some embodiments, die 204-3 may be electrically and mechanically coupled to package substrate 202 through DTPS interconnect in a manner similar to that of die 204-1 coupled to package substrate 202 through DTPS interconnect 210.

The DTD interconnect 230 disclosed herein may take any suitable form. DTD interconnect 230 may have finer pitch than DTPS interconnect 210 in the IC package. In some embodiments, the die 204 on both sides of a set of DTD interconnects 230 may be unpackaged die, and/or the DTD interconnects 230 may include small conductive bumps or pillars (e.g., copper bumps or pillars) attached to respective

conductive contacts

232, 234 by solder. DTD interconnect 230 may have a pitch that is too fine to be directly coupled to package substrate 202 (too fine to act as DTPS interconnect 210). In some embodiments, the set of DTD interconnects 230 may comprise solder. The DTD interconnect 230 comprising solder may comprise any suitable solder material, such as any of the materials discussed above. In some embodiments, the set of DTD interconnects 230 may comprise an anisotropically conductive material, such as any of the materials discussed above. In some embodiments, DTD interconnect 230 may be used as a data transfer channel, while DTPS interconnect 210 may be used for power and ground lines, among others.

In some embodiments, some or all of the DTD interconnects 230 in the IC package 200 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the

conductive contacts

232, 234 on both sides of the DTD interconnect 230 may be bonded together (e.g., at high pressure and/or high temperature) without the use of intervening solder or anisotropic conductive material. In some embodiments, thin solder caps may be used in metal-to-metal interconnects to provide planarity, and the solder may become intermetallic during processing. In some metal-to-metal interconnects utilizing hybrid bonding, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, or organic layers) may be present between the metals bonded together (e.g., between the copper pads or pillars that provide the associated conductive contacts 232, 234). In some embodiments, one side of the DTD interconnect 230 may include metal pillars (e.g., copper pillars) and the other side of the DTD interconnect may include metal contacts (e.g., copper contacts) recessed into the dielectric. In some embodiments, the metal-to-metal interconnect (e.g., copper-to-copper interconnect) may include a noble metal (e.g., gold) or a metal whose oxide is conductive (e.g., silver). In some embodiments, the metal-to-metal interconnect may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided through such interconnects may be limited to mitigate mechanical failure.

In some embodiments, some or all of the DTD interconnects 230 in the IC package 200 may be solder interconnects that include solder having a higher melting point than solder included in some or all of the DTPS interconnects 210. For example, in forming DTD interconnect 230 in IC package 200 prior to forming DTPS interconnect 210, solder-based DTD interconnect 230 may use a higher temperature solder (e.g., a melting point greater than 200 degrees celsius), while DTPS interconnect 210 may use a lower temperature solder (e.g., a melting point less than 200 degrees celsius). In some embodiments, the higher temperature solder may include: tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (eutectic tin bismuth) or tin, silver and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium.

In the IC package 200 disclosed herein, some or all of the DTPS interconnects 210 may have a larger pitch than some or all of the DTD interconnects 230. DTD interconnects 230 may have a smaller pitch than DTPS interconnects 210 because of a greater material similarity in different die 204 located on both sides of a set of DTD interconnects 230 than between die 204 and package substrate 202 located on both sides of a set of DTPS interconnects 210. Specifically, the material composition differences of die 204 and package substrate 202 may cause differential expansion and contraction of die 204 and package substrate 202 due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by such differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTD interconnect 210 may be formed larger and spaced farther apart than the DTD interconnect 230, which may be subject to less thermal stress due to the higher material similarity in the die 204 pairs on both sides of the DTD interconnect. In some embodiments, the DTPS interconnect 210 disclosed herein may have a pitch of between about 80 microns and 300 microns, while the DTD interconnect 230 disclosed herein may have a pitch of between about 7 microns and 100 microns.

The remainder of the description provided in connection with fig. 12A-12C applies to and may be combined with the embodiment of fig. 12D (or vice versa) and is therefore not repeated for the sake of brevity.

Fig. 12E illustrates that in some embodiments, the IC package 200 may further include a die 204-4 bonded to the die 204-3 using hybrid bonding as described herein. In some embodiments, die 204-3 may include any of the IC structures disclosed herein, and die 204-4 may include any of the other IC structures disclosed herein, such that the IC structure of die 204-3 is bonded to the IC structure of die 204-4 using hybrid bonding as described herein using bonding material/interface 130-2 as described herein, shown in the illustration of fig. 12E. For example, in some embodiments, die 204-3 may include IC structure 110 and die 204-4 may include IC structure 120, or vice versa, with

IC structures

110 and 120 of these dies being bonded according to any embodiment of the present disclosure to form microelectronic assembly 100-2. In other embodiments, any of the dies 204-3 and 204-4 may include a stack of two or more IC structures bonded together as described herein, the IC structures of the dies being bonded according to any embodiment of the present disclosure to form the microelectronic assembly 100-2. For example, in some embodiments, die 204-3 may include a stack of IC structures 110-1 bonded to IC structure 120-1, while die 204-4 may include a stack of IC structures 110-2 bonded to IC structure 120-2, and IC structure 120-1 of the stack of die 204-3 may be bonded to IC structure 110-2 of the stack of die 204-4 using bonding material/interface 130-2 shown in FIG. 12E. For example, such dies 204-3 and 204-4 may include the IC structure of the microelectronic assembly 100 according to any of the embodiments of fig. 11A-11C. In general, any of the dies 204-3 and 204-4 can include any number of one or more IC structures that are bonded to other IC structures within the same die or to IC structures of other dies, thereby forming the microelectronic assembly 100-2 in accordance with any of the hybrid bonding embodiments described herein. The microelectronic assembly 100 and bonding material 130 shown in fig. 12A are re-labeled as microelectronic assembly 100-1 and bonding material 130-1, respectively, in fig. 12E, to distinguish between different instances of the microelectronic assembly 100 and bonding material 130 shown in fig. 12E.

In some embodiments, one of the dies 204-3 and 204-4 may have a smaller footprint than the other, e.g., die 204-3 is narrower than die 204-4 as shown in the example of fig. 12E. For example, in some embodiments, the width of die 204-4 may be greater than the width of die 204-3 by a distance that may be between about 0.5 millimeters and 5 millimeters (e.g., between about 0.75 millimeters and 2 millimeters, or about 1 millimeter). Although die 204-4 is shown as being aligned on the right side with die 204-3, such alignment is not necessary in the various embodiments of IC package 200 described herein. The remainder of the description provided in connection with fig. 12A-12D applies to and may be combined with the embodiment of fig. 12E (or vice versa) and is therefore not repeated for the sake of brevity.

Fig. 12F illustrates that in some embodiments, IC package 200 may also include die 204-5. In some embodiments, die 204-5 may be electrically and mechanically coupled to die 204-2 through DTD interconnect 240 similar to DTD interconnect 230 described above. Specifically, the top surface of die 204-2 may include a set of conductive contacts 242 and the bottom surface of die 204-5 may include a set of conductive contacts 244. One or more of the conductive contacts 244 at the bottom surface of die 204-5 may be electrically and mechanically coupled to some of the conductive contacts 242 at the top surface of die 204-2 through DTD interconnect 240. Fig. 12F illustrates that in some embodiments, the pitch of DTD interconnect 240 may be different from the pitch of DTPS interconnect 210 (in other embodiments, these pitches may be substantially the same). In some embodiments, die 204-5 of IC package 200 may be a single sided die (in the sense that die 204-5 has conductive contacts 244 on only a single surface), as shown in fig. 12F. In other embodiments (not specifically shown), die 204-5 of IC package 200 described herein may be a dual sided die (the latter configured to couple die 204-5 to other components in the sense that die 204-5 has conductive contacts 244 on one surface and other conductive contacts on the opposite surface). Although not specifically shown in fig. 12F, in some embodiments, die 204-5 may be electrically and mechanically coupled to package substrate 202 through DTPS interconnect in a manner similar to that of die 204-1 coupled to package substrate 202 through DTPS interconnect 210. The remainder of the description provided in connection with fig. 12A-12E applies to and may be combined with the embodiment of fig. 12F (or vice versa) and is therefore not repeated for the sake of brevity.

Fig. 12G illustrates an embodiment of an IC package 200 that includes die 204-3 and 204-4 shown in fig. 12E and die 204-5 shown in fig. 12F. Fig. 12G further illustrates post-bond vias 140-1 provided in the microelectronic assembly 100-1 and post-bond vias 140-2 provided in the microelectronic assembly 100-2. The particular number and particular arrangement of die 204 and post-bond vias 140 is also shown in fig. 12G purely for illustrative purposes, and in other embodiments, other arrangements of die 204 and post-bond vias 140 are possible and are within the scope of the present disclosure. Any of the post-bond vias 140 shown in fig. 12G may be implemented in accordance with any of the embodiments of post-bond vias 140 described herein, e.g., in accordance with any of the embodiments of fig. 5-11.

Fig. 12G is intended to illustrate two features that may be implemented in various embodiments of IC package 200.

One feature is that in general, any post-bond vias 140 in one or more of the microelectronic assemblies 100 included in the IC package 200 may be, but need not be, coupled to conductive contacts coupling the die to other components via, for example, DTD interconnects or DTPS interconnects. For example, fig. 12G illustrates that at least some of the post-bond vias 140-1 can be coupled to one or more of the conductive contacts 214 located at the bottom of the microelectronic assembly 100-1 and one or more of the conductive contacts 242 located at the top of the microelectronic assembly 100-1. Although not specifically shown, in other embodiments of fig. 12G, at least some of the post-bond vias 140-1 may not be coupled to the conductive contacts 214 and/or the conductive contacts 242. Fig. 12G further illustrates that at least some of the post-bond vias 140-2 may not be coupled to any of the conductive contacts. Although not specifically shown, in other embodiments of fig. 12G, at least some of the post-bond vias 140-2 may be coupled to one or more of the conductive contacts 234.

Another feature is that in general, the pitch of the various interconnects between different dies 204 of the IC package 200 may be any suitable pitch, and in some embodiments, some or all of the pitches may be different, or some or all of the pitches may be the same. For example, in various embodiments, the pitch of post-bond vias 140-1 may be: 1) different or the same pitch as DTPS interconnect 210, and/or 2) different or the same pitch as DTD interconnects 230 and/or 240, and/or 3) different or the same pitch as post-bond via 140-2. In another example, in various embodiments, the pitch of post-bond vias 140-2 may be: 1) different or the same pitch as DTPS interconnect 210, and/or 2) different or the same pitch as DTD interconnects 230 and/or 240, and/or 3) different or the same pitch as post-bond via 140-1. In yet another embodiment, the pitch of the DTPS interconnect 210 may be: 1) different or the same pitch as post-bond via 140-1, and/or 2) different or the same pitch as DTD interconnect 230 and/or 240, and/or 3) different or the same pitch as post-bond via 140-2. Although not specifically shown in fig. 12, in various other embodiments of IC package 200, any of die 204 may be a mixed-pitch die (in the sense that any of die 204 may have multiple sets of conductive contacts with different pitches and/or multiple sets of post-bond vias 140 with different pitches). The remainder of the description provided in connection with fig. 12A-12F applies to and may be combined with the embodiment of fig. 12G (or vice versa) and is therefore not repeated for the sake of brevity.

Fig. 12H illustrates an embodiment of an IC package 200, which may further include one or more of a molding material 250, a Thermal Interface Material (TIM) 252, and a heat spreader 254. Although the molding material 250, TIM 252, and heat spreader 254 are shown for the example of IC package 200 shown in fig. 12D (where not all of the reference numerals shown in fig. 12D are shown in fig. 12H to avoid cluttering the drawing), one or more of the molding material 250, TIM 252, and heat spreader 254 may be used in any other embodiment of IC package 200 described herein.

The molding material 250 may extend around one or more die 204 on the package substrate 202. In some embodiments, the molding material 250 may extend over one or more of the die 204 on the package substrate 202. In some embodiments, the molding material 250 may extend around the associated DTPS interconnects 210 between one or more of the dies 204 and the package substrate 202. In such embodiments, the molding material 250 may act as an underfill material. In some embodiments, the molding material 250 may extend around the associated DTD interconnects 230 between different ones of the dies 204. In such embodiments, the molding material 250 may act as an underfill material. The molding material 250 may include a variety of different molding materials (e.g., an underfill material and a different overmold material). The molding material 250 may be an insulating material, such as a suitable epoxy material. In some embodiments, the molding material 250 may include an underfill material as an epoxy flux that aids in soldering the die 204-1 to the package substrate 202 when forming the DTPS interconnect 210, and later polymerizes and encapsulates the DTPS interconnect 210. The molding material 250 may be selected to have a Coefficient of Thermal Expansion (CTE) that may alleviate or minimize stress between the die 204 and the package substrate 202 caused by non-uniform thermal expansion in the IC package 200. In some embodiments, the value of the CTE of the molding material 250 may be between the CTE of the package substrate 202 (e.g., the CTE of the dielectric material of the package substrate 202) and the CTE of the die 204.

The TIM 252 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. TIM 252 may be a thermal interface material paste or a thermally conductive epoxy (which may be fluid when applied and harden when cured, as is known in the art). The TIM 252 may provide a path for heat generated by the die 204 to flow easily to the heat spreader 254 where the heat may be spread and/or dissipated. Some embodiments of the IC package 200 of fig. 12H may include sputtered backside metallization (not shown) across the molding material 250 and the die 204. For such embodiments, a TIM 252 (e.g., solder TIM) may be disposed on the backside metallization.

The heat spreader 254 may be used to dissipate heat from the die 204 (e.g., so that the heat may be more easily dissipated by a heat sink or other thermal management device). The heat spreader 254 may comprise any suitable thermally conductive material (e.g., metal, suitable ceramic, etc.), and may comprise any suitable features (e.g., fins). In some embodiments, the heat spreader 254 may be an integrated heat spreader.

The remainder of the description provided in connection with fig. 12A-12G applies to and may be combined with the embodiment of fig. 12H (or vice versa) and is therefore not repeated for the sake of brevity.

In some embodiments of fig. 12, die 204-1 may provide high density interconnect routing in a localized area of IC package 200. In some embodiments, the presence of die 204-1 may support direct chip attachment of fine-pitch semiconductor die (e.g., die 204-2 and 204-3) that cannot be directly fully attached to package substrate 202. Specifically, as described above, die 204-1 may support trace widths and spacing that may not be implemented in package substrate 202. The popularity of wearable and mobile electronic devices and internet of things (loT) applications has driven a decline in electronic system size, but the limitations of PCB manufacturing processes and the mechanical consequences of thermal expansion during use suggest that chips with fine interconnect pitches cannot be mounted directly to PCBs. Various embodiments of the IC package 200 disclosed herein may be capable of supporting chips with high density interconnects as well as chips with low density interconnects without sacrificing performance or manufacturability.

In various embodiments of fig. 12, any of die 204-3 and 204-5 may be single sided single pitch die; in other embodiments, any of the dies 204-3 and 204-5 may be dual sided dies, and additional components may be provided on the top surfaces of the dies 204-3 and 204-5. Additional components, such as surface mount resistors, capacitors, and/or inductors, may be disposed on the top or bottom surface of the package substrate 202 or embedded in the package substrate 202. More generally, any suitable number of dies 204 in IC package 200 may be dual-sided dies 204.

The elements of IC package 200 may have any suitable physical dimensions. Only a subset of the figures are labeled with reference numerals representing the form factors, but this is for clarity of illustration only, and any of the IC packages 200 disclosed herein may include components having the form factors discussed herein. For example, in some embodiments, the thickness 226 (labeled in fig. 12H) of the package substrate 202 may be between about 0.1 mm and 1.4 mm (e.g., between about 0.1 mm and 0.35 mm, between about 0.25 mm and 0.8 mm, or about 1 mm).

Exemplary apparatus

Microelectronic assemblies manufactured according to hybrid manufacturing and IC packages including such microelectronic assemblies as disclosed herein may be included in any suitable electronic device. Fig. 13-16 illustrate various examples of devices that may include one or more of the microelectronic assemblies and IC packages disclosed herein.

Fig. 13A and 13B are top views of a wafer and die, respectively, that may be included in one or more of the microelectronic assemblies 100 fabricated using hybrid fabrication in accordance with any of the embodiments disclosed herein. In some embodiments, die 1502 may be included in an IC package (e.g., IC package 200 shown in fig. 12) and/or an IC device (e.g., IC device 1600 shown in fig. 14) in accordance with any of the embodiments disclosed herein. For example, any of the die 1502 may function as the die 204 shown in fig. 12 and/or any of the die 1502 may function as the IC device 1600 shown in fig. 14. Wafer 1500 may be comprised of semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of the dice 1502 may be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC including an IC structure to be included in a microelectronic assembly fabricated using hybrid fabrication as described herein, e.g., an IC including IC structures 110 and/or 120 as described herein). After fabrication of the semiconductor product is completed (e.g., after one or more of the IC structures (e.g., ICs including IC structures 110 and/or 120 as described herein) to be included in the microelectronic assemblies fabricated using hybrid fabrication as described herein are fabricated), wafer 1500 may undergo a singulation process in which each of die 1502 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices including one or more IC structures (e.g., ICs including IC structures 110 and/or 120 disclosed herein) to be included in microelectronic assemblies fabricated using hybrid fabrication as described herein may take the form of wafer 1500 (e.g., unsingulated) or die 1502 (e.g., singulated). Die 1502 may include one or more transistors (e.g., some of transistors 1640 of fig. 14 discussed below), support circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other IC components. Die 1502 may include supporting circuitry to route electrical signals to various memory cells, transistors, capacitors, and any other IC components. In some embodiments, wafer 1500 or die 1502 may implement or include a memory device (e.g., a Static Random Access Memory (SRAM) device), a logic device (e.g., AND, OR, NAND or NOR gate), or any other suitable circuit element. Multiple individual ones of these devices may be combined on a single die 1502. For example, a memory array formed of multiple memory devices may be formed on the same die 1502 as a processing apparatus (e.g., processing apparatus 1802 of fig. 16) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

Fig. 14 is a cross-sectional side view of an IC device 1600 that may be included in any of the microelectronic assemblies 100 disclosed herein (e.g., in any of the IC structures 110 and/or 120). One or more of the IC devices 1600 may be included in one or more dies 1502 (fig. 13). One or more of the IC devices 1600 may be included in one or more of the IC structures 110 and/or 120 as described herein, for example, in the IC package 200 (fig. 12). One or more of the IC devices 1600 may be included in one or more dies 1502 (fig. 13). IC device 1600 may be formed on a die substrate 1602 (e.g., wafer 1500 of fig. 13) and may be included in a die (e.g., die 1502 of fig. 13). The die substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). For example, die substrate 1602 may include a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructure. In some embodiments, die substrate 1602 may be formed using alternative materials (which may or may not be bonded to silicon) including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as group II-VI, group III-V, or group IV may also be used to form die substrate 1602. Although a few examples of materials from which die substrate 1602 may be formed are described herein, any material may be used that may serve as a base for IC device 1600. The die substrate 1602 may be part of an singulated die (e.g., die 1502 of fig. 13) or a wafer (e.g., wafer 1500 of fig. 13).

IC device 1600 may include one or more device layers 1604 disposed on die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) formed on the die substrate 1602. Device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow between S/D regions 1620 in transistor 1640, and one or more S/D contacts 1624 to route electrical signals to/from S/D regions 1620. The transistor 1640 may include additional features not shown for clarity, such as device isolation regions and gate contacts, etc. The transistor 1640 is not limited to the type and configuration depicted in fig. 14, and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include fin-based field effect transistors (FinFET transistors), such as double gate transistors or tri-gate transistors, as well as wrap-around or fully-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor 1640 may include a gate 1622 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may comprise a layer or stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be comprised of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

In some embodiments, the gate electrode may be comprised of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1602 when viewed in cross section of the transistor 1640 in the source-channel-drain direction. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may be comprised of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

S/D regions 1620 may be formed within die substrate 1602 adjacent to gates 1622 of each transistor 1640. For example, S/D regions 1620 may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1602 to form the S/D regions 1620. The ion implantation process may be followed by an annealing process that activates the dopants and causes them to diffuse further into the die substrate 1602. In the latter process, die substrate 1602 may first be etched to form recesses in the locations of S/D regions 1620. Thereafter, an epitaxial deposition process may be performed to fill the recesses with the material used to fabricate S/D regions 1620. In some embodiments, S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorous. In some embodiments, one or more alternative semiconductor materials, such as germanium or a group III-V material or alloy, may be used to form S/D regions 1620. In other embodiments, one or more layers of metal and/or metal alloys may be used to form S/D regions 1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from devices (e.g., transistor 1640) of device layer 1604 through one or more interconnect layers (shown as interconnect layers 1606-1610 in fig. 14) disposed on device layer 1604. For example, conductive features of device layer 1604 (e.g., gate 1622 and S/D contacts 1624) may be electrically coupled with interconnect structures 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

Interconnect structure 1628 may be disposed within interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structure 1628 depicted in fig. 14. Although a particular number of interconnect layers 1606-1610 are shown in fig. 14, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structure 1628 may include wires (or traces) 1628a and/or vias 1628b filled with a conductive material (e.g., metal). Line 1628a may be arranged to route electrical signals in a direction substantially parallel to a plane of die substrate 1602 on which device layer 1604 is formed. For example, line 1628a may route electrical signals in a direction into and out of the page from the perspective of fig. 14. Vias 1628b may be arranged to route electrical signals in a direction substantially perpendicular to the plane of die substrate 1602 on which device layer 1604 is formed. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606-1610 together.

Interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628, as shown in fig. 14. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of dielectric material 1626 may be the same between different interconnect layers 1606-1610.

First interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly on device layer 1604. In some embodiments, first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. Line 1628a of first interconnect layer 1606 may be coupled with a contact (e.g., S/D contact 1624) of device layer 1604.

The second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b to couple the line 1628a of the second interconnect layer 1608 with the line 1628a of the first interconnect layer 1606. Although the lines 1628a and vias 1628b are structurally delineated with lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the lines 1628a and vias 1628b may have structural and/or material continuity (e.g., be filled simultaneously during a dual damascene process).

Third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed sequentially over second interconnect layer 1608 according to similar techniques and configurations described in connection with second interconnect layer 1608 or first interconnect layer 1606. In some embodiments, the "higher" the interconnect layer is in metallization stack 1619 in IC device 1600 (i.e., the farther from device layer 1604), the thicker may be.

IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. In fig. 14, the conductive contact 1636 is shown as taking the form of a bond pad. Conductive contact 1636 may be electrically coupled with interconnect structure 1628 and configured to route electrical signals of transistor(s) 1640 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 1636 to mechanically and/or electrically couple a chip including IC device 1600 with another component (e.g., a circuit board). IC device 1600 may include additional or alternative structures to route electrical signals from interconnect layers 1606-1610; for example, the conductive contacts 1636 may include other similar features (e.g., posts) that route electrical signals to external components. Conductive contact 1636 may optionally act as

conductive contact

122 or 124.

In some embodiments where IC device 1600 is a dual-sided die (e.g., similar to die 114-1), IC device 1600 may include another metallization stack (not shown) located on an opposite side of device layer(s) 1604. The metallization stack may include a plurality of interconnect layers as discussed above with reference to interconnect layers 1606-1610 to provide conductive vias (e.g., including conductive lines and vias) between device layer(s) 1604 and additional conductive contacts (not shown) located on a side of IC device 1600 opposite conductive contacts 1636. These additional conductive contacts may optionally act as

conductive contacts

122 or 124.

In other embodiments where IC device 1600 is a dual-sided die (e.g., similar to die 114-1), IC device 1600 may include one or more TSVs through die substrate 1602; these TSVs may be in contact with device layer(s) 1604 and may provide a conductive path between device layer(s) 1604 and additional conductive contacts (not shown) located on a side of IC device 1600 opposite conductive contacts 1636. These additional conductive contacts may optionally act as

conductive contacts

122 or 124.

Fig. 15 is a cross-sectional side view of an IC device assembly 1700 that includes components that may have one or more microelectronic assemblies fabricated using hybrid fabrication in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes several components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposite second side 1742 of the circuit board 1702; in general, the components may be disposed on one or both of

faces

1740 and 1742. In particular, any suitable ones of the components of the IC device assembly 1700 may include any of the one or more microelectronic assemblies fabricated using hybrid fabrication in accordance with any of the embodiments disclosed herein.

In some embodiments, the circuit board 1702 may be a PCB that includes multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in accordance with a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally in conjunction with other metal layers). In other embodiments, the circuit board 1702 may be a substrate other than a PCB.

The IC device assembly 1700 shown in fig. 15 includes an interposer-on package structure 1736 coupled to a first side 1740 of the circuit board 1702 by a coupling member 1716. The coupling component 1716 may electrically and mechanically couple the package on interposer structure 1736 to the circuit board 1702 and may include solder balls (e.g., as shown in fig. 15), male and female portions of sockets, adhesive, underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 1736 may include an IC package 1720 coupled to the interposer 1704 through a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1716. IC package 1720 may be or may include, for example, a die (die 1502 of fig. 13B), an IC device, or any other suitable component. In particular, IC package 1720 may include one or more microelectronic assemblies 100 and/or one or more IC packages 200 fabricated using hybrid fabrication as described herein. Although fig. 15 shows a single IC package 1720, multiple IC packages may be coupled to interposer 1704; in practice, additional interpolators may be coupled to interpolators 1704. The interposer 1704 may provide an intervening substrate for bridging the circuit board 1702 and the IC package 1720. In general, the interposer 1704 may spread the connection to a wider pitch or reroute the connection to a different connection. For example, the interposer 1704 may couple the IC package 1720 (e.g., die) to a Ball Grid Array (BGA) of the coupling component 1716 for coupling to the circuit board 1702. In the embodiment shown in fig. 15, an IC package 1720 and a circuit board 1702 are attached to opposite sides of an interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the interposer 1704. In some embodiments, three or more components may be interconnected by an interposer 1704.

The interposer 1704 may be formed of epoxy, fiberglass reinforced epoxy, ceramic material, or a polymeric material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include any number of metal lines 1710, vias 1708, and TSVs 1706. The interposer 1704 may also include embedded devices 1714, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as Radio Frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be formed on interposer 1704. The package-on-interposer 1736 may take the form of any package-on-interposer known in the art.

The IC device assembly 1700 may include an IC package 1724 coupled to a first side 1740 of the circuit board 1702 by a coupling member 1722. Coupling component 1722 may take the form of any of the embodiments discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

The IC device assembly 1700 shown in fig. 15 includes an on-package structure 1734 coupled to the second side 1742 of the circuit board 1702 by a coupling member 1728. On-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that IC package 1726 is disposed between circuit board 1702 and IC package 1732.

Coupling components

1728 and 1730 may take the form of any of the embodiments of coupling component 1716 discussed above, and

IC packages

1726 and 1732 may take the form of any of the embodiments of IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any package-on-package structure known in the art.

Fig. 16 is a block diagram of an exemplary computing device 1800 that may include one or more components that may include one or more microelectronic assemblies 100 fabricated using hybrid fabrication in accordance with any of the embodiments disclosed herein. For example, any suitable of the components of the computing device 1800 may include an IC package (e.g., the IC package 1720 shown in fig. 15 and/or the IC package 200 shown in fig. 12) that includes one or more microelectronic assemblies 100 fabricated using hybrid fabrication in accordance with any of the embodiments disclosed herein. Any of the components of the computing device 1800 may include an IC device 1400 (e.g., as shown in fig. 14). Any of the components of the computing device 1800 may include an IC device assembly 1700 (e.g., as shown in fig. 15).

Several components are illustrated in fig. 16 as being included in computing device 1800, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Further, in various embodiments, the computing device 1800 may not include one or more of the components shown in fig. 16, but the computing device 1800 may include interface circuitry for coupling to one or more components. For example, the computing device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the computing device 1800 may not include the audio input device 1818 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) with which the audio input device 1818 or the audio output device 1808 may be coupled.

The computing device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform the electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more Digital Signal Processors (DSPs), application Specific ICs (ASICs), central Processing Units (CPUs), graphics Processing Units (GPUs), cryptographic processors (special purpose processors executing cryptographic algorithms in hardware), server processors, or any other suitable processing device. The computing device 1800 may include a memory 1804, which memory 1804 may itself include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read Only Memory (ROM)), flash memory, solid state memory, and/or a hard disk drive. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802.

In some embodiments, the computing device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for transmitting data to and from the computing device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

The communication chip 1812 may implement any of a number of wireless standards or protocols including, but not limited to, institute of Electrical and Electronics Engineers (IEEE) standards including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), long Term Evolution (LTE) plans along with any amendments, updates and/or revisions (e.g., LTE-advanced plans, ultra Mobile Broadband (UMB) plans (also referred to as "3GPP 2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for worldwide interoperability for microwave access, which is an authentication mark for products that pass compliance and interoperability tests of the IEEE 802.16 standard. The communication chip 1812 may operate according to global system for mobile communications (GSM), general Packet Radio Service (GPRS), universal Mobile Telecommunications System (UMTS), high Speed Packet Access (HSPA), evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with enhanced data rates for GSM evolution (EDGE), GSM EDGE Radio Access Network (GERAN), universal Terrestrial Radio Access Network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), digital Enhanced Cordless Telecommunications (DECT), evolution-data optimized (EV-DO), derivatives thereof, and any other wireless protocol designated 3G, 4G, 5G and higher. In other embodiments, the communication chip 1812 may operate in accordance with other wireless protocols. The computing device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (e.g., AM or FM radio transmissions).

In some embodiments, the communication chip 1812 may manage wired communications, e.g., electrical, optical, or any other suitable communication protocol (e.g., ethernet). As noted above, the communication chip 1812 may include a plurality of communication chips. For example, the first communication chip 1812 may be dedicated to shorter range wireless communications such as Wi-Fi or bluetooth, and the second communication chip 1812 may be dedicated to longer range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, wiMAX, LTE, ev-DO, or other. In some embodiments, the first communication chip 1812 may be dedicated to wireless communication and the second communication chip 1812 may be dedicated to wired communication.

The computing device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 1800 to an energy source (e.g., AC line power) separate from the computing device 1800.

The computing device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a Liquid Crystal Display (LCD), a light emitting diode display, or a flat panel display.

The computing device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indication, such as a speaker, headphones, or ear bud.

The computing device 1800 may include an audio input device 1818 (or corresponding interface circuitry, as discussed above). The audio input device 1818 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

The computing device 1800 may include a GPS device 1816 (or corresponding interface circuitry, as discussed above). GPS device 1816 may communicate with a satellite-based system and may receive the location of computing device 1800, as is known in the art.

The computing device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

The computing device 1800 may include other input devices 1820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, a touch pad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a Radio Frequency Identification (RFID) reader.

The computing device 1800 may have any desired form factor, for example, a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile internet appliance, a music player, a tablet computer, a laptop computer, a notebook computer, an ultra-notebook computer, a Personal Digital Assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 1800 may be any other electronic device that processes data.

Selected examples

The following paragraphs provide various examples of the embodiments disclosed herein.

Example A1 provides a microelectronic assembly including a first IC structure having first interconnects and a second IC structure having second interconnects, the second IC structure being bonded to the first IC structure, wherein at least some of the first interconnects include a liner layer and a conductive filler material, at least some of the second interconnects include a liner layer and a conductive filler material, and a material composition of the liner layer of the first interconnects is different than a material composition of the liner layer of the second interconnects. For example, the liner of the first interconnect may be a liner with one or more of tantalum, tantalum nitride, titanium nitride, and tungsten carbide, and the liner of the second interconnect may be a liner with one or more of tantalum, tantalum nitride, and cobalt. Any material may be included in any of these liners in an amount between about 5% and 50%, indicating that the material is included by intentionally alloying the material, in contrast to including possible accidental doping or impurities for which any of these metals would be below about 0.1%.

Example A2 provides the microelectronic assembly of example A1, wherein the liner layer of the first interconnect is different from the liner layer of the second interconnect in thickness, e.g., at least about 5% different, at least about 10% different, or at least about 5-50% different. For example, the liner of the first interconnect may have a thickness of between about 1 nm and 6 nm (including all values and ranges therein), while the liner of the second interconnect may have a thickness of between about 4 nm and 10 nm (including all values and ranges therein).

Example A3 provides the microelectronic assembly of example A1 or A2, wherein a material composition of the conductive fill material of the first interconnect is different from a material composition of the conductive fill material of the second interconnect. For example, the conductive fill material of the first interconnect may include copper (Cu), and the conductive fill material of the second interconnect may include tungsten (W), aluminum (Al), ruthenium (Ru), cobalt (Co), or AlCu (e.g., in a ratio between 1:1 and 1:100).

Example A4 provides the microelectronic assembly of any of examples A1-A3, wherein the microelectronic assembly further includes a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure. Furthermore, in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to the support structure providing mechanical stability to the microelectronic assembly), the cross section of each of the first and second interconnects is a trapezoid comprising two parallel sides, one of which is a short side and the other is a long side. Further, for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side, and for each trapezoid of the second interconnect, the long side is closer to the bonding interface than the short side.

Example A5 provides the microelectronic assembly of any of examples A1-A3, wherein the microelectronic assembly further includes a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure; in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to the support structure providing mechanical stability to the microelectronic assembly), the cross-section of each of the first and second interconnects is trapezoidal including two parallel sides, one of which is a short side and the other is a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example A6 provides the microelectronic assembly of any of examples A1-A3, wherein the microelectronic assembly further includes a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure; in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to the support structure providing mechanical stability to the microelectronic assembly), the cross-section of each of the first and second interconnects is trapezoidal including two parallel sides, one of the sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the shorter side is closer to the bonding interface than the longer side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example A7 provides the microelectronic assembly according to any of the preceding examples a, wherein the second IC structure is bonded to the first IC structure such that at least a portion of the conductive fill material of at least one of the first interconnects contacts at least a portion of the conductive fill material of at least one of the second interconnects.

Example A8 provides the microelectronic assembly according to any of the preceding examples a, wherein the second IC structure is bonded to the first IC structure with an adhesive material located between the first IC structure and at least a portion of the second IC structure. For example, the adhesive material may be an etch stop material located between the two IC structures. In some embodiments, the bonding of the first and second IC structures may be achieved by contacting the adhesive material with the first and second IC structures and applying pressure at a suitably high temperature (e.g., between about 50 degrees celsius and 200 degrees celsius). Next, a backside portion of the wafer of one of the IC structures may be polished to expose a backside metal layer or active device, e.g., a transistor.

Example A9 provides the microelectronic assembly according to any of the preceding examples a, further comprising an etch stop material in at least a portion of the second IC structure where it is bonded to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon. The atomic percentage of any of these materials may be at least 1%, for example, between about 1% and 50%, indicating that these elements are deliberately added, as opposed to unexpected impurities, which are typically less than about 0.1%.

Example a10 provides the microelectronic assembly according to any of the preceding examples a, wherein the pitch of at least some of the first interconnects is different from the pitch of at least some of the second interconnects, e.g., at least about 5% different, or at least about 10% different.

Example a11 provides the microelectronic assembly according to any of the preceding examples a, wherein each of the first and second IC structures has a first face and an opposite second face (e.g., one of the first and second faces is a front face of the IC structure and the other is a back face of the IC structure); the second IC structure is bonded to the first IC structure by bonding a first face of the second IC structure to a first face of the first IC structure (which may include f2f, f2b, or b2b bonding); and the microelectronic assembly further includes a via extending from the second face of the second IC structure toward the first face of the second IC structure, through a bonding interface between the second IC structure and the first IC structure, and into the first IC structure.

Example a12 provides the microelectronic assembly of example a11, wherein the via extends to the second face of the first IC structure.

Example a13 provides a microelectronic assembly, comprising: a first IC structure including a first interconnect; a second IC structure including a second interconnect; and a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure, in such an assembly, in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to a support structure providing mechanical stability for the microelectronic assembly), each of the first and second interconnects has a cross-section that is a trapezoid including two parallel sides, one of the sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect the long side is closer to the bonding interface than the short side.

Example a14 provides the microelectronic assembly of example a13, wherein a material composition of the conductive fill material of the first interconnect is different from a material composition of the conductive fill material of the second interconnect.

Example a15 provides the microelectronic assembly of example a13 or a14, wherein the second IC structure is bonded to the first IC structure such that at least a portion of the conductive fill material of at least one of the first interconnects contacts at least a portion of the conductive fill material of at least one of the second interconnects.

Example a16 provides the microelectronic assembly of any of examples a13-a15, wherein the second IC structure is bonded to the first IC structure with an adhesive material located between the first IC structure and at least a portion of the second IC structure.

Example a17 provides the microelectronic assembly of any of examples a13-a16, further comprising an etch stop material in at least a portion of where the second IC structure is bonded to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon.

Example a18 provides the microelectronic assembly of any of examples a13-a17, wherein the pitch of at least some of the first interconnects is different than the pitch of at least some of the second interconnects, e.g., at least about 5% different, or at least about 10% different.

Example a19 provides the microelectronic assembly of any of examples a13-a18, wherein each of the first and second IC structures has a first face and an opposing second face; the face of the first IC structure bonded to the face of the second IC structure is the first face of the first IC structure; the face of the second IC structure bonded to the face of the first IC structure is the first face of the second IC structure; and the microelectronic assembly further includes a via extending from the second face of the second IC structure toward the first face of the second IC structure, through the bonding interface, and into the first IC structure.

Example a20 provides the microelectronic assembly of example a19, wherein the via extends to the second face of the first IC structure.

Example a21 provides a microelectronic assembly comprising: a first IC structure including a first interconnect; a second IC structure including a second interconnect, the second IC structure being bonded to the first IC structure; and an etch stop material located in at least a portion of a bonding interface of the second IC structure to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%, such as at least about 5%, for example, between about 1% and 50%, thereby indicating that these elements are intentionally added, as opposed to unexpected impurities that are typically less than about 0.1% in concentration.

Example a22 provides the microelectronic assembly of example a21, wherein a material composition of the conductive fill material of the first interconnect is different from a material composition of the conductive fill material of the second interconnect.

Example a23 provides the microelectronic assembly of example a21 or a22, wherein the second IC structure is bonded to the first IC structure such that at least a portion of the conductive fill material of at least one of the first interconnects contacts at least a portion of the conductive fill material of at least one of the second interconnects.

Example a24 provides the microelectronic assembly of any of examples a21-a23, wherein the second IC structure is bonded to the first IC structure with an adhesive material located between the first IC structure and at least a portion of the second IC structure.

Example a25 provides the microelectronic assembly of any of examples a21-a24, wherein the pitch of at least some of the first interconnects is different from the pitch of at least some of the second interconnects, e.g., at least about 5% different, or at least about 10% different.

Example a26 provides the microelectronic assembly according to any of examples a21-a25, wherein, in a plane substantially perpendicular to the bonding interface, a cross-section of each of the first and second interconnects is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect the long side is closer to the bonding interface than the short side.

Example a27 provides the microelectronic assembly of any of examples a21-a25, wherein, in a plane substantially perpendicular to the bonding interface, a cross-section of each of the first and second interconnects is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example a28 provides the microelectronic assembly according to any of examples a21-a25, wherein, in a plane substantially perpendicular to the bonding interface, a cross-section of each of the first and second interconnects is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the shorter side is closer to the bonding interface than the longer side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example a29 provides the microelectronic assembly of any of examples a21-a28, wherein each of the first and second IC structures has a first face and an opposing second face (e.g., one of the first and second faces is a front face and the other is a back face); the second IC structure is bonded to the first IC structure by bonding a first face of the second IC structure to a first face of the first IC structure (which may include f2f, f2b, or b2b bonding), and the microelectronic assembly further includes a via extending from a second face of the second IC structure toward the first face of the second IC structure, through a bonding interface between the second IC structure and the first IC structure, and into the first IC structure.

Example a30 provides the microelectronic assembly of example a29, wherein the via extends to the second face of the first IC structure.

Example a31 provides the microelectronic assembly according to any of the preceding examples a, wherein the first interconnect is integrated in one or more insulating layers of the metallization stack of the first IC structure and the second interconnect is integrated in one or more insulating layers of the metallization stack of the second IC structure.

Example a32 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of a central processing unit.

Example a33 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further includes or is part of a memory device, the memory device being, for example, a high bandwidth memory device.

Example a34 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of a logic circuit.

Example a35 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of input/output circuitry.

Example a36 provides the microelectronic assembly of any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of a field programmable gate array transceiver.

Example a37 provides the microelectronic assembly of any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of a field programmable gate array logic unit.

Example a38 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further comprises or is part of power delivery circuitry.

Example a39 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further includes or is part of a group III-V amplifier.

Example a40 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further includes or is part of peripheral component interconnect express circuitry or double data rate transmission circuitry.

Example a41 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further comprises a front-end transistor.

Example a42 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures further includes a back-end transistor.

Example a43 provides the microelectronic assembly according to any of the preceding examples a, wherein at least one of the first and second IC structures includes a TFT.

Example a44 provides an IC package comprising a microelectronic assembly according to any of the preceding examples a; and another IC component coupled to the IC die.

Example a45 provides the IC package of example a44, wherein the another IC component includes one of a package substrate, an interposer, or another IC die.

Example a46 provides a computing device comprising a carrier substrate and a microelectronic assembly coupled to the carrier substrate, wherein the microelectronic assembly is a microelectronic assembly according to any of the foregoing examples a (e.g., according to any of examples A1-a 43), or the microelectronic assembly is included in an IC package according to any of examples a44-a 45.

Example a47 provides the computing device of example a46, wherein the computing device is a wearable or handheld computing device.

Example a48 provides the computing device of example a46 or a47, wherein the computing device further comprises one or more communication chips and an antenna.

Example a49 provides the computing device of any of examples a46-a48, wherein the carrier substrate is a motherboard.

Example a50 provides a method of manufacturing a microelectronic assembly, the method comprising providing a microelectronic assembly according to any of the preceding examples a.

Example B1 provides a microelectronic assembly, comprising: a first IC structure including a first interconnect, the first IC structure having a first face and an opposing second face (e.g., one of the first and second faces is a front face of the IC structure and the other is a back face of the IC structure); a second IC structure including a second interconnect, the second IC structure having a first face and an opposing second face (e.g., one of the first and second faces is a front face of the IC structure and the other is a back face of the IC structure); a bonding interface at which the second face of the first IC structure is bonded to the first face of the second IC structure using an adhesive material; and a via extending from the second face of the second IC structure through one or more layers of the second interconnect toward the first IC structure. In such an assembly, the cross-section of each of the first interconnect, the second interconnect and the via is a trapezoid including two parallel sides, one of which is a short side and the other is a long side; for each trapezoid of the second interconnect, the shorter side is closer to the second face of the second IC structure than the longer side; and for the via the short side is farther from the second face of the second IC structure than the long side (the long side may be located at the second face of the second IC structure because the via extends from the second face of the second IC structure).

Example B2 provides the microelectronic assembly of example B1, wherein, for each trapezoid of the first interconnect, the shorter side is closer to the first face of the first IC structure than the longer side.

Example B3 provides the microelectronic assembly of example B1, wherein, for each trapezoid of the first interconnect, the long side is closer to the first face of the first IC structure than the short side.

Example B4 provides the microelectronic assembly of any of examples B1-B3, wherein the via extends into the first IC structure.

Example B5 provides the microelectronic assembly of example B4, wherein the via extends through one or more layers of the first interconnect toward the first face of the first IC structure but does not reach the first face (the via is a blind via).

Example B6 provides the microelectronic assembly of example B4, wherein the via extends to the first face of the first IC structure (i.e., the via is a through via extending through both the first and second IC structures).

Example B7 provides the microelectronic assembly according to any of the preceding examples B, wherein the first IC structure further comprises a support structure (e.g., substrate, wafer, or die) housing/supporting the first interconnect, the support structure having a first face and an opposing second face, and the first interconnect being located in one or more layers of the metallization stack provided over the second face of the support structure.

Example B8 provides the microelectronic assembly of example B7, wherein the first face of the first IC structure is the first face of the support structure.

Example B9 provides the microelectronic assembly according to any of the preceding examples B, wherein the first IC structure further comprises one or more transistors proximate the first face of the first IC structure.

Example B10 provides the microelectronic assembly according to any of the preceding examples B, wherein the second IC structure further includes one or more transistors proximate the second face of the second IC structure.

Example B11 provides a microelectronic assembly including a first IC structure and a second IC structure. The first IC structure includes: a support structure (e.g., a substrate, wafer, or die) having a first side (e.g., a bottom side) and an opposite second side (e.g., a top side); a metallization stack having a first face (e.g., bottom face) and an opposite second face (e.g., top face), the first face of the metallization stack being provided over the second face of the support structure; and a first interconnect provided in one or more layers of the metallization stack. The second IC structure includes a second interconnect, the second IC structure having a first face (e.g., bottom face) and an opposing second face (e.g., top face), wherein the first face of the second IC structure is bonded to the second face of the metallization stack of the first IC structure using an adhesive material. The assembly also includes a via extending from the first face of the support structure of the first IC structure through one or more layers of the metallization stack toward the second IC structure. In such an assembly, the cross-section of each of the first interconnect, the second interconnect and the via is a trapezoid including two parallel sides, one of which is a short side and the other is a long side; for each trapezoid of the first interconnect, the shorter side is closer to the first face of the support structure than the longer side; and for the via the short side is farther from the first face of the support structure than the long side (the short side may be located at the first face of the support structure because the via extends from the first face of the support structure).

Example B12 provides the microelectronic assembly of example B11, wherein, for each trapezoid of the second interconnect, the shorter side is closer to the second face of the second IC structure than the longer side.

Example B13 provides the microelectronic assembly of example B11, wherein, for each trapezoid of the second interconnect, the long side is closer to the second face of the second IC structure than the short side.

Example B14 provides the microelectronic assembly of any of examples B11-B13, wherein the via extends into the second IC structure.

Example B15 provides the microelectronic assembly of example B14, wherein the via extends through one or more layers of the second interconnect toward the second face of the second IC structure but does not reach the second face (i.e., the via is a blind via).

Example B16 provides the microelectronic assembly of example B14, wherein the via extends to the second face of the second IC structure (i.e., the via is a through via extending through both the first and second IC structures).

Example B17 provides the microelectronic assembly of any of examples B11-B16, wherein the first IC structure further includes one or more transistors proximate the second face of the support structure.

Example B18 provides the microelectronic assembly of any of examples B11-B17, wherein the second IC structure further includes one or more transistors proximate the second face of the second IC structure.

Example B19 provides a microelectronic assembly, comprising: a first IC structure including a first interconnect, the first IC structure having a first face (e.g., bottom face) and an opposing second face (e.g., top face); a second IC structure including a second interconnect, the second IC structure having a first face (e.g., bottom face) and an opposing second face (e.g., top face); a bonding interface at which the second face of the first IC structure is bonded to the first face of the second IC structure using an adhesive material; and a via extending from the second face of the second IC structure toward the first face of the second IC structure, through a bonding interface between the second IC structure and the first IC structure, and into the first IC structure.

Example B20 provides the microelectronic assembly of example B19, wherein, in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to a support structure providing mechanical stability to the microelectronic assembly), the cross-section of each of the first and second interconnects is a trapezoid comprising two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect the long side is closer to the bonding interface than the short side.

Example B21 provides the microelectronic assembly of example B19, wherein in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to a support structure providing mechanical stability to the microelectronic assembly), the cross-section of each of the first and second interconnects is a trapezoid comprising two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example B22 provides the microelectronic assembly of example B19, wherein, in a plane substantially perpendicular to the bonding interface (or in a plane substantially perpendicular to a support structure providing mechanical stability to the microelectronic assembly), the cross-section of each of the first and second interconnects is a trapezoid comprising two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the first interconnect, the shorter side is closer to the bonding interface than the longer side; and for each trapezoid of the second interconnect, the shorter side is closer to the bonding interface than the longer side.

Example B23 provides the microelectronic assembly of any of examples B19-B22, wherein the first IC structure further includes a support structure (e.g., a substrate, a wafer, or a die) having a first face (e.g., a bottom face) and an opposing second face (e.g., a top face), the first IC structure further includes a metallization stack having a first face (e.g., a bottom face) and an opposing second face (e.g., a top face), the first face of the metallization stack is provided over the second face of the support structure, the first interconnect is located in the metallization stack, the first face of the first IC structure is the first face of the support structure, the first face of the metallization stack is over the second face of the support structure, and the second face of the first IC structure is the second face of the metallization stack.

Example B24 provides the microelectronic assembly of any of examples B19-B22, wherein the second IC structure further includes a support structure (e.g., a substrate, a wafer, or a die) having a first face (e.g., a bottom face) and an opposing second face (e.g., a top face), the second IC structure further includes a metallization stack having a first face (e.g., a bottom face) and an opposing second face (e.g., a top face), the first face of the metallization stack is provided over the second face of the support structure, the second interconnect is located in the metallization stack, the second face of the second IC structure is the first face of the support structure, the first face of the metallization stack is over the second face of the support structure, and the first face of the second IC structure is the second face of the metallization stack.

Example B25 provides the microelectronic assembly of any of examples B19-B24, wherein the bonding interface includes an etch stop material in at least a portion of the second face of the first IC structure bonded to the first face of the second IC structure, the etch stop material including silicon, nitrogen, and carbon, wherein an atomic percentage of each of the silicon, nitrogen, and carbon in the etch stop material is at least about 1%. The atomic percentage of any of these materials may be at least 1%, for example, between about 1% and 50%, indicating that these elements are deliberately added, as opposed to unexpected impurities, which are typically less than about 0.1%.

Example B26 provides the microelectronic assembly of any of examples B19-B25, wherein at least some of the first interconnects include a liner and a conductive filler material, at least some of the second interconnects include a liner and a conductive filler material, and a material composition of the liner of the first interconnects is different than a material composition of the liner of the second interconnects.

Example B27 provides the microelectronic assembly of example B26, wherein the liner layer of the first interconnect is different from the liner layer of the second interconnect in thickness, e.g., at least about 5% different, at least about 10% different, or at least about 5-50% different.

Example B28 provides the microelectronic assembly of example B26 or B27, wherein a material composition of the conductive fill material of the first interconnect is different from a material composition of the conductive fill material of the second interconnect.

Example B29 provides the microelectronic assembly of any of examples B19-B28, wherein a material composition of the via is different than a material composition of the conductive fill material of the first interconnect or a material composition of the conductive fill material of the second interconnect.

Example B30 provides the microelectronic assembly of any of examples B19-B29, wherein the via extends to the first face of the first IC structure.

Example B31 provides the microelectronic assembly according to any of the preceding examples B, wherein the first interconnect is integrated in one or more insulating layers of the metallization stack of the first IC structure and the second interconnect is integrated in one or more insulating layers of the metallization stack of the second IC structure.

Example B32 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a central processing unit.

Example B33 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a memory device, the memory device being, for example, a high bandwidth memory device.

Example B34 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a logic circuit.

Example B35 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of input/output circuitry.

Example B36 provides the microelectronic assembly of any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a field programmable gate array transceiver.

Example B37 provides the microelectronic assembly of any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a field programmable gate array logic unit.

Example B38 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of power delivery circuitry.

Example B39 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of a group III-V amplifier.

Example B40 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises or is part of peripheral component interconnect express circuitry or double data rate transmission circuitry.

Example B41 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises a front-end transistor.

Example B42 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures further comprises a back-end transistor.

Example B43 provides the microelectronic assembly according to any of the preceding examples B, wherein at least one of the first and second IC structures comprises a TFT.

Example B44 provides an IC package comprising a microelectronic assembly according to any of the preceding examples B; and another IC component coupled to the IC die.

Example B45 provides the IC package of example B44, wherein the another IC component includes one of a package substrate, an interposer, or another IC die.

Example B46 provides a computing device comprising a carrier substrate and a microelectronic assembly coupled to the carrier substrate, wherein the microelectronic assembly is a microelectronic assembly according to any of the foregoing examples B (e.g., according to any of examples B1-B43), or the microelectronic assembly is included in an IC package according to any of examples B44-B45.

Example B47 provides the computing device of example B46, wherein the computing device is a wearable or handheld computing device.

Example B48 provides the computing device of example B46 or B47, wherein the computing device further comprises one or more communication chips and an antenna.

Example B49 provides the computing device of any of examples B46-B48, wherein the carrier substrate is a motherboard.

Example B50 provides a method of manufacturing a microelectronic assembly, the method comprising providing a microelectronic assembly according to any of the preceding examples B.

Example C1 provides an IC package, comprising: a package substrate having a first side and an opposite second side; and a microelectronic assembly coupled to the package substrate through a package interconnect, wherein the microelectronic assembly includes: a first IC structure having a first face and an opposing second face, wherein the first face of the first IC structure is at least partially between the second face of the package substrate and the second face of the first IC structure, and the first face of the first IC structure is coupled to the second face of the package substrate through a package interconnect; a second IC structure having a first face and an opposing second face, wherein the first face of the second IC structure is at least partially between the second face of the first IC structure and the second face of the second IC structure; bonding material bonding the second face of the first IC structure to the first face of the second IC structure; and a conductive via having at least a portion located in the first IC structure, at least a portion located in the second IC structure, and extending through the bonding material.

Example C2 provides the IC package of example C1, wherein the via is configured to provide electrical coupling between one or more components of the first IC structure and one or more components of the second IC structure.

Example C3 provides the IC package of example C1 or C2, wherein the package interconnect comprises a die-to-package interconnect.

Example C4 provides the IC package according to any one of the preceding examples C, wherein the package interconnect comprises solder.

Example C5 provides the IC package according to any one of the preceding examples C, wherein the package interconnect comprises an anisotropically conductive material.

Example C6 provides the IC package of any one of the preceding examples C, wherein the via is one of a plurality of vias, and each of the plurality of vias has at least a portion in the first IC structure, at least a portion in the second IC structure, and extends through the bonding material.

Example C7 provides the IC package of example C6, wherein a pitch of the plurality of vias is different than a pitch of the package interconnects.

Example C8 provides the IC package according to any one of the preceding examples C, wherein the first IC structure comprises a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the first IC structure, and the second IC structure comprises a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the second IC structure.

Example C9 provides the IC package of example C8, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the long side is closer to the bonding interface than the short side; and for each trapezoid of the plurality of interconnects of the second IC structure, the long side is closer to the bonding interface than the short side.

Example C10 provides the IC package of example C8, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the long side is closer to the bonding interface than the short side; and for each trapezoid of the plurality of interconnects of the second IC structure, the shorter side is closer to the bonding interface than the longer side.

Example C11 provides the IC package of example C8, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the shorter side is closer to the bonding interface than the longer side; and for each trapezoid of the plurality of interconnects of the second IC structure, the shorter side is closer to the bonding interface than the longer side.

Example C12 provides the IC package of any of examples C8-C11, wherein a portion of the via in the second IC structure is coupled to one or more of the plurality of interconnects of the second IC structure.

Example C13 provides the IC package of any of examples C8-C12, wherein a portion of the via in the first IC structure is coupled to one or more of the plurality of interconnects in the first IC structure.

Example C14 provides the IC package according to any one of examples C8-C13, wherein a portion of the via in the first IC structure is coupled to one or more of the package interconnects.

Example C15 provides the IC package according to any one of the preceding examples C, wherein the bonding material comprises an etch stop material in at least a portion where the second side of the first IC structure is bonded to the first side of the second IC structure, the etch stop material comprising silicon, nitrogen, and carbon, wherein the atomic percent of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, thereby indicating that these elements are intentionally added, as opposed to unexpected impurities that are typically less than about 0.1%.

Example C16 provides the IC package according to any one of the preceding examples C, wherein a surface area of the first face of the second IC structure is different than a surface area of the second face of the first IC structure.

Example C17 provides the IC package according to any one of the preceding examples C, further comprising a third IC structure having a first face and an opposing second face, wherein the first face of the third IC structure is at least partially between the second face of the first IC structure and the second face of the third IC structure, and the first face of the third IC structure is coupled to the second face of the first IC structure by a DTD interconnect.

Example C18 provides the IC package of example C17, wherein the DTD interconnect comprises solder.

Example C19 provides the IC package of example C17 or C18, wherein the DTD interconnect comprises an anisotropically conductive material.

Example C20 provides the IC package of any one of examples C17-C19, wherein the DTD interconnect is a plated interconnect.

Example C21 provides the IC package of any one of examples C17-C20, wherein the DTD interconnect is a copper-to-copper interconnect.

Example C22 provides the IC package of any of examples C17-C21, wherein the via is one of a plurality of vias, each of the plurality of vias having at least a portion in the first IC structure, at least a portion in the second IC structure, and extending through the bonding material, the plurality of vias having a pitch different from a pitch of the DTD interconnect.

Example C23 provides the IC package according to any one of examples C17-C21, wherein the IC package further comprises: a fourth IC structure having a first face and an opposing second face, wherein the first face of the fourth IC structure is at least partially between the second face of the third IC structure and the second face of the fourth IC structure; another bonding material bonding the second face of the third IC structure to the first face of the fourth IC structure; and another conductive via having at least a portion in the third IC structure, at least a portion in the fourth IC structure, and extending through the another bonding material.

Example C24 provides the IC package of example C23, wherein the further via is configured to provide electrical coupling between one or more components of the third IC structure and one or more components of the fourth IC structure.

Example C25 provides the IC package of example C23 or C24, wherein the via is one of a plurality of vias, each via of the plurality of vias having at least a portion located in a first IC structure, at least a portion located in a second IC structure, and extending through the bonding material; the further via is one of a plurality of further vias, each of the plurality of further vias having at least a portion located in a third IC structure, at least a portion located in a fourth IC structure, and extending through the further bonding material; and the pitch of the plurality of vias is different from the pitch of the plurality of other vias.

Example C26 provides the IC package of any of examples C23-C25, wherein a portion of the another via located in the third IC structure is coupled to one or more of the DTD interconnects.

Example C27 provides the IC package of any one of the preceding examples C, further comprising a molding material at least partially surrounding at least the second IC structure.

Example C28 provides the IC package according to any one of the preceding examples C, further comprising a heat spreader configured to dissipate heat from one or more of the first and second IC structures.

Example C29 provides the IC package according to any one of the preceding examples C, wherein the package substrate comprises one or more of a ceramic material and an organic material.

Example C30 provides an IC package according to any one of the preceding examples C, wherein the package substrate is a PCB.

Example C31 provides an IC package, comprising: a package substrate having a first side and an opposite second side; and a microelectronic assembly coupled to the package substrate through a package interconnect, wherein the microelectronic assembly includes: a first IC structure having a first face and an opposing second face, wherein the first face of the first IC structure is at least partially between the second face of the package substrate and the second face of the first IC structure, and the first face of the first IC structure is coupled to the second face of the package substrate through a package interconnect; and a second IC structure having a first face and an opposing second face, wherein the first face of the second IC structure is at least partially between the second face of the first IC structure and the second face of the second IC structure, and the second face of the first IC structure is bonded to the first face of the second IC structure. In such a microelectronic assembly, the first IC structure includes a first interconnect, the second IC structure includes a second interconnect, and the material composition of the conductive fill material of the first interconnect is different from the material composition of the conductive fill material of the second interconnect.

Example C32 provides the IC package of example C31, wherein the first interconnect further comprises an underlayer, and the second interconnect does not comprise an underlayer.

Example C33 provides the IC package of example C31, wherein the second interconnect further comprises an underlayer, and the first interconnect does not comprise an underlayer.

Example C34 provides the IC package of example C31, wherein the first interconnect further comprises a liner layer and a conductive filler material, the second interconnect further comprises a liner layer and a conductive filler material, and a material composition of the liner layer of the first interconnect is different than a material composition of the liner layer of the second interconnect.

Example C35 provides the IC package of example C34, wherein a thickness of the liner of the first interconnect is different than a thickness of the liner of the second interconnect.

Example C36 provides the IC package according to any one of examples C31-C35, further comprising a bonding interface bonding the second side of the first IC structure to the first side of the second IC structure.

Example C37 provides the IC package of example C36, wherein the bonding material comprises silicon, nitrogen, and carbon, wherein the atomic percent of each of the silicon, nitrogen, and carbon within the bonding material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, thereby indicating that these elements are intentionally added, in contrast to unexpected impurities that are typically less than about 0.1%.

Example C38 provides the IC package of any of examples C31-C37, wherein the first IC structure includes a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the first IC structure, and the second IC structure includes a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the second IC structure.

Example C39 provides the IC package of example C38, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the long side is closer to the bonding interface than the short side; and for each trapezoid of the plurality of interconnects of the second IC structure, the long side is closer to the bonding interface than the short side.

Example C40 provides the IC package of example C38, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the long side is closer to the bonding interface than the short side; and for each trapezoid of the plurality of interconnects of the second IC structure, the shorter side is closer to the bonding interface than the longer side.

Example C41 provides the IC package of example C38, wherein, in a plane substantially perpendicular to the package substrate, a cross-section of each of the plurality of interconnects of the first IC structure and the plurality of interconnects of the second IC structure is a trapezoid including two parallel sides, one of the two sides being a short side and the other being a long side; for each trapezoid of the plurality of interconnects of the first IC structure, the shorter side is closer to the bonding interface than the longer side; and for each trapezoid of the plurality of interconnects of the second IC structure, the shorter side is closer to the bonding interface than the longer side.

Example C42 provides the IC package of any of examples C31-C41, wherein the package interconnect comprises a die-to-package interconnect.

Example C43 provides the IC package of any of examples C31-C42, wherein the package interconnect comprises solder.

Example C44 provides the IC package according to any one of examples C31-C44, wherein the package interconnect comprises an anisotropically conductive material.

Example C45 provides the IC package of any of examples C31-C44, wherein a surface area of the first face of the second IC structure is different than a surface area of the second face of the first IC structure.

Example C46 provides the IC package of any of examples C31-C45, further comprising a third IC structure having a first face and an opposing second face, wherein the first face of the third IC structure is at least partially between the second face of the first IC structure and the second face of the third IC structure, and the first face of the third IC structure is coupled to the second face of the first IC structure by a DTD interconnect.

Example C47 provides the IC package of example C46, wherein the DTD interconnect comprises solder.

Example C48 provides the IC package of example C46 or C47, wherein the DTD interconnect comprises an anisotropically conductive material.

Example C49 provides the IC package according to any one of examples C46-C48, wherein the DTD interconnect is a plated interconnect.

Example C50 provides the IC package of any one of examples C46-C49, wherein the DTD interconnect is a copper-to-copper interconnect.

Example C51 provides the IC package of any of examples C46-C50, wherein the via is one of a plurality of vias, each of the plurality of vias having at least a portion in the first IC structure, at least a portion in the second IC structure, and extending through the bonding material, and the pitch of the plurality of vias is different than the pitch of the DTD interconnect.

Example C52 provides the IC package according to any one of examples C46-C51, wherein the IC package further comprises: a fourth IC structure having a first face and an opposing second face, wherein the first face of the fourth IC structure is at least partially between the second face of the third IC structure and the second face of the fourth IC structure; another bonding material bonding the second face of the third IC structure to the first face of the fourth IC structure; and another conductive via having at least a portion in the third IC structure and at least a portion in the fourth IC structure and extending through the another bonding material.

Example C53 provides the IC package of any of examples C31-C52, further comprising a molding material at least partially surrounding at least the second IC structure.

Example C54 provides the IC package according to any one of examples C31-C53, further comprising a heat spreader configured to dissipate heat from one or more of the first and second IC structures.

Example C55 provides the IC package of any of examples C31-C54, wherein the package substrate comprises one or more of a ceramic material and an organic material.

Example C56 provides the IC package according to any one of examples C31-C55, wherein the package substrate is a PCB.

Example C57 provides the IC package of any of examples C31-C56, wherein the first IC structure includes a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the first IC structure, and the second IC structure includes a plurality of interconnects integrated in one or more insulating layers of the metallization stack of the second IC structure.

Example C58 provides the IC package of any of examples C31-C57, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a central processing unit.

Example C59 provides the IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a memory device, the memory device being, for example, a high bandwidth memory device.

Example C60 provides the IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a logic circuit.

Example C61 provides the IC package according to any one of the preceding examples C, wherein at least one of the first and second IC structures further comprises or is part of input/output circuitry.

Example C62 provides the IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a field programmable gate array transceiver.

Example C63 provides an IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a field programmable gate array logic unit.

Example C64 provides the IC package of any one of the preceding examples C, wherein at least one of the first and second IC structures further comprises or is part of power delivery circuitry.

Example C65 provides the IC package according to any of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of a group III-V amplifier.

Example C66 provides the IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises or is part of peripheral component interconnect express circuitry or double data rate transmission circuitry.

Example C67 provides the IC package according to any one of the preceding examples C, wherein at least one of the first and second IC structures further comprises a front-end transistor.

Example C68 provides the IC package of any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure further comprises a back-end transistor.

Example C69 provides the IC package according to any one of the preceding examples C, wherein at least one of the first IC structure and the second IC structure includes a TFT.

Example C70 provides the IC package according to any one of the preceding examples C, wherein the microelectronic assembly is a microelectronic assembly according to any one of the preceding examples a or a microelectronic assembly according to any one of the preceding examples B.

Example C71 provides a computing device comprising an IC package according to any one of the preceding examples C.

Example C72 provides the computing device of example C71, wherein the computing device is a wearable or handheld computing device.

Example C73 provides the computing device of example C71 or C72, wherein the computing device further comprises one or more communication chips and an antenna.

Example C74 provides a method of manufacturing a micro IC package, the method comprising providing an IC package according to any one of the preceding examples C.

The above description of illustrated embodiments of the present disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific embodiments of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications can be made to the disclosure in light of the above detailed description.

Claims

1. A microelectronic assembly, comprising:

a first Integrated Circuit (IC) structure including a first interconnect; and

a second IC structure including a second interconnect, the second IC structure being bonded to the first IC structure;

wherein:

at least some of the first interconnects include a liner layer and a conductive fill material,

at least some of the second interconnects include a liner layer and a conductive filler material, an

The liner of the first interconnect has a material composition that is different from a material composition of the liner of the second interconnect.

2. The microelectronic assembly of claim 1, wherein a thickness of the liner of the first interconnect is different than a thickness of the liner of the second interconnect.

3. The microelectronic assembly as claimed in claim 1, wherein a material composition of the conductive fill material of the first interconnect is different from a material composition of the conductive fill material of the second interconnect.

4. The microelectronic assembly of claim 1, wherein:

the microelectronic assembly further includes a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure,

in a plane substantially perpendicular to the bonding interface, each of the first interconnect and the second interconnect has a cross section of a trapezoid including two parallel sides, one of the two parallel sides being a short side and the other of the two parallel sides being a long side,

For each trapezoid of the first interconnect, the long side is closer to the bonding interface than the short side, and

for each trapezoid of the second interconnect, the long side is closer to the bonding interface than the short side.

5. The microelectronic assembly of claim 1, wherein:

for each trapezoid of the second interconnect, the short side is closer to the bonding interface than the long side.

6. The microelectronic assembly of claim 1, wherein:

for each trapezoid of the first interconnect, the short side is closer to the bonding interface than the long side, and

7. The microelectronic assembly as claimed in claim 1, wherein the second IC structure is bonded to the first IC structure such that at least a portion of the conductive fill material of at least one of the first interconnects contacts at least a portion of the conductive fill material of at least one of the second interconnects.

8. The microelectronic assembly as claimed in any of claims 1-7, wherein the second IC structure is bonded to the first IC structure by an adhesive material located between at least a portion of the first IC structure and at least a portion of the second IC structure.

9. The microelectronic assembly of any of claims 1-7, further comprising an etch stop material in at least a portion where the second IC structure is bonded to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%.

10. The microelectronic assembly as claimed in any of claims 1-7, wherein a pitch of at least some of the first interconnects is different from a pitch of at least some of the second interconnects.

11. The microelectronic assembly of any of claims 1-7, wherein:

each of the first and second IC structures has a first face and an opposite second face,

the second IC structure is bonded to the first IC structure by bonding the first face of the second IC structure to the first face of the first IC structure, and

the microelectronic assembly also includes a via extending from the second face of the second IC structure toward the first face of the second IC structure, through a bonding interface between the second IC structure and the first IC structure, and into the first IC structure.

12. The microelectronic assembly as claimed in claim 11, wherein the vias extend to the second face of the first IC structure.

13. A microelectronic assembly, comprising:

a first Integrated Circuit (IC) structure including a first interconnect; and

a second IC structure including a second interconnect; and

a bonding interface at which a face of the first IC structure is bonded to a face of the second IC structure,

Wherein:

14. The microelectronic assembly of claim 13, further comprising an etch stop material in at least a portion where the second IC structure is bonded to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%.

15. The microelectronic assembly of claim 13 or 14, wherein:

the face of the first IC structure bonded to the face of the second IC structure is the first face of the first IC structure,

The face of the second IC structure bonded to the face of the first IC structure is the first face of the second IC structure, and

the microelectronic assembly also includes a via extending from the second face of the second IC structure toward the first face of the second IC structure, through the bonding interface, and into the first IC structure.

16. A microelectronic assembly, comprising:

a first Integrated Circuit (IC) structure including a first interconnect;

a second IC structure including a second interconnect, the second IC structure being bonded to the first IC structure; and

an etch stop material in at least a portion of a bonding interface where the second IC structure is bonded to the first IC structure, the etch stop material comprising silicon, nitrogen, and carbon, wherein an atomic percentage of each of silicon, nitrogen, and carbon within the etch stop material is at least about 1%.

17. The microelectronic assembly of claim 16, wherein:

18. The microelectronic assembly of claim 16, wherein:

19. The microelectronic assembly of claim 16, wherein:

20. The microelectronic assembly of any of claims 16-19, wherein: