CN116367538A

CN116367538A - Semiconductor structure

Info

Publication number: CN116367538A
Application number: CN202310392472.5A
Authority: CN
Inventors: 武强; 余兴; 张宏广
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2023-04-12
Filing date: 2023-04-12
Publication date: 2023-06-30

Abstract

A semiconductor structure, comprising: one or more vertically stacked units, wherein the stacked units comprise: a system control wafer comprising a system control circuit; the storage wafers comprise a plurality of storage units which are arranged in an array, the storage wafers are vertically stacked on the system control wafer, two adjacent storage wafers are bonded in pairs, and the storage units of one or more storage wafers are electrically connected with the system control circuit. The structure and performance of the semiconductor structure are optimized.

Description

Semiconductor structure

Technical Field

The present disclosure relates to semiconductor devices, and particularly to a semiconductor structure.

Background

Dynamic Random Access Memory (DRAM) typically includes an array of bit cells, each cell capable of storing bit information. A typical cell configuration includes a capacitor for storing a charge representing a bit to be stored and an access transistor that provides access to the capacitor during read and write operations. The access transistor is connected between the bit line and the capacitor and is gated (turned on or off) by the word line signal. During a read operation, a stored bit of information is read from the cell through the associated bit line. During a write operation, some information is stored into the cell from the bit line through the transistor. The cells are dynamic in nature and therefore require periodic updates.

The storage and retrieval of data has been a limiting factor in many aspects of the computing industry. Memory devices may limit the overall performance of modern computing devices. In order to make the memory faster, the memory structures have been scaled down to very small sizes, significantly increasing the density of the memory structures. In terms of the density of memory structures, two-dimensional memory structures have begun to reach theoretical limits, and three-dimensional memory structures can grasp the key to further increase memory density. However, three-dimensional memory devices require significant changes in structure and processing compared to two-dimensional memory devices. Tightly integrated computational logic and three-dimensional (3D) memory can implement large package caches.

Existing three-dimensional dynamic random access memory (3D DRAM) structures and performance are yet to be optimized.

Disclosure of Invention

The technical problem solved by the invention is to provide a semiconductor structure for optimizing the structure and performance of a three-dimensional dynamic random access memory (3D DRAM).

In order to solve the above technical problems, the present invention provides a semiconductor structure, including: one or more vertically stacked units, wherein the stacked units comprise: a system control wafer comprising a system control circuit; the storage wafers comprise a plurality of storage units which are arranged in an array, the storage wafers are vertically stacked on the system control wafer, two adjacent storage wafers are bonded in pairs, and the storage units of one or more storage wafers are electrically connected with the system control circuit.

Optionally, the storage unit includes: a substrate, a transistor on the substrate, the transistor including a gate on the substrate and source and drain electrodes in the substrate on both sides of the gate; the capacitor comprises a first end and a second end, and the first end is connected with the drain electrode; the memory wafer further includes: a plurality of word lines, wherein the word lines are parallel to a first direction, the first direction is parallel to the surface of the storage wafer, and any one word line is electrically connected with the gates of one row of transistors; and the bit lines are parallel to a second direction, the second direction is parallel to the surface of the storage wafer and perpendicular to the first direction, and any bit line is electrically connected with the sources of one row of transistors.

Optionally, the storage wafers and the system control wafers are vertically stacked along a third direction, the third direction is perpendicular to the first direction, the third direction is perpendicular to the second direction, the storage wafers comprise a first functional surface and a first nonfunctional surface in the third direction, and the first functional surface of one storage wafer is bonded with the first nonfunctional surface of the adjacent other storage wafer; the system control wafer includes a second functional side and a second non-functional side.

Optionally, the storage wafer further includes: a plurality of first via structures extending from the first nonfunctional surface to the first functional surface, any one of the first via structures being in electrical contact with one of the bit lines; a first connection structure located on a first functional surface of the memory wafer, any one of the first connection structures being electrically connected to one of the bit lines; a plurality of second through hole structures penetrating through the storage wafer from the first nonfunctional surface of the storage wafer to the first functional surface; the system control wafer further comprises: and a second connection structure extending from a second nonfunctional surface of the system control wafer to a second functional surface, the second connection structure being electrically connected to the system control circuit.

Optionally, the first non-functional surface of the storage wafer bonded to the system control wafer faces the second functional surface of the system control wafer.

Optionally, the storage wafer further includes: a plurality of third via structures extending from the first nonfunctional surface to the first functional surface, any one of the third via structures electrically connected to one of the word lines

Optionally, two adjacent storage wafers are bonded in pairs, and one or more storage units of the storage wafers are electrically connected with the system control circuit, including: the first through hole structures of the storage wafers bonded with the system control wafer are electrically connected with the system control circuit of the system control wafer, and bit lines corresponding to the positions of a plurality of storage wafers are connected to the system control circuit in series through the first connecting structures and the first through hole structures; the third through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the second through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and one third through hole structure or one second through hole structure of the storage wafer, or two ends of the second through hole structure are respectively and electrically connected with one third through hole structure of one storage wafer and one second through hole structure of the other storage wafer, or two ends of the second through hole structure are respectively and electrically connected with one second through hole structure of one storage wafer and one second through hole structure of the other storage wafer.

Optionally, the first functional surface of the storage wafer bonded to the system control wafer faces the second functional surface of the system control wafer.

Optionally, the storage wafer further includes: and a plurality of fourth via structures extending from the first functional surface to the first nonfunctional surface, any one of the fourth via structures being electrically connected to one of the word lines.

Optionally, two adjacent storage wafers are bonded in pairs, and one or more storage units of the storage wafers are electrically connected with the system control circuit, including: the first connecting structure on the first functional surface of one storage wafer is electrically contacted with the first through hole structure of the first nonfunctional surface of the other adjacent storage wafer, the first connecting structure and the first through hole structure which are electrically contacted are in one-to-one correspondence, the first connecting structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and bit lines corresponding to the positions of a plurality of storage wafers are connected to the system control circuit in series through the first connecting structure and the first through hole structure; the fourth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the second through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and a fourth through hole structure or a second through hole structure of the storage wafer, or two ends of the second through hole structure are respectively and electrically connected with the fourth through hole structure of the storage wafer and a second through hole structure of another storage wafer, or two ends of the second through hole structure are respectively and electrically connected with the second through hole structure of the storage wafer and the second through hole structure of another storage wafer.

Optionally, the storage wafer further includes: a plurality of fifth via structures extending from the first nonfunctional surface toward the first functional surface, any one of the fifth via structures being in electrical contact with one of the word lines; a third connection structure located on the first functional surface of the memory wafer, any one of the third connection structures being electrically connected to one of the word lines; and a plurality of sixth through hole structures penetrating through the storage wafer from the first nonfunctional surface to the first functional surface.

Optionally, the storage wafer further includes: and a plurality of seventh via structures extending from the first nonfunctional surface to the first functional surface, any one of the seventh via structures being electrically connected to one of the bit lines.

Optionally, two adjacent storage wafers are bonded in pairs, and one or more storage units of the storage wafers are electrically connected with the system control circuit, including: the third connecting structure on the first functional surface of one storage wafer is electrically contacted with the fifth through hole structure of the first nonfunctional surface of the other adjacent storage wafer, the third connecting structure and the fifth through hole structure which are electrically contacted are in one-to-one correspondence, the fifth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and a plurality of word lines corresponding to the positions of the storage wafers are connected to the system control circuit in series through the third connecting structure and the fifth through hole structure; the seventh through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of one sixth through hole structure are respectively and electrically connected with the system control circuit of the system control wafer and one seventh through hole structure or one sixth through hole structure of the storage wafer, or two ends of one sixth through hole structure are respectively and electrically connected with one seventh through hole structure of one storage wafer and one sixth through hole structure of the other storage wafer, or two ends of one sixth through hole structure are respectively and electrically connected with one sixth through hole structure of one storage wafer and one sixth through hole structure of the other storage wafer.

Optionally, the storage wafer further includes: and a plurality of eighth via structures extending from the first functional surface to the first nonfunctional surface, any one of the eighth via structures being electrically connected to one of the bit lines.

Optionally, two adjacent storage wafers are bonded in pairs, and one or more storage units of the storage wafers are electrically connected with the system control circuit, including: the third connecting structure on the first functional surface of one storage wafer is electrically contacted with the fifth through hole structure of the first nonfunctional surface of the adjacent other storage wafer, the third connecting structure and the fifth through hole structure which are electrically contacted are in one-to-one correspondence, the third connecting structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and a plurality of word lines corresponding to the positions of the storage wafers are connected to the system control circuit in series through the third connecting structure and the fifth through hole structure; the eighth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the sixth through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and an eighth through hole structure or a sixth through hole structure of the storage wafer, or two ends of the sixth through hole structure are respectively and electrically connected with an eighth through hole structure of the storage wafer and a sixth through hole structure of another storage wafer, or two ends of the sixth through hole structure are respectively and electrically connected with a sixth through hole structure of the storage wafer and a sixth through hole structure of another storage wafer.

Optionally, in the plurality of vertically stacked units, the second nonfunctional surface of the system control wafer in one stacked unit is bonded to the first functional surface or the first nonfunctional surface of the storage wafer in another stacked unit, and the system control circuit in the system control wafer of the plurality of stacked units is electrically connected to the system control circuit in the bottommost system control wafer through the storage wafer.

Optionally, the system control circuit includes: one or both of logic circuitry and analog circuitry; the logic circuit includes: a combination of one or more of a sampling amplifier circuit, a word line driving circuit, a data channel circuit, a power supply circuit, a clock circuit, a control circuit, and an input-output circuit; the analog circuit includes: a combination of one or more of a sampling amplifier circuit, a word line driving circuit, a data channel circuit, a power supply circuit, a clock circuit, a control circuit, and an input-output circuit.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

according to the technical scheme, in the semiconductor structure, the storage units and the system control circuits are respectively positioned on different wafers, the system control circuits for controlling the plurality of storage wafers are integrated on one system control wafer, so that the number of logic wafers matched with the storage wafers can be reduced, the system control circuits for controlling the storage wafers can be simplified, word lines and bit lines on the plurality of storage wafers can be uniformly controlled by the system control wafers, and therefore a plurality of storage arrays on the plurality of storage wafers can be integrated for addressing, reading, writing, repairing and controlling, signal transmission is facilitated, and overall circuit design and overall cost are simplified. Meanwhile, the process optimization of the memory chip and the logic chip is facilitated, and the stability of the product is improved.

Further, the first functional surface of the storage wafer bonded with the system control wafer faces the second functional surface of the system control wafer, so that the storage wafer does not need to be bonded with the second functional surface of the system control wafer through silicon via structures from the second functional surface, and the connecting structure of the first functional surface of the storage wafer can be directly bonded with the second functional surface of the system control wafer, thereby simplifying the process flow.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment;

FIG. 2 is a schematic diagram of another embodiment of a semiconductor structure;

FIGS. 3-5 are schematic diagrams illustrating a semiconductor structure according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

fig. 7 and 8 are schematic structural views of a semiconductor structure according to another embodiment of the present invention;

FIG. 9 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention;

fig. 10 is a schematic structural view of a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, three-dimensional dynamic random access memory (3D DRAM) structures and performance are yet to be optimized. The analysis will now be described with reference to specific examples.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor structure of an example of a currently existing HBM 3D stack, where the semiconductor structure includes: a first wafer 101 with a plurality of vertical micro bumps stacked and bonded, wherein the first wafer 101 comprises a logic area and a storage area, the storage area is provided with a plurality of storage units distributed in an array, and the logic area is provided with a system control circuit 103 for controlling the storage units; the system control wafer 100 comprises a functional surface and a non-functional surface which are opposite, the system control wafer 100 is provided with a system control circuit for controlling a plurality of first wafers 101, the plurality of first wafers 101 are stacked on the functional surface of the system control wafer 100, and the first wafers 101 are bonded with the system control wafer 100 by micro bumps.

Because the first wafer 101 includes both the memory cell array and the system control circuit 103, too many wires cannot be made on the first wafer 101 for direct bonding of the wafers, so that the plurality of first wafers 101 and the system control wafer 100 are bonded and electrically connected together through micro bumps (micro bumps) 104, the micro bump process needs to cut the wafers first and then bond the cut wafers together, and the micro bump process cannot cut the wafer after bonding the whole wafer. The area of the microbump 104 is much larger than the area of the wafer directly bonded (about 50 times) in unit area, and the impedance of the microbump 104 is also much larger than the impedance of the wafer directly bonded.

In addition, in the semiconductor structure, the first wafer 101 includes both the memory cell array and the system control circuit, so that the first wafer 101 needs a larger area to meet the design of the memory cell array and the system control circuit; secondly, the memory cell array and the system control circuit are integrated on a wafer, and the area of the logic area is not too large, so that high requirements are imposed on the manufacturing process of the system control circuit; again, each first wafer 101 is manufactured by the same process, and each first wafer 101 has the same system control circuit and auxiliary circuit, and the system control circuit and auxiliary circuit can be simplified, so that the system control circuit and auxiliary circuit on the first wafer 101 are redundant, and generate larger power consumption.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a semiconductor structure according to another embodiment; the semiconductor structure includes: a plurality of vertically stacked structures, wherein the stacked structures comprise a logic wafer 201 and a storage wafer 202 which is positioned on the logic wafer 201 and is bonded with the logic wafer 201, the storage wafer 202 is provided with a plurality of storage units distributed in an array, and a system control circuit for controlling the storage units is arranged in the logic wafer 201; the system control wafer 200 includes a functional surface and a non-functional surface opposite to each other, the system control wafer 200 has a system control circuit for controlling a plurality of logic wafers 201 and a storage wafer 202, and a plurality of first stacked structures are stacked on the functional surface of the system control wafer 200, and the logic wafers 201 are bonded to the system control wafer 200.

In the semiconductor structure, the memory cell array and the system control circuit are respectively located on different wafers, so that each memory wafer 202 needs to be bonded with one logic wafer 201, thus multiple layers need to be bonded, and the bonding process is complex; in addition, each logic wafer 201 is manufactured by the same process, and each logic wafer 201 has a system control circuit and an analog circuit with the same function, such as a power supply and CLOCK (CLOCK) circuit, and the functional repetition of the system control circuit and the analog circuit of this part can be simplified, so that the system control circuit on the logic wafer 201 is redundant and wastes the wafer area, and generates larger power consumption.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure, in which the number of logic wafers matched with a storage wafer can be reduced, the system control circuit for controlling the storage wafer can be simplified, signal transmission is facilitated, process optimization of each of the storage chip and the logic chip is facilitated, overall circuit design and overall cost are simplified, and product stability is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 5 are schematic structural views of a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 3, fig. 3 is an overall schematic diagram of the stacking unit, which includes: a system control wafer 300, the system control wafer 300 comprising a system control circuit; the storage wafers 301 include a plurality of storage units arranged in an array, the plurality of storage wafers are vertically stacked on the system control wafer 300, two adjacent storage wafers 301 are bonded in pairs, and one or more storage units of the storage wafers 301 are electrically connected with the system control circuit.

In the stacking unit, the storage units and the system control circuits are respectively located on different wafers, the system control circuits for controlling the plurality of storage wafers 301 are integrated on one system control wafer 300, so that the number of logic wafers matched with the storage wafers 301 can be reduced, the system control circuits for controlling the storage wafers 301 can be simplified, word lines and bit lines on the plurality of storage wafers 301 can be uniformly controlled by the system control wafer 300, and thus a plurality of storage arrays on the plurality of storage wafers 301 can be integrated for addressing, reading, writing, repairing and controlling, which is beneficial to signal transmission and simplifies the overall circuit design and the overall cost. Meanwhile, the process optimization of the memory chip and the logic chip is facilitated, and the stability of the product is improved.

Referring to fig. 4 and 5 in conjunction with fig. 3, fig. 4 is a schematic diagram of connection relationship between word lines and bit lines in the stacked unit, and fig. 5 is a schematic side view of a memory wafer 301 in the stacked unit, where the memory unit includes: a substrate (not shown), a transistor 303 on the substrate, the transistor 303 including a gate electrode (not shown) on the substrate, and a source electrode (not shown) and a drain electrode (not shown) in the substrate on both sides of the gate electrode; a capacitor 304, the capacitor 304 comprising a first end and a second end, the first end being connected to the drain.

With continued reference to fig. 3 to 5, in this embodiment, the storage wafer 301 further includes: a plurality of word lines 305, wherein the word lines 305 are parallel to a first direction X, the first direction X is parallel to the surface of the memory wafer 301, and any one word line 305 is electrically connected to the gates of one row of the transistors 303; a plurality of bit lines 306, wherein the bit lines 306 are parallel to a second direction Y, and the second direction Y is parallel to the surface of the memory wafer 301 and perpendicular to the first direction X, and any one bit line 306 is electrically connected to the sources of one row of the transistors 303.

In this embodiment, the storage wafers 301 and the system control wafer 300 are vertically stacked along a third direction Z, the third direction Z is perpendicular to the first direction X, the third direction Z is perpendicular to the second direction Y, the storage wafers 301 include a first functional surface S1 and a first nonfunctional surface S2 in the third direction Z, and the first functional surface S1 of one storage wafer 301 is bonded to the first nonfunctional surface S2 of another adjacent storage wafer 301; the system control wafer 300 includes a second functional surface S3 and a second non-functional surface S4.

In this embodiment, the first nonfunctional surface S2 of the storage wafer 301 bonded to the system control wafer 300 faces the second functional surface S3 of the system control wafer 300.

With continued reference to fig. 3 to 5, in this embodiment, the storage wafer 301 further includes: a plurality of first via structures 307 extending from the first nonfunctional surface S2 to the first functional surface S1, any one of the first via structures 307 being in electrical contact with one of the bit lines 306; a first connection structure 308 located on the first functional surface S1 of the memory wafer 301, and any one of the first connection structures 308 is electrically connected to one of the bit lines 306.

Any one of the bit lines 306 is electrically connected to the first via structure 307 of the first nonfunctional surface S2 and the first connection structure 308 of the first functional surface S1, respectively, so that the bit line 306 corresponding to the position of each memory wafer 301 can be connected in series to the system control circuit of the system control wafer 300.

With continued reference to fig. 3 to 5, in this embodiment, the storage wafer 301 further includes: a plurality of third via structures 309 extending from the first nonfunctional surface S2 to the first functional surface S1, any one of the third via structures 309 being electrically connected to one of the word lines 305; and a plurality of second via structures 310 penetrating from the first nonfunctional surface S2 to the first functional surface S1 of the memory wafer 301.

The third via structure 309 is used to individually connect each word line 305 to the system control circuitry of the system control wafer 300, and a plurality of word lines 305 in a plurality of memory wafers 301 are connected in parallel to the system control circuitry of the system control wafer 300.

The second via structure 310 penetrates through the storage wafer 301, and is used for electrically connecting the third via structure 309 of the upper storage wafer 301 with the second via structure of the lower storage wafer 301 or with the system control circuit of the system control wafer 300.

In this embodiment, two adjacent memory wafers 301 are bonded in pairs, and one or more memory units of the memory wafers 301 are electrically connected to the system control circuit, including: the first connection structure 308 on the first functional surface S1 of one storage wafer 301 is electrically contacted with the first through hole structure 307 on the first non-functional surface S2 of the adjacent other storage wafer 301, the first connection structure 308 and the first through hole structure 307 which are electrically contacted are in one-to-one correspondence, the first through hole structure 307 of the storage wafer 301 bonded with the system control wafer 300 is electrically connected with the system control circuit of the system control wafer 300, and the bit lines 306 of the storage arrays of a plurality of storage wafers 301 are connected in series with the first through hole structure 307 through the first connection structure 308 and the first through hole structure 307 and are connected to the system control wafer 301; the third via structure 309 of the memory wafer 301 bonded to the system control wafer 300 is electrically connected to the system control circuitry of the system control wafer 300.

When the upper layer of the storage wafer 301 is bonded with a storage wafer 301 and the lower layer is bonded with a system control wafer 300, two ends of one second through hole structure 310 are respectively electrically connected with a system control circuit of the system control wafer 300 and one third through hole structure 309 of the storage wafer 301; when the upper layer of the storage wafer 301 is bonded with a plurality of storage wafers 301 and the lower layer is bonded with a system control wafer 300, two ends of one second through hole structure 310 are respectively electrically connected with a system control circuit of the system control wafer 300 and one second through hole structure 310 of the storage wafer 301; when the upper layer of the memory wafer 301 is bonded to one memory wafer 301 and the lower layer of the memory wafer 301 is bonded to one memory wafer 301, two ends of one second via structure 310 are electrically connected to one third via structure 309 of the upper layer of the memory wafer 301 and one second via structure 310 of the lower layer of the memory wafer 301 respectively; when the upper layer of the memory wafer 301 is bonded with a plurality of memory wafers 301 and the lower layer of the memory wafer 301 is bonded with the memory wafer, two ends of the second via structure 310 are electrically connected with one second via structure 310 of the upper layer of the memory wafer 301 and one second via structure 310 of the lower layer of the memory wafer 301 respectively. In summary, the word lines 305 of the memory array of the plurality of memory wafers 301 are connected in parallel to the system control wafer 300 through the third via structure 309 and the second via structure 310, respectively.

In this embodiment, the system control circuit includes: one or both of logic circuitry and analog circuitry; the logic circuit includes: a combination of one or more of a Sense Amplifier (SA) circuit, a Word line Driver (WD) circuit, a Data Path (Data Path) circuit, a power supply circuit, a clock circuit, a Control circuit, and an input/output (I/O) circuit; the analog circuit includes: a combination of one or more of a Sense Amplifier (SA) circuit, a Word line Driver (WD) circuit, a Data Path (Data Path) circuit, a power supply circuit, a clock circuit, a Control circuit, and an input/output (I/O) circuit.

The system control circuit electrically connected to the word line 305 and the bit line 306 is designed according to the requirements.

In this embodiment, the system control wafer 300 further includes: a second connection structure 315 extending from the second non-functional surface S4 to the second functional surface S3, the second connection structure 315 being electrically connected to the system control circuit.

The second connection structure 315 is used for electrical connection with an external circuit or device.

With continued reference to fig. 3 to 5, in this embodiment, the method further includes: and a fourth connection structure 311 electrically connected to the other end of the capacitor 304, wherein the fourth connection structure 311 is connected to the upper plates of the capacitors 304 of the memory array of all the memory wafers 301.

With continued reference to fig. 3 to 5, in this embodiment, the method further includes: a bonding layer 302 between the storage wafers 301 and the system control wafer 300, the bonding layer 302 comprising: a first dielectric layer (not shown) located on the second functional surface S3 of the system control wafer 300 and a first connection board (not shown) located in the first dielectric layer, where the first dielectric layer exposes a surface of the first connection board, and the first connection board is electrically connected to the system control circuit; a second dielectric layer (not shown) located on the first functional surface S1 of the storage wafer 301 and a second connection board 312 located in the second dielectric layer, where the second dielectric layer exposes a surface of the second connection board 312, and the second connection board 312 is electrically connected to the first connection structure 308 or the fourth connection structure 311; a third dielectric layer (not shown) on the first nonfunctional surface S2 of the storage wafer 301 and a third connection plate 313 within the third dielectric layer (not shown), the third dielectric layer exposing a surface of the third connection plate 313, the third connection plate 313 being electrically connected to the first via structure 307 or the second via structure 310.

The bonding of the storage wafer 301 and the storage wafer 301 includes: the second dielectric layer is in contact with the third dielectric layer, and the third connection plate 313 is in electrical contact with the second connection plate 312; the bonding of the storage wafer 301 and the system control wafer 300 includes: the third dielectric layer is in contact with the first dielectric layer, and the third connection plate 313 is in electrical contact with the first connection plate.

In this embodiment, the bonding between the storage wafer 301 and the bonding between the storage wafer 301 and the system control wafer 300 include hybrid bonding (hybrid bonding).

Fig. 6 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 6 in conjunction with fig. 3, fig. 6 is a schematic diagram illustrating a connection relationship between bit lines and word lines in the stacked unit, and in this embodiment, the memory wafer 301 further includes: a plurality of fifth via structures 407 extending from the first non-functional surface S2 of the memory wafer 301 to the first functional surface S1, any one of the fifth via structures 407 being in electrical contact with one of the word lines 305; and third connection structures 408 located on the first functional surface S1 of the memory wafer 301, wherein any one of the third connection structures 408 is electrically connected to one of the word lines 305.

Any one of the word lines 305 is electrically connected to the fifth via structure 407 of the first nonfunctional surface S2 and the third connection structure 408 of the first functional surface S1, respectively, so that the word line 305 corresponding to the position of each memory wafer 301 can be connected in series to the system control circuit of the system control wafer 300.

With continued reference to fig. 6 in conjunction with fig. 3, in this embodiment, the storage wafer 301 further includes: a plurality of seventh via structures 409 extending from the first nonfunctional surface S2 to the first functional surface S1, any one of the seventh via structures 409 being electrically connected to one of the bit lines 306; a plurality of sixth via structures 410 penetrate the memory wafer 301 from the first nonfunctional surface S2 to the first functional surface S1.

The seventh via structure 409 is used to individually connect each bit line 306 to the system control circuit of the system control wafer 300, and the bit lines 306 in the memory wafers 301 are connected in parallel to the system control circuit of the system control wafer 300.

The sixth via structure 410 penetrates through the storage wafer 301, and is used for electrically connecting the seventh via structure 409 of the upper storage wafer 301 with the sixth via structure of the lower storage wafer 301 or with a system control circuit of the system control wafer 300.

In this embodiment, two adjacent memory wafers 301 are bonded in pairs, and one or more memory units of the memory wafers 301 are electrically connected to the system control circuit, including: the third connection structure 408 on the first functional surface S1 of one storage wafer 301 is electrically contacted with the fifth through hole structure 407 of the first non-functional surface S2 of the adjacent other storage wafer 301, the third connection structure 408 and the fifth through hole structure 407 which are electrically contacted are in one-to-one correspondence, the fifth through hole structure 407 of the storage wafer 301 bonded with the system control wafer 300 is electrically connected with the system control circuit of the system control wafer 300, and the word lines 305 of the storage arrays of a plurality of storage wafers 301 are connected in series with the fifth through hole structure 407 through the third connection structure 408 and are connected to the system control wafer 301; the seventh via structure 409 of the memory wafer 301 bonded to the system control wafer 300 is electrically connected to the system control circuitry of the system control wafer 300.

When the upper layer of the memory wafer 301 is bonded with a memory wafer 301 and the lower layer is bonded with a system control wafer 300, two ends of a sixth through hole structure 410 are electrically connected with a system control circuit of the system control wafer 300 and a seventh through hole structure 409 of the memory wafer 301 respectively; when the upper layer of the storage wafer 301 is bonded with a plurality of storage wafers 301 and the lower layer is bonded with a system control wafer 300, two ends of one sixth through hole structure 410 are respectively electrically connected with the system control circuit of the system control wafer 300 and one sixth through hole structure 410 of the storage wafer 301; when the upper layer of the memory wafer 301 is bonded to one memory wafer 301 and the lower layer of the memory wafer 301 is bonded to one memory wafer 301, two ends of one sixth through hole structure 410 are electrically connected to one seventh through hole structure 409 of the upper layer of the memory wafer 301 and one sixth through hole structure 410 of the lower layer of the memory wafer 301 respectively; when the upper layer of the memory wafer 301 is bonded with a plurality of memory wafers 301 and the lower layer of the memory wafer 301 is bonded with the memory wafer, two ends of the sixth via structure 410 are electrically connected with one sixth via structure 410 of the upper layer of the memory wafer 301 and one sixth via structure 410 of the lower layer of the memory wafer 301, respectively. In summary, the bit lines 306 of the memory array of the plurality of memory wafers 301 are connected in parallel to the system control wafer 300 through the sixth via structure 410 and the seventh via structure 409, respectively.

Fig. 7 and 8 are schematic structural views of a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 7 and 8, fig. 7 is an overall schematic diagram of the stacked unit, and fig. 8 is a schematic diagram of a connection relationship between word lines and bit lines in the stacked unit, the stacked unit includes: a system control wafer 500, the system control wafer 500 comprising a system control circuit; the storage wafers 501 comprise a plurality of storage units arranged in an array, wherein a plurality of storage wafers are vertically stacked on the system control wafer 500, two adjacent storage wafers 501 are bonded in pairs, and one or more storage units of the storage wafers 501 are electrically connected with the system control circuit.

In the stacking unit, the memory units and the system control circuits are respectively located on different wafers, the system control circuits for controlling the memory wafers 501 are integrated on one system control wafer 500, so that the number of logic wafers matched with the memory wafers 501 can be reduced, the system control circuits for controlling the memory wafers 501 can be simplified, word lines and bit lines on the memory wafers 501 can be uniformly controlled by the system control wafer 500, and thus, a plurality of memory arrays on the memory wafers 501 can be integrated for addressing, reading, writing, repairing and controlling, which is beneficial to signal transmission, and simplifies the overall circuit design and the overall cost. Meanwhile, the process optimization of the memory chip and the logic chip is facilitated, and the stability of the product is improved.

The memory cell includes: a substrate (not shown), a transistor (not shown) on the substrate, the transistor (not shown) including a gate (not shown) on the substrate, and a source (not shown) and a drain (not shown) in the substrate on both sides of the gate; a capacitor (not shown) including a first end and a second end, the first end being connected to the drain.

In this embodiment, the storage wafer 501 further includes: a plurality of word lines 505, wherein the word lines 505 are parallel to a first direction X, the first direction X is parallel to the surface of the memory wafer 501, and any one word line 505 is electrically connected with the gates of one row of the transistors 503; a plurality of bit lines 506, wherein the bit lines 506 are parallel to a second direction Y, the second direction Y is parallel to the surface of the memory wafer 501 and perpendicular to the first direction X, and any bit line 506 is electrically connected to the sources of a row of the transistors 503.

In this embodiment, the storage wafer 501 and the system control wafer 500 are vertically stacked along a third direction Z, where the third direction Z is perpendicular to the first direction X, and the third direction Z is perpendicular to the second direction Y, and the storage wafer 501 includes a first functional surface S1 and a first nonfunctional surface S2 in the third direction Z, and the first functional surface S1 of one storage wafer 501 is bonded to the first nonfunctional surface S2 of another adjacent storage wafer 501; the system control wafer 500 includes a second functional surface S3 and a second non-functional surface S4.

In this embodiment, the first functional surface S1 of the storage wafer 501 bonded to the system control wafer 500 faces the second functional surface S3 of the system control wafer 500. The first functional surface S1 of the storage wafer 501 faces the second functional surface S3 of the system control wafer 500, so that the storage wafer 501 does not need to be bonded to the second functional surface S3 of the system control wafer 500 by a through silicon via structure formed on the second functional surface S3, and the connection structure of the first functional surface S1 of the storage wafer 501 can be directly bonded to the second functional surface S3 of the system control wafer 500, thereby simplifying the process flow.

With continued reference to fig. 7 and 8, in this embodiment, the storage wafer 501 further includes: a plurality of first via structures 507 extending from the first nonfunctional surface S2 to the first functional surface S1, any one of the first via structures 507 being in electrical contact with one of the bit lines 506; a first connection structure 508 located on the first functional surface S1 of the memory wafer 501, and any one of the first connection structures 508 is electrically connected to one of the bit lines 506.

With continued reference to fig. 7 and 8, in this embodiment, the storage wafer 501 further includes: the storage wafer 501 further includes: a plurality of fourth via structures 509 extending from the first functional surface S1 to the first non-functional surface S2, any one of the fourth via structures 509 being electrically connected to one of the word lines 505; and a plurality of second via structures 510 penetrating from the first nonfunctional surface S2 to the first functional surface S1 of the memory wafer 501.

The seven via structure 509 is used to individually connect each word line 505 to the system control circuitry of the system control wafer 500, and a number of word lines 505 in a number of memory wafers 501 are connected in parallel to the system control circuitry of the system control wafer 500.

The second via structure 510 penetrates through the storage wafer 501, and is used for electrically connecting the seven via structures 509 of the upper storage wafer 501 with the second via structure of the lower storage wafer 501 or with the system control circuit of the system control wafer 500.

In this embodiment, two adjacent memory wafers 501 are bonded in pairs, and one or more memory cells of the memory wafers 501 are electrically connected to the system control circuit, which includes: the first connection structure 508 on the first functional surface S1 of one storage wafer 501 is electrically contacted with the first through hole structure 507 of the first non-functional surface S2 of the adjacent other storage wafer 501, the first connection structure 508 and the first through hole structure 507 which are electrically contacted are in one-to-one correspondence, the first connection structure 508 of the storage wafer 501 bonded with the system control wafer 500 is electrically connected with the system control circuit of the system control wafer 500, and the bit lines 506 of the storage arrays of a plurality of storage wafers 501 are connected in series with the first through hole structure 507 through the first connection structure 508 and are connected to the system control wafer 501; the fourth via structure 509 of the memory wafer 501 bonded to the system control wafer 500 is electrically connected to the system control circuitry of the system control wafer 500.

When the upper layer of the memory wafer 501 is bonded with a memory wafer 501 and the lower layer is bonded with a system control wafer 500, two ends of one second via structure 510 are respectively electrically connected with the system control circuit of the system control wafer 500 and one third via structure 509 of the memory wafer 501; when the upper layer of the storage wafer 501 is bonded with a plurality of storage wafers 501 and the lower layer is bonded with a system control wafer 500, two ends of one second through hole structure 510 are respectively electrically connected with a system control circuit of the system control wafer 500 and one second through hole structure 510 of the storage wafer 501; when the upper layer of the memory wafer 501 is bonded to one memory wafer 501 and the lower layer of the memory wafer 501 is bonded to one memory wafer, two ends of one second via structure 510 are electrically connected to one fourth via structure 509 of the upper layer of the memory wafer 501 and one second via structure 510 of the lower layer of the memory wafer 501 respectively; when the upper layer of the memory wafer 501 is bonded with a plurality of memory wafers 501 and the lower layer of the memory wafer 501 is bonded with the memory wafer, two ends of the second via structure 510 are electrically connected with one second via structure 510 of the upper layer of the memory wafer 501 and one second via structure 510 of the lower layer of the memory wafer 501 respectively. In summary, the word lines 505 of the memory array of the plurality of memory wafers 501 are connected in parallel to the system control wafer 500 through the fourth via structures 509 and the second via structures 510, respectively.

In this embodiment, the system control circuit includes: one or both of logic circuitry and analog circuitry; the logic circuit includes: a combination of one or more of a Sense Amplifier (SA) circuit, a Word line Driver (WD) circuit, a Data Path (Data Path) circuit, a power supply circuit, a clock circuit, a Control circuit, and an input/output (I/O) circuit; the analog circuit includes: a combination of one or more of a Sense Amplifier (SA) circuit, a Word line Driver (WD) circuit, a Data Path (Data Path) circuit, a power supply circuit, a clock circuit, a Control circuit, and an input/output (I/O) circuit. The system control circuit electrically connected to the word line 305 and the bit line 306 is designed according to the requirements.

In this embodiment, the system control wafer 300 further includes: a second connection structure 515 extending from the second non-functional surface S4 to the second functional surface S3, said second connection structure 515 being electrically connected to said system control circuit.

The second connection structure 515 is used for electrical connection with an external circuit or device.

Fig. 9 is a schematic structural view of a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 9 in conjunction with fig. 7, fig. 9 is a schematic diagram illustrating a connection relationship between bit lines and word lines in the stacked unit, and in this embodiment, the memory wafer 501 further includes: a plurality of fifth via structures 607 extending from the first non-functional surface S2 of the memory wafer 501 to the first functional surface S1, any of the fifth via structures 607 being in electrical contact with one of the word lines 505; and third connection structures 608 located on the first functional surface S1 of the memory wafer 601, where any of the third connection structures 608 is electrically connected to one of the word lines 505.

Any one of the word lines 505 is electrically connected to the fifth via structure 607 of the first non-functional surface S2 and the third connection structure 608 of the first functional surface S1, respectively, so that the word line 605 corresponding to the location of each memory wafer 501 can be connected in series to the system control circuit of the system control wafer 600.

In this embodiment, the storage wafer 501 further includes: a plurality of eighth via structures 609 extending from the first functional surface S1 to the first nonfunctional surface S2, any one of the eighth via structures 609 being electrically connected to one of the bit lines 506; a plurality of sixth via structures 610 penetrate the memory wafer 501 from the first nonfunctional surface S2 to the first functional surface S1.

The eighth via structure 609 is used to individually connect each bit line 506 to the system control circuit of the system control wafer 500, and a plurality of bit lines 506 in a plurality of memory wafers 501 are connected in parallel to the system control circuit of the system control wafer 500.

The sixth via structure 610 penetrates the storage wafer 501 and is used to electrically connect the eighth via structure 609 of the upper storage wafer 501 with the sixth via structure of the lower storage wafer 501 or with the system control circuit of the system control wafer 500.

In this embodiment, two adjacent memory wafers 501 are bonded in pairs, and one or more memory cells of the memory wafers 501 are electrically connected to the system control circuit, which includes: the third connection structure 608 on the first functional surface S1 of one storage wafer 501 is electrically contacted with the fifth through hole structure 607 of the first non-functional surface S2 of the adjacent other storage wafer 501, the third connection structure 608 and the fifth through hole structure 607 which are electrically contacted are in one-to-one correspondence, the third connection structure 608 of the storage wafer 501 bonded with the system control wafer 500 is electrically connected with the system control circuit of the system control wafer 500, and the word lines 505 of the storage arrays of a plurality of storage wafers 501 are connected in series through the third connection structure 608 and the fifth through hole structure 607 and connected to the system control wafer 501; the eighth via structure 609 of the memory wafer 501 bonded to the system control wafer 500 is electrically connected to the system control circuitry of the system control wafer 500.

When the upper layer of the memory wafer 501 is bonded to a memory wafer 501 and the lower layer is bonded to a system control wafer 500, two ends of one sixth via structure 610 are electrically connected to the system control circuit of the system control wafer 500 and one eighth via structure 609 of the memory wafer 501, respectively; when the upper layer of the memory wafer 501 is bonded with a plurality of memory wafers 501 and the lower layer is bonded with a system control wafer 500, two ends of one sixth through hole structure 610 are electrically connected with the system control circuit of the system control wafer 500 and one sixth through hole structure 610 of the memory wafer 501 respectively; when the upper layer of the memory wafer 501 is bonded to one memory wafer 501 and the lower layer of the memory wafer 501 is bonded to one memory wafer, two ends of one sixth through hole structure 610 are electrically connected to one eighth through hole structure 609 of the upper layer of the memory wafer 501 and one sixth through hole structure 610 of the lower layer of the memory wafer 501 respectively; when the upper layer of the memory wafer 501 is bonded with a plurality of memory wafers 501 and the lower layer of the memory wafer 501 is bonded with a plurality of memory wafers 501, two ends of the sixth via structure 610 are electrically connected with one sixth via structure 610 of the upper layer of the memory wafer 501 and one sixth via structure 610 of the lower layer of the memory wafer 501 respectively. In summary, the bit lines 506 of the memory array of the plurality of memory wafers 501 are connected in parallel to the system control wafer 500 through the sixth via structure 610 and the eighth via structure 609, respectively.

Referring to fig. 10, fig. 7 is a schematic diagram based on fig. 3, in this embodiment, the semiconductor structure includes a plurality of vertically stacked units, in which the second non-functional surface S4 of the system control wafer 300 in one stacked unit is bonded to the first functional surface S1 of the storage wafer 301 in another stacked unit, and the system control circuits in the system control wafer 300 of the plurality of stacked units are electrically connected to the system control circuits in the bottom system control wafer 300 through the storage wafer 301.

The system control circuits in the system control wafer 300 in the plurality of stacked units are electrically connected with the system control circuits in the bottommost system control wafer 300 through the storage wafer 301, that is, the system control circuits in the bottommost system control wafer 300 control the storage wafer 301 and the system control wafer 300 in the whole semiconductor structure, so that the circuits can be further simplified, the process optimization of the storage chips and the logic chips can be facilitated, the overall circuit design and the overall cost can be simplified, and the stability of the product can be improved. Meanwhile, the structure solves the problem that after the multi-layer storage wafers 301 are stacked, the area of one system control wafer 300 is insufficient.

In other embodiments, the first functional surface of the storage wafer bonded to the system control wafer is oriented toward the second functional surface of the system control wafer. And the system control circuits in the system control wafers of the plurality of stacked units are electrically connected with the system control circuits in the bottommost system control wafer through the storage wafers.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

one or more vertically stacked units, wherein,

the stacking unit includes: a system control wafer comprising a system control circuit;

the storage wafers comprise a plurality of storage units which are arranged in an array, the storage wafers are vertically stacked on the system control wafer, two adjacent storage wafers are bonded in pairs, and the storage units of one or more storage wafers are electrically connected with the system control circuit.

2. The semiconductor structure of claim 1, wherein the memory cell comprises: a substrate, a transistor on the substrate, the transistor including a gate on the substrate and source and drain electrodes in the substrate on both sides of the gate; the capacitor comprises a first end and a second end, and the first end is connected with the drain electrode; the memory wafer further includes: a plurality of word lines, wherein the word lines are parallel to a first direction, the first direction is parallel to the surface of the storage wafer, and any one word line is electrically connected with the gates of one row of transistors; and the bit lines are parallel to a second direction, the second direction is parallel to the surface of the storage wafer and perpendicular to the first direction, and any bit line is electrically connected with the sources of one row of transistors.

3. The semiconductor structure of claim 2, wherein the memory wafer and the system control wafer are vertically stacked along a third direction, the third direction being perpendicular to the first direction, the third direction being perpendicular to the second direction, the memory wafer including a first functional face and a first nonfunctional face in the third direction, the first functional face of one memory wafer being bonded to the first nonfunctional face of an adjacent other memory wafer; the system control wafer includes a second functional side and a second non-functional side.

4. The semiconductor structure of claim 3, wherein the memory wafer further comprises: a plurality of first via structures extending from the first nonfunctional surface to the first functional surface, any one of the first via structures being in electrical contact with one of the bit lines; a first connection structure located on a first functional surface of the memory wafer, any one of the first connection structures being electrically connected to one of the bit lines; a plurality of second through hole structures penetrating through the storage wafer from the first nonfunctional surface of the storage wafer to the first functional surface; the system control wafer further comprises: and a second connection structure extending from a second nonfunctional surface of the system control wafer to a second functional surface, the second connection structure being electrically connected to the system control circuit.

5. The semiconductor structure of claim 4, wherein a first nonfunctional side of the memory wafer bonded to a system control wafer is oriented toward a second functional side of the system control wafer.

6. The semiconductor structure of claim 5, wherein the memory wafer further comprises: and a plurality of third via structures extending from the first nonfunctional surface to the first functional surface, any one of the third via structures being electrically connected to one of the word lines.

7. The semiconductor structure of claim 6, wherein two adjacent memory wafers are bonded in pairs, and one or more memory cells of the memory wafers are electrically connected to the system control circuit, comprising: the first through hole structures of the storage wafers bonded with the system control wafer are electrically connected with the system control circuit of the system control wafer, and bit lines corresponding to the positions of a plurality of storage wafers are connected to the system control circuit in series through the first connecting structures and the first through hole structures; the third through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the second through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and one third through hole structure or one second through hole structure of the storage wafer, or two ends of the second through hole structure are respectively and electrically connected with one third through hole structure of one storage wafer and one second through hole structure of the other storage wafer, or two ends of the second through hole structure are respectively and electrically connected with one second through hole structure of one storage wafer and one second through hole structure of the other storage wafer.

8. The semiconductor structure of claim 4, wherein a first functional surface of the memory wafer bonded to a system control wafer is oriented toward a second functional surface of the system control wafer.

9. The semiconductor structure of claim 8, wherein the memory wafer further comprises: and a plurality of fourth via structures extending from the first functional surface to the first nonfunctional surface, any one of the fourth via structures being electrically connected to one of the word lines.

10. The semiconductor structure of claim 9, wherein two adjacent memory wafers are bonded in pairs, and one or more memory cells of the memory wafers are electrically connected to the system control circuit, comprising: the first connecting structure on the first functional surface of one storage wafer is electrically contacted with the first through hole structure of the first nonfunctional surface of the other adjacent storage wafer, the first connecting structure and the first through hole structure which are electrically contacted are in one-to-one correspondence, the first connecting structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and bit lines corresponding to the positions of a plurality of storage wafers are connected to the system control circuit in series through the first connecting structure and the first through hole structure; the fourth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the second through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and a fourth through hole structure or a second through hole structure of the storage wafer, or two ends of the second through hole structure are respectively and electrically connected with the fourth through hole structure of the storage wafer and a second through hole structure of another storage wafer, or two ends of the second through hole structure are respectively and electrically connected with the second through hole structure of the storage wafer and the second through hole structure of another storage wafer.

11. The semiconductor structure of claim 3, wherein the memory wafer further comprises: a plurality of fifth via structures extending from the first nonfunctional surface toward the first functional surface, any one of the fifth via structures being in electrical contact with one of the word lines; a third connection structure located on the first functional surface of the memory wafer, any one of the third connection structures being electrically connected to one of the word lines; and a plurality of sixth through hole structures penetrating through the storage wafer from the first nonfunctional surface to the first functional surface.

12. The semiconductor structure of claim 11, wherein a first nonfunctional side of the memory wafer bonded to a system control wafer is oriented toward a second functional side of the system control wafer.

13. The semiconductor structure of claim 12, wherein the memory wafer further comprises: and a plurality of seventh via structures extending from the first nonfunctional surface to the first functional surface, any one of the seventh via structures being electrically connected to one of the bit lines.

14. The semiconductor structure of claim 13, wherein two adjacent memory wafers are bonded in pairs, and one or more memory cells of the memory wafers are electrically connected to the system control circuit, comprising: the third connecting structure on the first functional surface of one storage wafer is electrically contacted with the fifth through hole structure of the first nonfunctional surface of the other adjacent storage wafer, the third connecting structure and the fifth through hole structure which are electrically contacted are in one-to-one correspondence, the fifth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and a plurality of word lines corresponding to the positions of the storage wafers are connected to the system control circuit in series through the third connecting structure and the fifth through hole structure; the seventh through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of one sixth through hole structure are respectively and electrically connected with the system control circuit of the system control wafer and one seventh through hole structure or one sixth through hole structure of the storage wafer, or two ends of one sixth through hole structure are respectively and electrically connected with one seventh through hole structure of one storage wafer and one sixth through hole structure of the other storage wafer, or two ends of one sixth through hole structure are respectively and electrically connected with one sixth through hole structure of one storage wafer and one sixth through hole structure of the other storage wafer.

15. The semiconductor structure of claim 11, wherein a first functional surface of the memory wafer bonded to a system control wafer is oriented toward a second functional surface of the system control wafer.

16. The semiconductor structure of claim 15, wherein the memory wafer further comprises: and a plurality of eighth via structures extending from the first functional surface to the first nonfunctional surface, any one of the eighth via structures being electrically connected to one of the bit lines.

17. The semiconductor structure of claim 16, wherein two adjacent memory wafers are bonded in pairs, and one or more memory cells of the memory wafers are electrically connected to the system control circuit, comprising: the third connecting structure on the first functional surface of one storage wafer is electrically contacted with the fifth through hole structure of the first nonfunctional surface of the adjacent other storage wafer, the third connecting structure and the fifth through hole structure which are electrically contacted are in one-to-one correspondence, the third connecting structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer, and a plurality of word lines corresponding to the positions of the storage wafers are connected to the system control circuit in series through the third connecting structure and the fifth through hole structure; the eighth through hole structure of the storage wafer bonded with the system control wafer is electrically connected with the system control circuit of the system control wafer; and two ends of the sixth through hole structure are respectively and electrically connected with a system control circuit of the system control wafer and an eighth through hole structure or a sixth through hole structure of the storage wafer, or two ends of the sixth through hole structure are respectively and electrically connected with an eighth through hole structure of the storage wafer and a sixth through hole structure of another storage wafer, or two ends of the sixth through hole structure are respectively and electrically connected with a sixth through hole structure of the storage wafer and a sixth through hole structure of another storage wafer.

18. The semiconductor structure of claim 3, wherein the second nonfunctional side of the system control wafer in one of the plurality of vertically stacked units is bonded to the first functional side or the first nonfunctional side of the memory wafer in another of the plurality of stacked units, the system control circuit in the system control wafer of the plurality of stacked units being electrically connected to the system control circuit in the bottommost system control wafer through the memory wafer.

19. The semiconductor structure of claim 1, wherein the system control circuit comprises: one or both of logic circuitry and analog circuitry; the logic circuit includes: a combination of one or more of a sampling amplifier circuit, a word line driving circuit, a data channel circuit, a power supply circuit, a clock circuit, a control circuit, and an input-output circuit; the analog circuit includes: a combination of one or more of a sampling amplifier circuit, a word line driving circuit, a data channel circuit, a power supply circuit, a clock circuit, a control circuit, and an input-output circuit.