CN116366052A - Isolated data retention system - Google Patents

Abstract

The present invention provides an isolated data retention system comprising: the front-stage subsystem and the rear-stage subsystem respectively work in different power domains, and the two power domains are respectively and independently powered on or powered off; the front-stage subsystem is used for performing control configuration when the power domain is electrified so as to output a control configuration signal to the rear-stage subsystem, and the rear-stage subsystem outputs a control execution signal to the peripheral circuit according to the control configuration signal; and the isolation domain is respectively connected with the front-stage subsystem and the rear-stage subsystem and is used for isolating the front-stage subsystem and the rear-stage subsystem so that after the front-stage subsystem is powered off, the control configuration signal is kept in the configuration before power off. The beneficial effects are that: the front subsystem is controlled and configured when being electrified, and after power failure, the control configuration signal is kept to be configured before power failure through the isolation domain, so that power failure storage can be automatically realized through a hardware structure while power consumption is reduced, customization is not needed, software intervention is not needed, and cost is reduced.

Description

Isolated data retention system

Technical Field

The invention relates to the field of semiconductor power devices, in particular to an isolated data retention system.

Background

The gate control Power (Power Gating) technology divides all the functional subsystems of the chip under different Power domains, and the Power consumption overhead of the dormancy subsystem is reduced to zero by independently controlling the turn-off of the Power supply of all the subsystems, so that the gate control Power (Power Gating) technology is a common and effective low-Power design means.

However, in practical application, the gating power supply technology has the situation that the front subsystem is in a power-off state and the rear subsystem communicated with the gating power supply technology is in a working state, in this case, the output of the front subsystem is likely to be in an intermediate level for a long time after power is off, so that normally open NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) tubes in the rear subsystem can be caused, a large amount of through Current (Crowbar Current) is caused, and even the system is damaged in severe cases.

In the prior art, the state before power failure is saved in a software mode, for example, the configuration value of a power failure domain is latched into FLASH, data in FLASH is read out after power supply is restored, the value before power failure is restored, an additional software intervention system is required, the software is required to be designed in a full customization mode, the cost is high, and meanwhile, the FLASH can further cause power consumption waste.

The foregoing background is only for the purpose of providing an understanding of the inventive concepts and technical aspects of the present invention and is not necessarily prior art to the present application and is not intended to be used to evaluate the novelty and creativity of the present application in the event that no clear evidence indicates that such is already disclosed at the filing date of the present application.

Disclosure of Invention

In order to solve the technical problems, the invention provides an isolated data retention system.

The technical problems solved by the invention can be realized by adopting the following technical scheme:

an isolated data retention system, comprising:

the front-stage subsystem and the rear-stage subsystem respectively work in different power domains, and the two power domains are respectively and independently powered on or powered off;

the front-stage subsystem is used for performing control configuration when the power domain is electrified so as to output a control configuration signal to the rear-stage subsystem, and the rear-stage subsystem outputs a control execution signal to a peripheral circuit according to the control configuration signal;

and the isolation domain is respectively connected with the front-stage subsystem and the rear-stage subsystem and is used for isolating the front-stage subsystem and the rear-stage subsystem so that the control configuration signal is kept in a configuration before power failure after the front-stage subsystem is powered off.

Preferably, the front stage subsystem and the back stage subsystem operate in different clock domains.

Preferably, the pre-stage subsystem comprises:

the configuration event generator is used for carrying out configuration of control event generation signals under the effect of effective configuration writing signals and outputting the configuration event generation signals to the isolation domain;

the configuration register is used for carrying out configuration of the output signal of the control register according to a configuration valid signal under the effect of the configuration writing signal and outputting the configuration to the isolation domain;

the control configuration signal includes the control event occurrence signal and the control register output signal.

Preferably, the configuration event generator comprises:

the two input ends of the first data selector are respectively connected with the Q output end and the Q non-output end of a first D trigger, and the chip selection signal end of the first data selector is connected with the configuration writing signal;

the input end of the first D trigger is connected with the output end of the first data selector, the clock signal end of the first D trigger is connected with a first clock signal, and the Q output end of the first D trigger outputs the control event occurrence signal.

Preferably, the configuration register includes:

a second data selector, a first input end of the second data selector is connected with the configuration valid signal, a second input end of the second data selector is connected with a Q output end of a second D trigger, and a chip selection signal end of the second data selector is connected with the configuration write signal;

the input end of the second D trigger is connected with the output end of the second data selector, the clock signal end of the second D trigger is connected with a first clock signal, and the Q output end of the second D trigger outputs the control register output signal.

Preferably, the isolation domain includes:

the system comprises a first ISO isolation module, a configuration event generator and a second ISO isolation module, wherein the enabling end of the first ISO isolation module is respectively connected with a power domain closing signal, and the input end of the first ISO isolation module is connected with the configuration event generator;

and the enabling end of the second ISO isolation module is connected with a power domain closing signal, and the input end of the second ISO isolation module is connected with the configuration register.

Preferably, the rear stage subsystem includes:

the state event module is connected with the output end of the first ISO isolation module;

and the state memory is respectively connected with the output of the second ISO isolation module and the state event module and is used for outputting the control execution signal according to the output signal of the first ISO isolation module under the control of receiving the output signal of the state event module.

Preferably, the status event module includes:

the input end of the third D trigger is connected with the output end of the first ISO isolation module, and the clock signal end of the third D trigger is connected with a second clock signal;

the input end of the fourth D trigger is connected with the Q output end of the third D trigger, and the clock signal end of the fourth D trigger is connected with the second clock signal;

the input end of the fifth D trigger is connected with the Q output end of the fourth D trigger, and the clock signal end of the fifth D trigger is connected with the second clock signal;

and the input end of the exclusive-or gate is respectively connected with the input end and the Q output end of the fifth D trigger, and the output end of the exclusive-or gate is connected with the state memory.

Preferably, the state memory includes:

the first input end of the third data selector is connected with the second ISO isolation module, the second input end of the third data selector is connected with the Q output end of a sixth D trigger, and the chip selection signal end of the third data selector is connected with the state event module;

and the input end of the sixth D trigger is connected with the output end of the third data selector, and the Q output end of the sixth D trigger outputs the control execution signal.

The technical scheme of the invention has the advantages that:

the invention provides an isolated data retention system, wherein a pre-stage subsystem is controlled and configured when power is on, a control configuration signal is kept as configuration before power failure through an isolated domain after power failure, power failure is reduced, meanwhile, power failure storage can be automatically realized through a hardware structure, customized software intervention control is not needed, and cost is reduced.

Drawings

FIG. 1 is a schematic diagram of an isolated data retention system according to a preferred embodiment of the present invention;

FIG. 2 is a block diagram showing the implementation of the isolated data retention system according to the preferred embodiment of the present invention;

FIG. 3 is a schematic diagram of an embodiment of an isolated data retention system according to the present invention;

FIG. 4 is a functional timing diagram of an isolated data retention system according to a preferred embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

Before detailing the function of the isolated data retention system, the function of the 4 standard cells used in the embodiments of the present invention, which are standard cell logic commonly used in digital integrated circuits, are briefly described herein, and are generally known structures and techniques for convenience of the following description:

the data selector MUX selects a specified one of a group of input signals to be supplied to the combinational logic circuit of the output terminal based on a given input address code. The embodiment of the invention adopts a standard alternative unit, and the logic function of the unit is as follows: when the chip select signal terminal S is at a high level '1', a signal of the first input terminal I1 is selected to be output to the output terminal O, and when the chip select signal terminal S is at a low level '0', a signal of the second input terminal I2 is selected to be output to the output terminal O.

The flip-flop is a sequential logic component with memory function applied to digital circuit, and can record binary digital signals "1" and "0". The D flip-flop DFF is a standard D flip-flop whose logic function is: when the clock signal terminal CK is at the rising edge, the value of the D input terminal is stored and output to the Q output terminal,

the output terminal is the inverse of the value of the D input terminal.

ISO is a standard isolation unit, whose function is to maintain a stable level at the output terminal O after the power domain in which the input terminal I is located is powered off. The specific logic functions are as follows: the enable end EN is a high level '1', and the output end O keeps a stable low level or a high level no matter whether the input end I supplies power or not, so that the logic of a power-on power domain using the signal can work normally, namely a later-stage subsystem can still work normally. The level of the output O may be either high OR low by selecting different implementations, typically distinguished by ISO AND OR ISO OR in a standard cell library. Since the output of the ISO is high or low in the first ISO isolation module and the second ISO isolation module, the first ISO isolation module and the second ISO isolation module can work normally, and the method is not limited.

XOR is a standard two-input exclusive OR gate, whose functional logic is: when the first input terminal I1 and the second input terminal I2 are the same, the output terminal O is at a low level '0', and when the first input terminal I1 and the second input terminal I2 are different, the output terminal O is at a high level '1'.

In the existing multi-power-domain and multi-clock-domain systems, in order to reduce the power consumption overhead, the system is put into a sleep mode, most of logic of the system is in a power-down (power-off) state in the sleep mode, and only a small part of logic is in a power-on state, and the system is woken up after waiting for a specific wake-up action to occur, namely the whole system is powered on again to operate. While the system may be maintained in sleep mode with very low power consumption overhead, interactions between the systems after power failure may damage the system.

In accordance with the foregoing problems with the prior art, the present invention provides an isolated data retention system that supports multiple power domains and spans clock domains, as shown in fig. 1, comprising:

a front-stage subsystem 1 and a rear-stage subsystem 2 respectively work in different power domains, and the two power domains are respectively and independently powered on or powered off;

the front-stage subsystem 1 is used for performing control configuration when the power domain is electrified so as to output a control configuration signal to the rear-stage subsystem 2, and the rear-stage subsystem 2 outputs a control execution signal to the peripheral circuit according to the control configuration signal;

and an isolation domain 3, which is respectively connected with the front-stage subsystem 1 and the rear-stage subsystem 2 and is used for isolating the front-stage subsystem 1 and the rear-stage subsystem 2 so as to keep the control configuration signal in the configuration before power failure after the front-stage subsystem 1 is powered off.

Further, in this embodiment, the method further includes: the Power control method comprises the steps of a first Power Domain power_domain_A and a second Power Domain power_domain_B, wherein a front subsystem 1 works in the first Power Domain power_domain_A; the back-end subsystem 2 operates in a second Power Domain power_domain_b. In both power domains, the front stage subsystem 1 outputs signals to control the operation of the back stage subsystem 2.

Further, to obtain more excellent on-chip power consumption, two power domains may be configured to be turned off or operated independently, respectively. Under the scene that the current-stage subsystem 1 is powered off and the later-stage subsystem 2 is still powered on, the output control configuration signal of the current-stage subsystem 1 can still keep the previous configuration after the power is off through the function of the isolation domain 3, so that the control function of the current-stage subsystem is ensured and the influence of the power failure of the working power domain is avoided.

Preferably, for example, when the control configuration signal is an enable signal, whether the subsequent subsystem 2 is operated is controlled by the enable signal. The front subsystem 1 is powered off (i.e. powered off) before, if the configured enable signal is valid, then the enable signal remains valid after it is powered off; if the configured enable signal is inactive, the enable signal remains inactive after it is powered down.

As a preferred embodiment, the front stage subsystem 1 and the back stage subsystem 2 operate in different clock domains.

Further, in this embodiment, the system further includes a first clock domain clk_a and a second clock domain clk_b, where the front subsystem 1 operates in the first clock domain clk_a and the rear subsystem 2 operates in the second clock domain clk_b.

Further, as shown in fig. 1, the system of the embodiment of the present invention includes: 3 input signals, namely a configuration Write signal CONFIG_Write, a configuration Valid signal CONFIG_valid and a power domain off signal SLEEP_On;1 output signal, i.e. the control execution signal STATE Valid, i.e. the signal that actually performs the control action. The combination of the configuration Write signal config_write and the configuration Valid signal config_valid is used for configuring a control value of the control configuration signal, and the working relationship is as follows: when the configuration Write signal config_write is Valid, the value of the configuration Valid signal config_valid is taken as the control configuration signal. Further, when the Power Domain off signal sleep_on is at a low level, the first Power Domain power_domain_a and the second Power Domain power_domain_b both work normally in a Power-On state; when the Power Domain off signal sleep_on is at a high level, the first Power Domain power_domain_a is powered off, and the second Power Domain power_domain_b continues to operate normally powered On.

Further, all signals in the front stage subsystem 1 operate in the first Power Domain power_domain_a and the first clock Domain clk_a, and all signals in the isolation Domain 3 and the rear stage subsystem 2 operate in the second Power Domain power_domain_b and the second clock Domain clk_b. For example, the configuration Write signal config_write and the configuration Valid signal config_valid operate in the first Power Domain power_domain_a and the first clock Domain clk_a; the Power Domain off signal sleep_on and the control execution signal state_valid operate under the second Power Domain power_domain_b and the second clock Domain clk_b.

As a preferred embodiment, wherein, as shown in fig. 2, the front stage subsystem 1 comprises:

a configuration EVENT generator 11 for performing configuration of the control EVENT generation signal CON_event_GEN under the effect of the configuration Write signal CONFIG_write and outputting the configuration EVENT generation signal CON_event_GEN to the isolation domain 3;

a configuration register 12 for performing configuration of the control register output signal CON_REG_OUT according to a configuration Valid signal CONFIG_valid under the effect of the configuration Write signal CONFIG_write and outputting to the isolation domain 3;

the control configuration signals include control event occurrence signals and control register output signals.

Specifically, in this embodiment, the front subsystem 1, i.e. the control configuration master domain, implements control configuration through the configuration EVENT generator 11 and the configuration register 12, where the input of the configuration EVENT generator 11 is a configuration Write signal config_write, the output is a control EVENT occurrence signal con_event_gen, and the output is transmitted to the rear subsystem 2 through the isolation domain 3; the configuration register 12 has an input of a configuration Write signal config_write and a configuration Valid signal config_valid, and an output of a control register output signal con_reg_out, and the output is transmitted to the subsequent subsystem 2 through the isolation domain 3.

As a preferred embodiment, wherein, as shown in fig. 2 and 3, the isolation domain 3 includes:

the enabling end of the first ISO isolation module 31 is respectively connected with a power domain shutdown signal sleep_on, and the input end of the first ISO isolation module 31 is connected with the configuration EVENT generator 11, namely receives a control EVENT generation signal con_event_gen;

the second ISO isolation module 32, the enable terminal of the second ISO isolation module 32 is connected to a power domain shutdown signal sleep_on, and the input terminal of the second ISO isolation module 32 is connected to the configuration register 12, i.e. receives the control register output signal con_reg_out.

Specifically, in this embodiment, after the current stage subsystem 1 is powered off through the isolation domain 3, the subsequent stage subsystem 2 can still work normally. Further, the isolation domain 3 specifically includes two ISO isolation modules, and the first ISO isolation module 31 outputs a con_event_iso signal to the rear subsystem 2 according to the power domain shutdown signal sleep_on and the control EVENT occurrence signal con_event_gen; the second ISO isolation module 32 outputs the con_reg_iso signal to the rear subsystem 2 according to the power domain off signal sleep_on control register output signal con_reg_out.

As a preferred embodiment, wherein, as shown in fig. 2, the rear stage subsystem 2 includes:

a state event module 21 connected to the output of the first ISO isolation module 31;

a STATE memory 22 connected to the output of the second ISO isolation module 32 and the STATE event module 21, respectively, for outputting a control execution signal state_valid according to the output signal of the first ISO isolation module 31 under the control of the output signal of the receiving STATE event module 21.

Specifically, in the present embodiment, the subsequent subsystem 2, i.e. the control generation execution domain, implements generation of a control execution signal state_valid through the STATE event module 21 and the STATE memory 22, where the control execution signal is used to actually perform a signal of a control action.

Further, the input of the STATE EVENT module 21 is CON_EVENT_ISO, and the output is STATE_UPDATE_EN; the state memory 22 includes 2 input signals, namely: the state_update_en signal output by the STATE event module 21 and the con_reg_iso signal output by the second ISO isolation module 32, where the output of the STATE memory 22 is a control execution signal state_valid, which is an output signal of an isolated data holding structure supporting multiple power domains and crossing clock domains.

As a preferred embodiment, wherein, as shown in fig. 3, the configuration event generator 11 includes:

a first data selector 111, two input ends of the first data selector 111 are respectively connected to the Q output end and the Q non-output end of a first D flip-flop 112, and a chip select signal end of the first data selector 111 is connected to the configuration Write signal config_write;

the input terminal of the first D flip-flop 112 is connected to the output terminal of the first data selector 111, the clock signal terminal of the first D flip-flop 112 is connected to a first clock signal clk_a, and the Q output terminal of the first D flip-flop 112 outputs the control event occurrence signal con_reg_out.

As a preferred embodiment, wherein, as shown in fig. 3, the configuration register 12 includes:

a second data selector 121, a first input terminal of the second data selector 121 is connected to the configuration valid signal, a second input terminal of the second data selector 121 is connected to a Q output terminal of a second D flip-flop 122, and a chip select signal terminal of the second data selector 121 is connected to the configuration Write signal config_write;

the input terminal of the second D flip-flop 122 is connected to the output terminal of the second data selector 121, the clock signal terminal of the second D flip-flop 122 is connected to a first clock signal clk_a, and the Q output terminal of the second D flip-flop 122 outputs the control register output signal con_event_gen.

As a preferred embodiment, wherein, as shown in fig. 3, the status event module 21 includes:

the input end of the third D flip-flop 211 is connected to the output end of the first ISO isolation module 31, i.e. inputs the con_event_iso signal, and the clock signal end of the third D flip-flop 211 is connected to a second clock signal clk_b_g;

a fourth D flip-flop 212, an input terminal of the fourth D flip-flop 212 is connected to the Q output terminal of the third D flip-flop 211, and a clock signal terminal of the fourth D flip-flop 212 is connected to the second clock signal clk_b_g;

a fifth D flip-flop 213, an input terminal of the fifth D flip-flop 213 is connected to the Q output terminal of the fourth D flip-flop 212, and a clock signal terminal of the fifth D flip-flop 213 is connected to the second clock signal clk_b_g;

an exclusive-or gate 214, wherein an input terminal of the exclusive-or gate 214 is connected to the input terminal and the Q output terminal of the fifth D flip-flop 213, respectively, an output terminal of the exclusive-or gate 214 is connected to the state memory 22, and the exclusive-or gate 214 outputs the valid_cap signal to the state memory 22.

As a preferred embodiment, wherein, as shown in fig. 3, the state memory 22 comprises:

a third data selector 221, wherein a first input terminal I1 of the third data selector 221 is connected to the second ISO isolation module 32, a second input terminal I2 of the third data selector 221 is connected to the Q output terminal of a sixth D flip-flop 222, and a chip select signal terminal S of the third data selector 221 is connected to the state event module 21;

an input terminal of the sixth D flip-flop 222 is connected to the output terminal of the third data selector 221, a Q output terminal of the sixth D flip-flop 222 outputs the control execution signal state_valid, and a clock signal terminal of the sixth D flip-flop 222 is connected to the clock signal clk_b.

FIG. 4 is a functional timing diagram showing the implementation of the preferred embodiment of the present invention. The relevant waveform symbols are defined as follows:

clk_a: a first clock signal waveform that is a first clock domain;

config_write: to configure the waveform of the write signal;

config_valid: to configure the waveform of the effective signal;

clk_b: a second clock signal waveform that is a second clock domain;

SLEEP_On: a control waveform for a power domain off signal;

state_valid: waveform of control execution signal outputted for the subsequent stage subsystem 2.

When the configuration Write signal is Valid during the Power-up period of the first Power Domain power_domain_a, i.e. config_write=1, config_valid=1 is written into state_valid=1;

when the Power of the first Power Domain power_domain_a is turned off, the config_valid is not asserted, but the control execution signal state_valid remains high during this period.

In the preferred embodiment, the functional logic to be adopted in the present application is all standard cells in a standard cell library commonly used in a digital semi-custom process, and specifically includes a data selector, a D flip-flop, an ISO isolation module, and a two-input exclusive-or gate. The design of the isolated data retention system can be realized by only adopting the four common standard units, and the system is not limited by a standard unit library when being used, so that the universality of the system is improved.

The two features of the system of the invention are: firstly, the power-off preservation can be automatically realized through a hardware structure without software operation; and secondly, the method can be realized based on a common standard cell library, and a special data holding unit is not needed.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.

Claims (9)

1. An isolated data retention system, comprising:

the front-stage subsystem and the rear-stage subsystem respectively work in different power domains, and the two power domains are respectively and independently powered on or powered off;

the front-stage subsystem is used for performing control configuration when the power domain is electrified so as to output a control configuration signal to the rear-stage subsystem, and the rear-stage subsystem outputs a control execution signal to a peripheral circuit according to the control configuration signal;

and the isolation domain is respectively connected with the front-stage subsystem and the rear-stage subsystem and is used for isolating the front-stage subsystem and the rear-stage subsystem so that the control configuration signal is kept in a configuration before power failure after the front-stage subsystem is powered off.

2. The isolated data retention system of claim 1, wherein the pre-stage subsystem and the post-stage subsystem operate in different clock domains.

3. The isolated data retention system of claim 1, wherein the pre-stage subsystem comprises:

the configuration event generator is used for carrying out configuration of control event generation signals under the effect of effective configuration writing signals and outputting the configuration event generation signals to the isolation domain;

the configuration register is used for carrying out configuration of the output signal of the control register according to a configuration valid signal under the effect of the configuration writing signal and outputting the configuration to the isolation domain;

the control configuration signal includes the control event occurrence signal and the control register output signal.

4. The isolated data retention system of claim 3, wherein the configuration event generator comprises:

the two input ends of the first data selector are respectively connected with the Q output end and the Q non-output end of a first D trigger, and the chip selection signal end of the first data selector is connected with the configuration writing signal;

the input end of the first D trigger is connected with the output end of the first data selector, the clock signal end of the first D trigger is connected with a first clock signal, and the Q output end of the first D trigger outputs the control event occurrence signal.

5. The isolated data retention system of claim 3, wherein the configuration register comprises:

a second data selector, a first input end of the second data selector is connected with the configuration valid signal, a second input end of the second data selector is connected with a Q output end of a second D trigger, and a chip selection signal end of the second data selector is connected with the configuration write signal;

the input end of the second D trigger is connected with the output end of the second data selector, the clock signal end of the second D trigger is connected with a first clock signal, and the Q output end of the second D trigger outputs the control register output signal.

6. The isolated data retention system of claim 3, wherein the isolated domain comprises:

the system comprises a first ISO isolation module, a configuration event generator and a second ISO isolation module, wherein the enabling end of the first ISO isolation module is respectively connected with a power domain closing signal, and the input end of the first ISO isolation module is connected with the configuration event generator;

and the enabling end of the second ISO isolation module is connected with a power domain closing signal, and the input end of the second ISO isolation module is connected with the configuration register.

7. The isolated data retention system of claim 6, wherein the post-stage subsystem comprises:

the state event module is connected with the output end of the first ISO isolation module;

and the state memory is respectively connected with the output of the second ISO isolation module and the state event module and is used for outputting the control execution signal according to the output signal of the first ISO isolation module under the control of receiving the output signal of the state event module.

8. The isolated data retention system of claim 7, wherein the status event module comprises:

the input end of the third D trigger is connected with the output end of the first ISO isolation module, and the clock signal end of the third D trigger is connected with a second clock signal;

the input end of the fourth D trigger is connected with the Q output end of the third D trigger, and the clock signal end of the fourth D trigger is connected with the second clock signal;

the input end of the fifth D trigger is connected with the Q output end of the fourth D trigger, and the clock signal end of the fifth D trigger is connected with the second clock signal;

and the input end of the exclusive-or gate is respectively connected with the input end and the Q output end of the fifth D trigger, and the output end of the exclusive-or gate is connected with the state memory.

9. The isolated data retention system of claim 7, wherein the state memory comprises:

the first input end of the third data selector is connected with the second ISO isolation module, the second input end of the third data selector is connected with the Q output end of a sixth D trigger, and the chip selection signal end of the third data selector is connected with the state event module;

and the input end of the sixth D trigger is connected with the output end of the third data selector, and the Q output end of the sixth D trigger outputs the control execution signal.

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