CN116364683A - Packaging substrate structure for realizing direct interconnection between chips and manufacturing method thereof - Google Patents
Packaging substrate structure for realizing direct interconnection between chips and manufacturing method thereof Download PDFInfo
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- CN116364683A CN116364683A CN202310240744.XA CN202310240744A CN116364683A CN 116364683 A CN116364683 A CN 116364683A CN 202310240744 A CN202310240744 A CN 202310240744A CN 116364683 A CN116364683 A CN 116364683A
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims abstract description 115
- 229910052751 metal Inorganic materials 0.000 claims abstract description 115
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000001465 metallisation Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- 238000012536 packaging technology Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
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Abstract
The invention relates to a packaging substrate structure for realizing direct interconnection between chips, which comprises: a substrate; a first dielectric layer; the first chip is buried in the first dielectric layer in an upward right side of the chip and is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad; a second dielectric layer; the first metal through hole penetrates through the second dielectric layer and is electrically connected with the second bonding pad; the second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad; a third dielectric layer; the third metal through hole penetrates through the third dielectric layer and the second dielectric layer and is electrically connected with the first bonding pad; a fourth metal via penetrating the third dielectric layer and electrically connected to the second metal via; the top surfaces of the third metal through hole and the fourth metal through hole are respectively provided with a bonding pad; and the second chip is flip-chip bonded on the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer through the bumps.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging substrate structure for realizing direct interconnection between chips and a manufacturing method thereof.
Background
In the conventional packaging technology, in order to realize interconnection communication between chips, the interconnection communication between chips is generally realized through wiring of a packaging substrate or rewiring of an interposer (a silicon interposer, etc.). On the one hand, with the rapid development of artificial intelligence technology, 5G technology, portable mobile communication devices, etc., the I/O density of semiconductor devices such as CPU, GPU, HBM and FPGAs has been drastically increased, and Pad Pitch has been decreased, so that conventional organic package substrates have been insufficient to support the above-mentioned high-density interconnection between chips. On the other hand, in the technology of the silicon adapter board (S I-I inter-plane), the wiring on the S I-I inter-plane can realize the line width and line distance of micron and submicron level, so that the requirement of high-density interconnection among a plurality of heterogeneous chips can be met. The process flow of S I-I ntersupporter comprises: TSV (Through S I l I con Vi a) and RDLs (Red I str I but I on Layer) are fabricated on S I-I-inter-chip, then a plurality of chips are mounted on S I-I-inter-chip by flip-chip (fp-chip), and finally S I-I-inter-chip mounted on a Substrate (submount) to complete inter-chip and chip-to-Substrate interconnect communication. However, the S I-I inter-pass requires the formation of TSVs, which is complicated in process, high in cost and low in yield of TSVs with high aspect ratio, and is a major impediment factor for large-scale popularization of TSV technology.
In addition, the inter-chip interconnection communication is performed by substrate routing or by interposer rerouting, which may result in signal delay and loss due to the added inter-chip trace length.
Therefore, how to realize high-density and low-loss interconnection between chips without an interposer and without re-wiring is a big problem to be solved.
Disclosure of Invention
To solve at least some of the above problems in the prior art, the present invention provides a package substrate structure for realizing direct interconnection between chips, comprising:
a substrate, wherein the front surface of the substrate is provided with a substrate bonding pad;
the first dielectric layer is arranged on the front surface of the substrate;
the first chip is buried in the first dielectric layer in an upward right side, and is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad;
a second dielectric layer covering the first dielectric layer and the first chip;
the first metal through hole penetrates through the second dielectric layer and is electrically connected with the second bonding pad of the first chip;
the second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad;
a third dielectric layer covering the second dielectric layer;
a third metal through hole penetrating the third dielectric layer and the second dielectric layer and electrically connected with the first bonding pad of the first chip;
a fourth metal via penetrating the third dielectric layer and electrically connected to the second metal via; the top surfaces of the third metal through hole and the fourth metal through hole and the upper surface of the third dielectric layer are respectively provided with a bonding pad; and
and the second chip is flip-chip welded on the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer through the bumps.
Further, the method further comprises the following steps:
the first rewiring layer is arranged on the upper surface of the second dielectric layer and is electrically connected with the first metal through hole and the second metal through hole; and
and the second rewiring layer is arranged on the upper surface of the third dielectric layer and is electrically connected with the first metal through hole and the second metal through hole.
Further, the second chip has a first bump and a second bump having a size larger than the first bump.
Further, the size of the first bump is matched with the size of the third metal through hole, and the size of the second bump is matched with the size of a bonding pad on the upper surface of the third dielectric layer.
Further, the first bump is composed of a copper column and a solder ball positioned at the head of the copper column; and/or
The second bump is a solder ball.
Further, the aperture of the third metal through hole is smaller than that of the first metal through hole.
The invention also provides a manufacturing method of the packaging substrate structure for realizing direct interconnection between chips, which comprises the following steps:
arranging a first dielectric layer on the front surface of a substrate with a substrate bonding pad, and forming a chip embedded groove in the first dielectric layer;
embedding a first chip patch into a chip embedding groove, wherein the first chip is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad;
arranging a second dielectric layer on the first dielectric layer and the first chip;
forming a first through hole communicated with a second bonding pad of the first chip in the second dielectric layer, forming a second through hole communicated with a bonding pad of the substrate in the second dielectric layer and the first dielectric layer, carrying out metallization conductive filling on the first through hole and the second through hole to form a first metal through hole and a second metal through hole, forming bonding pads on the top surfaces of the first metal through hole and the second metal through hole, and forming a first rewiring layer electrically connected with the bonding pads on the upper surface of the second dielectric layer;
a third dielectric layer is arranged on the second dielectric layer;
forming a third through hole communicated with a first bonding pad of the first chip in the third dielectric layer and the second dielectric layer, forming a fourth through hole communicated with a bonding pad on the top surface of the second metal through hole in the third dielectric layer, carrying out metallization conductive filling on the third through hole and the fourth through hole to form a third metal through hole and a fourth metal through hole, forming bonding pads on the top surfaces of the third metal through hole and the fourth metal through hole and the area to be bonded with the second chip on the upper surface of the third dielectric layer, and forming a second rewiring layer electrically connected with the bonding pads on the upper surface of the third dielectric layer;
and flip-chip bonding the second chip to the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer.
Further, the second chip is provided with a first bump and a second bump with a size larger than that of the first bump, the size of the first bump is matched with that of the third metal through hole, and the size of the second bump is matched with that of the bonding pad on the upper surface of the third dielectric layer.
Further, the first bump is composed of a copper column and a solder ball positioned at the head of the copper column; and/or
The second bump is a solder ball.
Further, the aperture of the third metal through hole is smaller than that of the first metal through hole.
The invention has at least the following beneficial effects: the invention discloses a packaging substrate structure for realizing direct interconnection between chips and a manufacturing method thereof, wherein a first chip in the packaging substrate structure is provided with two types of chip bonding pads with different sizes and densities, wherein the first bonding pad is a high-density and small-size bonding pad, the second bonding pad is larger than the first bonding pad in size and smaller than the first bonding pad in density, the first bonding pad is used for interconnecting the first chip and the second chip, the second bonding pad is used for interconnecting the first chip and the substrate, and the metal through holes are used for realizing the face-to-face shortest distance interconnection between the first chip and the second chip, so that loss can be reduced, electrical performance is improved.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
FIG. 1 is a schematic cross-sectional view of a package substrate structure for implementing chip-to-chip interconnection in accordance with one embodiment of the present invention; and
fig. 2A to 2G are schematic cross-sectional views illustrating a process of fabricating a package substrate structure for realizing chip-to-chip interconnection according to an embodiment of the present invention.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale.
In the present invention, the embodiments are merely intended to illustrate the scheme of the present invention, and should not be construed as limiting.
In the present invention, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present invention.
It should also be noted herein that, within the scope of the present invention, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as limiting or implying any relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and not for limiting the order of the steps, and in different embodiments of the present invention, the order of the steps may be adjusted according to the adjustment of the process.
Fig. 1 is a schematic cross-sectional view of a package substrate structure for realizing chip indirect interconnection according to an embodiment of the present invention.
As shown in fig. 1, a package substrate structure for realizing chip interconnection includes a substrate 101, a first dielectric layer 102, a first chip 103, a second dielectric layer 104, a first metal via 105, a second metal via 106, a third dielectric layer 107, a third metal via 108, a fourth metal via 109, and a second chip 110.
The front side of the substrate 101 has substrate pads.
The first dielectric layer 102 covers the front surface of the substrate 101. The first dielectric layer 102 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F ii m), pi D (Photo Imageab l e D I e l ectr I cMater I a l), etc.
The first chip 103 is embedded in the first dielectric layer 102, and its back is connected to the front side of the substrate, and the front side with the chip pad faces upward and is substantially flush with the upper surface of the first dielectric layer 102. The first chip 103 has two specifications of chip pads, wherein the first pad of the first chip 103 is a high-density, small-size pad, and the second pad of the first chip 103 is a low-density, large-size pad, and the size of the second pad is larger than the size of the first pad. The first bonding pad of the first chip is used for realizing electric interconnection between the chips, and the second bonding pad of the first chip is used for realizing electric interconnection between the first bonding pad and the substrate. In one embodiment of the invention, the back side of the first chip is attached to the front side of the substrate by a back side adhesive material (e.g., adhesive).
The second dielectric layer 104 covers the first dielectric layer 102 and the first chip 103. The second dielectric layer 104 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F I lm), pid (Photo Imageab l eD I e l ectr I c Mater I a l), etc.
The first metal via 105 penetrates the second dielectric layer 104 and is electrically connected to the second pad of the first chip 103. The top surface of the first metal via 105 is provided with a pad.
The second metal via 106 penetrates the second dielectric layer 104 and the first dielectric layer 102 and is electrically connected to the substrate pad. The top surface of the second metal via 106 is provided with a pad.
A first re-wiring layer (not shown) is disposed on the upper surface of the second dielectric layer 104 and electrically connects the first metal via 105 and the second metal via 106.
The third dielectric layer 107 covers the second dielectric layer 104. The third dielectric layer 107 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F ii m) or pid (Photo Imageab l e D I e l ectr I cMater I a l).
The third metal via 108 penetrates the third dielectric layer 107 and the second dielectric layer 104 and is electrically connected to the first pad of the first chip 103. The aperture of the third metal via 108 is smaller than the aperture of the first metal via 105.
The fourth metal via 109 penetrates the third dielectric layer 107 and is electrically connected to the second metal via 106.
The top surfaces of the third metal via 108 and the fourth metal via 109 and the upper surface of the third dielectric layer 107 are provided with pads.
A second redistribution layer (not shown) is disposed on the upper surface of the third dielectric layer 107 and electrically connects the third metal via 108, the fourth metal via 109, and the pad on the upper surface of the third dielectric layer 107.
The second chip 110 is flip-chip bonded to the pads on the top surface of the third metal via 108 and the pads on the upper surface of the third dielectric layer 107 by bump bonding. The second chip 110 has two types of bumps, wherein the first bump 111 of the second chip is a high-density small-size bump, the first bump 111 is composed of a copper pillar and a solder ball located at the copper pillar head, and the second bump 112 of the second chip is larger in size and smaller in density, so that the solder ball is selected as the second bump, and the second bump 112 of the second chip is larger in size than the first bump 111 of the second chip. The size of the first bump 111 matches the size of the third metal via 108 and the size of the second bump 112 matches the size of the pad on the upper surface of the third dielectric layer. The first bump 111 of the second chip 110 is used to realize electrical interconnection between chips, and the second bump 112 of the second chip 110 is used to realize electrical interconnection with a substrate. The size and density of the first bumps 111 of the second chip 110 are determined according to different bandwidth requirements between the first chip 103 and the second chip 110 and the aperture of the third metal vias 108. The first chip 103 and the second chip 110 are directly interconnected through the third metal via 108, so as to realize communication.
In the above package substrate structure, the first chip 103 and the substrate 101 are electrically interconnected through the first metal via 105, the first redistribution layer and the second metal via 106, so as to transmit a power signal. The second chip 110 is electrically interconnected with the substrate 101 through the second redistribution layer, the fourth metal via 109, and the second metal via 106, and transmits a power signal. The bandwidth of the data transmission between the first chip 103 and the second chip 110 determines the size and density of the first pads and the first bumps 111 and the size and density of the third metal vias 108. The small-sized first pads and the first bumps 111 realize signal interconnection between chips through metal through holes, and realize face-to-face shortest distance interconnection, so that interconnection density can be increased, transmission distance can be reduced, and loss can be reduced to the greatest extent. The large-sized second pads and second bumps 112 enable power interconnection of the first and second chips with the substrate, increasing the current capacity.
Fig. 2A to 2G are schematic cross-sectional views illustrating a process of fabricating a package substrate structure for realizing chip-to-chip interconnection according to an embodiment of the present invention.
In step 1, as shown in fig. 2A, a first dielectric layer 202 is disposed on the front surface of a substrate 201 with a substrate pad, and a chip embedded groove 203 is formed in the first dielectric layer 202. The substrate pads are located on the front side of the substrate 201. In one embodiment of the present invention, the first dielectric layer 202 is disposed on the front side of the substrate 201 through a lamination process. The first dielectric layer 202 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F I lm), pid (Photo Imageab l e D I e l ectr I c Mater I a l), etc. The thickness of the first dielectric layer 202 is determined by the thickness of the embedded chip, and the thickness of the first dielectric layer 202 is generally greater than or equal to the thickness of the embedded chip.
In step 2, as shown in fig. 2B, a first chip 204 is mounted in the chip mounting groove 203, the first chip has chip pads of two specifications, wherein a first pad 2041 of the first chip is a high-density small-size pad, a second pad 2042 of the first chip is a low-density large-size pad, and a size of the second pad 2042 is larger than a size of the first pad 2041. The first pads 2041 of the first chip 204 are for making electrical interconnections between the chips, and the second pads 2042 of the first chip 2042 are for making electrical interconnections with the substrate. In one embodiment of the invention, the first chip 204 is attached to the chip embedded groove bottom by a paste.
Step 3, as shown in fig. 2C, a second dielectric layer 205 is disposed on the first dielectric layer 202 and the first chip 204. In one embodiment of the present invention, the second dielectric layer 205 is disposed on the first dielectric layer 202 and the first chip 204 by a lamination process. The second dielectric layer 205 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F ii m) or pi D (Photo Imageab l e D I e l ectr I cMater I a l). The thickness of the second dielectric layer 205 needs to be determined according to the pore size of the next opening.
Step 4, as shown in fig. 2D, a first via hole for connecting to the second pad of the first chip 204 is formed in the second dielectric layer 205, a second via hole for connecting to the pad of the substrate is formed in the second dielectric layer 205 and the first dielectric layer 202, the first via hole and the second via hole are metalized and filled with a conductive material, a first metal via 206 and a second metal via 207 are formed, pads are formed on top surfaces of the first metal via 206 and the second metal via 207, and a first rewiring layer (not shown) for electrically connecting to the pads is formed on an upper surface of the second dielectric layer. In one embodiment of the invention, the size of the first through hole is smaller than the size of the second through hole. In one embodiment of the invention, the first and second vias are formed by photolithographic or laser drilling. Preferably, the first via is formed by photolithographic opening and the second via is formed by laser opening. Through this step, the first chip 204 can be turned on with the substrate 201.
In step 5, as shown in fig. 2E, a third dielectric layer 208 is disposed on the second dielectric layer 205. In one embodiment of the present invention, the third dielectric layer 208 is disposed on the second dielectric layer 205 by a lamination process. The third dielectric layer 208 may be a common dielectric material such as ABF (Aj I nomoto Bu l I D-up F I lm) and pid (Photo Imageab l e D I e l ectr I c Mater I a l). The thickness of the third dielectric layer 208 needs to be determined according to the pore size of the next opening.
In step 6, as shown in fig. 2F, a third via hole communicating with the first pad of the first chip 204 is formed in the third dielectric layer 208 and the second dielectric layer 205, a fourth via hole communicating with the top surface pad of the second metal via hole 207 is formed in the third dielectric layer 208, the third via hole and the fourth via hole are subjected to metallization conductive filling, a third metal via hole 209 and a fourth metal via hole 210 are formed, a pad is formed on the top surfaces of the third metal via hole 209 and the fourth metal via hole 210 and a region where the upper surface of the third dielectric layer 208 is to be bonded with the second chip, and a second rewiring layer (not shown) electrically connected to the pad is formed on the upper surface of the third dielectric layer 208. The second redistribution layer electrically connects top surface pads of the third metal via 209 and the fourth metal via 210 and pads of the upper surface of the third dielectric layer 208. The aperture of the third metal via 209 is smaller than the aperture of the first metal via 206. In one embodiment of the invention, the size of the third through hole is smaller than the size of the fourth through hole. In one embodiment of the invention, the third and fourth vias are formed by photolithographic or laser drilling. Preferably, the third via is formed by photolithographic opening and the fourth via is formed by laser opening.
In step 7, as shown in fig. 2G, the second chip 211 is flip-chip bonded to the pad on the top surface of the third metal via 209 and the pad on the upper surface of the third dielectric layer 208, so as to complete the interconnection between the second chip 211 and the first chip 204 and the substrate 201. The second chip 211 has two types of bumps, wherein the first bump 212 of the second chip 211 is a high-density small-size bump, the first bump 212 is composed of a copper pillar and a solder ball located at the copper pillar head, and the second bump 213 of the second chip 211 is larger in size and smaller in density, so that the solder ball is selected as the second bump, and the size of the second bump 213 of the second chip 211 is larger than that of the first bump 212 of the second chip 211. The size of the first bump 212 matches the size of the third metal via 209, and the size of the second bump 212 matches the size of the pad on the upper surface of the third dielectric layer 208. The first bump 212 of the second chip 211 is used to realize electrical interconnection between chips, and the second bump 213 of the second chip 211 is used to realize electrical interconnection with a substrate. The size and density of the first bumps 212 of the second chip 211 are determined according to different bandwidth requirements between the first chip 204 and the second chip 211 and the aperture of the third metal vias 209. The first chip 204 and the second chip 211 are directly interconnected through the third metal via 209, so as to realize communication. The first chip 204 is electrically interconnected with the substrate 201 through the first metal via 206, the first re-wiring layer and the second metal via 207, and power signals are transferred. The second chip 211 is electrically interconnected with the substrate 201 through the second redistribution layer, the fourth metal via 210, and the second metal via 207, and transmits a power signal.
While certain embodiments of the present invention have been described herein, those skilled in the art will appreciate that these embodiments are shown by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the present teachings without departing from the scope of the invention. The appended claims are intended to define the scope of the invention and to cover such methods and structures within the scope of these claims themselves and their equivalents.
Claims (10)
1. A package substrate structure for realizing direct interconnection between chips, comprising:
a substrate, wherein the front surface of the substrate is provided with a substrate bonding pad;
the first dielectric layer is arranged on the front surface of the substrate;
the first chip is buried in the first dielectric layer in an upward right side, and is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad;
a second dielectric layer covering the first dielectric layer and the first chip;
the first metal through hole penetrates through the second dielectric layer and is electrically connected with the second bonding pad of the first chip;
the second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad;
a third dielectric layer covering the second dielectric layer;
a third metal through hole penetrating the third dielectric layer and the second dielectric layer and electrically connected with the first bonding pad of the first chip;
a fourth metal via penetrating the third dielectric layer and electrically connected to the second metal via; the top surfaces of the third metal through hole and the fourth metal through hole and the upper surface of the third dielectric layer are respectively provided with a bonding pad; and
and the second chip is flip-chip welded on the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer through the bumps.
2. The package substrate structure for achieving direct inter-chip interconnection of claim 1, further comprising:
the first rewiring layer is arranged on the upper surface of the second dielectric layer and is electrically connected with the first metal through hole and the second metal through hole; and
and the second rewiring layer is arranged on the upper surface of the third dielectric layer and is electrically connected with the first metal through hole, the second metal through hole and the bonding pad on the upper surface of the third dielectric layer.
3. The package substrate structure for achieving direct inter-chip interconnection of claim 1, wherein the second chip has a first bump and a second bump having a larger size than the first bump.
4. The package substrate structure for achieving direct inter-chip interconnection of claim 3, wherein a size of the first bump is matched with a size of the third metal via, and a size of the second bump is matched with a size of a pad on an upper surface of the third dielectric layer.
5. The package substrate structure for realizing direct interconnection between chips as defined in claim 3, wherein said first bump is composed of a copper pillar and a solder ball located at the copper pillar head; and/or
The second bump is a solder ball.
6. The package substrate structure for achieving direct inter-chip interconnection of claim 1, wherein the aperture of the third metal via is smaller than the aperture of the first metal via.
7. A manufacturing method of a packaging substrate structure for realizing direct interconnection between chips is characterized by comprising the following steps:
arranging a first dielectric layer on the front surface of a substrate with a substrate bonding pad, and forming a chip embedded groove in the first dielectric layer;
embedding a first chip patch into a chip embedding groove, wherein the first chip is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad;
arranging a second dielectric layer on the first dielectric layer and the first chip;
forming a first through hole communicated with a second bonding pad of the first chip in the second dielectric layer, forming a second through hole communicated with a bonding pad of the substrate in the second dielectric layer and the first dielectric layer, carrying out metallization conductive filling on the first through hole and the second through hole to form a first metal through hole and a second metal through hole, forming bonding pads on the top surfaces of the first metal through hole and the second metal through hole, and forming a first rewiring layer electrically connected with the bonding pads on the upper surface of the second dielectric layer;
a third dielectric layer is arranged on the second dielectric layer;
forming a third through hole communicated with a first bonding pad of the first chip in the third dielectric layer and the second dielectric layer, forming a fourth through hole communicated with a bonding pad on the top surface of the second metal through hole in the third dielectric layer, carrying out metallization conductive filling on the third through hole and the fourth through hole to form a third metal through hole and a fourth metal through hole, forming bonding pads on the top surfaces of the third metal through hole and the fourth metal through hole and the area to be bonded with the second chip on the upper surface of the third dielectric layer, and forming a second rewiring layer electrically connected with the bonding pads on the upper surface of the third dielectric layer;
and flip-chip bonding the second chip to the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer.
8. The method of manufacturing a package substrate structure for implementing direct inter-chip interconnection of claim 7, wherein the second chip has a first bump and a second bump having a size larger than the first bump, the size of the first bump is matched with the size of the third metal via, and the size of the second bump is matched with the size of the bonding pad on the upper surface of the third dielectric layer.
9. The method for manufacturing a package substrate structure for realizing direct interconnection between chips as defined in claim 8, wherein said first bump is composed of a copper pillar and a solder ball located at a copper pillar head; and/or
The second bump is a solder ball.
10. The method of manufacturing a package substrate structure for achieving direct inter-chip interconnection of claim 7, wherein the aperture of the third metal via is smaller than the aperture of the first metal via.
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