CN116364163A - Error correction method and system based on NAND flash memory controller - Google Patents
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Abstract
The invention belongs to the technical field of memory main control chips, and particularly provides an error correction method and system based on a NAND flash memory controller, wherein the method comprises the following steps: the input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number; the write-in data and the random number are sent to an optimizing data module for optimization, and finally the optimized data are stored in the NAND storage particles; the input end reads a reading instruction, reads data from the NAND memory particles, performs error correction processing, and performs optimization processing through the same random number as that when the data is written; and transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction. The invention can use a plurality of different types of flash memory particles widely by designing and using a design structure and a method capable of improving the error correction efficiency, solves the problem that the error correction efficiency is low or the error correction can not be carried out when a large number of continuous identical data are written in which are difficult to solve in the error correction technology in the existing memory main control chip, and particularly when the memory data are long 1 or long 0, and effectively improves the error correction performance of the memory main control chip.
Description
Technical Field
The invention relates to the technical field of memory main control chips, in particular to an error correction method and system based on a NAND flash memory controller.
Background
With the rapid development of flash memory storage, various NAND grain products have emerged, including SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Tri-Level Cell), and QLC (Quad-Level Cell) products. The data storage page size (page size) of each flash granule product is not exactly the same, with 1024 bytes (1K), 2048bytes (2K), 4096bytes (4K) and 8192bytes (8K), and 16KBytes for use in seeking greater efficiency, etc. The NAND grain is maintained in the initialized state data "1" when new data is not written, and the NAND flash grain is read page by page, and then ECC error correction processing is performed in the memory master. Taking the storage characteristics of a three-layer cell (TLC) NAND cell as an example, as shown in fig. 2 (a) - (c), fig. 2 (a) shows that when external data is written into and stored in a TLC NAND memory cell, different data stores are characterized by voltages of stored charges in the memory cell in different intervals; FIG. 2 (b) shows that when the externally written data is a large amount of the same or similar data (e.g., all "1" s or all "0 s"), the charge-voltage distribution in the multiple NAND memory cells will be nearly uniform; fig. 2 (c) shows that when the charge of the data storage unit is lost or the temperature is changed, the voltage of the charge in the storage unit is shifted, and thus, part of the data is wrong, and the ECC is needed to correct the data.
When the actual embedded memory chip is applied, the chip is usually a memory main control chip plus 1 or more NAND particles, such as a U disk, an SD card, an eMMC chip or a UFS chip. In the design of the memory master control chip, each page space is divided into a plurality of Sector structures (sectors) for data processing and storage during data writing, but the actual stored data size is not always written into the NAND memory granule according to a complete page capacity, so that a lot of data can be maintained in an initial state of '1' or '0', and the data written into the NAND granule is caused to be long '1' or '0'.
Once written data is presented with a large amount of the same data, such as long "1" or "0", error correction will inevitably result in reduced error correction efficiency, increased error correction iteration times, or even error correction failure. Taking low density parity check code (Low Density Parity Check Code) LDPC error correction as an example, the parity check matrix required when the code length is long is required to satisfy "sparsity", i.e., the density of "1" in the check matrix is relatively low, and the longer the code length, the lower the density. The page capacity of the mainstream NAND grain reaches 8KBytes or 16KBytes, after the page capacity is divided into 4 or 8 sectors, each Sector has 1K or 2KBytes, and the required check matrix is very large. As shown in fig. 3, during LDPC decoding and error correction, the error correction function is implemented after multiple iterations by estimating the posterior probability or likelihood ratio of each bit value in the codeword with respect to the received codeword and channel parameters and then performing decoding attempts on the data with large probability. If the written data is long 0 or long 1, the decision cannot be measured by the posterior probability or the log likelihood ratio, and the reliability calculation result of the code word obtained after the iteration is not effectively used as the input of the next iteration, so that the error correction performance of the NAND memory main control chip is easily reduced, and even errors are caused.
Therefore, in the existing memory master control design, a design structure and a method which can be suitable for high-efficiency decoding and error correction when a HOST end master chip sends a large amount of continuous identical data, especially when a large amount of long '1' or long '0' data has to be written into NAND particles when one page capacity data is not full, are lacked.
Disclosure of Invention
The invention aims at the technical problems of reduced error correction performance and even errors when a HOST end main chip transmits a large amount of continuous identical data in the prior art.
The invention provides an error correction method based on a NAND flash memory controller, which comprises the following steps:
s1, an input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number;
s2, sending the written data and the random number to an optimization data module for optimization;
s3, writing the optimized data into storage particles after error correction coding;
s4, acquiring a read instruction, reading data from the storage particles, and decoding and correcting the data;
s5, carrying out de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the read-out data and the write-in optimization;
s6, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
Preferably, the S1 specifically includes: when the Host end sends a write instruction, the storage main control chip transmits data to the write data buffer module, and meanwhile, when the storage main control chip judges that the storage main control chip instructs to start the Random generator, the Random data generation module generates a Random number Random Key according to the configuration of the register and the Trim table.
Preferably, the random data generating module in S1 specifically includes:
controlling each corresponding register in the Trim configuration module through configuration control signals and initialization Key signals;
the write/read control signal of the Host system is analyzed and judged through a write/read instruction analysis module, and then the state machine control is carried out in a state control module according to the indication signal of the Trim configuration module;
the random data generating module generates a plurality of random data.
Preferably, the S1 specifically includes:
firstly, the memory main control chip judges whether the write instruction or the read instruction, if the write instruction is the write instruction, the sector write operation is judged, whether the random number generation needs to be started or not, if the write instruction is the write instruction, the state machine judgment is carried out according to the write instruction and the NAND type, and finally the random data is generated.
Preferably, the S2 specifically includes:
in the optimized data module under the write instruction, NAND write data of 32 Bytes or 32xN Bytes and random numbers are subjected to exclusive nor (XNOR) processing.
Preferably, the step S3 specifically includes:
the optimized data is decoded by an ECC error correction module, and the data is written into the storage particles by a read-write instruction data processing module after the decoding processing.
Preferably, the S4 to S6 specifically include: when the Host end sends a read instruction, the read instruction firstly reads data from the NAND memory, after ECC decoding and error correction, the read data after error correction is subjected to the same random number as the random number subjected to the error correction and writing optimization by a data De-optimization module (De-random), the processed data is transmitted to a read data buffer module, and finally the data is transmitted from the read data buffer module to the Host end through the read instruction processing.
Preferably, the S4 specifically includes:
and reading the data from the storage particles through the read-write instruction data processing module, and transmitting the data to the ECC error correction module for data decoding and error correction.
Preferably, the step S5 specifically includes:
if the read command is the read command, judging the read operation of the sector, judging whether the derandomization operation is to be performed, if so, judging the state machine according to the read command and the NAND type, and starting the derandomization operation; in the data de-optimization module under the read instruction, NAND read data of 32 Bytes or 32xN Bytes is subjected to exclusive nor (XNOR) processing with randomized data.
The invention also provides an error correction system based on the NAND flash memory controller, which is used for realizing an error correction method based on the NAND flash memory controller and comprises the following steps:
the writing data caching module is used for acquiring writing instructions at the input end and writing data into the data caching module;
the random number generation module is used for generating random numbers;
the optimized data module is used for optimizing the written data and the random number, performing error correction coding on the optimized data and writing the data into the storage particles;
the ECC error correction module is used for acquiring a read instruction, reading data from the storage particles, and performing decoding error correction on the data;
the read-write instruction data processing module is used for processing the data under the write instruction or the read instruction so that the data can be transmitted to the NAND memory grain chip;
the de-optimization processing module is used for performing de-optimization processing on the read data subjected to error correction according to the random number which is the same as that in the write optimization;
and the read data caching module is used for transmitting the processed data to the read data caching module and reading the data to the Host system through the read instruction.
The beneficial effects are that: the invention provides an error correction method and system based on a NAND flash memory controller, wherein the method comprises the following steps: acquiring a write instruction, writing write data into a write data buffer module, and generating a random number; transmitting the written data and the random number to an optimization data module for optimization; performing error correction processing on the random number which is the same as the random number when writing data; and transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction. The invention can use a plurality of different types of flash memory particles widely by designing and using a design structure and a method capable of improving the error correction efficiency, solves the problem that the error correction efficiency is low or the error correction can not be carried out when a large number of continuous identical data are written in the error correction technology in the existing memory main control chip, especially when the memory data are long 1 or long 0, and effectively improves the error correction performance of the memory main control chip.
Drawings
FIG. 1 is a schematic diagram of an error correction method based on a NAND flash memory controller;
FIG. 2 (a) is a graph of TLC NAND voltage versus data storage distribution provided in the background;
FIG. 2 (b) shows the same voltage of the memory cell when writing a large amount of the same data, provided in the background art;
fig. 2 (c) is a graph of charge loss- > resulting in voltage offset- > data error provided in the background;
FIG. 3 is a diagram of a BP decoding algorithm of an LDPC code provided in the background art;
FIG. 4 is a schematic diagram of a random data generation module according to the present invention;
FIG. 5 is a schematic diagram of a state control module provided by the present invention;
FIG. 6 is a schematic diagram of an optimized data module provided by the present invention;
fig. 7 is a schematic hardware structure of a possible electronic device according to the present invention;
fig. 8 is a schematic hardware structure of a possible computer readable storage medium according to the present invention.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
Fig. 1 is a diagram showing an error correction method based on a NAND flash memory controller, which includes the following steps:
s1, an input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number;
s2, sending the written data and the random number to an optimization data module for optimization;
s3, writing the optimized data into storage particles after error correction coding;
s4, acquiring a read instruction, reading data from the storage particles, and decoding and correcting the data;
s5, carrying out de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the read-out data and the write-in optimization;
s6, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
In a specific implementation scenario, as shown in fig. 1, when the Host sends a write instruction, the storage master control chip writes write data into the write data buffer module, and at the same time, when the storage master control chip determines that the storage master control chip instructs to start the Random generator, the Random data generation module generates a Random number Random Key according to the configuration of the register and the Trim table.
Then the written data and Random Key input by the system are subjected to data conversion through an optimized data module (Random), the user data is encoded through an ECC error correction module, then each data is processed through a read-write command data processing module, and the data is written into the NAND particles through a NAND interface. When the Host sends a read instruction, the read instruction firstly reads data from the NAND memory, and after ECC decoding and error correction, the data module (De-Random) is removed to perform error correction processing on the Random number Random Key which is the same as that when the data is written.
And finally, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
In the Random data generation module, as shown in fig. 4, the Random data generation module includes a Trim configuration module, a write/read command analysis module, a state control module, and a Random data generation module (i.e., a Random number generation module). Configuring each corresponding register in the Trim module through a configuration control signal and an initialization Key control signal; the write/read control signal of the Host system is analyzed and judged through the write/read instruction analysis module, then the state machine control is carried out in the state control module according to the indication signal of the Trim module, and finally the Random data generation module generates a plurality of Random data of 32 or 32xN Byte bytes.
In the state control module, as shown in fig. 5, the main control chip is firstly stored to judge whether the main control chip is a write instruction or a read instruction, if the main control chip is the write instruction, the main control chip is judged to be the Sector (Sector N) write operation, whether random number production needs to be started or not, if the main control chip is the write instruction, the main control chip is judged to be the read instruction, and if the main control chip is the write instruction, the main control chip is judged to be the Sector (Sector N) write operation, and if the main control chip is the Sector (Sector N) write operation, the main control chip is judged to be the random number production needs to be started, the main control chip is judged to be the random number production, and if the main control chip is the Sector, the main control chip is judged to be the Sector, the Sector; eventually random data is generated.
If the read command is a read command, judging whether the write operation is performed on the sector, judging whether the derandomization operation is performed or not, if so, judging the state machine according to the read command, the NAND type and the like, and starting the derandomization operation.
For the optimized data module (random) and the De-optimized data module (De-random), the optimized data module (De-random) can share a set of operation algorithms and module processes, and the basic principle is that, as shown in fig. 6, the optimized data module performs exclusive nor (XNOR) processing on user data of 32 bytes or 32xN bytes and randomized data under a write command, which is as follows, for example:
user data: 00 00 00 00 0 0F F0 00 00 0F F F F0 00 0 00 00 00
Random data: 1 3a b e 4 7 6 24 8 9a b d 2 6d 3 5a 9 4 2 8 3 6 59 0a c
Writing NAND data: 1 3a b e 4 7 6 24 7 6a b d 2 6d c a 5 6 4 2 8 3 65 9 0a c
In the data de-optimization module under the read instruction, the NAND read data of 32 Bytes or 32xN Bytes and the randomized data are processed by exclusive nor (XNOR), such as the following data as examples:
NAND read data: 1 3a b e 4 7 6 24 7 6a b d 2 6d c a 5 6 4 2 8 3 65 9 0a c
Random data: 1 3a b e 4 7 6 24 8 9a b d 2 6d 3 5a 9 4 2 8 3 65 9 0a c
User data: 00 00 00 00 0 0F F0 00 00 0F F F F0 00 0 00 00 00
From the above example, it can be seen that a large amount of the same or similar data written by the system at the beginning can still be completely read to the system through 2 times of exclusive or non-processing of writing and reading.
After the data passes through the design structure and the method of the random data generation module and the optimized data module, the long '1' or the long '0' data are processed and optimized, so that the data processing efficiency of the ECC error correction module in the next step is effectively improved, and the risk of incapability of effectively correcting errors is reduced.
The embodiment of the invention also provides an error correction system based on the NAND flash memory controller, which is used for realizing the error correction method based on the NAND flash memory controller, and comprises the following steps:
the writing data caching module is used for acquiring writing instructions at the input end and writing data into the data caching module;
the random data generation module is used for generating random numbers;
the optimized data module is used for optimizing the written data and the random number, performing error correction coding on the optimized data and writing the data into the storage particles;
the ECC error correction module is used for acquiring a read instruction, reading data from the storage particles, and performing decoding error correction on the data;
the read-write instruction data processing module is used for processing the data under the write instruction or the read instruction so that the data can be transmitted to the NAND memory grain chip;
the de-optimization processing module is used for performing de-optimization processing on the read data subjected to error correction according to the random number which is the same as that in the write optimization;
and the read data caching module is used for transmitting the processed data to the read data caching module and reading the data to the Host system through the read instruction.
Fig. 7 is a schematic diagram of an embodiment of an electronic device according to an embodiment of the present invention. As shown in fig. 7, an embodiment of the present invention provides an electronic device, including a memory 1310, a processor 1320, and a computer program 1311 stored in the memory 1310 and executable on the processor 1320, wherein the processor 1320 executes the computer program 1311 to implement the following steps: s1, an input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number;
s2, sending the written data and the random number to an optimization data module for optimization;
s3, writing the optimized data into storage particles after error correction coding;
s4, acquiring a read instruction, reading data from the storage particles, and decoding and correcting the data;
s5, carrying out de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the read-out data and the write-in optimization;
s6, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
Fig. 8 is a schematic diagram of an embodiment of a computer readable storage medium according to the present invention. As shown in fig. 8, the present embodiment provides a computer-readable storage medium 1400 on which is stored a computer program 1411, which computer program 1411, when executed by a processor, implements the steps of: s1, an input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number;
s2, sending the written data and the random number to an optimization data module for optimization;
s3, writing the optimized data into storage particles after error correction coding;
s4, acquiring a read instruction, reading data from the storage particles, and decoding and correcting the data;
s5, carrying out de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the read-out data and the write-in optimization;
s6, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. An error correction method based on a NAND flash memory controller is characterized by comprising the following steps:
s1, an input end acquires a writing instruction, writes writing data into a writing data caching module and generates a random number;
s2, sending the written data and the random number to an optimization data module for optimization;
s3, writing the optimized data into storage particles after error correction coding;
s4, acquiring a read instruction, reading data from the storage particles, and decoding and correcting the data;
s5, carrying out de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the read-out data and the write-in optimization;
s6, transmitting the processed data to a read data buffer module, and reading the data to a Host system through a read instruction.
2. The error correction method based on a NAND flash memory controller of claim 1, wherein S1 specifically comprises: when the Host end sends a write instruction, the storage main control chip writes data into the data buffer module, and at the same time, when the storage main control chip judges that the Random generator is started, the Random data generation module generates a Random number Random Key according to the configuration of the register and the Trim table.
3. The error correction method based on the NAND flash memory controller as claimed in claim 1, wherein the random data generating module in S1 specifically comprises:
controlling each corresponding register in the Trim configuration module through configuration control signals and initialization Key signals;
the write/read control signal of the Host system is analyzed and judged through a write/read instruction analysis module, and then the state machine control is carried out in a state control module according to the indication signal of the Trim configuration module;
the random data generating module generates a plurality of random data.
4. The error correction method based on a NAND flash memory controller as claimed in claim 3, wherein S1 specifically comprises:
firstly, the memory main control chip judges whether the write instruction or the read instruction, if the write instruction is the write instruction, the sector write operation is judged, whether the random number generation needs to be started or not, if the write instruction is the write instruction, the state machine judgment is carried out according to the write instruction and the NAND type, and finally the random data is generated.
5. The error correction method based on a NAND flash memory controller of claim 1, wherein S2-S3 specifically comprises:
in the optimized data module under the write instruction, the write data of 32 Bytes or 32xN Bytes and the random number are processed by exclusive nor (XNOR) to generate optimized data.
6. The error correction method based on the NAND flash memory controller of claim 1, wherein S3 specifically comprises:
the optimized data is encoded through an ECC error correction module, and then the processed data is written into the storage particles through a read-write instruction data processing module.
7. The error correction method based on the NAND flash memory controller as claimed in claim 1, wherein the S4 to S6 specifically include: when the Host sends a read command, the read command firstly reads data from the NAND memory, after ECC decoding and error correction, the read data after error correction is subjected to the same random number generated during the read data and the write optimization in a data De-optimization module (De-random), then the processed data is transmitted to a read data buffer module, and finally the data is transmitted from the read data buffer module to the Host through the read command processing.
8. The error correction method based on the NAND flash memory controller as claimed in claim 7, wherein S4 specifically comprises:
and reading the data from the storage particles through the read-write instruction data processing module, and transmitting the data to the ECC error correction module for data decoding and error correction.
9. The error correction method based on the NAND flash memory controller as claimed in claim 7, wherein said S5 specifically comprises:
if the read command is the read command, judging the read operation of the sector, judging whether the derandomization operation is to be performed, if so, judging the state machine according to the read command and the NAND type, and starting the derandomization operation; in the data de-optimization module under the read instruction, data with the ECC error correction completed for 32 Bytes or 32xN Bytes and the same randomized data at the time of writing are subjected to exclusive nor (XNOR) processing.
10. An error correction system based on a NAND flash memory controller, characterized in that the system is adapted to implement the error correction method based on a NAND flash memory controller according to any of claims 1-9, comprising:
the writing data caching module is used for acquiring writing instructions at the input end and writing data into the data caching module;
the random data generation module is used for generating random numbers;
the optimizing data module is used for optimizing the written data and the random number and transmitting the optimized data to the ECC error correction module for processing;
the ECC error correction module is used for data encoding and decoding error correction, and when a write instruction is received, the input data is encoded; when the instruction is read, decoding and correcting errors are carried out on the data;
the read-write instruction data processing module is used for processing the data under the write instruction or the read instruction so that the data can be transmitted to the NAND memory grain chip;
the de-optimization processing module is used for performing de-optimization processing on the random numbers which are the same as the random numbers subjected to error correction during the write optimization of the read data;
and the read data caching module is used for transmitting the processed data to the read data caching module and reading the data to the Host system through the read instruction.
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