CN116364013A

CN116364013A - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN116364013A
Application number: CN202310357239.3A
Authority: CN
Inventors: 孙拓; 皇甫鲁江
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-04-04
Filing date: 2023-04-04
Publication date: 2023-06-30

Abstract

A pixel circuit, a driving method thereof, a display panel and a display device are provided, and belong to the technical field of display. In the pixel circuit, a control circuit can control the on-off of a data signal end and a first node based on a grid driving signal; based on the compensation control signal, controlling the on-off of the second node and the third node; and adjusting the potentials of the first node and the second node. The other control circuit can control the on-off of the reference power supply end and the first node based on the compensation control signal, and control the on-off of the initial power supply end and the third node/fourth node based on the reset control signal. The control circuit can control the on-off of the driving power supply end and the fifth node and control the on-off of the third node and the fourth node based on the light-emitting control signal. The driving circuit may transmit the driving signal to the third node based on the potentials of the second node and the fifth node. Therefore, the threshold voltage of the driving transistor in the driving circuit can be reliably compensated, and the good display effect is ensured.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

The display panel generally includes a substrate, and a plurality of pixels on the substrate. Each pixel comprises a pixel circuit and a light emitting element, wherein the pixel circuit is coupled with the light emitting element and used for driving the light emitting element to emit light.

In the related art, a pixel circuit generally includes a light emission control circuit and a light emission driving circuit. The light emission control circuit includes a plurality of control transistors, and the light emission driving circuit includes a driving transistor. And the control transistors are respectively coupled with the gate signal end, the data signal end and the like, and are also coupled with the gates of the driving transistors for controlling the potentials of the gates of the driving transistors. The first electrode of the driving transistor is used for receiving a driving power supply signal, and the second electrode of the driving transistor is used for being coupled with the light-emitting element so as to transmit the driving signal to the light-emitting element based on the potential of the grid electrode and the driving power supply signal, and therefore the light-emitting element is driven to emit light.

However, due to factors such as process and materials, uniformity and stability of semiconductor characteristics such as threshold voltage or mobility of each driving transistor are poor, and thus the light emitting element cannot be reliably driven to emit light, resulting in poor display effect of the display panel.

Disclosure of Invention

A pixel circuit, a driving method thereof, a display panel and a display device are provided, which can solve the problem that the display effect of the display panel is poor because the light-emitting element cannot be reliably driven to emit light due to poor uniformity and stability of semiconductor characteristics such as threshold voltage or mobility in the related art.

The technical scheme is as follows:

in one aspect, there is provided a pixel circuit including:

the first control circuit is respectively coupled with a first grid driving end, a compensation control end, a driving power end, a data signal end, a first node, a second node and a third node, and is used for controlling the on-off of the data signal end and the first node based on a first grid driving signal provided by the first grid driving end, controlling the on-off of the second node and the third node based on a compensation control signal provided by the compensation control end, and regulating the potential of the first node and the potential of the second node based on a driving power signal provided by the driving power end;

the second control circuit is coupled with the compensation control end, the reset control end, the reference power end, the first initial power end, the first node and the target node respectively, and is used for controlling the on-off of the reference power end and the first node based on the compensation control signal and controlling the on-off of the first initial power end and the target node based on the reset control signal provided by the reset control end, wherein the target node comprises: the third node or a fourth node, the fourth node being coupled to a light emitting element;

The third control circuit is respectively coupled with a first light-emitting control end, a second light-emitting control end, the driving power end, the third node, the fourth node and the fifth node, and is used for controlling the on-off of the driving power end and the fifth node based on a first light-emitting control signal provided by the first light-emitting control end and controlling the on-off of the third node and the fourth node based on a second light-emitting control signal provided by the second light-emitting control end;

and a driving circuit coupled to the second node, the fifth node, and the third node, respectively, and configured to transmit a driving signal to the third node based on a potential of the second node and a potential of the fifth node.

Optionally, the first control circuit includes:

the data writing sub-circuit is respectively coupled with the first grid driving end, the data signal end and the first node and is used for controlling the on-off of the data signal end and the first node based on the first grid driving signal;

the compensation sub-circuit is respectively coupled with the compensation control end, the second node and the third node and is used for controlling the on-off of the second node and the third node based on the compensation control signal;

And the regulating sub-circuit is respectively coupled with the driving power supply end, the first node and the second node and is used for regulating the potential of the first node and the potential of the second node based on the driving power supply signal.

Optionally, the data writing sub-circuit includes: a data writing transistor;

the gate of the data writing transistor is coupled to the first gate driving end, the first pole of the data writing transistor is coupled to the data signal end, and the second pole of the data writing transistor is coupled to the first node.

Optionally, the compensation sub-circuit includes: a compensation transistor;

the gate of the compensation transistor is coupled to the compensation control terminal, the first pole of the compensation transistor is coupled to the second node, and the second pole of the compensation transistor is coupled to the third node.

Optionally, the adjusting sub-circuit includes: a first capacitor and a second capacitor;

one end of the first capacitor is coupled with the driving power supply end, and the other end of the first capacitor is coupled with the first node;

one end of the second capacitor is coupled with the first node, and the other end of the first capacitor is coupled with the second node.

Optionally, the second control circuit includes:

the first reset sub-circuit is respectively coupled with the compensation control end, the reference power end and the first node and is used for controlling the on-off of the reference power end and the first node based on the compensation control signal;

and the second reset sub-circuit is respectively coupled with the reset control end, the first initial power end and the target node and is used for controlling the on-off of the first initial power end and the target node based on the reset control signal.

Optionally, the first reset sub-circuit includes: a first reset transistor;

the grid electrode of the first reset transistor is coupled with the compensation control end, the first electrode of the first reset transistor is coupled with the reference power end, and the second electrode of the first reset transistor is coupled with the first node.

Optionally, the second reset sub-circuit includes: a second reset transistor;

the gate of the second reset transistor is coupled to the reset control terminal, the first pole of the second reset transistor is coupled to the first initial power terminal, and the second pole of the second reset transistor is coupled to the target node.

Optionally, the pixel circuit further includes:

and the reset circuit is respectively coupled with the second grid driving end, the second initial power end and the second node and is used for controlling the on-off of the second initial power end and the second node based on a second grid driving signal provided by the second grid driving end.

Optionally, the reset circuit includes: a third reset transistor;

the gate of the third reset transistor is coupled to the second gate driving terminal, the first pole of the third reset transistor is coupled to the second initial power terminal, and the second pole of the third reset transistor is coupled to the second node.

Optionally, the third control circuit includes: a first light emission control transistor and a second light emission control transistor; the driving circuit includes: a driving transistor;

the grid electrode of the first light-emitting control transistor is coupled with the first light-emitting control end, the first electrode of the first light-emitting control transistor is coupled with the driving power supply end, and the second electrode of the first light-emitting control transistor is coupled with the fifth node;

the grid electrode of the second light-emitting control transistor is coupled with the second light-emitting control end, the first electrode of the second light-emitting control transistor is coupled with the third node, and the second electrode of the second light-emitting control transistor is coupled with the fourth node;

The gate of the driving transistor is coupled to the second node, the first pole of the driving transistor is coupled to the fifth node, and the second pole of the driving transistor is coupled to the third node.

In another aspect, there is provided a driving method of a pixel circuit, which is applied to the pixel circuit according to the above aspect, the method including: a refresh frame and a hold frame performed sequentially; wherein the refresh frame comprises: the first stage, the second stage, the third stage and the fourth stage are sequentially executed;

in the first stage, a first control circuit controls the second node and the third node to be conducted based on a compensation control signal provided by a compensation control end, a second control circuit controls a reference power end to be conducted with the first node based on the compensation control signal, controls a first initial power end to be conducted with a target node based on a reset control signal provided by a reset control end, and a third control circuit controls the third node to be conducted with a fourth node based on a second light-emitting control signal provided by a second light-emitting control end;

in the second stage, if the target node is the fourth node, the first control circuit controls the second node to be conducted with the third node based on the compensation control signal, the second control circuit controls the reference power supply terminal to be conducted with the first node based on the compensation control signal, controls the first initial power supply terminal to be conducted with the fourth node based on the reset control signal, and the third control circuit controls the driving power supply terminal to be conducted with the fifth node based on the first light-emitting control signal provided by the first light-emitting control terminal; if the target node is the third node, the first control circuit controls the second node to be conducted with the third node based on the compensation control signal, the second control circuit controls the reference power supply end to be conducted with the first node based on the compensation control signal, and the third control circuit controls the driving power supply end to be conducted with the fifth node based on the first light emitting control signal;

In the third stage, if the target node is the fourth node, the first control circuit controls the data signal end to be conducted with the first node based on a first gate driving signal provided by a first gate driving end, the second control circuit controls the first initial power end to be conducted with the fourth node based on the reset control signal, and the third control circuit controls the driving power end to be conducted with the fifth node based on the first light emitting control signal; if the target node is the third node, the first control circuit controls the data signal end to be conducted with the first node based on the first gate driving signal, and the third control circuit controls the driving power end to be conducted with the fifth node based on the first light emitting control signal;

in the fourth stage, the third control circuit controls the driving power supply terminal to be conducted with the fifth node based on the first light-emitting control signal, controls the third node to be conducted with the fourth node based on the second light-emitting control signal, and transmits a driving signal to the third node based on the potentials of the second node and the fifth node so as to control the light-emitting element coupled with the fourth node to emit light;

In the holding frame, the second control circuit controls the first initial power supply terminal to be conducted with the target node based on the reset control signal, and the third control circuit controls the third node to be conducted with the fourth node based on the second light-emitting control signal;

and in the refresh frame and the hold frame, the first control circuit adjusts the potential of the first node and the potential of the second node based on a driving power supply signal supplied from the driving power supply terminal.

Optionally, the pixel circuit further includes: a reset circuit; the method further comprises the steps of:

in the first stage, the reset circuit controls the second initial power supply terminal to be conducted with the second node based on a second gate driving signal provided by the second gate driving terminal.

In still another aspect, there is provided a display panel including: a substrate, and a plurality of pixels located at one side of the substrate;

wherein the pixel includes: a light emitting element, and a pixel circuit as described in the above aspect, the pixel circuit being coupled to the light emitting element and configured to drive the light emitting element to emit light.

In still another aspect, there is provided a display device including: a signal supply circuit, a display panel as described in the above further aspect;

The signal providing circuit is coupled with a plurality of signal terminals coupled with the pixel circuit in the display panel and is used for providing signals for the signal terminals so as to control the pixel circuit to drive the coupled light emitting element to emit light.

In summary, the beneficial effects brought by the technical solution provided by the embodiments of the present disclosure at least may include:

a pixel circuit including three control circuits and one driving circuit, a display panel, and a display device are provided. Wherein, a control circuit can control the on-off of the data signal end and the first node based on the grid driving signal; the on-off of the second node and the third node can be controlled based on another compensation control signal; and the potentials of the first node and the second node can be adjusted by a coupling action. The other control circuit may control the on-off of the reference power supply terminal and the first node based on the compensation control signal, and may control the on-off of the initial power supply terminal and the third/fourth node based on the reset control signal. The control circuit can control the on-off of the driving power supply end and the fifth node and control the on-off of the third node and the fourth node based on the light-emitting control signal. The driving circuit may transmit the driving signal to the third node based on the potentials of the second node and the fifth node. Therefore, the threshold voltage of the driving transistor in the driving circuit can be reliably compensated, and the display effect of the display panel is better.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another pixel circuit provided in an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a further pixel circuit provided in an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a further pixel circuit according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a further pixel circuit according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a further pixel circuit provided in an embodiment of the disclosure;

fig. 7 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of still another pixel circuit provided in an embodiment of the disclosure;

fig. 9 is a flowchart of a driving method of a pixel circuit provided in an embodiment of the present disclosure;

FIG. 10 is a timing diagram of operation of a pixel circuit in a refresh frame provided in an embodiment of the present disclosure;

FIG. 11 is a timing diagram of operation of another pixel circuit in a refresh frame provided by an embodiment of the present disclosure;

FIG. 12 is a timing diagram of operation of yet another pixel circuit in a refresh frame provided by an embodiment of the present disclosure;

FIG. 13 is a timing diagram of operation of a pixel circuit in a hold frame provided in an embodiment of the present disclosure;

FIG. 14 is a timing diagram of operation of another pixel circuit in a hold frame provided by an embodiment of the present disclosure;

fig. 15 is a schematic structural view of a display panel according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings.

It should be noted that, the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor employed herein are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole. The middle terminal of the transistor is defined as a control electrode according to the form in the figure, and may be called a gate electrode, a signal input terminal as a source electrode, and a signal output terminal as a drain electrode. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor that is turned on when the gate is at a low level, turned off when the gate is at a high level, and an N-type switching transistor that is turned on when the gate is at a high level, and turned off when the gate is at a low level. Further, the plurality of signals in the various embodiments of the present disclosure each correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has 2 state quantities, and do not represent that the first potential or the second potential has a specific value in the whole text.

Organic light emitting diode (organic light emitting diode, OLED) displays are one of the hot spots in the current display research field, and compared with liquid crystal displays (liquid crystal display, LCD), OLED displays have the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed. In general, a pixel circuit is used in an OLED display to drive an OLED light emitting element to emit light. Also, with the development of display technology, the application range of OLED display has gradually expanded from the fields of small-sized watches, mobile phones, and tablets to the fields of large-sized personal computers (personal computer, PCs), monitors, and the like. A large size display is characterized by the number of pixels (PPI) included per inch, i.e. a higher resolution. In addition, since the scene difference required for a large-sized display is large, the required difference for the refresh rate is also large. For example, in text reading or power saving modes, the required refresh rate is typically below 10 hertz (Hz); in web browsing or video viewing modes, the required refresh rate is typically between 48Hz and 60 Hz; and, in a game scenario, the required refresh rate needs to reach even 120Hz to 144Hz, even 240Hz and above. Thus, it is desirable that the display be capable of good display at refresh rates of a few Hz to a few hundred Hz.

Currently, common pixel circuits are all 7T1C (i.e., including 7 transistors and 1 capacitor) structures, and data writing and compensation of the threshold voltage Vth are performed simultaneously by the same device in the pixel circuit. As a result, vth cannot be reliably compensated for in a short period of time (e.g., a high frame rate), and the effect of writing data is amplified, resulting in poor display quality of the display.

The embodiment of the disclosure provides a new pixel circuit, which can drive a light emitting element to emit light in a mode of separating data writing and Vth compensation, so that the compensation of Vth is not limited by the data writing time any more, and a better compensation effect can be realized in a shorter time (such as a large resolution and a high frame frequency).

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 1, the pixel circuit includes: a first control circuit 01, a second control circuit 02, a third control circuit 03, and a drive circuit 04.

The first control circuit 01 is coupled to the first gate driving end GT1, the compensation control end AZ, the driving power end VDD, the data signal end Vdt, the first node N1, the second node N2, and the third node N3, respectively. The first control circuit 01 is configured to control on/off of the data signal terminal Vdt and the first node N1 based on a first gate driving signal provided by the first gate driving terminal GT1, control on/off of the second node N2 and the third node N3 based on a compensation control signal provided by the compensation control terminal AZ, and adjust a potential of the first node N1 and a potential of the second node N2 based on a driving power signal provided by the driving power terminal VDD.

For example, the first control circuit 01 may control the data signal terminal Vdt to be turned on with the first node N1 when the potential of the first gate driving signal provided by the first gate driving terminal GT1 is the first potential, and at this time, the data signal provided by the data signal terminal Vdt may be transmitted to the first node N1. And, the first control circuit 01 may control the data signal terminal Vdt to be decoupled from the first node N1 when the potential of the first gate driving signal provided by the first gate driving terminal GT1 is the second potential.

Similarly, the first control circuit 01 may control the second node N2 to be turned on with the third node N3 when the potential of the compensation control signal provided by the compensation control terminal AZ is the first potential, and at this time, the potential of the second node N2 and the potential of the third node N3 may affect each other. And, the first control circuit 01 may control the second node N2 to be decoupled from the third node N3 when the potential of the compensation control signal provided by the compensation control terminal AZ is the second potential.

In addition, the first control circuit 01 can adjust the potential of the first node N1 and the potential of the second node N2 based on the driving power signal supplied from the driving power terminal VDD by the coupling action.

Alternatively, in embodiments of the present disclosure, the first potential may be an active potential, the second potential may be an inactive potential, and the first potential may be a low potential relative to the second potential. Of course, in some other embodiments, the first potential may be a high potential relative to the second potential.

The second control circuit 02 is coupled to the compensation control terminal AZ, the reset control terminal SC, the reference power terminal Vref, the first initial power terminal Vinit1, the first node N1, and the target node, respectively. The second control circuit 02 is configured to control on-off of the reference power supply terminal Vref and the first node N1 based on the compensation control signal, and control on-off of the first initial power supply terminal Vinit1 and the target node based on a reset control signal provided by the reset control terminal SC. Wherein the target node may comprise: the third node N3 or the fourth node N4, and the fourth node N4 may be coupled with the light emitting element L1. The target node shown in fig. 1 is a fourth node N4.

Alternatively, in fig. 1, the fourth node N4 may be coupled to the first pole of the light emitting element L1, and further, the second pole of the light emitting element L1 may be coupled to the pull-down power source terminal VSS. The light emitting element L1 emits light by a potential difference between the first electrode and the second electrode. One of the first and second poles of the light emitting element L1 may be an anode, and the other pole may be a cathode. In the pixel circuit shown in fig. 1, the first electrode of the light emitting element L1 is coupled to the fourth node N4, and the second electrode is a cathode coupled to the pull-down power source terminal VSS.

For example, the second control circuit 02 may control the reference power terminal Vref to be turned on with the first node N1 when the potential of the compensation control signal provided by the compensation control terminal AZ is the first potential, and at this time, the reference power signal provided by the reference power terminal Vref may be transmitted to the first node N1. And, the second control circuit 02 may control the reference power source terminal Vref to be decoupled from the first node N1 when the potential of the compensation control signal provided by the compensation control terminal AZ is the second potential.

Similarly, the second control circuit 02 may control the first initial power source terminal Vinit1 to be turned on with the target node when the potential of the reset control signal provided by the reset control terminal SC is the first potential, and at this time, the first initial power source signal provided by the first initial power source terminal Vinit1 may be transmitted to the target node, such as the third node or the fourth node. And, the second control circuit 02 may control the first initial power supply terminal Vinit1 to be decoupled from the target node when the potential of the reset control signal provided by the reset control terminal SC is the second potential.

The third control circuit 03 is coupled to the first light emitting control terminal EM1, the second light emitting control terminal EM2, the driving power terminal VDD, the third node N3, the fourth node N4, and the fifth node N5, respectively. The third control circuit 03 is configured to control on-off of the driving power supply terminal VDD and the fifth node N5 based on the first light emitting control signal provided by the first light emitting control terminal EM1, and control on-off of the third node N3 and the fourth node N4 based on the second light emitting control signal provided by the second light emitting control terminal EM 2.

For example, the third control circuit 03 may control the driving power terminal VDD to be turned on with the fifth node N5 when the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 is the first potential, and at this time, the driving power signal provided by the driving power terminal VDD may be transmitted to the fifth node N5. And, the third control circuit 03 may control the driving power supply terminal VDD to be decoupled from the fifth node N5 when the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 is the second potential.

Similarly, the third control circuit 03 may control the third node N3 to be turned on with the fourth node N4 when the potential of the second light emission control signal provided by the second light emission control terminal EM2 is the first potential, and at this time, the potential of the third node N3 may be further transmitted to the fourth node N4. And, the third control circuit 03 may control the third node N3 to be decoupled from the fourth node N4 when the potential of the second light emission control signal provided by the second light emission control terminal EM2 is the second potential.

The driving circuit 04 is coupled to the second node N2, the fifth node N5, and the third node N3, respectively. The driving circuit 04 is configured to transmit a driving signal (e.g., a driving current) to the third node N3 based on the potential of the second node N2 and the potential of the fifth node N5. When the third control circuit 03 controls the third node N3 to be turned on with the fourth node N4 coupled to the light emitting element L1, the driving signal can be further transmitted to the light emitting element L1, so as to drive the light emitting element L1 to emit light.

As can be seen from the operation principle of the above circuits, in the embodiment of the present disclosure, the data signal may be directly written to the first node N1 by the first control circuit 01 based on the first gate driving signal; based on the compensation control signal, the potentials of the second node N2 and the third node N3 are adjusted so that the threshold voltage Vth of the driving transistor included in the driving circuit 04 can be written into the second node N2, thereby realizing the compensation of the threshold voltage Vth; and adjusts the potential of the second node N2 based on the potential of the first node N1 by the coupling action. The data writing and the compensation are separated, the compensation time is not limited by the data writing time, and a good compensation effect is achieved in a short time, so that the display effect of the display panel is ensured to be good.

In addition, in the embodiment of the present disclosure, the second control circuit 02 may also reset the first node N1 and the target node (e.g., the third node N3 or the fourth node N4) based on different compensation control signals and reset control signals, and since the first control circuit 02 may control the third node N3 to be conducted with the second node N2, the third control circuit 03 may control the fourth node N4 to be conducted with the third node N3, so that the reset of the second node N2 may be achieved based on the reset control signals indirectly. So that the gate-source voltage difference Vgs of the driving transistor is approximately equal to the threshold voltage Vth when the driving transistor is reset in the hold frame, and the effect of low frame rate display is realized.

In summary, the embodiments of the present disclosure provide a pixel circuit including three control circuits and one driving circuit. Wherein, a control circuit can control the on-off of the data signal end and the first node based on the grid driving signal; the on-off of the second node and the third node can be controlled based on another compensation control signal; and the potentials of the first node and the second node can be adjusted by a coupling action. The other control circuit may control the on-off of the reference power supply terminal and the first node based on the compensation control signal, and may control the on-off of the initial power supply terminal and the third/fourth node based on the reset control signal. The control circuit can control the on-off of the driving power supply end and the fifth node and control the on-off of the third node and the fourth node based on the light-emitting control signal. The driving circuit may transmit the driving signal to the third node based on the potential of the second node and the potential of the fifth node. Therefore, the compensation of the threshold voltage of the driving transistor in the driving circuit can be realized, and the display effect of the display panel is better.

In addition, the data writing and the compensation of the threshold voltage can be separated from each other and are not influenced by each other, so that the effective compensation of the threshold voltage can be realized, and the display effect of the display panel can be better. And the effective reset of each node coupled with the driving circuit can be realized, so that the gate-source voltage difference of the driving transistor in the driving circuit can be approximately equal to the threshold voltage in the holding frame, and the low frame frequency display can be realized.

Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the disclosure. As shown in fig. 2, the first control circuit 01 may include: a data write sub-circuit 011, a compensation sub-circuit 012, and an adjustment sub-circuit 013.

The data writing sub-circuit 011 may be coupled to the first gate driving terminal GT1, the data signal terminal Vdt, and the first node N1, respectively. The data writing sub-circuit 011 can be used for controlling the on-off of the data signal terminal Vdt and the first node N1 based on the first gate driving signal.

For example, the data writing sub-circuit 011 may control the data signal terminal Vdt to be turned on with the first node N1 when the potential of the first gate driving signal is the first potential, and may control the data signal terminal Vdt to be decoupled from the first node N1 when the potential of the first gate driving signal is the second potential.

The compensation subcircuit 012 may be coupled to the compensation control terminal AZ, the second node N2, and the third node N3, respectively. The compensation sub-circuit 012 may be used to control on-off of the second node N2 and the third node N3 based on the compensation control signal.

For example, the compensation sub-circuit 012 may control the second node N2 to be turned on with the third node N3 when the potential of the compensation control signal is a first potential, and may control the second node N2 to be decoupled from the third node N3 when the potential of the compensation control signal is a second potential.

The regulator sub-circuit 013 may be coupled with the driving power supply terminal VDD, the first node N1, and the second node N2, respectively. The regulator sub-circuit 013 may be configured to regulate the potential of the first node N1 and the potential of the second node N2 by a coupling action based on the driving power supply signal.

Fig. 3 is a schematic structural diagram of still another pixel circuit according to an embodiment of the disclosure. As shown in fig. 3, the second control circuit 02 may include: a first reset sub-circuit 021 and a second reset sub-circuit 022.

The first reset sub-circuit 021 may be coupled to the compensation control end AZ, the reference power end Vref, and the first node N1, respectively. The first reset sub-circuit 021 may be used for controlling the on-off of the reference power supply terminal Vref and the first node N1 based on the compensation control signal.

For example, the first reset sub-circuit 021 may control the reference power terminal Vref to be turned on with the first node N1 when the potential of the compensation control signal is a first potential, and may control the reference power terminal Vref to be decoupled from the first node N1 when the potential of the compensation control signal is a second potential.

The second reset sub-circuit 022 may be coupled to the reset control terminal SC, the first initial power terminal Vinit1, and the target node, respectively. The second reset sub-circuit 022 may be configured to control on-off of the first initial power supply terminal Vinit1 and the target node based on the reset control signal.

For example, the second reset sub-circuit 022 may control the first initial power terminal Vinit1 to be turned on with the target node when the potential of the reset control signal is the first potential, and may control the first initial power terminal Vinit1 to be decoupled from the target node when the potential of the reset control signal is the second potential.

Optionally, in the pixel circuit shown in fig. 3, the target node is a fourth node N4, that is, the second reset sub-circuit 022 is coupled to the fourth node N4; in still another pixel circuit shown in fig. 4, the target node is a third node N3, i.e., the second reset sub-circuit 022 is coupled to the third node N3. When the target node is the fourth node N4 shown in fig. 3, the first initial power signal may be transmitted to the third node N3 through the fourth node N4 and further transmitted to the second node N2 through the third node N3, so as to implement indirect reset of the second node N2. When the target node is the third node N3 shown in fig. 4, the first initial power signal may be transmitted to the second node N2 through the third node N3, thereby implementing indirect reset of the second node N2.

Fig. 5 shows a schematic diagram of a further pixel circuit on the basis of fig. 3. As shown in fig. 5, the pixel circuit provided in the embodiment of the present disclosure may further include: and a reset circuit 05.

The reset circuit 05 may be coupled to the second gate driving terminal GT2, the second initial power terminal Vinit2, and the second node N2, respectively. The reset circuit 05 may be configured to control on/off of the second initial power supply terminal Vinit2 and the second node N2 based on a second gate driving signal provided by the second gate driving terminal GT 2.

For example, the reset circuit 05 may control the second initial power terminal Vinit2 to be turned on with the second node N2 when the potential of the second gate driving signal provided by the second gate driving terminal GT2 is the first potential, and at this time, the second initial power signal provided by the second initial power terminal Vinit2 may be transmitted to the second node N2. And, the reset circuit 05 may control the second initial power terminal Vinit2 to be decoupled from the second node N2 when the potential of the second gate driving signal provided by the second gate driving terminal GT2 is the second potential.

On the basis of setting the reset circuit 05, the second node N2 can be reset directly through the reset circuit 05, and the second reset sub-circuit 022 included in the second control circuit 02 is not needed, on the basis of resetting the target node, the second node N2 is reset indirectly, and the efficiency is higher.

Fig. 6 shows a schematic circuit structure of a pixel circuit according to an embodiment of the present disclosure, based on the structure shown in fig. 3. Fig. 7 shows a schematic circuit structure of another pixel circuit according to an embodiment of the present disclosure, based on the structure shown in fig. 4. Fig. 8 shows a schematic circuit configuration of a further pixel circuit according to the embodiment of the disclosure, based on the configuration shown in fig. 5.

As can be seen with reference to fig. 6-8, the data write sub-circuit 011 can include: the data is written to the transistor T1.

The gate of the data writing transistor T1 may be coupled to the first gate driving terminal GT1, the first pole of the data writing transistor T1 may be coupled to the data signal terminal Vdt, and the second pole of the data writing transistor T1 may be coupled to the first node N1.

With continued reference to fig. 6-8, the compensation subcircuit 012 may include: compensating transistor T2.

The gate of the compensation transistor T2 may be coupled to the compensation control terminal AZ, the first pole of the compensation transistor T2 may be coupled to the second node N2, and the second pole of the compensation transistor T2 may be coupled to the third node N3.

With continued reference to fig. 6-8, the regulator sub-circuit 013 may comprise: a first capacitor C1 and a second capacitor C2.

One end of the first capacitor C1 may be coupled to the driving power terminal VDD, and the other end of the first capacitor C1 may be coupled to the first node N1.

One end of the second capacitor C2 may be coupled to the first node N1, and the other end of the first capacitor C1 may be coupled to the second node N2.

With continued reference to fig. 6-8, the first reset sub-circuit 021 may include: a first reset transistor T3.

The gate of the first reset transistor T3 may be coupled to the compensation control terminal AZ, the first pole of the first reset transistor T3 may be coupled to the reference power terminal Vref, and the second pole of the first reset transistor T3 may be coupled to the first node N1.

With continued reference to fig. 6-8, the second reset sub-circuit 022 may include: and a second reset transistor T4.

The gate of the second reset transistor T4 may be coupled to the reset control terminal SC, the first pole of the second reset transistor T4 may be coupled to the first initial power terminal Vinit1, and the second pole of the second reset transistor T4 may be coupled to the target node. In fig. 6 and 8, the target node is a fourth node N4, i.e., the second pole of the second reset transistor T4 is coupled to the fourth node N4. In fig. 7, the target node is a third node N3, i.e., the second diode of the second reset transistor T4 is coupled to the third node N3.

With continued reference to fig. 8, the reset circuit 05 may include: and a third reset transistor T5.

The gate of the third reset transistor T5 may be coupled to the second gate driving terminal GT2, the first pole of the third reset transistor T5 may be coupled to the second initial power terminal Vinit2, and the second pole of the third reset transistor T5 may be coupled to the second node N2.

As can be seen with continued reference to fig. 6 to 8, the third control circuit 03 may include: a first light emission control transistor T6 and a second light emission control transistor T7. The driving circuit 04 may include: and a driving transistor T8.

The gate electrode of the first light emitting control transistor T6 may be coupled to the first light emitting control terminal EM1, the first electrode of the first light emitting control transistor T6 may be coupled to the driving power terminal VDD, and the second electrode of the first light emitting control transistor T6 may be coupled to the fifth node N5.

The gate of the second light-emitting control transistor T7 may be coupled to the second light-emitting control terminal EM2, the first pole of the second light-emitting control transistor T7 may be coupled to the third node N3, and the second pole of the second light-emitting control transistor T7 may be coupled to the fourth node N4.

The gate of the driving transistor T8 may be coupled to the second node N2, the first pole of the driving transistor T8 may be coupled to the fifth node N5, and the second pole of the driving transistor T8 may be coupled to the third node N3.

It should be noted that, referring to fig. 6 to 8, in the embodiment of the present disclosure, the data writing transistor T1 may write the data signal to the first node N1, the compensating transistor T2 may write the threshold voltage of the driving transistor T8 to the second node N2 (i.e., the gate of the driving transistor T8), and the first capacitor C1 and the second capacitor C2 may adjust the potential of the first node N1 and the potential of the second node N2, that is, the data writing and the threshold voltage compensation may be implemented through different devices, so that the data writing and the compensation may be separated from each other, and the compensating effect may be ensured. In addition, the first reset transistor T3, the second reset transistor T4 and/or the third reset transistor T5 may be used to reset the first node N1 and the second node N2, so that when the driving transistor T8 is reset by the holding frame, the gate-source voltage difference Vgs of the driving transistor T8 may be approximately equal to the threshold voltage, so that the display panel may implement low frame rate display.

Fig. 6 and 7 show a pixel circuit of a 7T2C structure, and fig. 8 shows a pixel circuit of an 8T2C structure. Of course, in some other embodiments, the pixel circuit may also be a 10T2C structure. The premise is that the three control circuits described in the embodiments of the present disclosure are included.

Alternatively, in the embodiments of the present disclosure, the transistors included in the illustrated pixel circuit may be P-type transistors, and the material may include a Low Temperature Polysilicon (LTPS) material, where the material refers to a material of an active layer of the transistor. Accordingly, as described in the above embodiments, the first potential (i.e., the active potential) of each signal may be a low potential, and the second potential (i.e., the inactive potential) may be a high potential. Of course, in some other embodiments, the transistors included in the pixel circuit may be N-type transistors, and the material may be an oxide material. Correspondingly, the first potential may be a high potential, and the second potential may be a low potential. Alternatively, among the transistors included in the pixel circuit, part of the transistors may be P-type transistors and part of the transistors may be N-type transistors. For example, in fig. 6, the driving transistor T8 may be a P-type transistor, and the remaining transistors may be N-type transistors.

Fig. 9 is a schematic diagram of a driving method of a pixel circuit according to an embodiment of the present disclosure, which may be applied to the pixel circuit shown in any one of fig. 1 to 8. The method comprises the following steps: refresh frames and hold frames are performed sequentially. Wherein refreshing the frame comprises: the first stage, the second stage, the third stage and the fourth stage are sequentially performed.

In the first stage, the first control circuit controls the second node and the third node to be turned on based on the compensation control signal provided by the compensation control terminal, the second control circuit controls the reference power terminal to be turned on with the first node based on the compensation control signal, and controls the first initial power terminal to be turned on with the target node based on the reset control signal provided by the reset control terminal, and the third control circuit controls the third node to be turned on with the fourth node based on the second light-emitting control signal provided by the second light-emitting control terminal.

In the second stage, if the target node is the fourth node, the first control circuit controls the second node to be connected to the third node based on the compensation control signal, the second control circuit controls the reference power supply terminal to be connected to the first node based on the compensation control signal, and controls the first initial power supply terminal to be connected to the fourth node based on the reset control signal, and the third control circuit controls the driving power supply terminal to be connected to the fifth node based on the first light emitting control signal provided by the first light emitting control terminal; if the target node is a third node, the first control circuit controls the second node to be conducted with the third node based on the compensation control signal, the second control circuit controls the reference power supply end to be conducted with the first node based on the compensation control signal, and the third control circuit controls the driving power supply end to be conducted with the fifth node based on the first light-emitting control signal.

Step 903, in the third stage, if the target node is the fourth node, the first control circuit controls the data signal end to be turned on with the first node based on the first gate driving signal provided by the first gate driving end, the second control circuit controls the first initial power end to be turned on with the fourth node based on the reset control signal, and the third control circuit controls the driving power end to be turned on with the fifth node based on the first light emitting control signal; if the target node is a third node, the first control circuit controls the data signal end to be conducted with the first node based on the first gate driving signal, and the third control circuit controls the driving power end to be conducted with the fifth node based on the first light emitting control signal.

In step 904, in the fourth stage, the third control circuit controls the driving power source terminal to be turned on with the fifth node based on the first light emitting control signal, controls the third node to be turned on with the fourth node based on the second light emitting control signal, and transmits the driving signal to the third node based on the potentials of the second node and the fifth node to control the light emitting element coupled to the fourth node to emit light.

In step 905, in the hold frame, the second control circuit controls the first initial power terminal to be turned on with the target node based on the reset control signal, and the third control circuit controls the third node to be turned on with the fourth node based on the second light emission control signal.

In the refresh frame and the hold frame, the first control circuit adjusts the potential of the first node and the potential of the second node based on the driving power supply signal supplied from the driving power supply terminal.

Optionally, as shown in fig. 5, the pixel circuit described in the embodiment of the disclosure may further include: and a reset circuit 05. Based on this, in the method described in the embodiment of the present disclosure, step 901 may further include:

Alternatively, taking the example that the transistors in the pixel circuit are P-type transistors, the first potential is a low potential, and the second potential is a high potential, on the basis of the three pixel circuit structures shown in fig. 6, 7 and 8, fig. 10, 11 and 12 respectively correspond to each other one by one to show the operation timing diagrams of the three pixel circuits. And fig. 10 to 12 are timing diagrams of the pixel circuits in the refresh frame. As can be seen with reference to fig. 10-12, the refresh frame may include four phases: a first stage t1, a second stage t2, a third stage t3 and a fourth stage t4.

First, in a first phase t1:

for any of the structures shown in fig. 6 to 8, the potential of the compensation control signal provided by the compensation control terminal Az, the potential of the second light-emitting control signal provided by the second light-emitting control terminal EM2, and the potential of the reset control signal provided by the reset control terminal SC are both low potentials; the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 and the potential of the first gate driving signal provided by the first gate driving terminal GT1 are both high potentials. That is, the compensation control terminal Az, the second light emission control terminal EM2, and the reset control terminal SC may all be placed at the low potential VGL; and both the first light emitting control terminal EM1 and the first gate driving terminal GT1 are set to the high potential VGH. Accordingly, the compensation transistor T2, the first reset transistor T3, the second reset transistor T4, and the second emission control transistor T7 are all turned on; and the data writing transistor T1 and the first light emitting control signal terminal T6 are both turned off. Further, the second node N2 is turned on with the third node N3, and the third node N3 is turned on with the fourth node N4.

On the basis of this, for the pixel circuit shown in fig. 6 and 8, i.e., the pixel circuit whose target node is the fourth node N4, the first initial power signal provided by the first initial power terminal Vinit1 may be transmitted to the fourth node N4 via the turned-on second reset transistor T4 to reset the fourth node N4 (i.e., the anode of the light emitting element L1), and may be transmitted to the second node N2 via the turned-on second reset transistor T4, the second light emission control transistor T7, and the compensation transistor T2 (i.e., the T4-T7-T2 path) to reset the second node N2 (i.e., the gate of the driving transistor T8).

For the pixel circuit shown in fig. 7, i.e., the pixel circuit whose target node is the third node N3, the first initial power signal provided by the first initial power terminal Vinit1 may be transmitted to the fourth node N4 via the turned-on second reset transistor T4 and the second light-emitting control transistor T7 (i.e., the T4-T7 path) to reset the fourth node N4 (i.e., the anode of the light-emitting element L1), and may be transmitted to the second node N2 via the turned-on second reset transistor T4 and the compensation transistor T2 (i.e., the T4-T2 path) to reset the second node N2 (i.e., the gate of the driving transistor T8).

And, for the structure shown in any one of fig. 6 to 8, the reference power signal provided by the reference power terminal Vref may be transmitted to the first node N1 through the turned-on first reset transistor T3 to reset the first node N1. Under the coupling action of the second capacitor C2, the potentials of the first node N1 and the second node N2 (i.e., the potentials at two ends of the second capacitor C2) can be kept stable, and the potential of the gate of the driving transistor T8 is eliminated during the refresh process of the previous frame.

In addition, for the pixel circuit further including the third reset transistor T5 shown in fig. 8, the potential of the second gate driving signal provided by the second gate driving terminal GT2 may be a low potential. Accordingly, the third reset transistor T5 may be turned on. Further, the second initial power signal provided by the second initial power terminal Vinit2 may be transmitted to the second node N2 through the turned-on third reset transistor T5 to reset the second node N2 (i.e., the gate of the driving transistor T8). On the basis of this, it can be further seen that the structure shown in fig. 8, with respect to the structures shown in fig. 6 and 7, can directly reset the gate of the driving transistor T8 by the third reset transistor T5 without resetting the gate of the driving transistor T8 by means of the second reset transistor T4. The first phase t1 may also be referred to as a reset phase.

Next, in the second stage t2:

for any of the structures shown in fig. 6 to 8, the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 and the potential of the compensation control signal provided by the compensation control terminal Az are both low potentials; the first gate driving end GT1 provides the first gate driving signal and the second light emitting control end EM2 provides the second light emitting control signal. That is, both the first light emission control terminal EM1 and the compensation control terminal Az may be placed at the low potential VGL; and both the first gate driving terminal GT1 and the second emission control terminal EM2 are placed at the high potential VGH. Correspondingly, the compensation transistor T2, the first reset transistor T3 and the first light emitting control signal terminal T6 may all be turned on; and the data writing transistor T1 and the second light emission control transistor T7 may both be turned off. Further, the second node N2 is turned on with the third node N3. And, for the structures shown in fig. 6 and 8, that is, the pixel circuit with the target node being the fourth node N4, the potential of the reset control signal provided by the reset control terminal SC is low, that is, the reset control terminal SC may be set at the low potential VGL. Accordingly, the second reset transistor T4 may be turned on. In the structure shown in fig. 7, that is, the pixel circuit with the target node being the third node N3, the potential of the reset control signal provided by the reset control terminal SC is high, that is, the reset control terminal SC may be set to the high potential VGH. Accordingly, the second reset transistor T4 may be turned off, and thus, leakage of the potential of the third node N3 may be avoided. In addition, since the gate of the driving transistor T8 is reset in the first stage T1, the driving transistor T8 can be turned on, and the fifth node N5 and the third node N3 are turned on.

On the basis of this, for the structure shown in any one of fig. 6 to 8, the reference power signal provided by the reference power terminal Vref may be continuously transmitted to the first node N1 through the turned-on first reset transistor T3. The driving power signal provided by the driving power terminal VDD may be transmitted to the second node N2 through the turned-on second light emission control transistor T7, the driving transistor T8 and the compensation transistor T2 (i.e., the T7-T8-T2 path) to charge the gate of the driving transistor T8, and the charging potential is related to the threshold voltage Vth of the driving transistor T8, so that the driving signal generated by the subsequent driving transistor T8 based on the potential of the second node N2 is independent of the threshold voltage Vth, and the compensation of the threshold voltage Vth of the driving transistor T8 is achieved. Since the low potential duration of the compensation control signal can be flexibly set, a longer duration (e.g., > 8H pulse) can be set, ensuring effective compensation for the threshold voltage Vth.

In addition, for the structures shown in fig. 6 and 8, the first initial power signal provided by the first initial power terminal Vinit1 may be continuously transmitted to the anode of the light emitting element L1 through the turned-on second reset transistor T4, so as to continuously reset the anode of the light emitting element L1. And, for the structure shown in fig. 8, the potential of the second gate driving signal provided by the second gate driving end GT2 may be a high potential. Accordingly, the third reset transistor T5 may be turned off. The second phase t2 may also be referred to as the compensation phase.

In the second phase T2, the gate potential of the driving transistor T8 may be charged to approximately vdd+vth, where Vdd refers to the potential of the driving power supply signal. Meanwhile, since the driving transistor T8 is in vgs=vth state for a long time, the bound carriers in the channel defect of the driving transistor T8 are separated from the defect due to the action of the gate voltage. Since the density of such bound carrier occupying defects is affected by the previous frame display state (i.e., vgs), for the reason of generation of afterimages and the like, it is generally required to be eliminated before data writing or Vth compensation. In the related art, a relatively negative Vgs is generally used, and the defect in the channel is filled with carriers. Although the mode is high in efficiency, the carrier occupies poor stability of the defect, and a reset process needs to be inserted into a frame to ensure the stability of display. In addition, for a pixel circuit that performs Vth compensation for a long time, the reset process and the compensation process have opposite effects on the channel defect state, and the reset efficiency is low. In the embodiment of the disclosure, the characteristic of the driving transistor T8 can be kept stable for a longer time by flexibly setting the pulse width of the compensation signal.

Then, in a third phase t3:

for any of the structures shown in fig. 6 to 8, the potential of the first light emitting control signal provided by the first light emitting control terminal EM1 and the potential of the first gate driving signal provided by the first gate driving terminal GT1 are both low potentials; the potential of the compensation control signal provided by the compensation control terminal Az and the potential of the second light-emitting control signal provided by the second light-emitting control terminal EM2 are both high potentials. That is, both the first light emitting control terminal EM1 and the first gate driving terminal GT1 may be placed at the low potential VGL; and both the compensation control terminal Az and the second emission control terminal EM2 are placed at the high potential VGH. Correspondingly, the data writing transistor T1 and the first light emitting control signal terminal T6 may both be turned on; and the compensation transistor T2, the first reset transistor T3, and the second emission control transistor T7 may all be turned off. And, for the structures shown in fig. 6 and 8, that is, the pixel circuit with the target node being the fourth node N4, the potential of the reset control signal provided by the reset control terminal SC is low, that is, the reset control terminal SC may be set at the low potential VGL. Accordingly, the second reset transistor T4 may be turned on. In the structure shown in fig. 7, that is, the pixel circuit with the target node being the third node N3, the potential of the reset control signal provided by the reset control terminal SC is high, that is, the reset control terminal SC may be set to the high potential VGH. Accordingly, the second reset transistor T4 may be turned off, and thus, leakage of the potential of the third node N3 may be avoided. In addition, the driving transistor T8 may remain turned on.

On the basis of this, for the structure shown in any one of fig. 6 to 8, the data signal provided by the data signal terminal Vdt can be transmitted to the first node N1 through the turned-on data writing transistor T1. The potential of the first node N1 is changed from the reference power signal of the previous stage to the data signal. Accordingly, the potential of the second node N2 (i.e., the gate of the driving transistor T8) may become: vdd+Vth+Vdt0-Vref0, vdt0 may refer to the potential of the data signal, and Vref0 may refer to the potential of the reference power signal. In addition, the driving power signal provided by the driving power terminal VDD may be transmitted to the fifth node N5 (i.e., the source of the driving transistor T8) through the turned-on second light emission control transistor T7. Further, it is possible to determine the gate-source voltage difference vgs=vg-vs= (vdd+vth+vdt0-Vref 0) -vdd=vdt0+vth-Vref 0 of the driving transistor T8, and realize the compensation of the threshold voltage Vth.

In addition, for the structures shown in fig. 6 and 8, the first initial power signal provided by the first initial power terminal Vinit1 may be continuously transmitted to the anode of the light emitting element L1 through the turned-on second reset transistor T4, so as to continuously reset the anode of the light emitting element L1. And, for the structure shown in fig. 8, the potential of the second gate driving signal provided by the second gate driving end GT2 may be a high potential. Accordingly, the third reset transistor T5 may be turned off. The third phase t3 may also be referred to as a data writing phase.

Finally, in a fourth phase t4:

for any of the structures shown in fig. 6 to 8, the potential of the first light emission control signal provided by the first light emission control terminal EM1 and the potential of the second light emission control signal provided by the second light emission control terminal EM2 are both low potentials; the potential of the compensation control signal provided by the compensation control terminal Az, the potential of the first gate driving signal provided by the first gate driving terminal GT1, and the potential of the reset control signal provided by the reset control terminal SC are both high potentials. That is, both the first light emission control terminal EM1 and the second light emission control terminal EM2 may be placed at the low potential VGL; and the compensation control terminal Az, the first gate driving terminal GT1 and the reset control terminal SC are all set at the high potential VGH. Accordingly, the first and second light emission control transistors T6 and T7 may be turned on, and the data writing transistor T1, the compensation transistor T2, the first and second reset transistors T3 and T4 may be turned off. And, the driving transistor T8 may remain on.

On the basis, for the structure shown in any one of fig. 6 to 8, the driving power signal provided by the driving power terminal VDD may be transmitted to the fifth node N5 through the turned-on first light emitting control transistor T6, the driving transistor T8 may generate the driving signal based on the potential of the second node N2 and the potential of the fifth node N5 and transmit the driving signal to the third node N3, and the turned-on second light emitting control transistor T7 may transmit the driving signal to the fourth node N4, that is, to the anode of the light emitting element L1, and the light emitting element L1 may reliably emit light under the voltage difference between the driving signal and the pull-down power signal VSS provided by the pull-down power terminal VSS. And, for the structure shown in fig. 8, the potential of the second gate driving signal provided by the second gate driving end GT2 may be a high potential. Accordingly, the third reset transistor T5 may be turned off. The fourth phase t4 may also be referred to as a lighting phase.

It should be noted that, in conjunction with the driving transistor T8, the formula of generating the driving signal (e.g., the driving current I0) is as follows: i0 =1/2 μ _n C _ox (W/L)*(Vgs-Vth) ² It can be seen that, in the second phase T2, the threshold voltage Vth of the driving transistor T8 is written into the second node N2, so that in the third phase T3, the driving current i0=1/2 μ generated by the driving transistor T8 is based on the gate-source voltage difference vgs=vg-vs= (vdd+vth+vdt0-Vref 0) -vdd=vdt0+vth-Vref 0 of the driving transistor T8 _n C _ox (W/L)*(Vdt0+Vth-Vref0-Vth)＝I0＝1/2μ _n C _ox (W/L) × (Vdt 0-Vref 0), independent of the threshold voltage Vth, thereby realizing compensation for the threshold voltage Vth. Wherein mu _n To drive the carrier mobility of transistor T8, C _ox To drive the crystalThe capacitance of the gate insulating layer of the transistor T8, W/L is the width-to-length ratio of the driving transistor T8, and is a constant determined by the manufacturing process of the display panel.

As can be seen from comparing fig. 10, 11 and 12, the time for resetting the anode of the light emitting element L1 is shortened in the structure shown in fig. 7 relative to the structure shown in fig. 6 and 8. In the structure shown in fig. 8, compared with the structures shown in fig. 6 and 7, since the third reset transistor T5 is provided to reset the gate of the driving transistor T8, the gate of the driving transistor T8 does not need to be reset by the first reset transistor T4. As can be seen from fig. 10 to 12, the embodiment of the present disclosure achieves the purpose of separating data writing and compensation, so that the compensation time is not limited by the data writing time any more, and the threshold voltage can be compensated better.

Fig. 13 also shows an operation timing chart of the pixel circuits shown in fig. 6 and 7 in the hold frame. Fig. 14 also shows a timing diagram of the operation of the pixel circuit shown in fig. 8 within a hold frame.

As can be seen with reference to fig. 13 and 14, within the hold frame:

for the structures shown in fig. 6 to 8, the potential of the reset control signal provided by the reset control terminal SC and the potential of the second light-emitting control signal provided by the second light-emitting control terminal EM2 are both low potentials; the potential of the first light emitting control signal provided by the first light emitting control terminal EM1, the potential of the compensation control signal provided by the compensation control terminal AZ, and the potential of the first gate driving signal provided by the first gate driving terminal GT are all high potentials. Accordingly, the second reset transistor T4 and the second light emission control transistor T7 may both be turned on; and the data writing transistor T1, the compensation transistor T2, the first reset transistor T3, and the first light emitting control transistor T6 may all be turned off. In addition, for the structure shown in fig. 8, the potential of the second gate driving signal provided by the second gate driving end GT2 may be a high potential. Accordingly, the third reset transistor T5 may be turned off.

Further, for the structures shown in fig. 6 and 8, i.e., the pixel circuit whose target node is the fourth node N4, the first initial power signal provided by the first initial power terminal Vinit1 may be transmitted to the fourth node N4 (i.e., the anode of the light emitting element L1) through the turned-on second reset transistor T4, so as to realize the reset of the anode of the light emitting element L1. And, the second light emission control transistor T7 (i.e., the T4-T7 path) which is turned on can be transmitted to the third node N3 (i.e., the drain of the driving transistor T8) to reset the threshold voltage Vth of the driving transistor T8. For the pixel circuit with the structure shown in fig. 7, i.e., the target node is the third node N3, the first initial power signal provided by the first initial power terminal Vinit1 can be transmitted to the third node N3 (i.e., the drain of the driving transistor T8) through the turned-on second reset transistor T4, so as to realize the reset of the threshold voltage Vth of the driving transistor T8. And, the second light emission control transistor T7 (i.e., the path T4-T7) which is turned on may be further transmitted to the fourth node N4 (i.e., the anode of the light emitting element L1), so as to reset the anode of the light emitting element L1. That is, the anode of the light emitting element L1 and the threshold voltage Vth of the driving transistor T8 may be reset at the holding frame so that the gate-source voltage difference Vgs of the driving transistor T8 rapidly drops to be approximately equal to Vth. Since the compensation transistor T2 is turned off, the gate potential of the driving transistor T8 is not affected. The light emission luminance of the display panel may remain unchanged until the light emission element L1 resumes light emission. Thus, better low-frame frequency display can be realized in a low-frequency refreshing state.

In summary, the embodiments of the present disclosure provide a driving method of a pixel circuit, where the pixel circuit includes three control circuits and a driving circuit. In the method, a control circuit can control the on-off of a data signal end and a first node based on a gate driving signal; the on-off of the second node and the third node can be controlled based on another compensation control signal; and the potentials of the first node and the second node can be adjusted by a coupling action. The other control circuit may control the on-off of the reference power supply terminal and the first node based on the compensation control signal, and may control the on-off of the initial power supply terminal and the third/fourth node based on the reset control signal. The control circuit can control the on-off of the driving power supply end and the fifth node and control the on-off of the third node and the fourth node based on the light-emitting control signal. The driving circuit may transmit the driving signal to the third node based on the potential of the second node and the potential of the fifth node. Therefore, the compensation of the threshold voltage of the driving transistor in the driving circuit can be realized, and the display effect of the display panel is better.

Fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 15, the display panel includes: a substrate 10, and a plurality of pixels 20 located on one side of the substrate 10.

Wherein the pixel 20 may include: a light emitting element L1, and a pixel circuit 00 as shown in any one of fig. 1 to 8. The pixel circuit 00 may be coupled to the light emitting element L1 and used to drive the light emitting element L1 to emit light.

Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 16, the display device includes: a signal supply circuit 000, and a display panel 100 as shown in fig. 15.

In fig. 15, the signal providing circuit 000 may be coupled to a plurality of signal terminals coupled to the pixel circuit 00 in the display panel 100, and is configured to provide signals to the plurality of signal terminals to control the pixel circuit 00 to drive the coupled light emitting element L1 to emit light. Optionally, as described in the foregoing embodiment, the plurality of signal terminals may include: the first gate driving terminal GT1, the second gate driving terminal GT2, the compensation control terminal AZ, the reset control terminal SC, the first light emitting control terminal EM1, and the second light emitting control terminal EM2. Taking the first gate driving terminal GT as an example, the signal providing circuit 000 to which the first gate driving signal is provided may be a gate driving circuit.

Optionally, the display device described in the embodiments of the present disclosure may be: OLED display devices, cell phones, tablet computers, flexible display devices, televisions, and any product or component having a display function.

It is noted that the terminology used in the description of the embodiments of the present disclosure is for the purpose of explaining the examples of the present disclosure only and is not intended to limit the present disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

For example, in the presently disclosed embodiments, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed.

"and/or" means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A pixel circuit, the pixel circuit comprising:

2. The pixel circuit according to claim 1, wherein the first control circuit includes:

3. The pixel circuit of claim 2, wherein the data writing sub-circuit comprises: a data writing transistor;

4. The pixel circuit of claim 2, wherein the compensation sub-circuit comprises: a compensation transistor;

5. The pixel circuit of claim 2, wherein the adjustment sub-circuit comprises: a first capacitor and a second capacitor;

6. The pixel circuit according to any one of claims 1 to 5, wherein the second control circuit includes:

7. The pixel circuit of claim 6, wherein the first reset sub-circuit comprises: a first reset transistor;

8. The pixel circuit of claim 6, wherein the second reset sub-circuit comprises: a second reset transistor;

9. The pixel circuit according to any one of claims 1 to 5, further comprising:

10. The pixel circuit according to claim 9, wherein the reset circuit comprises: a third reset transistor;

11. The pixel circuit according to any one of claims 1 to 5, wherein the third control circuit includes: a first light emission control transistor and a second light emission control transistor; the driving circuit includes: a driving transistor;

12. A driving method of a pixel circuit, characterized in that the method is applied to the pixel circuit according to any one of claims 1 to 11, the method comprising: a refresh frame and a hold frame performed sequentially; wherein the refresh frame comprises: the first stage, the second stage, the third stage and the fourth stage are sequentially executed;

13. The method of claim 12, wherein the pixel circuit further comprises: a reset circuit; the method further comprises the steps of:

14. A display panel, the display panel comprising: a substrate, and a plurality of pixels located at one side of the substrate;

wherein the pixel includes: a light emitting element, and a pixel circuit according to any one of claims 1 to 11, coupled to the light emitting element, for driving the light emitting element to emit light.

15. A display device, characterized in that the display device comprises: a signal supply circuit as claimed in claim 14;