CN116362175A - Method, device, equipment and storage medium for extracting pin constraint file - Google Patents
Method, device, equipment and storage medium for extracting pin constraint file Download PDFInfo
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- CN116362175A CN116362175A CN202310347712.XA CN202310347712A CN116362175A CN 116362175 A CN116362175 A CN 116362175A CN 202310347712 A CN202310347712 A CN 202310347712A CN 116362175 A CN116362175 A CN 116362175A
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
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Abstract
The application provides a method, a device, equipment and a storage medium for extracting a pin constraint file, wherein the method comprises the steps of obtaining a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function of a programmable logic device, wherein the pin information file comprises the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different; determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function; and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file. The method can achieve the effect of improving the accuracy of extracting the pin constraint file of the programmable logic device.
Description
Technical Field
The present application relates to the field of digital circuit design, and in particular, to a method, apparatus, device, and storage medium for extracting pin constraint files.
Background
Currently, programmable logic devices are widely used in digital circuit design. The programmable logic device is used as a semi-custom circuit in the field of application specific integrated circuits, which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable logic device. Along with the continuous improvement of the chip production process, the chip functions are more and more complex, so that the demands on the resources of the programmable logic devices are more and more increased, and the input and output quantity of the programmable logic devices is also greatly improved. When using the programmable logic device, a developer of the programmable logic device can normally use the programmable logic device after binding pins of the programmable logic device, and at present, two binding modes provided by manufacturers are approximately available: interface tool binding and pin constraint binding.
The method has great limitation, and when the input pins and the output pins of the programmable logic device are more, the interface binding and pin constraint mode needs to consume a great deal of time and is easy to make mistakes.
Therefore, how to improve the accuracy of extracting the pin constraint file of the programmable logic device is a technical problem to be solved.
Disclosure of Invention
The embodiment of the application aims to provide a method for extracting pin constraint files, and the effect of improving the accuracy of extracting pin constraint files of a programmable logic device can be achieved through the technical scheme of the embodiment of the application.
In a first aspect, an embodiment of the present application provides a method for extracting a pin constraint file, including obtaining a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located, where the pin information file includes the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different; determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function; and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file.
In the above embodiment, the network interface name is directly extracted from the target printed circuit board net list file, and the pin constraint file is automatically generated in a mode of matching the network interface name with the pins in the pin information file.
In some embodiments, before obtaining the plurality of pin names in the pin information file corresponding to the printed circuit board with the preset function where the programmable logic device is located, the method further includes:
screening the pin names and default network interface names in the programmable logic device resources to obtain pin information files;
and inputting default network interface names in the pin information files into a plurality of netlists according to different board-level network connection relations to obtain a plurality of printed circuit board network table files with different functions, wherein the printed circuit board network table files comprise target printed circuit board network table files.
In the above embodiment, some pin names and default network interface names are acquired in advance in the programmable logic device resource, different printed circuit board net list files are generated through different functions of the printed circuit board, when a user generates the pin constraint file, the pin constraint file with the corresponding function can be directly generated through the set printed circuit board net list file and the pin information file, and the generation efficiency is improved.
In some embodiments, after associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain the pin constraint file, further comprising:
And screening the pin names which are not associated in the pin names and the network interface names with errors in the network interface names to obtain an error prompt file, wherein prompt information in the error prompt file comprises at least one of a network interface name naming error prompt, an attribute error prompt, a repeated connection error prompt and an error prompt which does not accord with a preset naming rule.
In the above embodiment, the error prompt file may be generated by screening the pin names which are not associated in the plurality of pin names and the network interface names with errors in the plurality of network interface names, and the error prompt file may be used to notify the user of the error information when generating the pin constraint file.
In some embodiments, before filtering the pin names which are not associated in the plurality of pin names and the network interface names with errors in the plurality of network interface names, obtaining the error prompt file, the method further includes:
and searching the plurality of network interface names according to the naming rule of the hardware description language to obtain the network interface name with the error in the plurality of network interface names.
In the above embodiment, whether the network interface name has naming error or not can be searched, and the network interface name with the error can be filtered, so that the influence of the network interface name with the error on the generation result when the pin constraint file is generated can be avoided.
In some embodiments, determining a plurality of network interface names of the printed circuit board with the preset function from the target printed circuit board network table file corresponding to the printed circuit board with the preset function includes:
determining the network interface name of the printed circuit board with a preset function connected with any pin to obtain a network interface name set;
and acquiring default network interface names corresponding to the network interface name set from the target printed circuit board network table file to obtain a plurality of network interface names.
In the above embodiment, the default network interface name corresponding to the network interface name set may be directly obtained from the target printed circuit board network table file, and then the pin constraint file may be directly and automatically generated according to the obtained multiple network interface names.
In some embodiments, associating a plurality of pin names and a plurality of network interface names in a pin information file to obtain a pin constraint file includes:
synthesizing the plurality of network interface names into one synthesized network interface name;
and associating the synthesized network interface name with a plurality of pin names to obtain a pin constraint file.
In the above embodiment, the plurality of network interface names may be synthesized into one synthesized network interface name, where the network interface name is used to match with the plurality of pin names, so that the plurality of pins can be associated with one network interface name, and the pin constraint file under the corresponding function can be accurately generated.
In some embodiments, associating a plurality of pin names and a plurality of network interface names in a pin information file to obtain a pin constraint file includes:
sorting the plurality of network interface names according to the initial pinyin to obtain a sorted network interface name set;
and associating the ordered network interface name set with a plurality of pin names to generate a pin constraint file in a preset format.
In the embodiment, the network interface names in the output pin constraint file are ordered, so that a user can conveniently check and customize the network interface names of different types of packets.
In a second aspect, an embodiment of the present application provides an apparatus for extracting a pin constraint file, including:
the device comprises an acquisition module, a control module and a control module, wherein the acquisition module is used for acquiring a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located, wherein the pin information file comprises the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different;
the determining module is used for determining a plurality of network interface names of the printed circuit board with the preset function from the target printed circuit board network table file corresponding to the printed circuit board with the preset function;
And the generation module is used for associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file.
Optionally, the apparatus further includes:
the input module is used for screening the pin names and default network interface names in the programmable logic device resources before the acquisition module acquires a plurality of pin names in the pin information file corresponding to the printed circuit board with the preset function of the programmable logic device, so as to obtain the pin information file;
and inputting default network interface names in the pin information files into a plurality of netlists according to different board-level network connection relations to obtain a plurality of printed circuit board network table files with different functions, wherein the printed circuit board network table files comprise target printed circuit board network table files.
Optionally, the apparatus further includes:
and the screening module is used for screening the unassociated pin names in the pin names and the network interface names with errors in the network interface names after the generation module associates the pin names and the network interface names in the pin information file to obtain an error prompt file, wherein the prompt information in the error prompt file comprises at least one of a network interface name naming error prompt, an attribute error prompt, a repeated connection error prompt and an error prompt which does not accord with a preset naming rule.
Optionally, the apparatus further includes:
and the searching module is used for searching the plurality of network interface names according to the hardware description language naming rule before the screening module screens the pin names which are not associated in the plurality of pin names and the network interface names with errors in the plurality of network interface names to obtain the error prompt file, so as to obtain the network interface names with errors in the plurality of network interface names.
Optionally, the determining module is specifically configured to:
determining the network interface name of the printed circuit board with a preset function connected with any pin to obtain a network interface name set;
and acquiring default network interface names corresponding to the network interface name set from the target printed circuit board network table file to obtain a plurality of network interface names.
Optionally, the generating module is specifically configured to:
synthesizing the plurality of network interface names into one synthesized network interface name;
and associating the synthesized network interface name with a plurality of pin names to obtain a pin constraint file.
Optionally, the generating module is specifically configured to:
sorting the plurality of network interface names according to the initial pinyin to obtain a sorted network interface name set;
and associating the ordered network interface name set with a plurality of pin names to generate a pin constraint file in a preset format.
In a third aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing computer readable instructions that, when executed by the processor, perform the steps of the method as provided in the first aspect above.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method as provided in the first aspect above.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for extracting a pin constraint file according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for generating a pin constraint file and an error hint file with one key according to an embodiment of the present application;
FIG. 3 is a flowchart of an implementation method for extracting pin constraint files according to an embodiment of the present application;
FIG. 4 is a schematic block diagram of an apparatus for extracting pin constraint files according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an apparatus for extracting a pin constraint file according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Some of the terms referred to in the embodiments of the present application will be described first to facilitate understanding by those skilled in the art.
Terminal equipment: the mobile terminal, stationary terminal or portable terminal may be, for example, a mobile handset, a site, a unit, a device, a multimedia computer, a multimedia tablet, an internet node, a communicator, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a personal communications system device, a personal navigation device, a personal digital assistant, an audio/video player, a digital camera/camcorder, a positioning device, a television receiver, a radio broadcast receiver, an electronic book device, a game device, or any combination thereof, including the accessories and peripherals of these devices, or any combination thereof. It is also contemplated that the terminal device can support any type of interface (e.g., wearable device) for the user, etc.
And (3) a server: the cloud server can be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, and can also be a cloud server for providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, basic cloud computing services such as big data and artificial intelligent platforms and the like.
PCB: (Printed Circuit Board) the Chinese name printed circuit board, also called printed circuit board, is an important electronic component, is a support for electronic components, and is a carrier for electrical interconnection of electronic components. It is called a "printed" circuit board because it is made using electronic printing.
FPGA (Field Programmable Gate Array) is a product of further development on the basis of programmable devices such as PAL (programmable array logic), GAL (generic array logic) and the like. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. Verilog: the language is a language for describing the structure and the behavior of digital system hardware in text form, and can be used for representing logic circuit diagrams, logic expressions and logic functions completed by a digital logic system. Verilog HDL and VHDL are the two most popular hardware description languages in the world, both developed in the mid-80 s of the 20 th century.
IO: input/Output (Input/Output) is divided into two parts of IO devices and IO interfaces. On POSIX compatible systems, such as Linux system [1], I/O operations may be performed in a variety of ways, such as DIO (Direct I/O), AIO (Asynchronous I/O), memory-Mapped I/O (Memory Mapped I/O), etc., with different I/O ways having different implementations and capabilities, and with different I/O ways being selected as appropriate in different applications.
ASIC: (Application Specific Integrated Circuit) an application specific integrated circuit, is an integrated circuit designed and manufactured to meet the requirements of a specific user and the needs of a specific electronic system. ASIC design with CPLD (complex programmable logic device) and FPGA (field programmable gate array) is one of the most popular ways, and they share the feature of being user field programmable, and support the boundary scan technique, but have their own features in terms of integration level, speed, and programming mode.
The method and the device are applied to the scene of digital circuit design, and the specific scene is that a user clicks a one-click generation function, and the system can automatically generate the pin constraint file according to the pin file and the netlist file.
Currently, programmable logic devices are widely used in digital circuit design. The programmable logic device appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable logic device. Along with the continuous improvement of the chip production process, the chip functions are more and more complex, so that the demands on the resources of the programmable logic devices are more and more increased, and the input and output quantity of the programmable logic devices is also greatly improved. When using the programmable logic device, a developer of the programmable logic device can normally use the programmable logic device after binding pins of the programmable logic device, and at present, two binding modes provided by manufacturers are approximately available: interface tool binding and pin constraint binding. The method has great limitation, and when the input pins and the output pins of the programmable logic device are more, the interface binding and pin constraint mode needs to consume a great deal of time and is easy to make mistakes.
The method comprises the steps that a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located are obtained, wherein the pin information file comprises the pin names and a plurality of default network interface names corresponding to the pin names, and functions corresponding to different printed circuit boards are different; determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function; and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file. The network interface name is directly extracted from the target printed circuit board network table file, the pin constraint file is automatically generated in a mode of matching the network interface name with pins in the pin information file, and because the pin information file and the target printed circuit board network table file are set in advance, a user can directly and automatically generate the corresponding pin constraint file when using the pin constraint file, and the pin constraint file extraction method has the advantages that the operation is more convenient, and meanwhile the accuracy of extracting the pin constraint file of the programmable logic device can be improved.
In this embodiment of the present application, the execution body may be an extraction pin constraint file device in an extraction pin constraint file system, and in practical application, the extraction pin constraint file device may be electronic devices such as a terminal device and a server, which is not limited herein.
The method for extracting the pin constraint file according to the embodiment of the present application is described in detail below with reference to fig. 1.
Referring to fig. 1, fig. 1 is a flowchart of a method for extracting a pin constraint file according to an embodiment of the present application, where the method for extracting a pin constraint file shown in fig. 1 includes:
step 110: and acquiring a plurality of pin names in a pin information file corresponding to the printed circuit board with the preset function of the programmable logic device.
The pin information file includes a plurality of pin names and a plurality of default network interface (IO interface) names corresponding to the pin names, functions corresponding to different Printed Circuit Boards (PCBs) are different, and the printed circuit boards with different functions correspond to different types of printed circuit board net list files. The pin information file can also be called as a pin information standard file, can be downloaded from a resource database in the FPGA, and mainly comprises information such as the pin name of the FPGA chip, the name of a corresponding default FPGA board sub-network interface and the like. The preset function represents the function of the printed circuit board, and can be set in a self-defined manner, for example, the function can be used for providing mechanical support for fixing and assembling various electronic components such as an integrated circuit and the like; wiring and electrical connection or electrical insulation between various electronic components such as integrated circuits are realized to provide desired electrical characteristics; providing a solder resist pattern for automatic soldering; providing identification characters and figures for component insertion, inspection and maintenance; the electronic components can be automatically inserted or mounted, automatically soldered and automatically detected; providing the circuit with desired electrical, characteristic impedance and electromagnetic compatibility characteristics in a high speed or high frequency circuit; the printed board with the passive components embedded inside provides a certain electrical function, simplifies the electronic installation procedure and improves the reliability of the product; an effective chip carrier is provided for miniaturized chip packaging of electronic components. The method comprises the steps of obtaining a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function, wherein the pin information file comprises a network interface connection relation of the pin names in the pin information file corresponding to the printed circuit board with the preset function.
In some embodiments of the present application, before acquiring the plurality of pin names in the pin information file corresponding to the printed circuit board with the preset function where the programmable logic device is located, the method shown in fig. 1 further includes: screening the pin names and default network interface names in the programmable logic device resources to obtain pin information files; and inputting default network interface names in the pin information files into a plurality of netlists according to different board-level network connection relations to obtain a plurality of printed circuit board network table files with different functions, wherein the printed circuit board network table files comprise target printed circuit board network table files.
According to the method and the device, in the process, some pin names and default network interface names are acquired in advance in the programmable logic device resource, different printed circuit board net list files are generated through different functions of the printed circuit board, when a user generates the pin constraint files, the pin constraint files of corresponding functions can be directly generated through the set printed circuit board net list files and the pin information files, and the generation efficiency is improved.
The programmable logic device resource may be a database of an FPGA functional network. The board-level network connection relationship represents the connection relationship between pins and network interfaces in the printed circuit board, and a complete board-level network connection relationship can realize a printed circuit board with a preset function. The printed circuit board net list file may be considered as an intermediate file of the printed circuit board generated by the schematic diagram of the programmable logic device, for storing the pin names, network interface names of the corresponding function printed circuit boards, and connection relations, pairing relations, etc. of the pin names and network interface names of the boards. The network table files of the printed circuit boards can be directly called after being manufactured once, so that the manufacturing time is saved.
Step 120: and determining a plurality of network interface names of the printed circuit board with the preset function from the target printed circuit board network table file corresponding to the printed circuit board with the preset function.
The target printed circuit board net list file can be regarded as an intermediate file of the printed circuit board generated through the schematic diagram of the target programmable logic device, and is used for storing the pin names and the network interface names of the printed circuit board with preset functions, and the connection relation and the pairing relation of the pin names and the network interface names of the printed circuit board.
In some embodiments of the present application, determining a plurality of network interface names of a printed circuit board with a preset function from a target printed circuit board net list file corresponding to the printed circuit board with the preset function includes: determining the network interface name of the printed circuit board with a preset function connected with any pin to obtain a network interface name set; and acquiring default network interface names corresponding to the network interface name set from the target printed circuit board network table file to obtain a plurality of network interface names.
In the above process, the default network interface name corresponding to the network interface name set can be directly obtained from the target printed circuit board network table file, and then the pin constraint file can be directly and automatically generated according to the obtained multiple network interface names.
The network interface name set comprises network interface names corresponding to any pin in the printed circuit board in a connection relation. Because the network interface names in the network interface name set acquired at this time are obtained through naming, the network interface names at this time are required to be matched with default network interface names corresponding to the network table files of the target printed circuit board, and the network interface names in the network interface name set are corrected to obtain a plurality of network interface names.
Step 130: and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file.
The pin constraint file is used for storing the names of pins and network interfaces on the printed circuit board under a preset function and the connection relation between the pins and the network interfaces. Associating the plurality of pin names and the plurality of network interface names in the pin information file, wherein obtaining the pin constraint file comprises traversing the pin names, determining the connection relation between each pin and the network interface, and sorting according to the initial pinyin of the network interface names.
In some embodiments of the present application, after associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain the pin constraint file, the method shown in fig. 1 further includes: and screening the pin names which are not associated in the pin names and the network interface names with errors in the network interface names to obtain an error prompt file, wherein prompt information in the error prompt file comprises at least one of a network interface name naming error prompt, an attribute error prompt, a repeated connection error prompt and an error prompt which does not accord with a preset naming rule.
In the above process, the error prompt file may be generated by screening the pin names which are not associated in the plurality of pin names and the network interface names with errors in the plurality of network interface names, and the error prompt file may be used for notifying the user of error information when generating the pin constraint file.
Wherein the unassociated pin names represent names of pins that are not connected to the connected network interface. The network interface name in error indicates a network interface name that does not conform to a network interface name standard in the field or a network interface name that does not conform to a naming rule. The attribute error hint indicates that pins with different attributes are connected to the network interface, e.g., pins with power attributes are connected to the network interface with signal attributes. The repeated connection indicates that the network interface and the pin have multiple corresponding association relations. A failure to meet a preset naming rule indicates that the network interface name does not belong to a network interface name present in the pin information file.
In some embodiments of the present application, before filtering pin names that are not associated among the plurality of pin names and network interface names that have errors among the plurality of network interface names, the method shown in fig. 1 further includes: and searching the plurality of network interface names according to the naming rule of the hardware description language to obtain the network interface name with the error in the plurality of network interface names.
In the process, whether the network interface names are wrong in naming or not can be searched, the wrong network interface names are screened, and the influence of the wrong network interface names on the generation result when the pin constraint file is generated can be avoided.
Wherein a hardware description language (Verilog) can retrieve whether a naming error occurred in the network interface name.
In some embodiments of the present application, associating a plurality of pin names and a plurality of network interface names in a pin information file to obtain a pin constraint file includes: synthesizing the plurality of network interface names into one synthesized network interface name; and associating the synthesized network interface name with a plurality of pin names to obtain a pin constraint file.
In the above process, the network interface names can be synthesized into one synthesized network interface name, and the network interface name is used for matching the pin names, so that the association of the network interface name with the pins can be realized, and the pin constraint file under the corresponding function can be accurately generated.
The synthesized network interface means that a plurality of network interfaces can be synthesized into one network interface, so as to realize a new network interface function.
In some embodiments of the present application, associating a plurality of pin names and a plurality of network interface names in a pin information file to obtain a pin constraint file includes: sorting the plurality of network interface names according to the initial pinyin to obtain a sorted network interface name set; and associating the ordered network interface name set with a plurality of pin names to generate a pin constraint file in a preset format.
In the process, the network interface names in the output pin constraint file are ordered, so that a user can conveniently check and customize the network interface names of different types of packets.
The preset format can be set according to requirements and can be arranged according to the initial sequence of pinyin.
In the process shown in fig. 1, the pin information file includes a plurality of pin names and a plurality of default network interface names corresponding to the pin names, and functions corresponding to different printed circuit boards are different by acquiring the pin names in the pin information file corresponding to the printed circuit board with the preset function where the programmable logic device is located; determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function; and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file. The network interface name is directly extracted from the target printed circuit board network table file, the pin constraint file is automatically generated in a mode of matching the network interface name with pins in the pin information file, and because the pin information file and the target printed circuit board network table file are set in advance, a user can directly and automatically generate the corresponding pin constraint file when using the pin constraint file, and the pin constraint file extraction method has the advantages that the operation is more convenient, and meanwhile the accuracy of extracting the pin constraint file of the programmable logic device can be improved.
In the steps shown in fig. 1, extracting the IO information related to the FPGA from the PCB netlist file, performing error detection on the pins and the network interface information, associating the network interface information conforming to the rules with the pins to form a constraint file, and prompting the information not conforming to the rules. Therefore, the development time and difficulty of a developer are greatly reduced, the working efficiency is improved, and meanwhile, the accuracy of the constraint file is ensured. One-touch conversion completion may be implemented.
The method for generating the pin constraint file and the error prompt file by one key according to the embodiment of the present application is described in detail below with reference to fig. 2.
Referring to fig. 2, fig. 2 is a flowchart of a method for generating a pin constraint file and an error prompt file by one key according to an embodiment of the present application, where the method for generating the pin constraint file and the error prompt file by one key shown in fig. 2 includes:
step 210: and loading a pin information file of a corresponding model of the FPGA.
Specific: and acquiring and loading a standard pin information file of the programmable logic device with the corresponding model, and extracting the pin name in the pin information file.
Step 220: and loading the corresponding type of printed circuit board net list file.
Specific: and acquiring a printed circuit board network table file under a preset function, and loading to obtain the connection relation between the pins and the network interface.
Step 230: the algorithm matching pins and network interfaces are executed.
Specific: and matching the network interface connected with the pins in the pin information file from the printed circuit board network table file by using a preset script and algorithm.
Step 240: and outputting a pin constraint file and an error prompt file.
Specific: and combining the pin names obtained by successful matching with the network interface names to obtain pin constraint files, and inputting the pin names and the network interface names with errors, unmatched, attribute errors and naming errors into error prompt files.
In addition, the specific method and steps shown in fig. 2 may refer to the method shown in fig. 1, and will not be repeated here.
An implementation method for extracting a pin constraint file according to an embodiment of the present application is described in detail below with reference to fig. 3.
Referring to fig. 3, fig. 3 is a flowchart of an implementation method for extracting a pin constraint file according to an embodiment of the present application, where the implementation method for extracting a pin constraint file shown in fig. 3 includes:
step 310: and acquiring the pin names in the pin information file corresponding to the printed circuit board where the programmable logic device is located one by one.
Specific: traversing the pin names in the pin information file.
Step 320: network interface names associated with pin names in the pin information file are extracted from the target printed wiring board net list file.
Specific: and extracting the network interface names with association relation with the pin names extracted from the pin information file from the target printed circuit board network table file according to the external interfaces of the printed circuit boards with corresponding functions.
Step 330: the pin name and the network interface name are associated.
Specific: and associating the network interface name with the pin name.
Step 340: whether the pin names in the pin information file are all acquired.
Specific: it is detected whether the pin name in the pin information file is complete by traversing the query, if so, step 350 is entered, and if not, step 310 is returned.
Step 350: and error screening is carried out on the pin names and the network interface names.
Specific: pin names and network interface names that are wrong, unmatched, attribute wrong and naming wrong are filtered.
Step 360: the network interface names are ordered.
Specific: and ordering the network interface names and the corresponding pin names according to the initial letters of the network interface names to obtain the pin constraint file.
In addition, the specific method and step shown in fig. 3 may refer to the method shown in fig. 1, and will not be repeated here.
The method of extracting the pin constraint file is described above through fig. 1, and the apparatus for extracting the pin constraint file is described below with reference to fig. 4 to 5.
Referring to fig. 4, a schematic block diagram of an apparatus 400 for extracting a pin constraint file according to an embodiment of the present application is provided, where the apparatus 400 may be a module, a program segment, or a code on an electronic device. The apparatus 400 corresponds to the embodiment of the method of fig. 1 described above, and is capable of performing the steps involved in the embodiment of the method of fig. 1. The specific functions of the apparatus 400 will be described below, and detailed descriptions thereof will be omitted herein as appropriate to avoid redundancy.
Optionally, the apparatus 400 includes:
an obtaining module 410, configured to obtain a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where the programmable logic device is located, where the pin information file includes the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different;
a determining module 420, configured to determine a plurality of network interface names of the printed circuit board with a preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function;
The generating module 430 is configured to associate a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file.
Optionally, the apparatus further includes:
the input module is used for screening the pin names and default network interface names in the programmable logic device resources before the acquisition module acquires a plurality of pin names in the pin information file corresponding to the printed circuit board with the preset function of the programmable logic device, so as to obtain the pin information file; and inputting default network interface names in the pin information files into a plurality of netlists according to different board-level network connection relations to obtain a plurality of printed circuit board network table files with different functions, wherein the printed circuit board network table files comprise target printed circuit board network table files.
Optionally, the apparatus further includes:
and the screening module is used for screening the unassociated pin names in the pin names and the network interface names with errors in the network interface names after the generation module associates the pin names and the network interface names in the pin information file to obtain an error prompt file, wherein the prompt information in the error prompt file comprises at least one of a network interface name naming error prompt, an attribute error prompt, a repeated connection error prompt and an error prompt which does not accord with a preset naming rule.
Optionally, the apparatus further includes:
and the searching module is used for searching the plurality of network interface names according to the hardware description language naming rule before the screening module screens the pin names which are not associated in the plurality of pin names and the network interface names with errors in the plurality of network interface names to obtain the error prompt file, so as to obtain the network interface names with errors in the plurality of network interface names.
Optionally, the determining module is specifically configured to:
determining the network interface name of the printed circuit board with a preset function connected with any pin to obtain a network interface name set; and acquiring default network interface names corresponding to the network interface name set from the target printed circuit board network table file to obtain a plurality of network interface names.
Optionally, the generating module is specifically configured to:
synthesizing the plurality of network interface names into one synthesized network interface name; and associating the synthesized network interface name with a plurality of pin names to obtain a pin constraint file.
Optionally, the generating module is specifically configured to:
sorting the plurality of network interface names according to the initial pinyin to obtain a sorted network interface name set; and associating the ordered network interface name set with a plurality of pin names to generate a pin constraint file in a preset format.
Referring to fig. 5, a schematic structural diagram of an apparatus for extracting pin constraint files according to an embodiment of the present application may include a memory 510 and a processor 520. Optionally, the apparatus may further include: a communication interface 530 and a communication bus 540. The apparatus corresponds to the embodiment of the method of fig. 1 described above, and is capable of performing the steps involved in the embodiment of the method of fig. 1, and specific functions of the apparatus may be found in the following description.
In particular, the memory 510 is used to store computer readable instructions.
A communication interface 530 for communicating signaling or data with other node devices. For example: for communication with a server or terminal, or with other device nodes, the embodiments of the application are not limited in this regard.
A communication bus 540 for implementing direct connection communication of the above components.
The communication interface 530 of the device in the embodiment of the present application is used for performing signaling or data communication with other node devices. The memory 510 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. Memory 510 may also optionally be at least one storage device located remotely from the aforementioned processor. The memory 510 has stored therein computer readable instructions which, when executed by the processor 520, perform the method process described above in fig. 1. Processor 520 may be used on apparatus 400 and to perform the functions herein. By way of example, the processor 520 described above may be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable logic device (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, and the embodiments are not limited in this regard.
Embodiments of the present application also provide a readable storage medium, which when executed by a processor, performs a method process performed by an electronic device in the method embodiment shown in fig. 1.
It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding procedure in the foregoing method for the specific working procedure of the apparatus described above, and this will not be repeated here.
In summary, the embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for extracting a pin constraint file, where the method includes obtaining a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located, where the pin information file includes the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different; determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function; and associating a plurality of pin names and a plurality of network interface names in the pin information file to obtain a pin constraint file. The method can achieve the effect of improving the accuracy of extracting the pin constraint file of the programmable logic device.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method for extracting pin constraint files, comprising:
acquiring a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located, wherein the pin information file comprises the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and the functions corresponding to different printed circuit boards are different;
determining a plurality of network interface names of the printed circuit board with the preset function from a target printed circuit board network table file corresponding to the printed circuit board with the preset function;
and associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain a pin constraint file.
2. The method of claim 1, wherein before the obtaining the plurality of pin names in the pin information file corresponding to the printed circuit board with the preset function where the programmable logic device is located, the method further comprises:
screening the pin names and default network interface names in the programmable logic device resources to obtain the pin information files corresponding to the printed circuit boards with the preset functions where the programmable logic devices are located;
And inputting default network interface names in the pin information files into a plurality of netlists according to different board-level network connection relations to obtain a plurality of printed circuit board net list files with different functions, wherein the printed circuit board net list files comprise the target printed circuit board net list files.
3. The method of claim 1 or 2, wherein after said associating said plurality of pin names and said plurality of network interface names in said pin information file to obtain a pin constraint file, said method further comprises:
and screening the pin names which are not associated in the pin names and the network interface names with errors in the network interface names to obtain an error prompt file, wherein prompt information in the error prompt file comprises at least one of a network interface name naming error prompt, an attribute error prompt, a repeated connection error prompt and an error prompt which does not accord with a preset naming rule.
4. The method of claim 3, wherein prior to said filtering out pin names of said plurality of pin names that are not associated with network interface names that are incorrect, and network interface names of said plurality of network interface names, obtaining an error hint file, said method further comprises:
And searching the network interface names according to the naming rule of the hardware description language to obtain the network interface name with the error in the network interface names.
5. The method according to claim 1 or 2, wherein determining the network interface names of the printed circuit boards with the preset function from the target printed circuit board network table file corresponding to the printed circuit boards with the preset function includes:
determining the network interface name of the printed circuit board with the preset function connected with any pin to obtain a network interface name set;
and acquiring default network interface names corresponding to the network interface name set from the target printed circuit board network table file to obtain the network interface names.
6. The method according to claim 1 or 2, wherein said associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain a pin constraint file comprises:
synthesizing the plurality of network interface names into a synthesized network interface name;
and associating the synthesized network interface name with the plurality of pin names to obtain the pin constraint file.
7. The method according to claim 1 or 2, wherein said associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain a pin constraint file comprises:
sorting the plurality of network interface names according to initial pinyin to obtain a sorted network interface name set;
and associating the ordered network interface name set with the plurality of pin names to generate the pin constraint file in a preset format.
8. An apparatus for extracting pin constraint files, comprising:
the device comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a plurality of pin names in a pin information file corresponding to a printed circuit board with a preset function where a programmable logic device is located, wherein the pin information file comprises the plurality of pin names and a plurality of default network interface names corresponding to the plurality of pin names, and functions corresponding to different printed circuit boards are different;
the determining module is used for determining a plurality of network interface names of the printed circuit board with the preset function from the target printed circuit board network table file corresponding to the printed circuit board with the preset function;
and the generation module is used for associating the plurality of pin names and the plurality of network interface names in the pin information file to obtain a pin constraint file.
9. An electronic device, comprising:
a memory and a processor, the memory storing computer readable instructions that, when executed by the processor, perform the steps in the method of any of claims 1-7.
10. A computer-readable storage medium, comprising:
computer program which, when run on a computer, causes the computer to perform the method according to any of claims 1-7.
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| CN202310347712.XA CN116362175A (en) | 2023-04-03 | 2023-04-03 | Method, device, equipment and storage medium for extracting pin constraint file |
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| CN202310347712.XA CN116362175A (en) | 2023-04-03 | 2023-04-03 | Method, device, equipment and storage medium for extracting pin constraint file |
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| CN116362175A true CN116362175A (en) | 2023-06-30 |
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| CN202310347712.XA Pending CN116362175A (en) | 2023-04-03 | 2023-04-03 | Method, device, equipment and storage medium for extracting pin constraint file |
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