CN116362174A - IGBT design parameter global optimization method and system - Google Patents

IGBT design parameter global optimization method and system Download PDF

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CN116362174A
CN116362174A CN202310588502.XA CN202310588502A CN116362174A CN 116362174 A CN116362174 A CN 116362174A CN 202310588502 A CN202310588502 A CN 202310588502A CN 116362174 A CN116362174 A CN 116362174A
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杨鑫
王岳松
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Abstract

The invention discloses a global optimization method and a global optimization system for IGBT design parameters, which realize automatic searching of global optimal design parameters by adopting a particle swarm algorithm, and a designer can realize automatic searching of global optimal parameters only by giving performance requirements, so that the method and the system have low experience dependence on IGBT chip designers, lower manual extraction difficulty and cost and have wider applicability; in the process of selecting the global optimum performance design parameters, the trade-off relation of various performances is reasonably considered, and the global optimum of the design parameters is realized. The overall optimization process of the design parameters is efficient and reliable.

Description

IGBT design parameter global optimization method and system
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a global optimization method and system for IGBT design parameters.
Background
The IGBT (Insulated Gate Bipolar Transistor ) has advantages of easy driving and protection and high switching frequency as a core fully-controlled switching device in a power electronic apparatus, and is widely used in power electronic systems of various power classes. The design parameters of the power semiconductor chip often need to be selected in a compromise way in consideration of different requirements of an application end, and a chip design engineer usually uses an empirical formula to reversely push the design parameters according to the design requirements. However, in the IGBT chip design process, there is often a contradictory relationship between chip performances, which makes it difficult to consider different performances of the chip, and the selection of globally optimal performance design parameters is very challenging. The current IGBT physical model is continuously developed and perfected, can reflect the relation between parameters and the performance of an IGBT chip, and has higher precision. Through the combination of the high-precision IGBT physical model and the algorithm, the method is very significant in efficiently obtaining the global optimal scheme of IGBT design parameters.
At present, an IGBT chip designer mainly obtains the performance of an IGBT chip corresponding to the IGBT design parameters through finite element simulation software TCAD, and then determines the design parameters according to the performance of the chip. However, finite element simulation software TCAD simulation takes a long time, which results in a very inefficient chip design process. In addition, this design process is extremely dependent on designer experience and it is difficult to obtain globally optimal design parameters.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a global optimization method and a global optimization system for IGBT design parameters, which improve the design efficiency of IGBT chips.
In order to solve the technical problems, the invention adopts the following technical scheme: a global optimization method for IGBT design parameters comprises the following steps:
s1, defining the dimension of each particle as D, wherein D is the number of IGBT design parameters to be optimized, the position of each dimension of the particle corresponds to a design parameter variable value, initializing the optimization range of the design parameters, and initializing the speed and position of the particle;
respectively assigning the positions of each dimension of the ith particle to corresponding design parameters, and initializing the performance evaluation function of each particle by using the design parameter values of each particle; wherein i=1, 2, … …, N; n is the number of particles; the performance evaluation function is used for evaluating one or more of conduction characteristics, blocking characteristics, switching loss and short circuit capacity corresponding to the design parameters;
s2, updating the position of the ith particle in the d dimension when the (t+1) th iteration is updated by using the following formula
Figure SMS_1
：
Figure SMS_2
The method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>
Figure SMS_3
For the t iteration, the position of the ith particle in the D dimension is t is greater than or equal to 1, d=1, 2, … …, D;
Figure SMS_4
，/>
Figure SMS_5
for the t+1th iteration, the speed of the ith particle in the d-th dimension,ωas the weight of the inertia is given,C 1 andC 2 the individual weights and the group weights are respectively,R 1 andR 2 is a random number between 0 and 1, ">
Figure SMS_6
For the t-th iteration, the individual optimal positions of the ith particle in the d-th dimension,
Figure SMS_7
when the iteration is the t-th iteration, the optimal position of the population in the d-th dimension; updating the performance evaluation function by using the updated position;
wherein, the individual optimal position refers to: for any particle, if the updated performance evaluation function value corresponding to the particle is better than the historical performance evaluation function value of the particle, the position of the particle is the optimal position of the individual;
the group optimal position refers to the position of the particle corresponding to the minimum value in the evaluation function values corresponding to all particles in the current iteration;
s3, judging whether a termination condition is met, if so, outputting a design parameter value corresponding to the updated position; otherwise, the iteration number is increased by 1, and the step S2 is returned.
According to the invention, the particle swarm algorithm is adopted to realize automatic searching of the global optimal design parameters, and a designer can realize automatic searching of the global optimal parameters only by giving out performance requirements, so that the method has low experience dependence on IGBT chip designers, reduces the manual extraction difficulty and cost, and has wider applicability. The method reasonably utilizes the advantage that the physical model can be iterated quickly, and adopts the particle swarm optimization algorithm, so that the overall optimization process of the design parameters is efficient and reliable, and the design efficiency of the IGBT chip is greatly improved.
Further, in the present invention, the performance evaluation function may be a conduction characteristic evaluation functionSSE ON The conduction characteristic evaluation functionSSE ON The expression is:
Figure SMS_8
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX ON For the on-voltage corresponding to the design parameter,ER ON in order to achieve the desired value of the on-voltage,ω ON 、b ON 、K ON is a trade-off constant.
Further, in the present invention, the performance evaluation function may be a blocking characteristic evaluation functionSSE OFF The blocking characteristic evaluation functionSSE OFF The expression is:
Figure SMS_9
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX OFF For the corresponding pass-through voltage of the design parameter,ER OFF for the expected value of the on-voltage>
Figure SMS_10
，qIs the charge per unit of electron and,εis the dielectric constant of silicon and is defined by the following formula,N B is the doping concentration of the N-drift region,W B for the thickness of the N-drift region,ER OFF as a result of the expected value of the punch-through voltage,ω OFF 、b OFF 、K OFF is a trade-off constant.
Further, in the present invention, the performance evaluation function may be a switching loss evaluation functionSSE E The switching loss evaluation functionSSE E The expression is:
Figure SMS_11
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX E For the switching losses corresponding to the design parameters, ER E in order to obtain the expected value of the switching loss,ω E 、b E 、K E is a trade-off constant.
Further, in order to improve the reliability of the IGBT chip design, in the present invention, the performance evaluation function may be a short circuit capability evaluation functionSSE SC The short circuit capability evaluation functionSSE SC The expression is:
Figure SMS_12
whereinX SC For the short-circuit time corresponding to the design parameter,
Figure SMS_13
，T CR for the highest critical temperature, T, of the IGBT chip HS For the initial temperature of IGBT chip, V DC Is the collector DC power supply voltage, J ，CSAT For IGBT saturation current density, C V Is the specific heat of the volume,ER SC for the expected result value of the short-circuit time,ω SC 、b SC 、K SC in order to weigh the constants in order to be able to balance,W B for the thickness of the N-drift region,W H is the buffer layer thickness.
The performance evaluation functionSSEThe expression is:SSE=SSE ON +SSE OFF +SSE E +SSE SC the method comprises the steps of carrying out a first treatment on the surface of the Wherein,,SSE ON for the function of the evaluation of the on-characteristic,SSE OFF in order to evaluate the function of the blocking characteristic,SSE E as a function of the switching loss evaluation,SSE SC evaluating a function for short circuit capability;
the conduction characteristic evaluation functionSSE ON The expression is:
Figure SMS_14
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX ON For the on-voltage corresponding to the design parameter,ER ON is the expected value of the on voltage;
the blocking characteristic evaluation functionSSE OFF The expression is:
Figure SMS_15
；X OFF for the pass-through voltage corresponding to the design parameter, +.>
Figure SMS_16
，qIs the charge per unit of electron and,εis the dielectric constant of silicon and is defined by the following formula,N B doping concentration for the N-drift region;W B for the thickness of the N-drift region,ER OFF is the expected value of the punch-through voltage;
the switching loss evaluation functionSSE E The expression is:
Figure SMS_17
； X E for the switching losses corresponding to the design parameters,ER E is the expected value of the switching loss;
the short circuit capability assessment functionSSE SC The expression is:
Figure SMS_18
，X SC for the short-circuit time corresponding to the design parameter, +.>
Figure SMS_19
，T CR For the highest critical temperature, T, of the IGBT chip HS For the initial temperature of IGBT chip, V DC Is the collector DC power supply voltage, J C，SAT For IGBT saturation current density, C V Is the specific heat of the volume,ER SC for the expected result value of the short-circuit time,W B for the thickness of the N-drift region,W H is the thickness of the buffer layer;
ω ON 、b ON 、K ON 、ω OFF 、b OFF 、K OFF 、ω E 、b E 、K E 、ω SC 、b SC 、K SC is a trade-off constant.
In the invention, the termination conditions are as follows: after the t+1st iteration is completed, the design parameter performance evaluation function value corresponding to the population optimal position matrix of the particle population is smaller than or equal to a preset parameter performance evaluation function threshold.
In the present invention, the termination condition may be: the iteration number reaches a preset maximum iteration number.
In the present invention, the design parameters may include: MOS transconductance coefficient, half width between cells, chip active area, ratio of area between cells to active device area, N-drift region doping concentration, N-drift region thickness, N-drift region carrier lifetime, gate capacitance, gate threshold voltage, trench depth, buffer layer doping concentration, buffer layer carrier lifetime, buffer layer thickness.
As an inventive concept, the present invention also provides an IGBT design parameter global optimization system, including:
one or more processors;
and a memory having one or more programs stored thereon, which when executed by the one or more processors cause the one or more processors to implement the steps of the above-described method of the present invention.
Compared with the prior art, the invention has the following beneficial effects:
(1) According to the invention, the particle swarm algorithm is adopted to realize automatic searching of the global optimal design parameters, a designer can realize automatic searching of the global optimal parameters only by giving performance requirements, the degree of experience dependence on IGBT chip designers is low, the manual extraction difficulty and cost are reduced, and the applicability is wider;
(2) In the process of selecting the overall optimal performance design parameters, the trade-off relation of various performances is reasonably considered, and the overall optimal performance of the design parameters is realized;
(3) The overall optimization process of the design parameters is efficient and reliable.
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Fig. 1 is a flowchart of an automatic parameter extraction method for an IGBT physical model according to an embodiment of the present invention;
FIG. 2 is a flowchart of an automatic parameter extraction computer program according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a circuit for obtaining dynamic results;
FIG. 4 is a schematic diagram of a cell structure;
FIG. 5 is a graph showing the variation of function values in an iterative optimization process according to an embodiment of the present invention;
fig. 6 (a) to fig. 6 (d) are graphs of variation of the optimal performance evaluation function values of the on-state characteristics, the off-state characteristics, the switching loss and the short-circuit capability in the iterative optimization process according to the embodiment of the invention;
FIG. 7 is a graph of output characteristics of global optimum design parameters according to an embodiment of the present invention;
FIG. 8 is a graph of turn-on characteristics of global optimum design parameters under 700V/30A/300K conditions according to an embodiment of the present invention;
FIG. 9 is a graph of shutdown characteristics for a global optimum design parameter under 700V/30A/300K conditions in accordance with an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, the embodiment of the invention provides a global optimization method for an IGBT design parameter, which is to efficiently obtain the global optimal design parameter of the IGBT by combining a high-precision IGBT physical model and a particle swarm optimization algorithm, ensure that the IGBT design parameter is reasonably balanced and optimal among different performances, and reduce labor cost and difficulty.
Embodiment 1 of the present invention includes the following design works: a) The method comprises the following steps Determining IGBT chip design parameters and parameter ranges according to design requirements; b) The method comprises the following steps Establishing a performance evaluation function according to the performance index of the application requirement; c) The method comprises the following steps And (5) realizing the flow by global optimization of design parameters. D) The method comprises the following steps And (5) globally and automatically iterating and optimizing design parameters.
A) The method comprises the following steps Determining IGBT chip design parameters and parameter ranges according to design requirements;
the parameters required to optimize the design in this embodiment includeK p 、l m 、A、a i 、N B 、W B 、τ、C g 、V th 、W P 、N H 、τ NH 、W H . The IGBT cell structure designed by the embodiment is shown in fig. 4. Wherein the method comprises the steps ofK p Is MOS transconductance coefficient;l m is half width between units;Ais the chip active area;a i is the ratio of the area between the cells to the area of the active device;N B doping concentration for the N-drift region;W B is the N-drift region thickness;τcarrier lifetime for the N-drift region;C g is a gate capacitance;V th is the gate threshold voltage;W P is the depth of the groove;N H doping concentration for the buffer layer;τ NH carrier life for the buffer layer;W H is the buffer layer thickness.
The optimized design parameters are not limited to the 13 parameters described above.
The present embodiment describes the optimization of the design parameters of a trench gate cut (FS) IGBT rated at 1200V and 40A according to the application environment and application requirements of the IGBT chip designed to determine the range of the optimized design parameters. The ranges of the optimum design parameters determined according to their voltage-current levels are shown in table 1. Wherein Lb represents the lower limit of the design parameter range.
Figure SMS_20
B) The method comprises the following steps Establishing a performance evaluation function according to the performance index of the application requirement;
in one implementation, the performance metrics may include: conduction characteristics, blocking characteristics, switching losses, and shorting capability.
According to the embodiment of the invention, the current relatively accurate IGBT physical model is used for obtaining the electrical characteristics corresponding to the design parameters, and the electrical characteristics are used for performance evaluation.
This example uses a physical model of L.Lu (see: L.Lu, Z.Chen, A.Bryant, J.L. Hudgins, P.R. Palmer and E.Santi, "Modeling of MOS-SideCarrier Injection in Trench-Gate IGBTs," in IEEE Transactions on Industry Applications, vol. 46, no. 2, pp. 875-883, march-april 2010, doi: 10.1109/TIA.2009.2039770.). It is understood that the physical model used in the present application is not limited to this model, and the IGBT physical model is only used to obtain the electrical characteristics corresponding to the design parameters for performance evaluation.
In one implementation, the turn-on voltage is obtained by a forward turn-on characteristic (output characteristic curve) obtained by an IGBT physical model, and the switching loss is obtained by calculation of an turn-on/off waveform of the IGBT physical model.
An inductive circuit schematic diagram for obtaining dynamic results in the IGBT physical model is shown in fig. 3.
In the inductive circuit, the turn-on process of the IGBT is affected by the diode, and the turn-off process is hardly affected by the diode, so that the turn-off loss is used as the evaluation of the switching loss in the embodiment of the invention.
In one implementation, the blocking characteristic refers to the withstand voltage of the device, and for FS IGBTs, the nominal voltage value is typically the drift region critical punch-through voltage, and an equation derived from poisson's equation is used to calculate the withstand voltage:
Figure SMS_21
whereinV D Is the voltage of the punch-through,qis the charge per unit of electron and,εis the dielectric constant of silicon.
In one implementation, the short circuit capability calculation formula is as follows:
Figure SMS_22
。
wherein t is SCSOA For short-circuit time, T CR For IGBT chips to withstand the highest critical temperature (for silicon, the critical temperature is approximately 700K), T HS For the initial temperature of IGBT chip, V DC Is the collector DC power supply voltage, J C，SAT For IGBT saturation current density, C V Is the specific heat capacity (1.66J cm for silicon) -3 K）。
The saturated current calculation method comprises the following steps:
Figure SMS_23
whereinV GE Is the IGBT gate-emitter voltage.
In one implementation, the performance evaluation function is:SSE=SSE ON +SSE OFF +SSE E +SSE SC whereinSSE ON For the function of the evaluation of the on-characteristic,SSE OFF in order to evaluate the function of the blocking characteristic,SSE E as a function of the switching loss evaluation,SSE SC a function is evaluated for short circuit capability.
In one implementation, the conduction characteristic evaluation functionSSE ON ：
Figure SMS_24
WhereinX ON For the on-characteristics corresponding to the design parameters,ER ON in this embodiment, the expected value of the conduction characteristic is set according to the application requirementER ON The value was 1.8V (inV GE =15V,I C =40a, chip temperature of 2An on-state voltage drop value at 5 ℃);ω ON 、b ON 、K ON to balance the constants, one chooses to balance between application requirements and different performance.
In one implementation, the blocking characteristic evaluation functionSSE OFF ：
Figure SMS_25
WhereinX OFF For the blocking characteristics corresponding to the design parameters,ER OFF to set the expected value of the blocking characteristic according to the application requirement, in this embodimentER OFF A value of 1200V; wherein the method comprises the steps ofω OFF 、b OFF 、K OFF To balance the constants, one chooses to balance between application requirements and different performance.
In one implementation, the switching loss evaluation functionSSE E ：
Figure SMS_26
WhereinX E For the switching losses corresponding to the design parameters,ER E for the expected value of the switching loss, the expected value of the switching loss is set according to the application requirement, and in the embodimentER E A value of 3mJ (turn-off loss at a collector voltage of 700V, a collector current of 30A, a drive resistance of 16 ohms, a chip temperature of 25 ℃); wherein the method comprises the steps ofω E 、b E 、K E To balance the constants, one chooses to balance between application requirements and different performance.
In one implementation, the short circuit capability assessment functionSSE SC ：
Figure SMS_27
WhereinX SC For the short-circuit capability corresponding to the design parameters,ER SC in order to set the expected result value of the short-circuit capability according to the application requirement, the expected result value of the short-circuit capability is set in the embodimentER SC A value of 20μs (conduction voltage drop value when collector DC power supply voltage is 700V); wherein the method comprises the steps ofω SC 、b SC 、K SC To balance the constants, one chooses to balance between application requirements and different performance.
In one implementation, regarding the method for calculating the trade-off constant, several performance values may be given in advance, and the performance evaluation function values of the several performance values may be given according to the application requirement and the design requirement, and the trade-off constant may be obtained by a function fitting method.
The performance values and performance evaluation function values in this example are shown in table 2:
Figure SMS_28
there are many well-established methods of function fitting in the prior art, and this example uses cftool in Matlab for fitting. The trade-off constants obtained by fitting are shown in table 3 below.
Figure SMS_29
It is to be understood that the performance evaluation function of the present application is not limited to the above form. The performance evaluation function includes a trade-off constant, which may be obtained by a method of function fitting.
C) The method comprises the following steps The design parameters globally optimize the creation of an automated computer program.
Referring to fig. 2, the automatic parameter extraction process includes the steps of:
c1 A) of: setting a design parameter optimization range;
c2 A) of: defining N particles for optimizing design parameters, wherein the position of each dimension of the particles represents a design parameter variable value, and the speed and the position of the particles are randomly generated within a set range;
the dimension D of each particle is equal to the number of design parameters to be optimized. In a computer program, particles are represented by a matrix of size 1 x D, the initial positions of the particles being randomly generated within a set parameter search range. The speed of the particles is also represented by a 1 x D matrix, the maximum movement speed of the particles is twenty percent of the parameter searching range, the minimum speed is zero, and the initial speed of the particles is randomly generated within the allowable range of the particle speed.
C3 A) of: the particle position information is endowed to design parameter variables, and a performance evaluation function is called to obtain a design parameter performance evaluation result;
and respectively endowing the values of the D dimensions of the ith particle with corresponding design parameter variables, and updating the design parameters of each iteration by the method. And calling the performance evaluation function to obtain a design parameter performance evaluation result after updating the design parameter.
And B, automatically calculating the conduction characteristic, the blocking characteristic, the switching loss and the short circuit capacity corresponding to the current design parameter in the process of calling the performance evaluation function, wherein the calculation method is shown in the step B.
C4 A) of: updating the current speed of the particles, and updating the positions of the particles according to the current speed of the particles;
the particle moves towards the optimal direction of the individual and the optimal direction of the group on the basis of the original inertial velocity, and the particle updates the current velocity by the calculation method:
Figure SMS_30
。
the particle updates its own position according to its own speed, and the calculation method for updating the particle position:
Figure SMS_31
。
Figure SMS_32
for the t+1st iteration, the position of the ith particle in the D dimension, t is greater than or equal to 1, d=1, 2, … …, D;
Figure SMS_33
for the t+1th iteration, the speed of the ith particle in the d-th dimension,ωas the weight of the inertia is given,C 1 andC 2 the individual weights and the group weights are respectively,R 1 andR 2 is a random number between 0 and 1, ">
Figure SMS_34
For the t-th iteration, the individual optimal position of the ith particle in the d-th dimension,/>
Figure SMS_35
And at the t-th iteration, the optimal position of the population in the d-th dimension.
The individual optimal position acquisition process may be as follows: recording the design parameter evaluation result of each particle, and if the design parameter evaluation result of the particle is better than the historical design parameter evaluation result of the particle (the smaller the error evaluation function value is, the better), updating the parameter value of the particle to the optimal position of the individual.
In this embodiment, it is not easy to understand that the evaluation result of the historical design parameters refers to the individual optimal position before the t+1st iteration.
The population optimal position acquisition process may employ the following manner: if the evaluation result of a certain particle design parameter is better than the evaluation result of all other particle design parameters, updating the parameter value of the dimension of the particle to the group optimal position.
At iteration 1, i.e. when t=1, the optimal position of the individual, i.e. the position at initialization.
C5 A) of: judging whether a termination condition is met, if so, finishing the design parameter optimization to exit the design parameter optimization program and outputting an optimal solution, and if not, returning to the step C3);
the optimal solution is the group optimal position.
The termination condition is either condition one or condition two.
Condition one: after the t-th iteration is completed, the performance evaluation function value of the design parameter corresponding to the population optimal position matrix of the particle population is smaller than or not larger than the preset parameter performance evaluation function threshold.
Condition II: the iteration number reaches a preset maximum iteration number.
D) The method comprises the following steps And (5) globally and automatically iterating and optimizing design parameters.
In the embodiment, 15 particle iterations are used for carrying out overall automatic iterative optimization on design parameters for 18 times, a change curve chart of a performance function value in the iterative optimization process is shown in fig. 5, and change curve charts of an optimal performance evaluation function value of conducting characteristics, blocking characteristics, switching loss and short circuit capacity in the iterative optimization process are shown in fig. 6 (a) to 6 (d).
The design parameters obtained by global automatic iterative optimization of the design parameters in this embodiment are shown in table 4.
Figure SMS_36
In the implementation, the on-voltage drop of the design parameters obtained through the overall automatic iterative optimization of the design parameters is 1.8V, the withstand voltage is 1900V, the turn-off loss is 4.6 mJ, and the short circuit capacity is 25μs. In the embodiment, the design parameters obtained through global automatic iterative optimization of the design parameters are substituted into an accurate IGBT physical model to obtain electric characteristic output characteristics shown in fig. 7, the on characteristics under the working condition of 700V/30A/300K are shown in fig. 8, and the off characteristics under the working condition of 700V/30A/300K are shown in fig. 9. As can be seen from fig. 7 to 9, for a trench gate Stop (FS) IGBT with a rated voltage of 1200V and a rated current of 40A, the performance of on-voltage drop, switching speed, etc. under the designed parameters are excellent.
Example 2
Embodiment 2 of the present invention provides an IGBT design parameter global optimization system corresponding to embodiment 1 above, where the system may be a processing device for a client, such as a mobile phone, a notebook computer, a tablet computer, a desktop computer, etc., to execute the method of the above embodiment.
The system of the present embodiment includes a memory, a processor, and a computer program stored on the memory; the processor executes the computer program on the memory to implement the steps of the method of embodiment 1 described above.
In some implementations, the memory may be high-speed random access memory (RAM: random Access Memory), and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
In other implementations, the processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other general-purpose processor, which is not limited herein.
Example 3
Embodiment 3 of the present invention provides a computer-readable storage medium corresponding to embodiment 1 described above, on which a computer program/instructions is stored. The steps of the method of embodiment 1 described above are implemented when the computer program/instructions are executed by a processor.
The computer readable storage medium may be a tangible device that retains and stores instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination of the preceding.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The solutions in the embodiments of the present application may be implemented in various computer languages, for example, object-oriented programming language Java, and an transliterated scripting language JavaScript, etc.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (10)

1. The global optimization method for the IGBT design parameters is characterized by comprising the following steps of:
s1, defining the dimension of each particle as D, wherein D is the number of IGBT design parameters to be optimized, the position of each dimension of the particle corresponds to a design parameter variable value, initializing the optimization range of the design parameters, and initializing the speed and position of the particle;
respectively assigning the positions of each dimension of the ith particle to corresponding design parameters, and initializing the performance evaluation function of each particle by using the design parameter values of each particle; wherein i=1, 2, … …, N; n is the number of particles; the performance evaluation function is used for evaluating one or more of conduction characteristics, blocking characteristics, switching loss and short circuit capacity corresponding to the design parameters;
s2, updating the position of the ith particle in the d dimension when the (t+1) th iteration is updated by using the following formula
Figure QLYQS_1
：
Figure QLYQS_2
The method comprises the steps of carrying out a first treatment on the surface of the Wherein (1)>
Figure QLYQS_3
For the t iteration, the position of the ith particle in the D dimension is t is greater than or equal to 1, d=1, 2, … …, D;
Figure QLYQS_4
，/>
Figure QLYQS_5
for the t+1th iteration, the speed of the ith particle in the d-th dimension,ωas the weight of the inertia is given,C 1 andC 2 the individual weights and the group weights are respectively,R 1 andR 2 is a random number between 0 and 1, ">
Figure QLYQS_6
For the t-th iteration, the individual optimal position of the ith particle in the d-th dimension,/>
Figure QLYQS_7
When the iteration is the t-th iteration, the optimal position of the population in the d-th dimension; updating the performance evaluation function by using the updated position;
wherein, the individual optimal position refers to: for any particle, if the updated performance evaluation function value corresponding to the particle is better than the historical performance evaluation function value of the particle, the position of the particle is the optimal position of the individual;
the group optimal position refers to the position of the particle corresponding to the minimum value in the evaluation function values corresponding to all particles in the current iteration;
s3, judging whether a termination condition is met, if so, outputting a design parameter value corresponding to the updated position; otherwise, the iteration number is increased by 1, and the step S2 is returned.
2. The IGBT design parameter global optimization method of claim 1 wherein the performance evaluation function is a turn-on characteristic evaluation functionSSE ON The conduction characteristic evaluation functionSSE ON The expression is:
Figure QLYQS_8
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX ON For the on-voltage corresponding to the design parameter,ER ON in order to achieve the desired value of the on-voltage,ω ON 、b ON 、K ON is a trade-off constant.
3. The IGBT design parameter global optimization method of claim 1 wherein the performance evaluation function is a blocking characteristic evaluation functionSSE OFF The blocking characteristic evaluation functionSSE OFF The expression is:
Figure QLYQS_9
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX OFF For the corresponding pass-through voltage of the design parameter,ER OFF for the expected value of the on-voltage>
Figure QLYQS_10
，qIs the charge per unit of electron and,εis the dielectric constant of silicon and is defined by the following formula,N B is the doping concentration of the N-drift region,W B for the thickness of the N-drift region,ER OFF as a result of the expected value of the punch-through voltage,ω OFF 、b OFF 、K OFF is a trade-off constant.
4. According to claim 1The IGBT design parameter global optimization method is characterized in that the performance evaluation function is a switching loss evaluation functionSSE E The switching loss evaluation functionSSE E The expression is:
Figure QLYQS_11
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX E For the switching losses corresponding to the design parameters, ER E in order to obtain the expected value of the switching loss,ω E 、b E 、K E is a trade-off constant.
5. The IGBT design parameter global optimization method of claim 1 wherein the performance evaluation function is a short circuit capability evaluation functionSSE SC The short circuit capability evaluation functionSSE SC The expression is:
Figure QLYQS_12
whereinX SC For the short-circuit time corresponding to the design parameter,
Figure QLYQS_13
，T CR for the highest critical temperature, T, of the IGBT chip HS For the initial temperature of IGBT chip, V DC Is the collector DC power supply voltage, J ，CSAT For IGBT saturation current density, C V Is the specific heat of the volume,ER SC for the expected result value of the short-circuit time,ω SC 、b SC 、K SC in order to weigh the constants in order to be able to balance,W B for the thickness of the N-drift region,W H is the buffer layer thickness.
6. The IGBT design parameter global optimization method of claim 1 wherein the performance evaluation functionSSEThe expression is:SSE=SSE ON +SSE OFF +SSE E +SSE SC the method comprises the steps of carrying out a first treatment on the surface of the Wherein,,SSE ON for the function of the evaluation of the on-characteristic,SSE OFF in order to evaluate the function of the blocking characteristic,SSE E as a function of the switching loss evaluation,SSE SC evaluating a function for short circuit capability;
the conduction characteristic evaluation functionSSE ON The expression is:
Figure QLYQS_14
the method comprises the steps of carrying out a first treatment on the surface of the Wherein the method comprises the steps ofX ON For the on-voltage corresponding to the design parameter,ER ON is the expected value of the on voltage;
the blocking characteristic evaluation functionSSE OFF The expression is:
Figure QLYQS_15
； X OFF for the pass-through voltage corresponding to the design parameter, +.>
Figure QLYQS_16
，qIs the charge per unit of electron and,εis the dielectric constant of silicon and is defined by the following formula,N B doping concentration for the N-drift region;W B for the thickness of the N-drift region,ER OFF is the expected value of the punch-through voltage;
the switching loss evaluation functionSSE E The expression is:
Figure QLYQS_17
； X E for the switching losses corresponding to the design parameters,ER E is the expected value of the switching loss;
the short circuit capability assessment functionSSE SC The expression is:
Figure QLYQS_18
， X SC for the short-circuit time corresponding to the design parameter, +.>
Figure QLYQS_19
，T CR For the highest critical temperature, T, of the IGBT chip HS For the initial temperature of IGBT chip, V DC Is the collector DC power supply voltage, J C，SAT For IGBT saturation current density, C V Is the specific heat of the volume,ER SC for the expected result value of the short-circuit time,W B for the thickness of the N-drift region,W H is the thickness of the buffer layer;
ω ON 、b ON 、K ON 、ω OFF 、b OFF 、K OFF 、ω E 、b E 、K E 、ω SC 、b SC 、K SC is a trade-off constant.
7. The IGBT design parameter global optimization method according to one of claims 1 to 6, characterized in that the termination condition is: after the t+1st iteration is completed, the design parameter performance evaluation function value corresponding to the population optimal position matrix of the particle population is smaller than or equal to a preset parameter performance evaluation function threshold.
8. The IGBT design parameter global optimization method according to one of claims 1 to 6, characterized in that the termination condition is: the iteration number reaches a preset maximum iteration number.
9. The IGBT design parameter global optimization method according to one of claims 1 to 6, characterized in that the design parameters include: MOS transconductance coefficient, half width between cells, chip active area, ratio of area between cells to active device area, N-drift region doping concentration, N-drift region thickness, N-drift region carrier lifetime, gate capacitance, gate threshold voltage, trench depth, buffer layer doping concentration, buffer layer carrier lifetime, buffer layer thickness.
10. An IGBT design parameter global optimization system, comprising:
one or more processors;
a memory having one or more programs stored thereon, which when executed by the one or more processors, cause the one or more processors to implement the steps of the method of any of claims 1-9.
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