CN116360859B - Power domain access method, device, equipment and storage medium - Google Patents
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a power domain access method, a device, equipment and a storage medium, and relates to the technical field of electronic information technology. The method comprises the steps of obtaining codes of power domains to be accessed; wherein the code consists of a base address index, an offset address index and a bit domain address index; determining an address to the power domain according to the code of the power domain; and accessing the address of the power domain and operating the power domain. By adopting the technical scheme, the power domain in the register can be quickly accessed, and the access efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of electronic information technologies, and in particular, to a method, an apparatus, a device, and a storage medium for accessing a power domain.
Background
At present, in modern chips, internal modules are more and more complex, so that for the convenience of back-end implementation, all performance monitoring unit registers cannot be uniformly placed in one place, but are divided into a plurality of larger parts according to the requirements of back-end layout wiring, and are stored separately.
In the existing method for accessing the register, which bit field of which register is to be accessed, the absolute address of the register needs to be manually calculated, and the absolute address is transmitted into a register read-write function to realize the access of the register.
The development of the code needs to be repeated at the time of code writing. For example, the registers of the power management unit in the project are scattered in three register forms, the base address of each form is different, if the up-down current path function codes are developed according to the traditional method, three function codes need to be developed, the function code development is complex, the use is not clear enough, and the efficiency is low.
Therefore, there is a need for a power domain access method that can achieve fast access to a power domain in a register, improve access efficiency of the power domain, and improve maintenance rate of codes.
Disclosure of Invention
The application provides a power domain access method, a device, equipment and a storage medium, which can realize rapid access to a power domain in a register and improve access efficiency.
In a first aspect, the present application provides a method for accessing a power domain, the method including:
acquiring codes of power domains to be accessed; wherein the code consists of a base address index, an offset address index and a bit domain address index;
determining an address to the power domain according to the code of the power domain;
and accessing the address of the power domain and operating the power domain.
In one example, the determining the address to the power domain according to the encoding of the power domain includes:
determining a first address according to the base address index; wherein the first address characterizes an address of a register set where the power domain is located;
determining a second address according to the offset address index and the first address; wherein the second address characterizes an address of the register;
and determining the address of the power domain according to the bit domain address index and the second address.
In one example, the sum of the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index is the same as the sum of the encoded numbers of bits.
In one example, the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index are dynamically adjusted according to user settings.
In one example, the operating the power domain includes:
and powering up, powering down, resetting or turning off a clock for the power domain.
In one example, before the obtaining the encoding of the power domain to be accessed, the method further comprises:
macro definition is carried out on the address of the power domain, and the code of the power domain is obtained;
and storing the codes of the power domains into a preset database.
In one example, the method further comprises:
acquiring a request message for verifying a queue serial peripheral interface module;
calling a function of powering on or powering off according to the request message;
and writing codes of the power domains corresponding to the queue serial peripheral interface modules in the functions so as to verify the queue serial peripheral interface modules.
In one example, the power domain is encoded as a 32-bit unsigned integer.
In a second aspect, the present application provides an access device for a power domain, the device comprising:
the first acquisition unit is used for acquiring codes of power domains to be accessed; wherein the code consists of a base address index, an offset address index and a bit domain address index;
a determining unit, configured to determine an address to the power domain according to the code of the power domain;
and the access unit is used for accessing the address of the power domain and operating the power domain.
In one example, the determining unit includes:
the first determining module is used for determining a first address according to the base address index; wherein the first address characterizes an address of a register set where the power domain is located;
the second determining module is used for determining a second address according to the offset address index and the first address; wherein the second address characterizes an address of the register;
and a third determining module, configured to determine an address of the power domain according to the bit domain address index and the second address.
In one example, the sum of the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index is the same as the sum of the encoded numbers of bits.
In one example, the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index are dynamically adjusted according to user settings.
In one example, before the obtaining the encoding of the power domain to be accessed, the apparatus further comprises:
the definition unit is used for carrying out macro definition on the address of the power domain to obtain the code of the power domain;
and the storage unit is used for storing the codes of the power domains into a preset database.
In one example, the apparatus further comprises:
the second acquisition unit is used for acquiring a request message verified by the queue serial peripheral interface module;
the calling unit is used for calling a function which is electrified or powered off according to the request message;
and the writing unit is used for writing the code of the power domain corresponding to the queue serial peripheral interface module in the function so as to verify the queue serial peripheral interface module.
In one example, the power domain is encoded as a 32-bit unsigned integer.
In one example, an access unit includes:
and the operation module is used for carrying out the operations of powering on, powering off, resetting or closing the clock on the power domain.
In a third aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method as described in the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having stored therein computer-executable instructions for performing the method according to the first aspect when executed by a processor.
In a fifth aspect, the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the method according to the first aspect.
The access method, the device, the equipment and the storage medium of the power domain provided by the application are characterized in that codes of the power domain to be accessed are obtained; the code consists of a base address index, an offset address index and a bit domain address index; determining an address to the power domain according to the code of the power domain; and accessing the address of the power domain and operating the power domain. By adopting the technical scheme, the power domain in the register can be quickly accessed, and the access efficiency is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a flowchart of a method for accessing a power domain according to a first embodiment of the present application;
fig. 2 is a schematic structural diagram of a power management unit according to a first embodiment of the present application;
fig. 3 is a flowchart of a power domain access method according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of an access device for a power domain according to a third embodiment of the present application;
fig. 5 is a schematic structural diagram of an access device for a power domain according to a fourth embodiment of the present application;
fig. 6 is a block diagram of an electronic device, according to an example embodiment.
Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
In modern chips, the internal modules are more and more complex, as are the power domain interfaces. At present, at least about 200 power domains exist in a chip. For the convenience of the back-end implementation, all the power management units cannot be uniformly placed in one place, but are divided into a plurality of larger parts according to the requirements of the back-end layout wiring, and are stored separately.
Taking an actual project as an example, since the power management units in the project are dispersed in three register forms, the base address of each form is different, and if the up-down current path function is developed according to a conventional method, three functions need to be developed. The function development is complex and is not clear enough when in use.
The unified coding mode of the base address index, the offset address index and the bit domain address index is realized by macro definition, and compared with the existing method, different base addresses, different offset addresses and all bit domains can be managed in a unified way. The method is clearer and simpler in process development, code writing and maintenance.
The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a flowchart of a power domain access method according to an embodiment of the present application. The first embodiment comprises the following steps:
s101, acquiring codes of power domains to be accessed, wherein the codes consist of a base address index, an offset address index and a bit domain address index.
In one example, the power domains are partitioned according to power logic that includes both designed physical entities and connections between power domains, where the modules operating at the same voltage are the same power domain.
In this embodiment, the power management unit includes a plurality of registers, and each of the registers includes a plurality of power domains, where each power domain is a bit domain. For a better illustration of the present embodiment, reference may be made to a schematic configuration of a power management unit shown in fig. 2, and it may be seen from fig. 2 that the power management unit a includes registers a to N, and the register a includes power domains 0 to 9. In this embodiment, since the number of power domains is more than one, different power domains need to be encoded in order to distinguish between the different power domains.
S102, determining an address to the power domain according to the code of the power domain.
In this embodiment, the address to the power domain is determined by the coding of the power domain and the rule of the coding, and the power domain is accessed.
S103, accessing the address of the power domain and operating the power domain.
In this embodiment, the operation on the power domain includes the operation of powering up, powering down, resetting, or turning off the clock on the power domain. For a chip, a plurality of power domains and subsystems are integrated to play the functions of the chip, the working speed and the performance requirements of different power domains are different, and the power domains need to be operated at different clock frequencies and different working voltages according to actual needs. For power domains that temporarily do not need to operate, either reducing dynamic power consumption by clock flipping by reducing the clock frequency or turning off the clock, or reducing static power consumption by powering off can be used.
According to the access method of the power domain, the code of the power domain to be accessed is obtained; the code consists of a base address index, an offset address index and a bit domain address index; indexing to the address of the power domain according to the code of the power domain; and accessing the address of the power domain and operating the power domain. By adopting the technical scheme, the power domain in the register can be quickly accessed, and the access efficiency is improved.
Fig. 3 is a flowchart of a power domain access method according to a second embodiment of the present application. The second embodiment includes the following steps:
s301, acquiring codes of power domains to be accessed, wherein the codes consist of a base address index, an offset address index and a bit domain address index.
In this embodiment, before obtaining the code of the power domain to be accessed, the method further includes:
macro definition is carried out on the address of the power domain, and the code of the power domain is obtained;
and storing the codes of the power domain into a preset database.
In one example, a macro definition specifies an identifier to characterize a string of characters. For example, define SM 0; define VID 1; define NOC 2. Wherein defined SM 0 characterizes SM as 0; define VID 1 characterizes VID as 1; defined NOC 2 characterizes a NOC of 2. Further, the code of the power domain is a 32-bit unsigned integer, the unsigned integer is stored in a preset database, and then the code of the power domain to be accessed is obtained from the preset database.
S302, determining a first address according to the base address index; wherein the first address characterizes an address of a register set where the power domain is located.
In this embodiment, the base address index is an index of a register set having the same base address of a register, e.g., registers A-G, having the same base address of a register, then registers A-G are the same index, e.g., 0. If the registers H-L have the same base register address, then the registers H-L are of the same index, e.g., 1. Depending on the use scenario, a larger bit width may be given to represent more register sets, if desired. In this embodiment, if the base address index is 0, the first address is registers A-G; if the base address index is 1, the first address is the register H-L.
The sum of the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index is the same as the sum of the encoded numbers of bits. For example, if the number of encoded bits is 32 bits, 31 bits to 12 bits represent the number of bits of the base address index, 11 bits to 8 bits represent the number of bits of the offset address index, and 7 bits to 0 bits represent the number of bits of the bit field index. And for all the power domains, the actual positions of the power domains planned by the chip designer are corresponding to the macro definition.
S303, determining a second address according to the offset address index and the first address; wherein the second address characterizes an address of the register.
In this embodiment, the offset address index indicates the index of a certain register itself in the register set of the same base address. For example, the first address is a register a-G, where in the register a-G, the offset address index of the register a is 0 and the offset address index of the register G is 6, and a specific register, that is, the second address 10, can be determined according to the offset address index and the first address.
S304, determining the address of the power domain according to the bit domain address index and the second address.
In this embodiment, the bit field address index represents the code of each bit field in a register, for example, in the register a, assuming that 10 power fields are defined and 10 corresponding bit fields are respectively corresponding to indexes 0-9, so that the bit field index in the macro definition is used as an unsigned number, and the decimal value represented by the unsigned number is the corresponding index 0-9. Specifically, the address of the power domain may be 100, then the first bit domain in register A of registers A-G is characterized. The advantage of this arrangement is that the macro definition method is adopted to decouple the user from the developer, the user does not need to learn the definition of the power management unit, and the up-down current path function generated based on the set of coding method can be directly used.
For a better illustration, see the macro-defined procedure given below, there are approximately 300 actual power domains.
define SM 0；
define VID 1；
define NOC 2；
define pcie_dma_pd ((SM<<12) + (2<<8) + 13)；
define vid_wave627_0_pd ((VID<<12) + (0<<8) + 14)；
define noc_ddr0_pd ((NOC<<12) + (3<<8) + 14)；
In this embodiment, three different base address indices are used, SM, VID, NOC respectively, so that the base address index actually has only 3 values, namely 0, 1, 2, which are related to the actual item.
In one example, the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index are dynamically adjusted according to user settings.
In particular, different bit widths may be used to represent different base address indexes for different project requirements.
In each identical base address, no more than 16 registers are defined, so the bit width of the offset address index is set to 4 to meet the requirement, i.e., 11 bits-8 bits.
There are 32 bit fields in each register at most, corresponding to 32 power supply fields, and each power supply field is a set of logic units which are independently powered up and powered down in the chip. At present, 7 bits to 0 bits are set, so that the requirements are satisfied. In general, according to this method, at most, individual power domains can be managed uniformly, which is far from the actual chip.
S305, accessing the address of the power domain, and powering on, powering off, resetting or turning off the clock for the power domain.
In this embodiment, the operations of powering up, powering down, resetting, or turning off the clock may save the energy consumption of the power domain that does not work.
In one example, a request message is obtained to authenticate a queue serial peripheral interface module; calling a function of powering up or powering down according to the request message; and writing codes of power domains corresponding to the queue serial peripheral interface modules in the functions so as to verify the queue serial peripheral interface modules.
In this embodiment, the request message for verifying the queue serial peripheral interface module is initiated by the user, which indicates that the user needs to verify the queue serial peripheral interface module, and then needs to access the power domain corresponding to the queue serial peripheral interface module. Specifically, after receiving the request message, a function of powering on or powering off is called, and the code of the power domain is written into the function, so that verification of the queue serial peripheral interface module is realized.
According to the access method of the power domain, the code of the power domain to be accessed is obtained, the first address is determined according to the base address index, the second address is determined according to the offset address index and the first address, the address of the power domain is determined according to the bit domain address index and the second address, the address of the power domain is accessed, and the power domain is powered on, powered off, reset or turned off. By adopting the technical scheme, the defects that personnel need to develop different codes respectively to perform power-on and power-off or other operations can be overcome, programming and code checking are easy due to the unified coding mode, and the reliability of the codes is improved.
Fig. 4 is a schematic structural diagram of an access device for a power domain according to a third embodiment of the present application. Specifically, the apparatus 40 of the third embodiment includes:
a first obtaining unit 401, configured to obtain an encoding of a power domain to be accessed; wherein the code consists of a base address index, an offset address index, and a bit field address index.
A determining unit 402, configured to determine an address to the power domain according to the code of the power domain.
An access unit 403, configured to access an address of the power domain and operate on the power domain.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Fig. 5 is a schematic structural diagram of an access device for a power domain according to a fourth embodiment of the present application. Specifically, the apparatus 50 of the fourth embodiment includes:
a first obtaining unit 501, configured to obtain an encoding of a power domain to be accessed; wherein the code consists of a base address index, an offset address index, and a bit field address index.
A determining unit 502, configured to determine an address to the power domain according to the code of the power domain.
An access unit 503, configured to access the address of the power domain and operate the power domain.
In one example, the determining unit 502 includes:
a first determining module 5021, configured to index to a first address according to the base address index; wherein the first address characterizes an address of a register set where the power domain is located.
A second determining module 5022, configured to determine a second address according to the offset address index and the first address; wherein the second address characterizes an address of the register.
The third determining module 5023 is configured to determine the address of the power domain according to the bit domain address index and the second address.
In one example, the sum of the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index is the same as the sum of the encoded numbers of bits.
In one example, the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index are dynamically adjusted according to user settings.
In one example, prior to obtaining the encoding of the power domain to be accessed, the apparatus 50 further comprises:
a defining unit 504, configured to macro-define the address of the power domain, and obtain the code of the power domain.
A saving unit 505, configured to save the code of the power domain to a preset database.
In one example, the encoding of the power domain is a 32-bit unsigned integer.
In one example, the apparatus 50 further comprises:
a second obtaining unit 506, configured to obtain a request message for verifying the queue serial peripheral interface module.
And the calling unit 507 is used for calling the function of powering on or powering off according to the request message.
And the writing unit 508 is configured to write the code of the power domain corresponding to the queue serial peripheral interface module in the function, so as to verify the queue serial peripheral interface module.
In one example, the access unit 503 includes:
the operation module 5031 is configured to perform operations of powering up, powering down, resetting, or turning off a clock on the power domain.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Fig. 6 is a block diagram of an electronic device, which may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like, in accordance with an exemplary embodiment.
The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input/output (I/O) interface 612, a sensor component 614, and a communication component 616.
The processing component 602 generally controls overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 602 can include one or more modules that facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.
The memory 604 is configured to store various types of data to support operations at the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 604 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The power supply component 606 provides power to the various components of the electronic device 600. The power supply components 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.
The multimedia component 608 includes a screen between the electronic device 600 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and/or a rear camera. When the electronic device 600 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 610 is configured to output and/or input audio signals. For example, the audio component 610 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 600 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, audio component 610 further includes a speaker for outputting audio signals.
The I/O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 614 includes one or more sensors for providing status assessment of various aspects of the electronic device 600. For example, the sensor assembly 614 may detect an on/off state of the electronic device 600, a relative positioning of the components, such as a display and keypad of the electronic device 600, the sensor assembly 614 may also detect a change in position of the electronic device 600 or a component of the electronic device 600, the presence or absence of a user's contact with the electronic device 600, an orientation or acceleration/deceleration of the electronic device 600, and a change in temperature of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 616 is configured to facilitate communication between the electronic device 600 and other devices, either wired or wireless. The electronic device 600 may access a wireless network based on a communication standard, such as WiFi,2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.
In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 604, including instructions executable by processor 620 of electronic device 600 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
A non-transitory computer readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform a method of accessing a power domain of the electronic device.
The application also discloses a computer program product comprising a computer program which, when executed by a processor, implements a method as described in the present embodiment.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present application may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or electronic device.
In the context of this application, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data electronic device), or that includes a middleware component (e.g., an application electronic device), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and an electronic device. The client and the electronic device are generally remote from each other and typically interact through a communication network. The relationship of client and electronic devices arises by virtue of computer programs running on the respective computers and having a client-electronic device relationship to each other. The electronic equipment can be cloud electronic equipment, also called cloud computing electronic equipment or cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service (Virtual Private Server or VPS for short) are overcome. The electronic device may also be an electronic device of a distributed system. It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions disclosed in the present application can be achieved, and are not limited herein.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (11)
1. A method for accessing a power domain, the method comprising:
acquiring codes of power domains to be accessed from a preset database; wherein the code consists of a base address index, an offset address index and a bit domain address index;
determining an address to the power domain according to the code of the power domain;
accessing the address of the power domain and operating the power domain; the operation comprises power-on, power-off, reset and clock closing operations performed on the power domain.
2. The method of claim 1, wherein said determining an address to said power domain based on said encoding of said power domain comprises:
determining a first address according to the base address index; wherein the first address characterizes an address of a register set where the power domain is located;
determining a second address according to the offset address index and the first address; wherein the second address characterizes an address of the register;
and determining the address of the power domain according to the bit domain address index and the second address.
3. The method of claim 2, wherein a sum of the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index is the same as the sum of the encoded numbers of bits.
4. The method of claim 2, wherein the number of bits of the base address index, the number of bits of the offset address index, and the number of bits of the bit field address index are dynamically adjusted according to user settings.
5. The method of claim 1, wherein operating the power domain comprises:
and powering up, powering down, resetting or turning off a clock for the power domain.
6. A method according to any one of claims 1-3, characterized in that before said retrieving the code of the power domain to be accessed from a preset database, the method further comprises:
macro definition is carried out on the address of the power domain, and the code of the power domain is obtained;
and storing the codes of the power domains into a preset database.
7. The method according to claim 1, wherein the method further comprises:
acquiring a request message for verifying a queue serial peripheral interface module;
calling a function of powering on or powering off according to the request message;
and writing codes of the power domains corresponding to the queue serial peripheral interface modules in the functions so as to verify the queue serial peripheral interface modules.
8. The method of claim 1, wherein the power domain is encoded as a 32-bit unsigned integer.
9. An access device for a power domain, the device comprising:
the first acquisition unit is used for acquiring codes of power domains to be accessed from a preset database; wherein the code consists of a base address index, an offset address index and a bit domain address index;
a determining unit, configured to determine an address to the power domain according to the code of the power domain;
the access unit is used for accessing the address of the power domain and operating the power domain; the operation comprises power-on, power-off, reset and clock closing operations performed on the power domain.
10. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-8.
11. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-8.
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Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008058823A1 (en) * | 2008-11-25 | 2010-05-27 | Rohde & Schwarz Gmbh & Co. Kg | Method and apparatus for analyzing code domain power and code domain error power |
| CN104978282A (en) * | 2014-04-04 | 2015-10-14 | 上海芯豪微电子有限公司 | Cache system and method |
| CN106354657A (en) * | 2016-08-23 | 2017-01-25 | 北京小米移动软件有限公司 | Register accessing method, device and system |
| CN109254930A (en) * | 2017-07-13 | 2019-01-22 | 华为技术有限公司 | Data access method and device |
| CN109597646A (en) * | 2017-09-30 | 2019-04-09 | 英特尔公司 | Processor, method and system with configurable space accelerator |
| CN209728674U (en) * | 2019-04-10 | 2019-12-03 | 浙江大华技术股份有限公司 | Powered-off fault protects circuit, power supply unit and computer equipment |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112307431A (en) * | 2020-11-09 | 2021-02-02 | 哲库科技(上海)有限公司 | VDSP, data processing method and communication equipment |
| CN112818199A (en) * | 2021-01-28 | 2021-05-18 | 平安普惠企业管理有限公司 | Webpage access method and device, computer equipment and storage medium |
| CN113383317A (en) * | 2019-01-31 | 2021-09-10 | 华为技术有限公司 | Processing device, method and related equipment |
| CN113711678A (en) * | 2019-04-02 | 2021-11-26 | 瑞典爱立信有限公司 | Network node, User Equipment (UE) and related method for scheduling UE by network node |
| CN113791822A (en) * | 2021-11-15 | 2021-12-14 | 沐曦集成电路(上海)有限公司 | Memory access device and method for multiple memory channels and data processing equipment |
| CN115617800A (en) * | 2022-10-18 | 2023-01-17 | 联仁健康医疗大数据科技股份有限公司 | Data reading method and device, electronic equipment and storage medium |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8560807B2 (en) * | 2011-12-14 | 2013-10-15 | International Business Machines Corporation | Accessing a logic device through a serial interface |
| US10013258B2 (en) * | 2014-09-29 | 2018-07-03 | International Business Machines Corporation | Single instruction array index computation |
| US20170177360A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Instructions and Logic for Load-Indices-and-Scatter Operations |
| US11073554B2 (en) * | 2019-09-27 | 2021-07-27 | Intel Corporation | Hardware-based local-state retention fault detection |
-
2023
- 2023-03-31 CN CN202310342581.6A patent/CN116360859B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102008058823A1 (en) * | 2008-11-25 | 2010-05-27 | Rohde & Schwarz Gmbh & Co. Kg | Method and apparatus for analyzing code domain power and code domain error power |
| CN104978282A (en) * | 2014-04-04 | 2015-10-14 | 上海芯豪微电子有限公司 | Cache system and method |
| CN106354657A (en) * | 2016-08-23 | 2017-01-25 | 北京小米移动软件有限公司 | Register accessing method, device and system |
| CN109254930A (en) * | 2017-07-13 | 2019-01-22 | 华为技术有限公司 | Data access method and device |
| CN109597646A (en) * | 2017-09-30 | 2019-04-09 | 英特尔公司 | Processor, method and system with configurable space accelerator |
| CN113383317A (en) * | 2019-01-31 | 2021-09-10 | 华为技术有限公司 | Processing device, method and related equipment |
| CN113711678A (en) * | 2019-04-02 | 2021-11-26 | 瑞典爱立信有限公司 | Network node, User Equipment (UE) and related method for scheduling UE by network node |
| CN209728674U (en) * | 2019-04-10 | 2019-12-03 | 浙江大华技术股份有限公司 | Powered-off fault protects circuit, power supply unit and computer equipment |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112307431A (en) * | 2020-11-09 | 2021-02-02 | 哲库科技(上海)有限公司 | VDSP, data processing method and communication equipment |
| CN112818199A (en) * | 2021-01-28 | 2021-05-18 | 平安普惠企业管理有限公司 | Webpage access method and device, computer equipment and storage medium |
| CN113791822A (en) * | 2021-11-15 | 2021-12-14 | 沐曦集成电路(上海)有限公司 | Memory access device and method for multiple memory channels and data processing equipment |
| CN115617800A (en) * | 2022-10-18 | 2023-01-17 | 联仁健康医疗大数据科技股份有限公司 | Data reading method and device, electronic equipment and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| Hypersafe: A lightweight approach to provide lifetime hypervisor control-flow integrity;Wang Z;《2010 IEEE symposium on security and privacy》;380-395 * |
| 基于闪存的剖分影像数据专用存储技术研究;刘强;《中国优秀硕士学位论文全文数据库信息科技辑》(第01期);I137-83 * |
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|---|---|
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