CN116346782A

CN116346782A - Address allocation method, device, bus system, main equipment and medium

Info

Publication number: CN116346782A
Application number: CN202310302407.9A
Authority: CN
Inventors: 丁德彬; 熊海峰; 陈立新
Original assignee: Nanjing Taisi Microelectronics Co ltd; Shanghai Taisi Microelectronics Co ltd
Current assignee: Nanjing Taisi Microelectronics Co ltd; Shanghai Taisi Microelectronics Co ltd
Priority date: 2023-03-27
Filing date: 2023-03-27
Publication date: 2023-06-27

Abstract

The embodiment of the application provides an address allocation method, an address allocation device, a bus system, a master device and a medium. The method comprises the following steps: acquiring initial detection current values of detection resistors in each candidate slave device; adjusting the output current value of a variable current source in each candidate slave device, and acquiring the detection current value of a detection resistor in each candidate slave device; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value; at least returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device; each candidate slave is assigned an address based on the candidate slave furthest from the master. The method can reduce the delay of the slave equipment and improve the reliability of communication.

Description

Address allocation method, device, bus system, main equipment and medium

Technical Field

The embodiment of the application relates to the technical field of automobile bus systems, in particular to an address allocation method, an address allocation device, a bus system, a main device and a medium.

Background

In the control system of the automotive electronics, the master device transmits control signals, typically via a bus, and the control units of each slave device are interconnected. The Local interconnection network (Local InterconnectNetwork, LIN) is a low-cost serial communication network, CAN realize the control of a distributed electronic system in an automobile, and the LIN bus is an auxiliary bus network, so that the LIN bus CAN greatly save cost under the conditions of not needing a controller Local network (ControllerArea Network, CAN) bus and a multifunctional condition, such as communication among automobile atmosphere lamps. The LIN bus system includes a plurality of slave devices, and the master device needs to selectively drive one or more slave devices, so that address allocation needs to be performed on the slave devices.

In the prior art, two different current sources are provided in the slave device, the current flowing through the internal resistor is measured by the two different current sources flowing at different time points, the slave device farthest from the master device is determined according to the current flowing through the internal resistor, and then the address is allocated.

However, in the prior art, the maximum driving current of the master device outside is 20mA, which limits the current passing through the internal resistor, so that an internal resistor with a larger resistance needs to be set, and in the daisy chain structure of the LIN bus system, the internal resistor in the slave device may cause delay of the farthest slave device, resulting in reduced reliability of communication.

Disclosure of Invention

The embodiment of the application provides an address allocation method, an address allocation device, a bus system, a master device and a medium, which can reduce the delay of slave devices and improve the reliability of communication.

In a first aspect, an embodiment of the present application provides an address allocation method, which is applied to a bus system, where the bus system includes: a master device and a plurality of slave devices, each slave device is connected with the master device through a bus, and each slave device comprises a detection resistor and a variable current source;

the method comprises the following steps:

obtaining initial detection current values of the detection resistors in each candidate slave device, wherein the initial detection current values are current values flowing through the detection resistors when the variable current source is disconnected from the detection resistors, the candidate slave devices are slave devices which are not assigned with addresses in all the slave devices, and the resistance values of the detection resistors are smaller than or equal to 0.2 omega;

adjusting the output current value of the variable current source in each candidate slave device, and obtaining the detection current value of the detection resistor in each candidate slave device, wherein the detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the changes of the output current values before and after each adjustment are the same;

Updating the candidate slave devices according to the difference value between the detection current value of the detection resistor and the initial detection current value in each candidate slave device;

returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, and obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device;

an address is assigned to each candidate slave device based on the candidate slave device furthest from the master device.

In some embodiments, said updating said candidate slave devices according to the difference between said detected current value of said detected resistance and said initial detected current value in each of said candidate slave devices comprises:

determining whether the difference value corresponding to each candidate slave device meets a preset condition according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value;

and determining the candidate slave equipment corresponding to the difference value meeting the preset condition as the new candidate slave equipment.

In some embodiments, the meeting the preset condition includes: the difference is less than or equal to a preset current difference.

In some embodiments, before said adjusting the output current value of the variable current source in each of the candidate slave devices, further comprises:

determining the candidate slave devices which do not meet the preset conditions and correspond to the difference values as candidate slave devices to be disconnected;

and controlling the variable current source in the candidate slave device to be disconnected to disconnect from the detection resistor.

In some embodiments, before the obtaining the initial detection current value of the detection resistor in each candidate slave device, the method further includes:

determining the number of the output current values according to the clock signals of the candidate slave devices and a preset distribution time threshold value;

determining each output current value of the variable current source according to the number of the output current values;

the variable current source is configured based on the order in which the output current values are from small to large.

In some embodiments, the determining the number of output current values according to the clock signal of each candidate slave device and a preset distribution time threshold value includes:

determining the minimum pulse width and the maximum pulse width in each clock signal according to the clock signal of each candidate slave device;

Determining the time for the variable current source to last for the same output current value according to the minimum pulse width and the maximum pulse width;

and determining the number of the output current values according to the time that the variable current source continuously outputs the same current value and the preset distribution time threshold.

In some embodiments, the determining each output current value of the variable current source according to the number of output current values comprises:

and determining each output current value of the variable current source according to the maximum current value bearable by the main equipment and the number of the output current values.

generating an addressing command and sending the addressing command to each slave device, wherein the slave devices are used for reading addresses according to the addressing command;

determining whether each slave device has allocated an address according to an address reading result sent by each slave device;

and determining the slave devices with unassigned addresses as the candidate slave devices.

In a second aspect, an embodiment of the present application provides an address allocation apparatus, which is applied to a bus system, where the bus system includes a master device and a plurality of slave devices, each slave device is connected to the master device through a bus, and each slave device includes a detection resistor and a variable current source;

The device comprises:

the acquisition module is used for acquiring initial detection current values of the detection resistors in each candidate slave device, wherein the initial detection current values are current values flowing through the detection resistors when the variable current source is disconnected from the detection resistors, the candidate slave devices are slave devices which are not assigned with addresses in all the slave devices, and the resistance values of the detection resistors are smaller than or equal to 0.2 omega;

the determining module is used for adjusting the output current value of the variable current source in each candidate slave device and obtaining the detection current value of the detection resistor in each candidate slave device, wherein the detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the change of the output current value before and after each adjustment is the same; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor and the initial detection current value in each candidate slave device; returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, and obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device;

And the allocation module is used for allocating an address to each candidate slave device based on the candidate slave device farthest from the master device.

In a third aspect, embodiments of the present application provide a bus system, including: a master device and a plurality of slave devices, each slave device is connected with the master device through a bus, and each slave device comprises a detection resistor and a variable current source;

the master device is configured to perform the steps of any of the methods provided in the first aspect.

In a fourth aspect, embodiments of the present application provide a host device, including a processor, configured to execute a computer program stored in a memory, where the processor implements any of the methods provided in the first aspect when executing the computer program.

In a fifth aspect, embodiments of the present application provide a computer storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of any of the methods provided in the first aspect.

According to the technical scheme, the initial detection current value of the detection resistor in each candidate slave device is obtained, when the variable current source is disconnected from the detection resistor, the current value of the detection resistor flows, the candidate slave devices are slave devices which are not assigned with addresses in all the slave devices, and the resistance value of the detection resistor is smaller than or equal to 0.2 omega; adjusting the output current value of a variable current source in each candidate slave device, and acquiring the detection current value of a detection resistor in each candidate slave device, wherein the detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the change of the output current value before and after each adjustment is the same; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value; at least returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device; and based on the candidate slave device farthest from the master device, an address is allocated to each candidate slave device, so that the resistance value of the detection resistor can be reduced, the delay of the detection resistor on the slave device can be reduced, and the reliability of communication can be improved. In addition, the output current values before and after each adjustment are the same, so that the output current value of the variable current source can be raised in a step change mode, the problem of unstable address allocation caused by low resistance of the detection resistor can be avoided, and the stability of address allocation is improved.

The foregoing description is only an overview of the technical solutions of the embodiments of the present application, and may be implemented according to the content of the specification, so that the technical means of the embodiments of the present application can be more clearly understood, and the following detailed description of the present application will be presented in order to make the foregoing and other objects, features and advantages of the embodiments of the present application more understandable.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art bus system;

FIG. 2 is a schematic diagram of another prior art bus system;

FIG. 3 is a schematic diagram of a bus system according to an embodiment of the present disclosure;

fig. 4 is a flow chart of an address allocation method according to an embodiment of the present application;

fig. 5 is a flowchart of another address allocation method according to an embodiment of the present application;

Fig. 6 is a flowchart of another address allocation method according to an embodiment of the present application;

fig. 7 is a flowchart of another address allocation method according to an embodiment of the present application;

FIG. 8 is a timing chart of address assignment according to an embodiment of the present disclosure;

FIG. 9 is a state diagram of address assignment according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of an address allocation device according to an embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

The terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the drawings are intended to cover, but not exclude, other matters. The word "a" or "an" does not exclude the presence of a plurality.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of the phrase "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order, and may be used to expressly or implicitly include one or more such features.

In the description of the present application, unless otherwise indicated, the meaning of "plurality" means two or more (including two), and similarly, "plural sets" means two or more (including two).

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, e.g., the terms "connected" or "coupled" of a mechanical structure may refer to a physical connection, e.g., the physical connection may be a fixed connection, e.g., by a fastener, such as a screw, bolt, or other fastener; the physical connection may also be a detachable connection, such as a snap-fit or snap-fit connection; the physical connection may also be an integral connection, such as a welded, glued or integrally formed connection. "connected" or "connected" of circuit structures may refer to physical connection, electrical connection or signal connection, for example, direct connection, i.e. physical connection, or indirect connection through at least one element in the middle, so long as circuit communication is achieved, or internal communication between two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

Fig. 1 is a schematic diagram of a bus system in the prior art, as shown in fig. 1, where the bus system includes a master device 10 and a plurality of slave devices 20, all of the slave devices 20 are connected to the master device 10 through a bus, and each of the slave devices 20 is electrically connected to the bus in a daisy chain manner. The number of slave devices 20 may be a positive integer of 2 or more, for example, the number of slave devices 20 may be 15, which is not particularly limited in the embodiment of the present application.

Illustratively, fig. 2 is a schematic diagram of another bus system in the prior art, and fig. 2 is a schematic diagram of a slave device 20 including a first current source I and a second current source I' based on the embodiment shown in fig. 1. The first current source I is electrically connected to the main device 10 through a first switch S ', and the second current source I' is electrically connected to the main device 10 through a second switch s″. Furthermore, the first current source I and the second current source I' are each electrically connected to the BUS via a diode. If the first switch S' is closed, the slave device 20 is connected to the first current source I, i.e. the first current source I is connected to the bus system; if the second switch S "is closed, the slave device 20 accesses the second current source I ', i.e. the second current source I ' is accessed into the bus system, and the first switch S ' and the second switch S" are not closed at the same time.

The slave device 20 also includes a sense resistor R _s The BUS sequentially connects all the detection resistors R _s Are connected in series. Each detection resistor R _s Is electrically connected to the positive and negative input terminals of a differential amplifier AMP, and the output terminal of the differential amplifier AMP is electrically connected to an analog-to-digital converter ADC, so that the differential amplifier AMP can flow through a detection resistor R _s Amplifying the voltage drop generated by the current of (a) and transmitting the amplified voltage drop to an analog-to-digital converter ADC. The ADC can obtain the flow through the detection resistor R based on the received amplified voltage drop _s Is set according to the current level of the battery. When a current source is connected from the device 20, the current flows through each detection resistor R _s The magnitude of the current of (2) and the detection resistor R _s Inversely related to the distance between the main devices 10, i.e. the sense resistor R _s The greater the distance between the slave device 20 and the master device 10, the more the sense resistor R _s The smaller the current value of (2), the more based on the sense resistor R _s Can locate the slave device 20 furthest from the master device 10 and based thereon for each slave device20 performs address assignment.

The bus system shown in fig. 1 and 2 has a maximum drive current of 20mA outside the master device 10, which limits the flow through the sense resistor R _s The detection resistor R with larger resistance value is needed to be set _s . However, in the bus system, the sense resistor R in the slave device 20 _s When the resistance of (a) is large, delay of the most remote slave device 20 may be caused, for example, the detection resistor R in each slave device 20 _s The resistance values of the bus system are all 1 omega, and the bus system comprises 15 slave devices 20, so that 15 omega of resistance is brought to the slave device 20 at the farthest end, waveform distortion is serious, even communication errors of the bus system are caused, and the reliability of communication is reduced.

In order to solve the above problems, the present application provides an address allocation method, by acquiring an initial detection current value of a detection resistor in each candidate slave device, where the initial detection current value is a current value flowing through the detection resistor when a variable current source is disconnected from the detection resistor, the candidate slave device is a slave device to which no address is allocated in all slave devices, and the resistance value of the detection resistor is less than or equal to 0.2Ω; adjusting the output current value of a variable current source in each candidate slave device, and acquiring the detection current value of a detection resistor in each candidate slave device, wherein the detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the change of the output current value before and after each adjustment is the same; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value; at least returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device; and based on the candidate slave device farthest from the master device, an address is allocated to each candidate slave device, so that the resistance value of the detection resistor can be reduced, the delay of the detection resistor on the slave device can be reduced, and the reliability of communication can be improved. In addition, the output current values before and after each adjustment are the same, so that the output current value of the variable current source can be raised in a step change mode, the problem of unstable address allocation caused by low resistance of the detection resistor can be avoided, and the stability of address allocation is improved.

Fig. 3 is a schematic structural diagram of a bus system according to an embodiment of the present application, and as shown in fig. 3, a bus system 100 includes: a master device 10 and a plurality of slave devices 20, each slave device 20 being connected to the master device 10 via a BUS, each slave device 20 comprising a sense resistor R _s And a variable current source I).

Illustratively, the bus system 100 includes: one master device 10 and n slave devices 20, for example, n may be 15. The slave device 20 includes a sense resistor R _s And one variable current source I ", the output current value of the variable current source I" may be changed stepwise, for example, the output current value of the variable current source I "ranges from 0mA to 20mA, and the amount of change of the adjacent two output current values is 0.5mA. The master device 10 may perform the steps of any of the method embodiments provided herein.

The technical solutions of the method embodiments in the present application are described in detail below with reference to several specific embodiments.

Fig. 4 is a flow chart of an address allocation method provided in the embodiment of the present application, where the embodiment of the method shown in fig. 4 is applied to the bus system 100 shown in fig. 3, and specific steps of the address allocation method include:

s101, obtaining initial detection current values of detection resistors in candidate slave devices.

When the initial detection current value is the current value of the detection resistor when the variable current source is disconnected from the detection resistor, the candidate slave devices are slave devices which are not assigned with addresses in all the slave devices, and the resistance value of the detection resistor is smaller than or equal to 0.2 omega.

The candidate slave devices may be part of all the slave devices in the bus system, or all the slave devices, depending on whether each slave device is assigned an address. If all the slave devices in the bus system are not allocated with addresses, determining that all the slave devices are candidate slave devices; if a part of the slave devices in the bus system are not allocated addresses, the part of the slave devices are determined to be candidate slave devices. The resistance value of the detection resistor may be set smaller, for example, the resistance value of the detection resistor may be less than or equal to 0.2Ω.

First, as shown in fig. 3, the pull-up switch S in each candidate slave device is closed, and the voltage on the BUS is pulled up through the pull-up resistor R; at the same time, the first switch S' in each candidate slave device is opened. As such, variable current source I "is not connected to bus system 100. At this time, the current on the BUS BUS flows through the sense resistor R in each candidate slave _s The flow of the detection resistor R in each candidate slave device can be acquired through the differential amplifier AMP and the analog-to-digital converter ADC in each candidate slave device _s The magnitude of the current of each candidate slave device can be acquired, namely the detection resistor R in each candidate slave device _s Thus, the detection resistance R of each candidate slave device can be obtained _s Is set, the initial detection current value of (a).

S102, adjusting output current values of variable current sources in the candidate slave devices, and acquiring detection current values of detection resistors in the candidate slave devices.

The detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the change of the output current value before and after each adjustment is the same.

Then, when the current pull-up switch in each candidate slave device is closed and the first switch is opened, the first switch in each candidate slave device is closed and the pull-up switch is opened, so that the variable current source and the detection resistor in each candidate slave device can be conducted, namely, the variable current source in each candidate slave device is connected to the bus system, and the output current value of the variable current source is I1, namely, the change of the output current values before and after adjustment is I1. When the first switch in each candidate slave device is closed, if the output current value of the variable current source in each candidate slave device is I1, the output current value of the variable current source in each candidate slave device can be adjusted to be I2, and the change of the output current values before and after adjustment is I2-I1; if the output current value of the variable current source in each candidate slave device is I2, the output current value of the variable current source in each candidate slave device can be adjusted to be I3, and the change of the output current values before and after adjustment is I3-I2; if the output current value of the variable current source in each candidate slave is Ia, the output current value of the variable current source in each candidate slave may be adjusted to Ib, the change in the output current value before and after adjustment is Ib-Ia, and i1=i2-i1=i3-i2=ib-Ia. Thus, the output current value of the variable current source can be increased in a stepwise manner, and when the resistance value of the detection resistor is low, the problem of unstable address allocation can be avoided.

After the output current value of the variable current source in each candidate slave device is adjusted, the current value of the detection resistor in each candidate slave device can be obtained, namely, the detection current value of the detection resistor in each candidate slave device is obtained.

S103, updating the candidate slave devices according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value.

The execution is returned to S102 twice.

Based on the above embodiment, if the initial detection current value of the detection resistor in any candidate slave device a is I0, and the output current value of the variable current source in the candidate slave device a is I1, the detection current value of the detection resistor in the candidate slave device a is I1, and the difference between the initial detection current value I0 and the detection current value I1 of the detection resistor in the candidate slave device a, i.e. I1-I0, can be determined. And determining part or all of all the candidate slave devices as new candidate slave devices based on the difference value i1-i0 corresponding to each candidate slave device.

For the new candidate slave devices, the output current value of the variable current source in each candidate slave device is adjusted to be I2, the detection current value of the detection resistor in each candidate slave device is I2, and part or all of all the candidate slave devices are determined to be the new candidate slave devices based on the difference value I2-I0 between the initial detection current value I0 and the detection current value I2 of the detection resistor R in each candidate slave device. Thus, the first return execution S102 is realized.

For the new candidate slave devices, the output current value of the variable current source in each candidate slave device is adjusted to be I3, the detection current value of the detection resistor in each candidate slave device is obtained to be I3, and part or all of all the candidate slave devices are determined to be the new candidate slave devices based on the difference value I3-I0 between the initial detection current value I0 and the detection current value I3 of the detection resistor in each candidate slave device. Thus, the second return execution S102 is realized.

In summary, three times S102-S103 are performed, where, when S102 is performed for the first time, the variable current source in each candidate slave device is turned on, and when the output current value of the variable current source is I1, the first detected current value I1 is obtained, and the first update of the candidate slave device is performed. When S102 is executed for the second time, the output current value of the variable current source in each candidate slave device is adjusted to I2, a second detected current value I2 is obtained, and the candidate slave device is updated for the second time. When S102 is executed for the third time, the output current value of the variable current source in each candidate slave device is adjusted to I3, a second detected current value I3 is obtained, and the candidate slave device is updated for the third time.

S104, determining whether the number of candidate slave devices is one.

If yes, executing S105; if not, return to S102.

After the candidate slave devices are updated for the third time, determining whether the number of the updated candidate slave devices is one, and if the number of the candidate slave devices is one, determining that the updated candidate slave devices are the candidate slave devices farthest from the master device; if the number of candidate slave devices is greater than one, the process further needs to return to S102, to adjust the output current value of the variable current source in each candidate slave device again, update the candidate slave devices again, and determine whether the number of candidate slave devices is one again until the number of candidate slave devices is one.

For example, if the candidate slaves B, C and D are the candidate slaves after the third update, it is apparent that the number of candidate slaves is greater than one, the output current values of the variable current sources in each of the candidate slaves B, C and D are again adjusted, the detection current values of the detection resistances in each of the candidate slaves B, C and D are acquired, and the candidate slaves are updated the fourth time. After updating the candidate slave devices for the fourth time, the candidate slave devices are C and D, obviously, the number of the candidate slave devices is larger than one, the output current values of the variable current sources in the candidate slave devices C and D are adjusted again, the detection current values of the detection resistors in the candidate slave devices C and D are obtained, and the candidate slave devices are updated for the fifth time. After updating the candidate slave device for the fifth time, the candidate slave device is D.

It should be noted that the embodiment of the present application uses only five examples to describe the number of times S102 to S103 is executed when the number of candidate slave devices is determined to be one. In practical applications, the number of times of executing S102-S103 is not particularly limited, and it is sufficient that the number of times of executing S102-S103 is greater than or equal to three.

S105, determining the candidate slave device as the candidate slave device farthest from the master device.

Based on the above embodiment, after updating the candidate slave device for the fifth time, the number of candidate slave devices is one, and the candidate slave device is D, it may be determined that the candidate slave device D is the candidate slave device farthest from the master device.

And S106, assigning an address to each candidate slave device based on the candidate slave device farthest from the master device.

On the basis of the above embodiment, the candidate slave device farthest from the master device may be located, and then the address may be allocated to the farthest candidate slave device. Then, addresses are assigned to neighboring candidate slaves of the farthest candidate slave, and so on, an address may be assigned to each candidate slave to ensure proper communication between the master and the slaves.

The application provides an address allocation method, which comprises the steps of obtaining initial detection current values of detection resistors in candidate slave devices, wherein the initial detection current values are current values of the detection resistors when a variable current source is disconnected from the detection resistors, the candidate slave devices are slave devices which are not allocated with addresses in all the slave devices, and the resistance values of the detection resistors are smaller than or equal to 0.2 omega; adjusting the output current value of a variable current source in each candidate slave device, and acquiring the detection current value of a detection resistor in each candidate slave device, wherein the detection current value is the current value flowing through the detection resistor when the variable current source is conducted with the detection resistor, and the change of the output current value before and after each adjustment is the same; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value; at least returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device; and based on the candidate slave device farthest from the master device, an address is allocated to each candidate slave device, so that the resistance value of the detection resistor can be reduced, the delay of the detection resistor on the slave device can be reduced, and the reliability of communication can be improved. In addition, the output current values before and after each adjustment are the same, so that the output current value of the variable current source can be raised in a step change mode, the problem of unstable address allocation caused by low resistance of the detection resistor can be avoided, and the stability of address allocation is improved.

Fig. 5 is a flowchart of another address allocation method provided in the embodiment of the present application, and fig. 5 is a specific description of one possible implementation manner when S103 is performed based on the embodiment shown in fig. 4, as follows:

s201, determining whether the difference value corresponding to each candidate slave device meets a preset condition according to the difference value between the detection current value of the detection resistor in each candidate slave device and the initial detection current value.

The preset condition may be, for example, a preset current difference i _th For example, the current difference i is preset _th May be 10mA. Meeting the preset condition may be greater than or equal to the preset current difference i _th For example, based on the above embodiment, the satisfaction of the preset condition may be greater than or equal to 10mA.

Based on the initial detection current value i0 and the detection current value i of the detection resistor in each candidate slave device, a difference value i-i0 between the initial detection current value i0 and the detection current value i of the detection resistor in each candidate slave device, namely a difference value i-i0 corresponding to each candidate slave device, can be determined. Respectively comparing the difference value i-i0 corresponding to each candidate slave device with a preset current difference value i _th Comparing, if i-i0 is greater than or equal to i _th Determining that the preset condition is met; if i-i0<i _th And determining that the preset condition is not met.

S202, determining the candidate slave devices corresponding to the difference values meeting the preset conditions as new candidate slave devices.

Based on the result of whether the difference value corresponding to each candidate slave device meets the preset condition or not, all the difference values meeting the preset condition can be screened out, and the candidate slave devices corresponding to the difference values are determined to be new candidate slave devices. For example, if the difference value corresponding to the candidate slave device a satisfies the preset condition, the difference value corresponding to the candidate slave device B satisfies the preset condition, and the difference value corresponding to the candidate slave device C does not satisfy the preset condition, the candidate slave devices a and B may be determined as new candidate slave devices.

The gist of the embodiment of the present application is to locate the candidate slave device farthest from the master device, and since the further the candidate slave device is from the master device, the smaller the difference value corresponding to the candidate slave device is, the candidate slave device corresponding to the difference value smaller than the preset current difference value is proposed as a new candidate slave device. Therefore, the selection range of the candidate slave equipment furthest can be effectively reduced, and finally the purpose of locating the candidate slave equipment furthest from the master equipment is achieved.

On the basis of the above embodiment, before S102 is performed for the second time, the following steps may be performed:

And S301, determining the candidate slave devices corresponding to the difference values which do not meet the preset conditions as candidate slave devices to be disconnected.

Based on the result of whether the difference value corresponding to each candidate slave device meets the preset condition or not, all the difference values which do not meet the preset condition can be screened out, and the candidate slave devices corresponding to the difference values are determined as candidate slave devices to be disconnected. For example, based on the above-described embodiments, the candidate slave device C may be determined as the candidate slave device to be disconnected.

S301, controlling a variable current source in the candidate slave device to be disconnected to disconnect from the detection resistor.

For example, the first switch in the candidate slave device to be disconnected may be opened such that the variable current source in the candidate slave device to be disconnected is disconnected from the detection resistor. For example, based on the above-described embodiment, the first switch in the candidate slave device C is turned off, so that the variable current source in the candidate slave device C is disconnected from the detection resistor.

The candidate slave device to be disconnected is a difference set between the set of candidate slave devices before updating and the set of candidate slave devices after updating, and because the output current value of the variable current source in the candidate slave device after updating can be increased, the variable current source in the candidate slave device to be disconnected is disconnected from the detection resistor, i.e. the variable current source in the candidate slave device to be disconnected is not connected into the bus system, and the current provided by the variable current source in the bus system can be prevented from exceeding the driving capability current of the main device.

In the embodiment of the application, the candidate slave device corresponding to the difference value which does not meet the preset condition is determined to be the candidate slave device to be disconnected; the variable current source in the candidate slave device to be disconnected is controlled to be disconnected with the detection resistor, so that the current provided by the variable current source in the bus system can be prevented from exceeding the driving capacity current of the main device, and the stability of communication can be improved.

Fig. 6 is a flowchart of another address allocation method according to an embodiment of the present application, and fig. 6 is a flowchart of another address allocation method according to an embodiment of the present application, before S101 is executed, the address allocation method further includes the following steps:

s401, determining the number of output current values according to clock signals of candidate slave devices and a preset distribution time threshold value.

Illustratively, due to the limitations of slave technology, jitter exists between the clock signals of each slave, i.e., there is a difference between the clock signals of the candidate slaves. For example, the pulse width of the clock signal of the candidate slave a is T1, the pulse width of the clock signal of the candidate slave B is T2, the pulse width of the clock signal of the candidate slave C is T3, and t1+.t2+.t3.

As a specific description of one possible implementation when S401 is performed, the following is given:

S4011, determining a minimum pulse width and a maximum pulse width in each clock signal according to the clock signals of each candidate slave device.

For example, if on the basis of the above embodiment, it may be determined that T1> T2> T3, and thus, the minimum pulse width in the clock signals of all candidate slave devices may be determined to be T3 and the maximum pulse width may be determined to be T1.

S4012, determining a time for which the variable current source continues to the same output current value according to the minimum pulse width and the maximum pulse width.

For example, it may be determined that the variable current source maintains the same output current value for more than a maximum pulse width, while the variable current source maintains the same output current value for less than twice the minimum pulse width. For example, on the basis of the above embodiment, the time T for which the variable current source maintains the same output current value satisfies: t3< T <2 x T1. In this way, in the maintaining time of the same output current value, the variable current source in each candidate slave device can be ensured to provide stable current for the bus system, so that a relatively accurate detection current value can be obtained.

S4013, determining the number of output current values according to the time that the variable current source continues to the same output current value and a preset distribution time threshold.

The preset allocation time threshold is exemplified by the time required for allocating addresses normally, wherein the preset allocation time threshold can be an empirical value or can be a more reasonable time required for allocating addresses based on experiments. The ratio of the preset distribution time threshold to the same output current value of the variable current source can be determined according to the same output current value of the preset distribution time threshold and the same output current value of the variable current source, and the number of the output current values is determined based on the ratio of the same output current value of the preset distribution time threshold and the same output current value of the variable current source.

For example, the preset allocation time threshold is T _th The variable current source continues to output the same current value for a period of time T, if T _th T is an integer, T can be determined _th T is the number of output current values; if T _th T is a non-integer and can be determined to be greater than T _th The minimum integer of/T is the number of output current values.

In the embodiment of the application, the minimum pulse width and the maximum pulse width in each clock signal are determined according to the clock signals of each candidate slave device; determining the time for the variable current source to last the same output current value according to the minimum pulse width and the maximum pulse width; according to the time that the variable current source continuously outputs the same current value and the preset distribution time threshold value, the number of the output current values is determined, and the variable current source in each candidate slave device can supply stable current to the bus system within the maintaining time of the same output current value, so that a relatively accurate detection current value can be obtained.

S402, determining each output current value of the variable current source according to the number of the output current values.

As a possible implementation manner when S402 is performed, each output current value of the variable current source may be determined according to the maximum current value and the number of output current values that the master device can withstand.

Illustratively, the maximum current value that the master device can withstand is 20mA, and thus the output current value of the variable current source is less than 20mA. For example, the output current value of the variable current source is less than or equal to 16mA. The method can divide 0mA-16mA into a plurality of steps on average, wherein the number of the steps is the number of output current values, and the current value corresponding to each step is one output current value.

For example, based on the above embodiment, the number of output current values is 32, and the output current values are started from 0.5mA, and each step is raised by 0.5mA until being raised to 16mA.

S403, configuring a variable current source based on the order of the output current values from small to large.

Illustratively, all the output current values determined in the above embodiment are arranged in order from small to large, and each variable current source is configured based on the order from small to large of the output current values, so that the first output current value of the variable current source is 0.5mA, the second output current value is 1mA, and so on when the variable current source is in operation, the last output current value of the variable current source is increased by 0.5mA on the basis that the last output current value of the variable current source is the previous output current value, until the last output current value of the variable current source is 16mA.

Fig. 7 is a flowchart of another address allocation method according to an embodiment of the present application, and fig. 7 is a flowchart of another address allocation method according to an embodiment of the present application, before S101 is executed, the address allocation method further includes the following steps:

s501, an addressing command is generated and sent to each slave device.

The slave device is arranged to read the address in accordance with the addressing command.

For example, if a master device needs to communicate with a slave device, an address command is generated and sent to all slave devices that are electrically connected to the master device. After the slave device receives the address command, the address of the slave device may be read.

S502, determining whether each slave device has allocated an address according to the address reading result sent by each slave device.

For example, if the slave device does not read the address, the address read result is null, and it may be determined that the slave device is not assigned the address; if the slave device reads the address, the address reading result is the address of the slave device, and it can be determined that the slave device has been assigned the address.

S503, determining the slave devices with unassigned addresses as candidate slave devices.

According to the embodiment, the slave devices which are allocated with the addresses do not need to be allocated with the addresses again, so that the slave devices which are not allocated with the addresses can be selected as candidate slave devices, the addresses are allocated only for the slave devices which are not allocated with the addresses, repeated address allocation is avoided, and the efficiency of address allocation can be improved.

As a specific embodiment of the present application, the address allocation process can be described by using the timing diagram of fig. 8 and the state diagram of fig. 9, and can be divided into 5 processes:

(1) The master device sends an automatic addressing command, the slave device receives the automatic addressing interrupt, starts addressing, and keeps the state unchanged for the slave device without the automatic addressing function. After automatic addressing is started, all slave devices turn off the pull-up resistor and the variable current source, and the slave devices judge whether addresses are allocated or not.

(2) The default state is restored if the address has been allocated waiting for the addressing command to end. Otherwise, the voltage of the detection resistor is amplified by the differential amplifier AMP and sent to the ADC, and the offset current of the detection resistor is converted and marked as I0.

(3) The configuration is started by pulling up the variable current source by the slave device in a step-up manner, firstly, all the slave devices configure the current source I1, the actual measured current on the measured detection resistor is recorded as I1, and IDIFF1=I1-I0 is calculated. If IDIFF1 is greater than the threshold, the variable current source is turned off and the default state is restored after waiting for the addressing command to end. If IDIFF1 is less than the set threshold, a variable current source is added to I2, the measured current across the sense resistor is noted as I2, and IDIFF2 = I2-I0 is calculated. If IDIFF2 is greater than the threshold, the variable current source is turned off and the default state is restored after waiting for the addressing command to end. If IDIFF2 is less than the set threshold, the step-up of the variable current source to I3 is continued, and the cycle is continued until the maximum current In, IDIFF n=in—i0, is calculated.

(4) After the variable current source is increased to the maximum current, IDIFFn is larger than a set threshold value, the variable current source is turned off, and the default state is restored after the addressing command is ended. If IDIFFn is smaller than the set threshold, the slave device which is farthest from the master device in all the slave devices without address allocation is identified, the judgment result is stored in the RAM of the slave device, and the master device allocates the address to the slave device. And finally, recovering the default state, closing all variable current sources, and opening the pull-up resistor of the slave device.

(5) It is detected whether all slave devices have been assigned addresses.

LIN Bus Shunt Slave Node Position Detection Revision 1.0.0 issued by LIN alliance prescribes that the maximum current driven by the master device is 20mA, the steps above are exemplified below, the pull-up current source is changed by 0.5mA each step, the maximum current is 16mA, the set comparison threshold current is 10mA, the number of slave devices to be allocated with addresses is 15, and the current on the detection resistor of each slave device at different time points can be given in Table 1.

Table 1 current across sense resistor

The offset current I0 is measured at time t0 above, 0.5mA is added to all slave devices at time t1, the current on all slave devices does not exceed 10mA, so all slave device current sources still turn on at time t2, the slave device current sources become 1mA at time t2, the slave device 4-slave device 1 current sources exceed 10mA, the slave device 4-slave device 1 current sources turn off at time t3, the current sources become 1.5mA, the slave device 8-slave device 1 current sources exceed 10mA, the current sources turn off at the next time, the current sources become 2mA at time t4, the slave device 9-slave device 1 current exceeds 10mA, the current sources turn off at the next time, so the current sources of unselected slave devices continue to increase, the current sources become 16mA at time tn, the slave device 14-slave device 1 current exceeds 10mA, only the slave device 15 is not selected last, the slave device which is considered to be farthest from the master device among the slave devices without address assignment is then assigned to the slave device 15. This is repeated until all slave devices have assigned addresses and the automatic addressing ends.

In practical application, the clock errors among different slave devices need to be considered, and certain clock margins need to be considered when calculating the time of different steps.

An embodiment of the present application further provides an address allocation device, and fig. 10 is a schematic structural diagram of the address allocation device provided in the embodiment of the present application, where the address allocation device shown in fig. 10 is applied to a bus system shown in fig. 3, and the address allocation device includes:

and the obtaining module 110 is configured to obtain an initial detection current value of the detection resistor in each candidate slave device, where the initial detection current value is a current value flowing through the detection resistor when the variable current source is disconnected from the detection resistor, the candidate slave devices are slave devices to which no address is allocated in all slave devices, and a resistance value of the detection resistor is less than or equal to 0.2 Ω.

A determining module 120, configured to adjust an output current value of the variable current source in each candidate slave device, and obtain a detection current value of the detection resistor in each candidate slave device, where the detection current value is a current value flowing through the detection resistor when the variable current source is turned on with the detection resistor, and changes of the output current value before and after each adjustment are the same; updating the candidate slave devices according to the difference value between the detection current value of the detection resistor and the initial detection current value in each candidate slave device; and at least returning to execute the adjustment of the output current value of the variable current source in each candidate slave device at least twice, obtaining the detection current value of the detection resistor in each candidate slave device until the number of the candidate slave devices is one, and determining that the candidate slave device is the candidate slave device farthest from the master device.

An allocation module 130, configured to allocate an address to each candidate slave device based on the candidate slave device farthest from the master device.

In some embodiments, the determining module 120 is further configured to determine, according to a difference between the detected current value of the detected resistor and the initial detected current value in each of the candidate slave devices, whether the difference corresponding to each of the candidate slave devices meets a preset condition; and determining the candidate slave equipment corresponding to the difference value meeting the preset condition as the new candidate slave equipment.

In some embodiments, the determining module 120 is further configured to determine the candidate slave device corresponding to the difference value that does not meet the preset condition as a candidate slave device to be disconnected; and controlling the variable current source in the candidate slave device to be disconnected to disconnect from the detection resistor.

In some embodiments, the determining module 120 is further configured to determine the number of output current values according to the clock signal of each candidate slave device and a preset distribution time threshold; and determining each output current value of the variable current source according to the number of the output current values.

The address allocation device further includes:

and the configuration module is used for configuring the variable current source based on the order of the output current values from small to large.

In some embodiments, the determining module 120 is further configured to determine, according to the clock signals of each of the candidate slave devices, a minimum pulse width and a maximum pulse width in each of the clock signals; determining the time for the variable current source to last for the same output current value according to the minimum pulse width and the maximum pulse width; and determining the number of the output current values according to the time that the variable current source continuously outputs the same current value and the preset distribution time threshold.

In some embodiments, the determining module 120 is further configured to determine each of the output current values of the variable current source according to a maximum current value that the master device can withstand and a number of the output current values.

In some embodiments, the address allocation apparatus further comprises:

the generation module is used for generating an addressing command and sending the addressing command to each slave device, and the slave devices are used for reading addresses according to the addressing command.

The determining module 120 is further configured to determine, according to the address reading result sent by each slave device, whether each slave device has allocated an address; and determining the slave devices with unassigned addresses as the candidate slave devices.

The embodiment of the application also provides a master device, which comprises: and a processor for executing the computer program stored in the memory, wherein the processor implements the steps of any method embodiment of the present application when executing the computer program.

The embodiment of the application also provides a computer storage medium, and a computer program is stored on the computer storage medium, and when the computer program is executed by a processor, the steps of any method embodiment are realized.

Any combination of one or more computer readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

Those skilled in the art will appreciate that while some embodiments herein include certain features that are included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The above embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. An address allocation method, characterized in that it is applied to a bus system, where the bus system includes a master device and a plurality of slave devices, each slave device is connected to the master device through a bus, and each slave device includes a detection resistor and a variable current source;

The method comprises the following steps:

2. The method of claim 1, wherein updating the candidate slave devices based on the difference between the detected current value of the detected resistor and the initial detected current value in each of the candidate slave devices comprises:

3. The method of claim 2, wherein the meeting a preset condition comprises: the difference is less than or equal to a preset current difference.

4. The method of claim 2, wherein prior to said adjusting the output current value of the variable current source in each of the candidate slave devices, further comprising:

5. The method of any of claims 1-4, wherein prior to obtaining the initial sense current value for the sense resistor in each candidate slave device, further comprising:

6. The method of claim 5, wherein determining the number of output current values based on the clock signal of each candidate slave device and a preset distribution time threshold value comprises:

7. The method of claim 5, wherein determining each output current value of the variable current source based on the number of output current values comprises:

8. The method of any of claims 1-4, wherein prior to obtaining the initial sense current value for the sense resistor in each candidate slave device, further comprising:

9. An address allocation apparatus, characterized in that it is applied to a bus system, said bus system includes a master device and a plurality of slave devices, each said slave device is connected with said master device through the bus, each said slave device includes a detection resistor and a variable current source;

The device comprises:

10. A bus system, comprising: a master device and a plurality of slave devices, each slave device is connected with the master device through a bus, and each slave device comprises a detection resistor and a variable current source;

the master device being adapted to perform the steps of the method of any of claims 1-8.

11. A master device, comprising: a processor for executing a computer program stored in a memory, which processor, when executing the computer program, implements the method of any of claims 1-8.

12. A computer storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method according to any of claims 1-8.