CN116346088A - TFET-based single-edge master-slave trigger and trigger module - Google Patents
TFET-based single-edge master-slave trigger and trigger module Download PDFInfo
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Abstract
The invention relates to the technical field of dynamic random access memory, in particular to a single-edge master-slave trigger based on TFET, which is also called as TDFF, and a trigger module designed based on the TDFF. The TDFF of the present invention includes 12 PTFET transistors, 13 NTFET transistors, and one inverter INV. The invention builds the trigger based on TFET, does not use a transmission gate or a transmission tube structure, further avoids the forward bias P-I-N current problem caused by the transmission gate, and controls the correct transmission of data through the intermediate node and the clock signal CLK. Although the CLK is a single-phase clock, the invention can realize the trigger function by matching with the circuit design of the TFET transistor without setting a clock inverter for the CLK. And through simulation test, the invention has low power consumption index and larger advantages.
Description
Technical Field
The present invention relates to the Field of dynamic random access memory technology, and more particularly, to a single-edge master-slave flip-flop (TDFF) based on a TFET (Tunneling Field-Effect Transistor, tunneling Field effect transistor) and a trigger module designed based on the TDFF.
Background
A flip-flop is a memory cell circuit that can only be operated when triggered by a clock signal, and is distinguished from a latch that is not controlled by a clock signal. Typically, the flip-flop will be designed using CMOS (e.g., using metal oxide semiconductor field effect transistors, metal Oxide Semiconductor Field Effect Transistor, MOSFETs) technology.
Ideally, the MOSFET has a large on-state current when operated, and no or very weak leakage current in the off-state. However, as the device size is continuously reduced, various secondary effects are continuously displayed, leakage current is continuously increased, and power consumption per unit area is continuously increased, so that the ideal state is more and more difficult to realize. At 65nm technology, the static power consumption and the dynamic power consumption of the chip are quite close. The increase of the power consumption of the CMOS circuit may cause fluctuation of the operating state of the device, affect the quality of the chip, and the increase of the leakage current seriously affects the static power consumption of the circuit. In order to reduce the static power consumption of the circuit, the supply Voltage (VDD) and the off-state current (Ioff) are reduced, so that a high switching ratio and a small subthreshold swing SS (Subthreshold swing) are required.
In order to solve the problem of reducing the power consumption of the chip, researchers have proposed a gated clock technique, a multi-supply voltage technique, and the like, which can reduce the power consumption of the circuit to some extent, but also increase the complexity of the circuit. Because the conduction mechanism of the MOSFET device is realized by means of drift diffusion of carriers, the subthreshold swing (Subthreshold Swing, SS) of the MOSFET is difficult to break through the limit of 60Mv/dec at room temperature, and the most direct method for reducing the power consumption is to reduce the power supply voltage, but the reduction of the power supply voltage reduces the switching ratio of current, and even causes the circuit to be difficult to work normally. Further, fin field effect transistors (Fin Field Effect Transistor, finFET) have been developed, which have a large contact area between the gate and the channel and have a good gate control capability, and are widely focused, but it is still difficult to break through 60mV/edc at room temperature. With the shrinking transistor size, leakage power becomes an important issue in designing efficient, energy-efficient and high-performance circuits.
Accordingly, the inventors have employed a Tunneling Field Effect Transistor (TFET) as a new replacement device. TFETs are of great interest because of their operating mechanism with band tunneling: for an N-type TFET, which is not affected by thermal electron emission, electron tunneling occurs between energy bands without fermi-tailing, so that its subthreshold swing can be lower than 60mv/dec, and compared with a MOSFET, the TFET has larger on-current and stronger driving capability than the MOSFET under the condition of smaller gate-source voltage (Vgs). And TFET has the process manufacture of traditional MOSFET, can work at low voltage, has higher switching ratio, thus can reduce the circuit power consumption, so under the condition of low voltage, the performance of TFET is superior to MOSFET. However, when the TFET is formed into a transmission gate structure, an uncontrolled P-I-N current is easy to occur, and transmission errors can be caused.
Disclosure of Invention
Based on the above, it is necessary to provide a single-edge master-slave trigger and a trigger module based on TFET for solving the problems that the power consumption is high when the existing trigger is based on MOSFET design and the P-I-N current is easy to occur when the existing trigger is based on TFET design.
The invention is realized by adopting the following technical scheme:
in a first aspect, the invention provides a single edge master-slave flip-flop based on a TFET, which comprises 12 PTFET transistors (P1-P12), 13 NTFET transistors (N1-N13), and an inverter INV.
The input end of the inverter INV is connected with the input signal D, and the output end is connected with the inverted signal DB.
The source of P1 is connected to the power supply VDD and the gate is connected to the clock signal CLK. The source of P2 is connected to the drain of P1 and the gate is connected to the input signal D. The source of P3 is connected to the power supply VDD and the gate is connected to the inversion signal DB. The source of P4 is connected to the drain of P3 and the gate is connected to the clock signal CLK. The source of P5 is connected to the power supply VDD, and the gate is connected to the drain of P2 and provided with an intermediate node DN.
The drain electrode of N1 is connected with the drain electrode of P2, and the gate electrode is connected with the drain electrode of P4 and is provided with an intermediate node A. The source electrode of N2 is grounded GND, the grid electrode is connected with the input signal D, and the drain electrode is connected with the source electrode of N1. The drain of N3 is connected to the drain of P4 and the gate is connected to the inversion signal DB. The source of N4 is grounded GND, the grid is connected with the clock signal CLK, and the drain is connected with the source of N3. The source of N5 is connected to the drain of N4, the gate is connected to the drain of P5 and is provided with an intermediate node B, and the drain is connected to the gate of P5 and is provided with an intermediate node DN.
The source of P6 is connected to the power supply VDD and the gate is connected to the clock signal CLK. P7 has a source connected to the power supply VDD and a gate connected to the intermediate node A. The source of P8 is connected to the drain of P7 and the gate is connected to the intermediate node B. The source of P9 is connected to the power supply VDD, and the gate is connected to the drain of P6 and provided with an intermediate node C. P10 has a source connected to the power supply VDD and a gate connected to the clock signal CLK. The source of P11 is connected to the drain of P10, and the drain is connected to the drain of P9 and provided with an output node Q. The source of P12 is connected to the power supply VDD and the gate is connected to the drain of P9.
The source electrode of N6 is grounded GND, the grid electrode is connected with the grid electrode of P5, and the drain electrode is connected with the drain electrode of P5. The source electrode of N7 is connected with the drain electrode of N4, the grid electrode is connected with the grid electrode of N6, and the drain electrode is connected with the drain electrode of P5. The drain of N8 is connected to the drain of P6 and the gate is connected to the clock signal CLK. The source electrode of N9 is grounded GND, the grid electrode is connected with the middle node B, and the drain electrode is connected with the source electrode of N8. The drain of N10 is connected to the drain of P9 and the gate is connected to the clock signal CLK. The source electrode of N11 is grounded GND, the grid electrode is connected with the grid electrode of P9, and the drain electrode is connected with the source electrode of N10. The source electrode of N12 is connected with the drain electrode of N11, the grid electrode is connected with the grid electrode of P11, and the drain electrode is connected with the drain electrode of P11. The source of N13 is grounded GND, the gate is connected to the gate of P12 and is provided with an intermediate node QN, and the drain is connected to the drain of P12.
Implementation of such TFET-based single edge master-slave flip-flops is in accordance with methods or processes of embodiments of the present disclosure.
In a second aspect, the present invention discloses a trigger module, which adopts the circuit layout of the single-edge master-slave trigger based on TFET as disclosed in the first aspect. The pins of the trigger module comprise 5 pins. The first pin is connected to the gates of P2 and N2, and is used for transmitting the input signal D. The second pins are connected to the gates of P1, P4, N4, P6, N8, P10, N10 for transmitting the clock signal CLK. The third pin is connected to sources of P1, P3, P5, P6, P7, P9, P10, and P12 for connecting to the power supply VDD. The fourth pin is connected to the sources of N2, N4, N6, N9, N11, N13 for grounding GND. The fifth pin is connected with the output node Q and is used for outputting data.
Compared with the prior art, the invention has the following beneficial effects:
the invention builds the trigger based on TFET, does not use a transmission gate or a transmission tube structure, further avoids the forward bias P-I-N current problem caused by the transmission gate, and controls the correct transmission of data through the intermediate node and the clock signal CLK. Although the CLK is a single-phase clock, the invention can realize the trigger function by matching with the circuit design of the TFET transistor without setting a clock inverter for the CLK. And through simulation test, the invention has low power consumption index and larger advantages.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a circuit configuration diagram of a TFET-based single edge master slave flip-flop (TDFF) provided in embodiment 1 of the present invention;
FIG. 2 is a simulated waveform diagram of the TDFF of FIG. 1;
FIG. 3 is a circuit diagram of a first single edge master slave flip-flop (TSPC) of the prior art;
FIG. 4 shows a second single edge master-slave flip-flop (S) 2 CFF);
FIG. 5 is a circuit diagram of a third single edge master slave flip-flop (ESRFF) of the prior art;
FIG. 6 is a circuit diagram of a fourth single edge master slave flip-flop (CSRFF) of the prior art;
FIG. 7 is a graph of dynamic power consumption versus waveforms for the TDFF of FIG. 1 and four flip-flops of the prior art;
fig. 8 is a block diagram of a trigger chip according to embodiment 2 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that when an element is referred to as being "mounted to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "secured to" another element, it can be directly secured to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or/and" as used herein includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, a circuit configuration diagram of a TFET-based single edge master-slave flip-flop (TDFF) provided in embodiment 1 is shown. As shown in fig. 1, TDFF includes 12 PTFET transistors (P1 to P12), 13 NTFET transistors (N1 to N13), and one inverter INV.
The input end of the inverter INV is connected with the input signal D, and the output end is connected with the inverted signal DB.
The source of P1 is connected to the power supply VDD and the gate is connected to the clock signal CLK. The source of P2 is connected to the drain of P1 and the gate is connected to the input signal D. The source of P3 is connected to the power supply VDD and the gate is connected to the inversion signal DB. The source of P4 is connected to the drain of P3 and the gate is connected to the clock signal CLK. The source of P5 is connected to the power supply VDD, and the gate is connected to the drain of P2 and provided with an intermediate node DB.
The drain electrode of N1 is connected with the drain electrode of P2, and the gate electrode is connected with the drain electrode of P4 and is provided with an intermediate node A. The source electrode of N2 is grounded GND, the grid electrode is connected with the input signal D, and the drain electrode is connected with the source electrode of N1. The drain of N3 is connected to the drain of P4 and the gate is connected to the inversion signal DB. The source of N4 is grounded GND, the grid is connected with the clock signal CLK, and the drain is connected with the source of N3. The source of N5 is connected to the drain of N4, the gate is connected to the drain of P5 and is provided with an intermediate node B, and the drain is connected to the gate of P5 and is provided with an intermediate node DN.
The source of P6 is connected to the power supply VDD and the gate is connected to the clock signal CLK. P7 has a source connected to the power supply VDD and a gate connected to the intermediate node A. The source of P8 is connected to the drain of P7 and the gate is connected to the intermediate node B. The source of P9 is connected to the power supply VDD, and the gate is connected to the drain of P6 and provided with an intermediate node C. P10 has a source connected to the power supply VDD and a gate connected to the clock signal CLK. The source of P11 is connected to the drain of P10, and the drain is connected to the drain of P9 and provided with an output node Q. The source of P12 is connected to the power supply VDD and the gate is connected to the drain of P9.
The source electrode of N6 is grounded GND, the grid electrode is connected with the grid electrode of P5, and the drain electrode is connected with the drain electrode of P5. The source electrode of N7 is connected with the drain electrode of N4, the grid electrode is connected with the grid electrode of N6, and the drain electrode is connected with the drain electrode of P5. The drain of N8 is connected to the drain of P6 and the gate is connected to the clock signal CLK. The source electrode of N9 is grounded GND, the grid electrode is connected with the middle node B, and the drain electrode is connected with the source electrode of N8. The drain of N10 is connected to the drain of P9 and the gate is connected to the clock signal CLK. The source electrode of N11 is grounded GND, the grid electrode is connected with the grid electrode of P9, and the drain electrode is connected with the source electrode of N10. The source electrode of N12 is connected with the drain electrode of N11, the grid electrode is connected with the grid electrode of P11, and the drain electrode is connected with the drain electrode of P11. The source of N13 is grounded GND, the gate is connected to the gate of P12 and is provided with an intermediate node QN, and the drain is connected to the drain of P12.
The above connection relationship can also be expressed as:
the input signal D is connected with the grid electrode of the P2, the grid electrode of the N2 and the input end of the INV.
The inversion signal DB is connected with the output of INV, the grid electrode of P3 and the grid electrode of N3.
The clock signal CLK is connected to the gate of P1, the gate of P4, the gate of N4, the gate of P6, the gate of N8, the gate of N10, and the gate of P10.
The source of P1, P3, P5, P6, P7, P9, P10, and P12 are connected to a power supply VDD.
The source of N2, the source of N4, the source of N6, the source of N9, the source of N11, and the source of N13 are connected to ground GND.
The drain of P1 is connected to the source of P2.
The drain of P2 is connected to the drain of N1, the gate of P5, the gate of N6, the drain of N5, the gate of N7, and the node therebetween is defined as intermediate node DN.
The grid electrode of N1 is connected with the drain electrode of P4, the drain electrode of N3, the grid electrode of P7, the drain electrode of N2 and the grid electrode of P7, and the node between the grid electrodes is defined as an intermediate node A.
The drain of P3 is connected to the source of P4.
The drain electrode of N4 is connected with the source electrode of N3, the source electrode of N5 and the source electrode of N7.
The drain of P5 is connected to the drain of N6, the gate of N5, the drain of N7, the gate of N9, the gate of P8, and the node therebetween is designated as an intermediate node B.
The drain of P6 is connected to the drain of N8, the drain of P8, the gate of gate N11 of P9, and the node therebetween is defined as intermediate node C.
The drain of N9 is connected to the source of N8.
The drain of P7 is connected to the drain of P8.
The drain of P9 is connected to the drain of N10, the drain of P11, the gate of P12, the gate of N13, the drain of N12, and the node therebetween is defined as output node Q.
The drain electrode of N11 is connected with the source electrode of N10 and the source electrode of N12.
The drain of P10 is connected to the source of P11.
The drain of P12 is connected to the gate of P11, the gate of N12, the drain of N13, and the node therebetween is defined as intermediate node QN.
The circuit structure can be divided into a master stage and a slave stage. The main stage comprises N1, N2, N3, N4, N5, N6, N7, P1, P2, P3, P4, P5 and INV. The slave stages include P6, P7, P8, P9, P10, P11, P12, N8, N9, N10, N11, N12.
In general, TDFF operates periodically with CLK states in each cycle including a first stage low level and a second stage high level, with CLK rising single edge triggered.
If the current period CLK is in the first phase, the master transmits the data of the input signal D, and the slave stores the data transmitted from the master when the CLK is in the second phase in the previous period.
If the current period CLK is in the second phase, the master stores the data of the input signal D transmitted when the current period CLK is in the first phase, and the slave transmits the data transmitted from the master when the CLK is in the first phase in the previous period.
Of course, when the TDFF initially works, the output node Q of the slave stage initially pre-stores "0" or "1", and as the periodic work starts, the pre-stored data of the output node Q will be covered by the data transmitted from the master stage of the previous period.
In short, if the current period CLK is in the first stage, the input signal D is high, and the intermediate node B is high; next, the current period CLK is in the second phase, and the intermediate node B is still high regardless of whether the input signal D is high or low. Correspondingly, if the current period CLK is in the first stage, the output node Q stores the data transmitted by the main stage when the CLK is in the second stage in the previous period; next, the current period CLK is in the second phase, the intermediate node B is high, and the output node Q is correspondingly high.
If the current period CLK is in the first stage, the input signal D is low, and the intermediate node B is correspondingly low; next, the current period CLK is in the second phase, and the intermediate node B is still low regardless of whether the input signal D is high or low. Correspondingly, if the current CLK is in the first stage, the output node Q stores the data transmitted by the main stage when the CLK is in the second stage in the previous period; next, the current CLK is in the second phase, the intermediate node B is low, and the output node Q is correspondingly low.
Referring to fig. 2, taking the output node Q as an example, several cases of its operation are specifically described, and the operation principle of TDFF is also described as follows:
the output node Q is flipped 0→1, i.e., Q has stored a "0" and is written with a "1" next.
The input signal D is "1" (high), DB is inverted from D, low, N2 on, P3 on.
If the clock signal CLK is low, for the main stage, P1 and P4 are turned on, A is connected to VDD via P3 and P4 and charged, A is high; the high level A turns on N1, DN is grounded GND through N1 and N2, and DN is discharged to be low level; DN of low level turns on P5, B is connected with VDD through P5 and charged, B is high level; in the above process, for the slave stage, P6 is turned on, C is connected to VDD through P6 and charged, C is high, C at high turns on N11, Q is "0" (low), QN is high, N12 is turned on, Q is grounded through N11 and N12, and is maintained at low.
Then, when the clock rising edge (CLK goes high) comes, P1, P4 are off and N4 is on for the master stage;
if the input signal D is kept at a high level, DB is at a low level, N2 is opened, N3 is closed, A is kept at the original state at the high level, N1 is opened, DN is discharged to the low level through the grounding of N1 and N2, and B is at the high level and is consistent with the input signal D; b of high level turns on N5, DN is maintained at low level through N5, N4 grounding, thus B is maintained at high level;
if the input signal D jumps and goes low, a remains in the original state (i.e., the state when D is high and CLK is low), P3 and P4 are turned on, a is high, DN is low, and B is high, i.e., the change of the input signal D does not affect B.
For the slave stage, N8 is turned on, N9 is turned on, C discharges to low level through N8, N9 ground, C at low level turns on P9, Q is connected to VDD through P9 and charged, Q is high level, and it is consistent with input signal D.
(II) output node Q goes 0→0, i.e., Q has stored a "0" and is written next with a "0".
The input signal D is "0" (low level), DB is inverted from D, and is high, P2 is on, and N3 is on.
If the clock signal CLK is low, for the main stage, P1 and P4 are turned on, DN is connected to VDD via P1 and P2 and charged, DN is high, and B is low; in the above process, for the slave stage, P6 is turned on, C is charged through the P6 and VDD connection, C is high, C at high turns N11 on, Q is "0" (low), QN is high, N12 is turned on, Q is grounded through N11 and N12, and is maintained at low.
Then, when the clock rising edge (CLK goes high) comes, P1, P4 are off and N4 is on for the master stage;
if the input signal D is kept at a low level, DB is at a high level, N2 is closed, N3 is opened, A is at a low level through N3 and N4 grounding discharge, the low level A enables N1 to be closed, the input signal D cannot be input into the main stage, DN is kept at the original state at the high level, and B is kept at the low level and consistent with the input signal D; DN of high level turns N7 on, B is grounded through N7 and N4 and is maintained at low level;
if the input signal D jumps and goes high, a remains in the original state (i.e., D is low and CLK is high), N3 and N4 are turned on, a is low, DN remains in the original state and DN is high, and B is low, i.e., the change of the input signal D does not affect B.
For the slave stage, N8 is opened, N9 is closed, N10 is opened, P8 is opened, P7 is opened, C is connected with VDD through P8 and P7 and is charged, C is in a high level, C in the high level opens N11, and Q is discharged through N10 and N11 in a grounding mode; q is low and remains the same as input signal D.
(III) the output node Q is flipped 1-0, i.e., Q has stored a "1" and is then written with a "0".
The input signal D is '0' (low level), DB is inverted from D, and is high level, P2 is open, N3 is open; if the clock signal CLK is low, P1 and P4 are turned on, DN is connected to VDD via P1 and P2 and charged, DN is high, and B is low; in the above process, for the slave stage, P6 and P10 are turned on, C is connected to VDD through P6 and charged, C is high, C at high level turns N11 on, Q is "1" (high level), QN is low, P11 is turned on, Q is charged through P11 and P10 connection to VDD and maintained at high level.
Then, when the clock rising edge (CLK goes high) comes, P1, P4 are off and N4 is on for the master stage;
if the input signal D is kept at a low level, DB is at a high level, N3 is opened, A is discharged to be at a low level through grounding of N3 and N4, A at the low level is closed, the input signal D cannot be input into the main stage, DN is kept at the original state at the high level, and B is at the low level; DN of high level turns N7 on, B is grounded through N7 and N4 and is maintained at low level;
if the input signal D jumps and goes high, a remains in the original state (i.e., D is low and CLK is high), N3 and N4 are turned on, a remains low, DN remains high, and B remains low, i.e., the change of the input signal D does not affect B.
For the slave stage, N8 is opened, N9 is closed, N10 is opened, P7 is opened, P8 is opened, C is connected with VDD through P8 and P7 and is charged, C is in a high level, C in the high level opens N11, and Q is discharged through N10 and N11 in a grounding mode; q is low and remains the same as input signal D.
(IV) output node Q goes 1→1, i.e., Q has stored a "1", and then "1" is written.
The input signal D is "1" (high level), DB is inverted from D, is low level, N2 is open, P3 is open; if the clock signal CLK is low, for the master stage P1, P4 are on, A is connected and charged through P3, P4 and VDD, A is high; the high level A turns on N1, DN is grounded GND through N1 and N2, and DN is discharged to be low level; DN of low level turns on P5, B is connected with VDD through P5 and charged, B is high level; in the above process, for the slave stage, P6 and P10 are turned on, C is connected to VDD through P6 and charged, C is high, C at high level turns N11 on, Q is "1" (high level), QN is low, P11 is turned on, Q is charged through P11 and P10 connection to VDD and maintained at high level.
Then, when the clock rising edge (CLK goes high) comes, P1, P4 are off and N4 is on for the master stage;
if the input signal D remains high, DB is low, N2 is on, N3 is off, a remains in the original state (i.e., D is high, CLK is low), at which time a is high, N1, N2 are on, DN is low, and B is high.
If the input signal D jumps, it goes low, N2 is turned off, and P1 is also turned off, DN remains low, and B goes high, i.e., it indicates that the change of the input signal D does not affect B.
For the slave stage, N8 is on, N9 is on, C discharges to low level through N8, N9 ground, C at low level turns on P9, Q charges with VDD connection, Q is high level, and it remains consistent with input signal D.
From the above, the TDFF can accurately transmit and store data.
In order to verify the power consumption of the TDFF, the embodiment 1 also uses TDFF and four single-edge master-slave flip-flops (TSPC, S 2 CFF, ESRFF, CSRFF) are subjected to simulation comparison, and the simulation conditions are Corner: TT; temperature:27 ℃; VDD:0.6V. Wherein the circuit of TSPC is referred to in FIG. 3, S 2 The CFF circuit is seen in fig. 4, the esrff circuit is seen in fig. 5, and the csrff circuit is seen in fig. 6. Wherein the frequency of the input signal D is adjustable, and a switching factor alpha is generally adopted D Characterization. Alpha D The larger the representation of the input signal D D The higher the frequency of change. Alpha D The smaller the frequency of change of the input signal D. Theoretically, α D Positively correlated with power consumption.
Referring to FIG. 7, for a simulated power consumption comparison, each single edge master-slave triggerThe average is taken multiple times. It can be seen that TDFF is at alpha D When=0, the power consumption is slightly larger than CSREF and ESREF and obviously smaller than TSPC and S 2 CFF. TDFF at alpha D When the power consumption is equal to or less than 20%, 50% and 100%, the power consumption is obviously less than CSREF, ESREF, TSPC, S 2 CFF. Therefore, it can be said that TDFF has a great advantage of low power consumption.
The low power consumption advantage of TDFF can also be analyzed in principle:
due to the adoption of TFET tube construction, the power consumption can be reduced compared with the CMOS technology. For the intermediate node C, only P7-P8 or P6 needs to be opened for charging, so that the redundant charging process of C is avoided, and the power consumption is reduced. In addition, the frequency of the clock signal CLK is varied by a switching factor alpha CLK Characterization. If a two-phase clock is used, a clock inverter is required to be introduced into the flip-flop to generate the clock inversion signal CLKB, so that the clock load can be reduced and the switching factor alpha is also achieved CLK But always 1, which causes the clocked inverter to operate at high frequency and increases power consumption. The TDFF only uses a single-phase clock, and can realize the function of a trigger without setting a clock inverter for CLK by matching with the circuit design of the TFET transistor, thereby reducing the power consumption.
Example 2
The embodiment 2 discloses a trigger module, which adopts the circuit layout of the single-edge master-slave trigger based on the TFET in the embodiment 1. The mode of packaging into a module is easier to popularize and apply.
The pins of the trigger module comprise 5 pins. The first pin is connected to the gates of P2 and N2, and is used for transmitting the input signal D. The second pins are connected to the gates of P1, P4, N4, P6, N8, P10, N10 for transmitting the clock signal CLK. The third pin is connected to sources of P1, P3, P5, P6, P7, P9, P10, and P12 for connecting to the power supply VDD. The fourth pin is connected to the sources of N2, N4, N6, N9, N11, N13 for grounding GND. The fifth pin is connected with the output node Q and is used for outputting data.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. A TFET-based single edge master-slave flip-flop comprising:
the input end of the inverter INV is connected with the input signal D, and the output end of the inverter INV is connected with the inverted signal DB;
PTFET transistor P1, its source connects to power VDD, the grid connects to clock signal CLK;
PTFET transistor P2, its source connects the drain electrode of P1, the grid connects the input signal D;
PTFET transistor P3, its source connects power VDD, the grid connects inverted signal DB;
PTFET transistor P4, its source connects the drain electrode of P3, the grid connects the clock signal CLK;
PTFET transistor P5, its source connects power VDD, the grid connects drain-source resistance of P2 and sets up the intermediate node DN;
NTFET transistor N1, its drain electrode connects the drain electrode of P2, the grid electrode connects the drain electrode of P4 and has intermediate node A;
NTFET transistor N2, its source is grounded GND, the grid connects input signal D, the drain-source resistance connects the source of N1;
NTFET transistor N3, its drain electrode connects drain electrode of P4, grid electrode connects inverted signal DB;
NTFET transistor N4, its source is grounded GND, the grid connects clock signal CLK, the drain electrode connects the source of N3;
NTFET transistor N5, its source connects the drain electrode of N4, the grid connects the drain electrode of P5 and there is intermediate node B, the drain electrode connects the grid of P5 and there is intermediate node DN;
PTFET transistor P6, its source connects power VDD, the grid connects clock signal CLK;
PTFET transistor P7, the source of which is connected to power supply VDD, and the gate of which is connected to intermediate node A;
PTFET transistor P8, with its source connected to the drain of P7 and its gate connected to intermediate node B;
a PTFET transistor P9 having a source connected to the power supply VDD, a gate connected to the drain of P6, and an intermediate node C;
PTFET transistor P10, the source of which is connected to power supply VDD, and the gate of which is connected to clock signal CLK;
a PTFET transistor P11 having a source connected to the drain of P10, a drain connected to the drain of P9, and an output node Q;
PTFET transistor P12, its source connects power VDD, the drain electrode of grid connection P9;
NTFET transistor N6, its source electrode is grounded GND, the grid connects grid of P5, the drain electrode connects the drain electrode of P5;
NTFET transistor N7, its source connects the drain electrode of N4, the grid connects the grid of N6, the drain electrode connects the drain electrode of P5;
NTFET transistor N8, its drain electrode connects drain electrode of P6, grid electrode connects clock signal CLK;
NTFET transistor N9, its source electrode is grounded GND, the grid connects the middle node B, the drain electrode connects the source electrode of N8;
NTFET transistor N10, its drain electrode connects drain electrode of P9, the grid electrode connects clock signal CLK;
NTFET transistor N11, its source is grounded GND, the grid connects grid of P9, the drain-source resistance connects the source of N10;
NTFET transistor N12, its source connects the drain electrode of N11, the grid connects the grid of P11, the drain electrode connects the drain electrode of P11; and
the NTFET transistor N13 has a source connected to GND, a gate connected to the gate of P12 and provided with an intermediate node QN, and a drain connected to the drain of P12.
2. The TFET-based single edge master-slave flip-flop of claim 1, wherein N1, N2, N3, N4, N5, N6, N7, P1, P2, P3, P4, P5, INV comprise master stages and P6, P7, P8, P9, P10, P11, P12, N8, N9, N10, N11, N12 comprise slave stages.
3. The TFET-based single edge master-slave flip-flop of claim 2, wherein the single edge master-slave flip-flop operates periodically, wherein the CLK state in each period includes a low level for the first phase and a high level for the second phase, the CLK rising single edge triggered;
if the current period CLK is in the first stage, the master stage transmits the data of the input signal D, and the slave stage stores the data transmitted by the master stage when the CLK is in the second stage in the previous period;
if the current period CLK is in the second phase, the master stores the data of the input signal D transmitted when the current period CLK is in the first phase, and the slave transmits the data transmitted from the master when the CLK is in the first phase in the previous period.
4. The TFET-based single edge master-slave flip-flop of claim 3, wherein the output node qinitial of the slave stage is pre-stored with a "0" or a "1".
5. The TFET-based single edge master-slave flip-flop of claim 3, wherein if the current period CLK is in the first phase, the input signal D is high and the intermediate node B is high; next, the current period CLK is in the second phase, and the intermediate node B is still high regardless of whether the input signal D is high or low.
6. The TFET-based single edge master-slave flip-flop of claim 5, wherein if a current period CLK is in a first phase, the output node Q stores data from the master stage when CLK is in a second phase in a previous period; next, the current period CLK is in the second phase, the intermediate node B is high, and the output node Q is correspondingly high.
7. The TFET-based single edge master-slave flip-flop of claim 3, wherein if the current period CLK is in the first phase, the input signal D is low and the intermediate node B is low; next, the current period CLK is in the second phase, and the intermediate node B is still low regardless of whether the input signal D is high or low.
8. The TFET-based single edge master-slave flip-flop of claim 7, wherein if the current CLK is in the first phase, the output node Q stores data from the master stage when the CLK is in the second phase during the previous period; next, the current CLK is in the second phase, the intermediate node B is low, and the output node Q is correspondingly low.
9. A trigger module, characterized in that a circuit layout of a TFET-based single edge master-slave flip-flop according to any of claims 1-8 is used.
10. The trigger module of claim 9, wherein the pins of the trigger module comprise:
the first pin is connected with the grid electrodes of P2 and N2 and is used for transmitting an input signal D;
a second pin connected to the gates of P1, P4, N4, P6, N8, P10, N10 for transmitting the clock signal CLK;
a third pin connected to sources of P1, P3, P5, P6, P7, P9, P10, and P12 for connecting to power supply VDD;
a fourth pin connected to sources of N2, N4, N6, N9, N11, N13 for grounding GND; and
and a fifth pin connected to the output node Q for outputting data.
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| CN202310216710.7A CN116346088A (en) | 2023-03-03 | 2023-03-03 | TFET-based single-edge master-slave trigger and trigger module |
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| CN202310216710.7A CN116346088A (en) | 2023-03-03 | 2023-03-03 | TFET-based single-edge master-slave trigger and trigger module |
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