CN116345933A - Parallel inverter system and impedance compression method thereof - Google Patents

Parallel inverter system and impedance compression method thereof Download PDF

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Publication number
CN116345933A
CN116345933A CN202310336959.1A CN202310336959A CN116345933A CN 116345933 A CN116345933 A CN 116345933A CN 202310336959 A CN202310336959 A CN 202310336959A CN 116345933 A CN116345933 A CN 116345933A
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impedance
inductance
load
compression branch
branch
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管乐诗
刘畅
姚婷婷
王懿杰
徐殿国
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Harbin Institute of Technology
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Harbin Institute of Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4815—Resonant converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks

Abstract

The invention discloses a parallel inverter system and an impedance compression method thereof, and relates to a high-frequency inverter impedance compression circuit and a modulation method thereof. The purpose is in order to overcome current megahertz inverter and adopt passive network to carry out impedance adjustment, can only restrict to the resistive load that changes, when contain the capacitive or inductive component that changes in the load, the impedance scope of input presents the problem of diverging trend, wherein parallelly connected inverter system includes: the first impedance compression branch is used for compressing the load impedance to a first impedance compression branch impedance interval; the value of the central point of the impedance section of the first impedance compression branch is recorded as zGoalu; a second impedance compression branch for compressing the varying load impedance to a second impedance compression branch impedance interval; the value of the central point of the impedance section of the second impedance compression branch is recorded as zGoall; a first impedance matching network for matching zgolu to an ideal impedance point of the first inverter unit; and the second impedance matching network is used for matching zGoall to an ideal impedance point of the second inversion unit.

Description

Parallel inverter system and impedance compression method thereof
Technical Field
The invention relates to a high-frequency inversion impedance compression circuit and a modulation method thereof.
Background
In recent years, multi-megahertz inverters have been widely used in radio frequency plasma acceleration, wireless power transfer, and magnetic resonance imaging systems. In these systems, the inverter needs to work under dynamically changing load, but the resonant inverter such as Class D, E, Φn is very sensitive to load, and can only maintain a soft switching state under rated load, and in addition, due to the higher switching frequency, the multi-megahertz inverter is often difficult to realize single-period closed-loop control through frequency or duty ratio adjustment. In order to provide an ideal equivalent load for an inverter in a dynamic load environment, a current common solution is to add a primary impedance modulation network between the inverter and the load.
The existing impedance matching network is generally composed of a plurality of vacuum capacitors with adjustable capacitance values and fixed inductors, and when the load impedance changes, the matching network adjusts the vacuum capacitors in a closed loop mode in a stepping motor driving vacuum capacitor adjusting mode according to the measured reflected power. However, the impedance matching network has extremely slow response speed due to the adjustment mode of the stepping motor drive, and the vacuum capacitor has high cost and large volume, so that the improvement of the whole power density of the inverter system is restricted.
Thus, in addition to dynamically modulating impedance, passive networks are also often used to compress widely varying load impedance into narrower intervals to statically adjust the range of variation of impedance. However, the existing passive networks have limited regulation capability and can only limit variable resistive loads, and when the load contains variable capacitive or inductive components, the input impedance range cannot be controlled, and even tends to diverge.
Disclosure of Invention
The invention aims to solve the problem that when the existing megahertz inverter adopts a passive network to carry out impedance adjustment, a variable resistive load can be limited, and when the load contains a variable capacitive or inductive component, the input impedance range shows a divergent trend, and provides a parallel inverter system and an impedance compression method thereof.
The invention provides a parallel inversion system, which comprises a first inversion unit, a second inversion unit, a first impedance matching network and a second impedance matching network, wherein the first inversion unit is connected with the first impedance matching network;
the voltage input end of the first inversion unit is used for being electrically connected with the voltage output end of the first adjustable direct current power supply; the voltage output end of the first inversion unit is electrically connected with the voltage input end of the first impedance matching network to form a first impedance compression branch;
the voltage input end of the second inversion unit is used for being electrically connected with the voltage output end of the second adjustable direct current power supply; the voltage output end of the second inversion unit is electrically connected with the voltage input end of the second impedance matching network to form a second impedance compression branch;
the current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used for being electrically connected with the current input end of the load; the load contains varying capacitive and/or inductive components;
a first impedance compression branch for compressing a variable load impedance z Load Compressed to a first impedance compression branch impedance interval z U The method comprises the steps of carrying out a first treatment on the surface of the Impedance section z of first impedance compression branch U The coordinates on the rectangular impedance coordinate system are (R, X), R E [0,10 ]]，X∈[8,16]The method comprises the steps of carrying out a first treatment on the surface of the And the first impedance compression branch impedance interval z U The value of the center point of (2) is denoted as z GoalU ；
A second impedance compression branch for compressing the variable load impedance z Load Compressed to a second impedance compression branch impedance interval z L The method comprises the steps of carrying out a first treatment on the surface of the Second impedance compression branch impedance interval z L The coordinates on the rectangular impedance coordinate system are (R ', X '), R ' E [0,10 ]]，X’∈[-8,-16]The method comprises the steps of carrying out a first treatment on the surface of the And the second impedance compression branch impedance interval z L The value of the center point of (2) is denoted as z GoalL ；
A first impedance matching network for matching z GoalU Matching to an ideal impedance point of the first inversion unit;
a second impedance matching network for matching z GoalL Matching to an ideal impedance point of the second inversion unit;
and the ideal impedance point of the first inversion unit is the same as the ideal impedance point of the second inversion unit.
The invention also provides an impedance compression method of the parallel inversion system, which is based on the parallel inversion system and comprises the following specific steps:
step one, the variable load impedance z Load Compressing the first impedance compression branch impedance interval z U And a second impedance compression branch impedance interval z L ；；
Step two, Z is taken GoalU And z GoalL Matching to ideal impedance points of the first inversion unit and the second inversion unit respectively.
The beneficial effects of the invention are as follows:
1. the variation range of the impedance of each branch of the inverter system can be limited to a limited area centering on a specific point;
2. a widely varying load can be compressed to a small range of input impedance centered around an ideal value;
3. under a wide range of loads, the resonant inverter can work in an ideal load environment, and the voltage across the switch can always keep soft switching.
Drawings
Fig. 1 is a schematic diagram of a circuit topology of a parallel inverter system of the present invention;
FIG. 2 shows the impedance z of the load impedance compressed to the first impedance compression branch U The method comprises the steps of carrying out a first treatment on the surface of the Compressing the load impedance to the impedance z of the second impedance compression branch L Is a schematic diagram of the principle of (a);
FIG. 3 shows the first impedance center z in the present invention GoalU And a second impedance center z GoalL Ideal impedance point z respectively matched to the first inversion voltage source and the second inversion voltage source Inv Is a schematic diagram of the principle of (a).
Fig. 4 is a schematic diagram of simulation results of impedance variation ranges of a first impedance compression branch and a second impedance compression branch in the parallel inverter system and the impedance compression method thereof according to the present invention;
FIG. 5 is a schematic diagram of simulation results of the input end impedance variation range of the parallel inverter system and the impedance compression method thereof according to the present invention;
fig. 6 is a schematic diagram of a simulation result of a drain-source voltage waveform of a switch in the parallel inverter system and an impedance compression method thereof according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
Detailed description of the preferred embodiments
The parallel inverter system of the present embodiment includes a first inverter unit 1, a second inverter unit 2, a first impedance matching network 3, and a second impedance matching network 4;
the voltage input end of the first inversion unit 1 is used for being electrically connected with the voltage output end of the first adjustable direct current power supply; the voltage output end of the first inversion unit 1 is electrically connected with the voltage input end of the first impedance matching network 3 to form a first impedance compression branch;
the voltage input end of the second inversion unit 2 is used for being electrically connected with the voltage output end of the second adjustable direct current power supply; the voltage output end of the second inversion unit 2 is electrically connected with the voltage input end of the second impedance matching network 4 to form a second impedance compression branch;
the current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used for being electrically connected with the current input end of the load 5; the load 5 contains varying capacitive and/or inductive components;
a first impedance compression branch for compressing a variable load impedance z Load Compressed to the firstImpedance compression branch impedance interval z U The method comprises the steps of carrying out a first treatment on the surface of the Impedance section z of first impedance compression branch U The coordinates on the rectangular impedance coordinate system are (R, X), R E [0,10 ]]，X∈[8,16]The method comprises the steps of carrying out a first treatment on the surface of the And the first impedance compression branch impedance interval z U The value of the center point of (2) is denoted as z GoalU ；
A second impedance compression branch for compressing the variable load impedance z Load Compressed to a second impedance compression branch impedance interval z L The method comprises the steps of carrying out a first treatment on the surface of the Second impedance compression branch impedance interval z L The coordinates on the rectangular impedance coordinate system are (R ', X '), R ' E [0,10 ]]，X’∈[-8,-16]The method comprises the steps of carrying out a first treatment on the surface of the And the second impedance compression branch impedance interval z L The value of the center point of (2) is denoted as z GoalL ；
A first impedance matching network 3 for matching z GoalU Matching to an ideal impedance point of the first inverter unit 1;
a second impedance matching network 4 for matching z GoalL Matching to an ideal impedance point of the second inverter unit 2;
and the ideal impedance point of the first inverter unit 1 is the same as the ideal impedance point of the second inverter unit 2.
Detailed description of the preferred embodiments
The present embodiment is a further description of the first embodiment, in which the first inverter unit 1 includes a capacitor C INU Inductance L FU Switching device S U Capacitance C FU Inductance L RU And capacitor C RU ；
The positive electrode of the first adjustable DC power supply is simultaneously connected with the capacitor C INU And inductance L FU Is electrically connected to one end of the first wire;
inductance L FU At the same time with the other end of the switching device S U Source, capacitance C of (2) FU And inductance L RU Is electrically connected to one end of the first wire; inductance L RU And the other end of (C) and the capacitor C RU Is electrically connected to one end of the first wire; capacitor C RU The other end of the first inverter unit 1 is used as a voltage output end;
negative electrode of first adjustable DC power supply and capacitor C INU Is a switching device S U Drain of (C) and capacitance C FU The other ends of the two electrodes are grounded;
the second inverter unit 2 includes a capacitor C INL Inductance L FL Switching device S L Capacitance C FL Inductance L RL And capacitor C RL ；
The positive electrode of the second adjustable DC power supply is simultaneously connected with the capacitor C INL And inductance L FL Is electrically connected to one end of the first wire;
inductance L FL At the same time with the other end of the switching device S L Source, capacitance C of (2) FL And inductance L RL Is electrically connected to one end of the first wire; inductance L RL And the other end of (C) and the capacitor C RL Is electrically connected to one end of the first wire; capacitor C RL The other end of the second inverter unit 2 is used as a voltage output end;
negative electrode of second adjustable DC power supply and capacitor C INL Is a switching device S L Drain of (C) and capacitance C FL The other ends of the two are grounded.
Other technical features of the present embodiment are exactly the same as those of the second embodiment.
Detailed description of the preferred embodiments
In this embodiment, the first impedance matching network 3 and the second impedance matching network 4 are both T-type impedance matching networks;
the first impedance matching network 3 comprises an inductance L U1 Capacitance C U2 And inductance L U3 ；
Inductance L U1 One end of (2) and a capacitor C RU Is electrically connected with the other end of the first part;
inductance L U1 At the same time with the capacitor C U2 And inductance L U3 Is electrically connected to one end of the first wire;
capacitor C U2 The other end of the (b) is electrically connected with the load 5; inductance L U3 The other end of the first electrode is grounded;
the second impedance matching network 4 comprises an inductance L L1 Inductance L L2 And inductance L L3 ；
Inductance L L1 One end of (2) and a capacitor C RL Is electrically connected with the other end of the first part;
inductance L L1 At the same time with the inductance L L2 And inductance L L3 Is electrically connected to one end of the first wire;
inductance L L2 The other end of the (b) is electrically connected with the load 5; inductance L L3 The other end of which is grounded.
Other technical features of the present embodiment are exactly the same as those of the third embodiment.
Detailed description of the preferred embodiments
The impedance compression method of the parallel inverter system of the present embodiment is further described with respect to the parallel inverter system of the first, second or third embodiment, and specific steps in the present embodiment are as follows:
step one, the variable load impedance z Load Compressing the first impedance compression branch impedance interval z U And a second impedance compression branch impedance interval z L ；；
Step two, Z is taken GoalU And z GoalL Matching to ideal impedance points of the first inverter unit 1 and the second inverter unit 2, respectively.
Other technical features of the present embodiment are exactly the same as those of the first, second or third embodiments.
Detailed description of the preferred embodiments
In this embodiment, a step one is specifically as follows:
step one, obtaining z through simulation on an impedance rectangular coordinate system GoalU And z GoalL The first impedance compression branch impedance section z U At z GoalU In the (R, X) region as the center point, the second impedance compression branch impedance section z L At z GoalL In the region (R ', X') being the center and obtaining the impedance interval z of the second impedance compression branch L And the first impedance compression branch impedance interval z U Corresponding relation of (3);
step two, by adjusting the current amplitude and the current phase of the first impedance compression branch and the second impedance compression branch,impedance z of load Load Matching to the impedance section z of the first impedance compression branch U And a second impedance compression branch impedance interval z L Where it is located.
Other technical features of the present embodiment are exactly the same as those of the fourth embodiment.
Detailed description of the preferred embodiments six
In this embodiment, in the step one, the impedance z of the second impedance compression branch is obtained by the following formula L And the first impedance compression branch impedance interval z U Corresponding relation of (3):
Figure BDA0004156731280000051
wherein z is Load For load impedance, z L Compressing the impedance of the branch for a second impedance, Z Load For the magnitude of the load impedance,
Figure BDA0004156731280000052
k is the scaling factor of the impedance range, k=0.4-0.5, which is the phase of the load impedance; i is an imaginary unit.
Other technical features of the present embodiment are exactly the same as those of the fifth embodiment.
Detailed description of the preferred embodiments
In this embodiment, the first step is described as follows:
Figure BDA0004156731280000053
wherein I is U A current amplitude of the output current of the first impedance compression branch I L Outputting a current magnitude of the current for the second impedance compression branch;
Figure BDA0004156731280000054
the current phase of the output current for the first impedance compression branch,/->
Figure BDA0004156731280000055
The second impedance compresses the current phase of the output current of the branch.
Other technical features of the present embodiment are exactly the same as those of the sixth embodiment.
Detailed description of the preferred embodiments
In this embodiment, a seventh embodiment is further described, and in this embodiment, the second step is specifically as follows:
step two, according to z GoalU 、z GoalL And the value z of the ideal impedance point Inv Obtaining impedance parameters of the first impedance matching network 3 and the second impedance matching network 4;
step two, calculating to obtain the input direct current voltage V of the first inversion unit 1 INU And the phase of the switch drive signal
Figure BDA0004156731280000061
The input DC voltage V of the second inverter unit 2 INL And phase of the switch drive signal->
Figure BDA0004156731280000062
Input voltage v of first impedance matching network 3 U And an input voltage v of the second impedance matching network 4 L ；
And through the input DC voltage V of the first inverter unit 1 INU And the phase of the switch drive signal
Figure BDA0004156731280000063
Controlling the first impedance matching network 3 to be z GoalU Matching to the ideal impedance point of the first inverter unit 1, and the input DC voltage V through the second inverter unit 2 INL And phase of the switch drive signal->
Figure BDA0004156731280000064
Controlling the second impedance matching network 4 to make z GoalL Matching to the ideal impedance point of the second inverter unit 2.
Other technical features of the present embodiment are exactly the same as those of the seventh embodiment.
Detailed description of the preferred embodiments nine
In the eighth embodiment, in the first step, the impedance parameters of the first impedance matching network 3 and the second impedance matching network 4 are obtained by the following equation:
Figure BDA0004156731280000065
wherein, R is GoalU ，X GoalU Z respectively GoalU Resistance and reactance components of (a); r is R GoalL ，X GoalL Z respectively GoalL Resistance and reactance components of (a); r is R inv ，X inv The values z of the ideal impedance points respectively Inv Resistance and reactance components of (a); z CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 Respectively the inductance L U1 Capacitance C U2 Inductance L U3 Inductance L L1 Inductance L L2 And inductance L L3 Impedance value.
Other technical features of the present embodiment are exactly the same as those of the eighth embodiment.
Detailed description of the preferred embodiments
In the present embodiment, in the second step, the input dc voltage V of the first inverter unit 1 is obtained by the following equation INU And the phase of the switch drive signal
Figure BDA0004156731280000066
And the input dc voltage V of the second inverter unit 2 INL And phase of the switch drive signal->
Figure BDA0004156731280000067
Figure BDA0004156731280000071
Wherein P is Load For the desired output power, R Load Is a load resistance component;
the input voltage v of the first impedance matching network 3 is obtained by U And an input voltage v of the second impedance matching network 4 L ：
Figure BDA0004156731280000072
Other technical features of this embodiment are exactly the same as those of the ninth embodiment.
Examples
The equivalent circuit of the invention for the ultrahigh frequency inverter system is shown in figure 1. The inverter system is formed by connecting two groups of ultrahigh frequency resonant Class E voltage sources with adjustable amplitude and phase in parallel, wherein the amplitude of the voltage sources is formed by inputting direct current voltage V INU ,V INL Control of the voltage source phase by the phase of the switch drive signal
Figure BDA0004156731280000075
And (5) controlling. Each branch is connected with an additional T-shaped matching network.
The impedance compression method comprises two steps, namely, firstly, controlling the amplitude and the phase of the current in an impedance compression branch to change the load impedance z load Compressed to a narrower interval, z U ,z L Second, z is further advanced by T-network in the branch U And z L Matching to the ideal impedance point z Inv 。
Load impedance z load To z U ，z L The compression method of (2) is shown in fig. 2. For the parallel inverter system circuit of fig. 1, the upper and lower leg impedances z U ,z L There is a correspondence, thus at any load impedance z Load Next, first, z is obtained U ,z L Are all at z GoalU ，z GoalL Z in a limited region of the centre L And (5) taking a value. z GoalU ，z GoalL Can be obtained by simulation, provided thatz U ,z L Is the smallest and lies on the positive half of the x-axis.
Figure BDA0004156731280000073
Wherein z is Load ,z L Z is the load impedance and the lower arm impedance Load ,
Figure BDA0004156731280000074
The magnitude and phase of the load impedance, respectively. k is the scaling factor of the impedance range, when k=0, only the lower leg impedance z L Compressed, when k=1, only the upper leg impedance z U Is compressed. Typically k is selected to be between 0.4 and 0.5 such that z U And z L And vary within the same range.
When the target impedance z L After being determined, the load impedance z can be adjusted by, for example, adjusting the magnitude and phase of the medium current Load Matching to z U ' (New z U ) And z L Where it is located.
Figure BDA0004156731280000081
Is compressed to z GoalU ,z GoalL The branch impedance z being the centre U ,z L Further matching to the ideal impedance point of the inverter is required: z Inv . Thus, the T-network in each leg can be designed to divide z GoalU ,z GoalL Matching to z Inv 。
Figure BDA0004156731280000082
Wherein R is GoalU ,X GoalU ,R GoalL ,X GoalL Respectively the impedance center z GoalU ,z GoalL And a reactive component of (a) is provided. R is R inv ,X inv Is the target impedance z Inv And a reactive component of (a) is provided. z CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 Is the element resistance value in the T-type resistance network. z CU1 ,z CU2 ,z CU1 ,z CU2 Determine the impedance center position, z CU3 ，z CL3 Is determined by z Inv Is the range of impedance variation in the center. In general, z CU3 ，z CL3 Should be greater than z U And z L 。
After the related parameters of the T-shaped network are determined, the distribution relation of the current amplitude and the phase in the T-shaped network can be indirectly controlled by the amplitude and the phase of the input voltage, so that the input voltage v of the network is compressed by the impedance U ，v L Can be obtained by calculation.
Figure BDA0004156731280000083
Wherein P is Load For the desired output power, R Load Is the load resistance component. The inverter system inputs DC voltage V INU ,V INL Phase with the switch driving signal
Figure BDA0004156731280000085
Can be finally obtained by solving.
Figure BDA0004156731280000084
The effect is as follows:
1. as shown in fig. 4, the range of variation of the impedance of each branch of the inverter system can be limited to a limited area centered at a specific point based on the proposed parallel inverter system.
2. As shown in fig. 5, under the proposed parallel inverter system and its impedance compression method, a widely varying load can be compressed to a small range of input impedance centered around an ideal value.
3. As shown in fig. 6, under the condition of the proposed parallel inversion system, the resonant inverter can work under the ideal load environment under the wide range of loads, and the voltage across the switch can always keep soft switching.
The designed parallel type Class E inversion system and the impedance compression method are the plasma generator and the wireless power transmission system facing the object. The output power is 50W, the working frequency is 13.56MHz, the rated duty ratio is 50%, and the load range is 20+ -50 j omega-80+ -50 j omega. The wide-range impedance can be mapped into an ideal area through reasonable parameter design, the passive elements in the system are radio frequency inductors and capacitors, the inductors are formed by winding copper strips with the thickness of 3x0.15mm, the quality factor of the inductors can be remarkably improved at the frequency of megahertz, and the overall efficiency of the inverter is improved. The component parameters of the main circuit can be determined from the nominal operating conditions, the specific parameters being shown in table 1.
Table 1 high frequency inversion system parameters
Figure BDA0004156731280000091
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other embodiments.

Claims (10)

1. The parallel inversion system is characterized by comprising a first inversion unit (1), a second inversion unit (2), a first impedance matching network (3) and a second impedance matching network (4);
the voltage input end of the first inversion unit (1) is used for being electrically connected with the voltage output end of the first adjustable direct current power supply; the voltage output end of the first inversion unit (1) is electrically connected with the voltage input end of the first impedance matching network (3) to form a first impedance compression branch;
the voltage input end of the second inversion unit (2) is used for being electrically connected with the voltage output end of the second adjustable direct current power supply; the voltage output end of the second inversion unit (2) is electrically connected with the voltage input end of the second impedance matching network (4) to form a second impedance compression branch;
the current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used for being electrically connected with the current input end of the load (5); -said load (5) comprises therein a varying capacitive and/or inductive component;
the first impedance compression branch is used for compressing the variable load impedance z Load Compressed to a first impedance compression branch impedance interval z U The method comprises the steps of carrying out a first treatment on the surface of the The first impedance compression branch impedance interval z U The coordinates on the rectangular impedance coordinate system are (R, X), R E [0,10 ]]，X∈[8,16]The method comprises the steps of carrying out a first treatment on the surface of the And the first impedance compression branch impedance interval z U The value of the center point of (2) is denoted as z GoalU ；
The second impedance compression branch is used for compressing the variable load impedance z Load Compressed to a second impedance compression branch impedance interval z L The method comprises the steps of carrying out a first treatment on the surface of the The impedance section z of the second impedance compression branch L The coordinates on the rectangular impedance coordinate system are (R ', X '), R ' E [0,10 ]]，X’∈[-8,-16]The method comprises the steps of carrying out a first treatment on the surface of the And the second impedance compression branch impedance interval z L The value of the center point of (2) is denoted as z GoalL ；
The first impedance matching network (3) is used for matching z GoalU Matching to an ideal impedance point of the first inversion unit (1);
the second impedance matching network (4) is used for matching z GoalL Matching to an ideal impedance point of the second inversion unit (2);
and the ideal impedance point of the first inversion unit (1) is the same as the ideal impedance point of the second inversion unit (2).
2. Parallel inverter system according to claim 1, characterized in that the first inverter unit (1) comprises a capacitor C INU Inductance L FU Switching device S U Capacitance C FU Inductance L RU And capacitor C RU ；
The positive electrode of the first adjustable DC power supply is simultaneously connected with the capacitor C INU And inductance L FU Is electrically connected to one end of the first wire;
inductance L FU At the same time with the other end of the switching device S U Source, capacitance C of (2) FU And inductance L RU Is electrically connected to one end of the first wire; inductance L RU And the other end of (C) and the capacitor C RU Is electrically connected to one end of the first wire; capacitor C RU The other end of the first inverter unit (1) is used as a voltage output end of the first inverter unit;
negative electrode of first adjustable DC power supply and capacitor C INU Is a switching device S U Drain of (C) and capacitance C FU The other ends of the two electrodes are grounded;
the second inversion unit (2) comprises a capacitor C INL Inductance L FL Switching device S L Capacitance C FL Inductance L RL And capacitor C RL ；
The positive electrode of the second adjustable DC power supply is simultaneously connected with the capacitor C INL And inductance L FL Is electrically connected to one end of the first wire;
inductance L FL At the same time with the other end of the switching device S L Source, capacitance C of (2) FL And inductance L RL Is electrically connected to one end of the first wire; inductance L RL And the other end of (C) and the capacitor C RL Is electrically connected to one end of the first wire; capacitor C RL The other end of the first inverter unit (2) is used as a voltage output end of the second inverter unit;
negative electrode of second adjustable DC power supply and capacitor C INL Is a switching device S L Drain of (C) and capacitance C FL The other ends of the two are grounded.
3. The parallel inverter system of claim 2, wherein the first impedance matching network (3) and the second impedance matching network (4) are both T-type impedance matching networks;
the first impedance matching network (3) comprises an inductance L U1 Capacitance C U2 And inductance L U3 ；
Inductance L U1 One end of (2) and a capacitor C RU Is electrically connected with the other end of the first part;
inductance L U1 At the same time with the capacitor C U2 And inductance L U3 Is electrically connected to one end of the first wire;
capacitor C U2 The other end of the power supply is electrically connected with a load (5); inductance L U3 The other end of the first electrode is grounded;
the second impedance matching network (4) comprises an inductance L L1 Inductance L L2 And inductance L L3 ；
Inductance L L1 One end of (2) and a capacitor C RL Is electrically connected with the other end of the first part;
inductance L L1 At the same time with the inductance L L2 And inductance L L3 Is electrically connected to one end of the first wire;
inductance L L2 The other end of the power supply is electrically connected with a load (5); inductance L L3 The other end of which is grounded.
4. Impedance compression method of parallel inverter system, characterized in that based on one of claims 1-3, the specific steps are as follows:
step one, the variable load impedance z Load Compressing the first impedance compression branch impedance interval z U And a second impedance compression branch impedance interval z L ；；
Step two, Z is taken GoalU And z GoalL Is matched with ideal impedance points of the first inversion unit (1) and the second inversion unit (2) respectively.
5. The method of impedance compression of a parallel inverter system of claim 4, wherein step one is as follows:
step one, obtaining z through simulation on an impedance rectangular coordinate system GoalU And z GoalL The first impedance compression branch impedance section z U At z GoalU In the (R, X) region as the center point, the second impedance compression branch impedance section z L At z GoalL In the region of (R ', X') which is the center,and obtain the impedance interval z of the second impedance compression branch L And the first impedance compression branch impedance interval z U Corresponding relation of (3);
step two, the load impedance z is adjusted by adjusting the current amplitude and the current phase of the first impedance compression branch and the second impedance compression branch Load Matching to the impedance section z of the first impedance compression branch U And a second impedance compression branch impedance interval z L Where it is located.
6. The method of impedance compression of a parallel inverter system according to claim 5, wherein in step one, the impedance z of the second impedance compression branch is obtained by the following formula L And the first impedance compression branch impedance interval z U Corresponding relation of (3):
Figure FDA0004156731270000031
wherein z is Load For load impedance, z L Compressing the impedance of the branch for a second impedance, Z Load For the magnitude of the load impedance,
Figure FDA0004156731270000036
k is the scaling factor of the impedance range, k=0.4-0.5, which is the phase of the load impedance; i is an imaginary unit.
7. The method of impedance compression of a parallel inverter system of claim 6, wherein in step two, the method comprises the following steps:
Figure FDA0004156731270000032
wherein I is U A current amplitude of the output current of the first impedance compression branch I L Outputting a current magnitude of the current for the second impedance compression branch;
Figure FDA0004156731270000033
the current phase of the output current for the first impedance compression branch,/->
Figure FDA0004156731270000034
The second impedance compresses the current phase of the output current of the branch.
8. The method of impedance compression of a parallel inverter system of claim 7, wherein step two is specifically as follows:
step two, according to z GoalU 、z GoalL And the value z of the ideal impedance point Inv Obtaining impedance parameters of the first impedance matching network (3) and the second impedance matching network (4);
step two, calculating to obtain the input direct-current voltage V of the first inversion unit (1) INU And the phase of the switch drive signal
Figure FDA0004156731270000037
The input DC voltage V of the second inverter unit (2) INL And phase of the switch drive signal->
Figure FDA0004156731270000038
And an input voltage v of the first impedance matching network (3) U And an input voltage v of the second impedance matching network (4) L ；
And through the input DC voltage V of the first inversion unit (1) INU And the phase of the switch drive signal
Figure FDA0004156731270000039
Controlling the first impedance matching network (3) to change z GoalU Matching to the ideal impedance point of the first inverter unit (1), and the input DC voltage V through the second inverter unit (2) INL And phase of the switch drive signal->
Figure FDA00041567312700000310
Controlling a second impedance matchA distribution network (4) for distributing z GoalL Matching to the ideal impedance point of the second inversion unit (2).
9. The method of impedance compression of a parallel inverter system according to claim 8, wherein in step two, the impedance parameters of the first impedance matching network (3) and the second impedance matching network (4) are obtained by:
Figure FDA0004156731270000035
wherein, R is GoalU ，X GoalU Z respectively GoalU Resistance and reactance components of (a); r is R GoalL ，X GoalL Z respectively GoalL Resistance and reactance components of (a); r is R inv ，X inv The values z of the ideal impedance points respectively Inv Resistance and reactance components of (a); z CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 Respectively the inductance L U1 Capacitance C U2 Inductance L U3 Inductance L L1 Inductance L L2 And inductance L L3 Impedance value.
10. The method for compressing the impedance of the parallel inverter system according to claim 9, wherein in the second step, the input dc voltage V of the first inverter unit (1) is obtained by the following formula INU And the phase of the switch drive signal
Figure FDA0004156731270000043
And the input DC voltage V of the second inverter unit (2) INL And phase of the switch drive signal->
Figure FDA0004156731270000044
Figure FDA0004156731270000041
Wherein P is Load For the desired output power, R Load Is a load resistance component;
the input voltage v of the first impedance matching network (3) is obtained by U And an input voltage v of the second impedance matching network (4) L ：
Figure FDA0004156731270000042
CN202310336959.1A 2023-03-31 2023-03-31 Parallel inverter system and impedance compression method thereof Pending CN116345933A (en)

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