CN116344539A - 具有用来引起压缩沟道应变的栅极插塞的集成电路 - Google Patents
具有用来引起压缩沟道应变的栅极插塞的集成电路 Download PDFInfo
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Abstract
本发明的主题是“具有用来引起压缩沟道应变的栅极插塞的集成电路”。公开的实施例针对先进的集成电路结构制作,并且特别地,针对使用栅极插塞来引起压缩沟道应变的集成电路。可以描述或者请求保护其他实施例。
Description
技术领域
公开的实施例在先进的集成电路结构制作的领域中,并且特别地,在使用栅极插塞来引起压缩沟道应变的集成电路的领域中。
背景技术
在过去的几十年里,集成电路中的特征的按比例缩放一直是日益增长的半导体行业背后的驱动力。按比例缩小到越来越小的特征使半导体芯片的有限的不动产(realestate)上的功能单元的增加的密度成为可能。例如,缩小晶体管尺寸考虑在芯片上结合增加数量的存储器或逻辑器件,有助于具有增加的容量的产品的制作。然而,对于愈来愈多的容量的驱动并不是没有问题。优化每个器件的性能的必要性变得日益重要。本公开的实施例解决了这些和其他问题。
附图说明
图1A和图1B是根据本公开的实施例的集成电路(IC)结构的横截面视图。
图2说明了根据公开的各种实施例的计算装置的示例。
图3说明了包括公开的一个或多个实施例的中介层(interposer)的示例。
具体实施方式
在一些实施例中,描述了使用栅极插塞来引起压缩沟道应变的集成电路。在下列描述中,阐述了诸如具体集成和材料体系的许多具体细节,以便提供对本公开的实施例的透彻理解。对于本领域技术人员来说将会显而易见的是,可以在没有这些具体细节的情况下实施本公开的实施例。在其他实例中,没有详细描述诸如集成电路设计布局的公知特征以便于不会不必要地模糊本公开的实施例。此外,要意识到,附图中示出的各种实施例是说明性的代表并且不必按比例绘制附图中示出的各种实施例。
下列详细描述本质上仅是说明性的并且不是用来限制主题的实施例或者这样的实施例的应用和使用的。如本文中所使用的,词“示范性的”指“用作示例、实例或说明”。本文中作为示范描述的任何实现不一定要被解释为比其他实现更优选或有利。此外,没有要被前述的技术领域、背景技术、发明内容或下面的具体实施方式中呈现的任何明示或暗示的理论约束的意图。
本说明书包括提及“一个实施例”或“实施例”。短语“在一个实施例中”或“在实施例中”的出现不一定指相同的实施例。可以以与本公开一致的任何合适的方式来组合特定的特征、结构或特性。
术语。下列段落为本公开(包括所附的权利要求)中发现的术语提供了定义或上下文:
“包括”。这个术语是开放式的。如在所附的权利要求中所使用的,这个术语不排除附加的结构或操作。
“被配置成”。各种单元或部件可以被描述或被要求为“被配置成”执行任务或多个任务。在这样的上下文中,“被配置成”被使用来通过指示单元或部件包括在操作期间执行那些任务或多个任务的结构来暗示结构。像这样,即使当指定的单元或部件不是当前操作的(例如不是开着的或活动的)时,单元或部件也可以被说成是被配置成执行任务。陈述单元或电路或部件“被配置成”执行一个或多个任务明确地不是用来为那个单元或部件援引美国法典第35编第112节第六款(35 U.S.C. §112,sixth paragraph)。
“第一”、“第二”等。如本文中所使用的,这些术语被用作名词前面的标签并且不暗示任何类型的排序(例如空间的、时间的、逻辑的等)。
“耦合的”-下列描述指元件或节点或特征被“耦合”在一起。如本文中所使用的,除非另有明确说明,否则“耦合的”指一个元件或节点或特征被直接地或间接地结合到另一个元件或节点或特征(或者直接地或间接地与另一个元件或节点或特征连通),并且不一定以机械方式。
另外,也可以在下列描述中仅仅出于参考的目的来使用某些术语并且某些术语因此不会规定为是限制的。例如,诸如“上部的”、“下部的”、“在……上面”和“在……下面”的术语指所参考的附图中的方向。诸如“前”、“后”“后部”、“侧”、“外侧”和“内侧”的术语描述了在通过参考描述讨论中的部件的文本和相关联的附图会弄清楚的一致但任意的参照系内的部件的部分的取向或位置或者两者。这样的术语可以包括上面具体提及的词、其派生词以及类似含义的词。
“抑制”-如本文中所使用的,抑制被用来描述减少或最小化效应。当部件或特征被描述为抑制动作、运动或条件时,它可完全防止结果或成果或未来状态。另外,“抑制”还可以指减少或减轻可能以其他方式发生的成果、性能或效应。因此,当部件、元件或特征被称为抑制结果或状态时,它不需要完全防止或消除结果或状态。
本文中描述的实施例可以针对前道工序(FEOL)半导体处理和结构。FEOL是集成电路(IC)制作的第一部分,其中在半导体衬底或层中图案化各个器件(例如晶体管、电容器、电阻器等)。FEOL通常覆盖直到(但不包括)金属互连层的沉积的每件事物。在最后的FEOL操作之后,结果通常是具有隔离的晶体管的晶片(例如没有任何导线)。
本文中描述的实施例可以针对后道工序(BEOL)半导体处理和结构。BEOL是IC制作的第二部分,其中各个器件(例如晶体管、电容器、电阻器等)与晶片上的布线互连,例如金属化层或多个金属化层。BEOL包括触点、绝缘层(电介质)、金属层和用于芯片到封装连接的接合部位。在制作阶段的BEOL部分中,形成触点(焊盘)、互连导线、通孔和介电结构。对于现代IC工艺,可以在BEOL中添加多于10个金属层。
下面描述的实施例可适用于FEOL处理和结构、BEOL处理和结构、或者FEOL和BEOL处理和结构两者。特别地,虽然可以使用FEOL处理场景来说明示范性的处理方案,但是这样的方法也可适用于BEOL处理。同样地,虽然可以使用BEOL处理场景来说明示范性的处理方案,但是这样的方法也可适用于FEOL处理。
可以实现一个或多个实施例以实现3D铁电RAM(FRAM、FeRAM或F-RAM)从而潜在地增加未来技术节点的SoC中的后端逻辑加存储器的单片集成。为了提供上下文,FRAM是在构建上类似于DRAM的随机存取存储器,但是使用铁电层而不是介电层来实现非易失性。按照惯例,FRAM和DRAM两者是一个晶体管(1T)/一个电容器(1C)单元阵列,其中每个单元包括在前端耦合到单个电容器的存取晶体管。电容器可以被耦合到半导体后端中的叠层中更高的位线(COB)。
如上面所介绍的,集成电路器件面临的一个性能问题与由于有限的沟道迁移率造成的不足的晶体管性能有关。如下面所描述的,本公开的实施例通过提供包括压缩薄膜以在有源沟道中施加压缩应变的鳍修整隔离(FTI)插塞(也被称为栅极插塞)来帮助提高这样的沟道迁移率。
除了别的以外,本公开的实施例还帮助提高沟道迁移率并且改进晶体管性能。还可以分别针对NMOS和PMOS来图案化公开的实施例以使它们与CMOS工艺兼容。公开的实施例还适用于任何非平面晶体管,诸如鳍式场效应晶体管(FinFET)、叉片式晶体管或全环绕栅极(GAA)晶体管。
图1A和图1B是根据各种实施例的IC结构的横截面。图1A说明了GAA或叉片式结构的示例,同时图1B说明了FinFET结构的示例。还可以和任何其他合适的非平面晶体管配置一起使用本公开的实施例。
在图1A中示出的示例中,器件100包括衬底层118以及耦合到衬底层118的一对外延层109。一对鳍修整隔离(FTI)插塞114被耦合到衬底层118并且包括压缩薄膜。栅极间隔物层104被布置在相应的FTI插塞114和它们的相应的相邻外延层109之间。
在图1A(说明GAA或叉片式示例)中,硅沟道112被布置在两个外延层109之间并且被耦合到功函数金属(WFM)102,所述功函数金属(WFM)102又被耦合到高k介电材料110。在图1B(说明FinFET示例)中,沟道130被布置在两个外延层109之间。外延层109被耦合到接触金属区108和介电层106。在一些实施例中,高k介电材料110包括:HfO2、ZrO2或TiO2。
在图1A和1B两者中,FTI插塞114的压缩薄膜适于施加从相应的FTI插塞114向外到它们的相应的沟道112、130的压缩应变116。FTI插塞114可以包括任何合适的压缩材料或者材料的组合。例如,在一些实施例中,压缩薄膜包括:SiGe、SiO、SiN或AlN。
在一些实施例中,在沟道112、130中测量的压缩应变将会与FTI插塞114和沟道112、130之间的距离负相关。FTI插塞离沟道越近,它的在沟道中施加压缩应变的能力就越高。
在一些实施例中,在PMOS器件附近的FTI插塞中的薄膜性质和在NMOS器件附近的另一个FTI插塞中的薄膜性质可以是不同的。例如,可以利用如SiGe、SiO、SiN、AlN的相对压缩的材料来调整PMOS-FTI插塞,并且NMOS-FTI可以由拉伸薄膜组成。
可以在诸如半导体衬底的衬底上形成或者执行发明的实施例的实现。在一个实现中,半导体衬底可以是使用块状硅或绝缘体上硅子结构形成的晶体衬底。在其他实现中,可以使用备选材料来形成半导体衬底,所述备选材料可以或者可以不与硅结合,所述备选材料包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、砷化铟镓、锑化镓、或者III-V族或IV族材料的其他组合。虽然在这里描述了可以形成衬底的材料的几个示例,但是可以用作在其上可以建造半导体器件的基础的任何材料属于本发明的精神和范围。
可以在衬底上制作诸如金属氧化物半导体场效应晶体管(MOSFET或者仅仅是MOS晶体管)的多个晶体管。在发明的各种实现中,MOS晶体管可以是平面晶体管、非平面晶体管或者两者的组合。非平面晶体管包括诸如双栅极晶体管和三栅极晶体管的FinFET晶体管以及诸如纳米带和纳米线晶体管的环绕或全环绕栅极晶体管。虽然本文中描述的实现可以仅说明平面晶体管,但是应当注意,还可以使用非平面晶体管来实现发明。
每个MOS晶体管包括由至少两层形成的栅极叠层:栅极介电层和栅电极层。栅极介电层可以包括一层或者层的叠层。一个或多个层可以包括氧化硅、二氧化硅(SiO2)和/或高k介电材料。高k介电材料可以包括诸如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌的元素。可以在栅极介电层中使用的高k材料的示例包括但不限于氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。在一些实施例中,当使用高k材料时,可以在栅极介电层上执行退火工艺以提高它的质量。
在栅极介电层上形成栅电极层,并且取决于晶体管将是PMOS晶体管还是NMOS晶体管,栅电极层可以由至少一种P型功函数金属或N型功函数金属组成。在一些实现中,栅电极层可以由两个或多于两个金属层的叠层组成,其中一个或多个金属层是功函数金属层并且至少一个金属层是填充金属层。
对于PMOS晶体管,可被用于栅电极的金属包括但不限于钌、钯、铂、钴、镍和例如氧化钌的导电金属氧化物。P型金属层将使能形成具有在大约4.9eV和大约5.2eV之间的功函数的PMOS栅电极。对于NMOS晶体管,可被用于栅电极的金属包括但不限于铪、锆、钛、钽、铝、这些金属的合金以及诸如碳化铪、碳化锆、碳化钛、碳化钽和碳化铝的这些金属的碳化物。N型金属层将使能形成具有在大约3.9eV和大约4.2eV之间的功函数的NMOS栅电极。
在一些实现中,栅电极可以由“U”形结构组成,所述“U”形结构包括与衬底的表面基本平行的底部部分以及与衬底的顶面基本垂直的两个侧壁部分。在另一实现中,形成栅电极的金属层中的至少一个金属层可以仅仅是与衬底的顶面基本平行并且不包括与衬底的顶面基本垂直的侧壁部分的平面层。在发明的另外的实现中,栅电极可以由U形结构和平面的非U形结构的组合组成。例如,栅电极可以由在一个或多个平面的非U形层的顶上形成的一个或多个U形金属层组成。
在发明的一些实现中,可以在栅极叠层的相对侧上形成给栅极叠层装托架的一对侧壁间隔物。侧壁间隔物可以由诸如氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅和氧氮化硅的材料形成。用于形成侧壁间隔物的工艺在本领域中是公知的并且通常包括沉积和蚀刻工艺步骤。在备选的实现中,可以使用多个间隔物对,例如,可以在栅极叠层的相对侧上形成两对、三对或者四对侧壁间隔物。
如本领域公知的,在邻近每个MOS晶体管的栅极叠层的衬底内形成源极区和漏极区。通常使用或者注入/扩散工艺或者蚀刻/沉积工艺来形成源极区和漏极区。在前者的工艺中,可以将诸如硼、铝、锑、磷或砷的掺杂物离子注入衬底以形成源极区和漏极区。激活掺杂物并且促使它们进一步扩散进衬底的退火工艺通常接着离子注入工艺发生。在后者的工艺中,可以首先蚀刻衬底以在源极区和漏极区的位置处形成凹槽。然后可以执行外延沉积工艺以利用被用来制作源极区和漏极区的材料来填充凹槽。在一些实现中,可以使用诸如硅锗或碳化硅的硅合金来制作源极区和漏极区。在一些实现中,可以利用诸如硼、砷或磷的掺杂物原位掺杂外延沉积的硅合金。在另外的实施例中,可以使用诸如锗或III-V族材料或合金的一种或多种备选半导体材料来形成源极区和漏极区。并且在另外的实施例中,可以使用金属和/或金属合金的一个或多个层来形成源极区和漏极区。
在MOS晶体管的上方沉积一种或多种层间电介质(ILD)。可以使用因它们的在集成电路结构中的适用性而已知的介电材料来形成ILD层,诸如低k介电材料。可以被使用的介电材料的示例包括但不限于二氧化硅(SiO2)、碳掺杂氧化物(CDO)、氮化硅、诸如全氟环丁烷或聚四氟乙烯的有机聚合物、氟硅酸盐玻璃(FSG)、以及诸如倍半硅氧烷、硅氧烷或有机硅酸盐玻璃的有机硅酸盐。ILD层可以包括孔或气隙以进一步减小它们的介电常数。
图2说明了根据发明的一个实现的计算装置200。计算装置200容纳板202。板202可以包括多个部件,包括但不限于处理器204和至少一个通信芯片206。处理器204被物理且电耦合到板202。在一些实现中,至少一个通信芯片206也被物理且电耦合到板202。在另外的实现中,通信芯片206是处理器204的一部分。
取决于它的应用,计算装置200可以包括可以或可以不被物理且电耦合到板202的其他部件。这些其他部件包括但不限于易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、指南针、加速度计、陀螺仪、扬声器、相机和大容量存储装置(诸如硬盘驱动器、光盘(CD)、数字多功能光盘(DVD)等等)。
通信芯片206使能用于到计算装置200的和来自计算装置200的数据的传输的无线通信。术语“无线”和其派生词可以被用来描述可以通过使用通过非固体介质的调制电磁辐射来传递数据的电路、装置、系统、方法、技术、通信信道等。术语并不暗示相关联的装置不包含任何导线,虽然在一些实施例中它们可能不包含任何导线。通信芯片206可以实现多个无线标准或协议中的任何无线标准或协议,包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物以及被指定为3G、4G、5G及以上的任何其他无线协议。计算装置200可以包括多个通信芯片206。例如,第一通信芯片206可以专用于诸如Wi-Fi和蓝牙的更短程无线通信,并且第二通信芯片206可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等等的更长程无线通信。
计算装置200的处理器204包括封装在处理器204内的集成电路管芯。在发明的一些实现中,处理器的集成电路管芯包括诸如根据发明的实现建造的MOS-FET晶体管的一个或多个器件。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其他电子数据的任何装置或者装置的一部分。
通信芯片206还包括封装在通信芯片206内的集成电路管芯。根据发明的另一实现,通信芯片的集成电路管芯包括诸如根据发明的实现建造的MOS-FET晶体管的一个或多个器件。
在另外的实现中,容纳在计算装置200内的另一个部件可以包含集成电路管芯,所述集成电路管芯包括诸如根据发明的实现建造的MOS-FET晶体管的一个或多个器件。
在各种实现中,计算装置200可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器或数字视频记录仪。在另外的实现中,计算装置200可以是处理数据的任何其他电子装置。
图3说明了包括发明的一个或多个实施例的中介层(interposer)300。中介层300是用来将第一衬底302桥接到第二衬底304的居间衬底。第一衬底302可以是例如集成电路管芯。第二衬底304可以是例如存储器模块、计算机主板或另一个集成电路管芯。通常,中介层300的目的是将连接扩展到更宽的间距或者将连接重新布线到不同的连接。例如,中介层300可以将集成电路管芯耦合到球栅阵列(BGA)306,所述球栅阵列(BGA)306随后可以被耦合到第二衬底304。在一些实施例中,第一衬底和第二衬底302/304被附接到中介层300的相对侧。在其他实施例中,第一衬底和第二衬底302/304被附接到中介层300的相同侧。并且在另外的实施例中,通过中介层300的方式来互连三个或多于三个衬底。
中介层300可以由环氧树脂、玻璃纤维增强环氧树脂、陶瓷材料或诸如聚酰亚胺的聚合物材料形成。在另外的实现中,中介层300可以由备选的刚性或柔性材料形成,所述备选的刚性或柔性材料可以包括诸如硅、锗以及其他III-V族和IV族材料的、上面描述的供半导体衬底之用的相同材料。
中介层300可以包括金属互连308和通孔310,包括但不限于硅穿孔(TSV)312。中介层300可以进一步包括嵌入式器件314,所述嵌入式器件314包括无源器件和有源器件两者。这样的器件包括但不限于电容器、去耦电容器、电阻器、电感器、保险丝、二极管、变压器、传感器和静电放电(ESD)器件。还可以在中介层300上形成诸如射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件的更复杂的器件。根据发明的实施例,本文中公开的设备或者工艺可以被用在中介层300的制作中。
虽然上面已经描述了具体实施例,但是这些实施例不是用来限制本公开的范围的,即使其中仅关于特定特征描述了单个实施例。除非另有说明,公开中提供的特征的示例规定为是说明性的而非限制性的。上面的描述用来覆盖如对于受益于本公开的本领域技术人员来说将会是显而易见的这样的备选方案、修改和等效物。
本公开的范围包括本文中(或者明确地或者隐含地)公开的任何特征或者特征的组合或者其任何概括,无论其是否缓解了本文中解决的问题中的任何问题或所有问题。因此,在本申请(或向其要求优先权的申请)的审查期间,可以将新的权利要求明确表达为特征的任何这样的组合。特别地,参考所附的权利要求,可以将来自从属权利要求的特征与独立权利要求的特征组合,并且可以以任何适当的方式而不仅仅是以所附的权利要求中列举的特定组合来组合来自相应独立权利要求的特征。
下列示例属于另外的实施例。可以将不同实施例的各种特征与所包括的一些特征以及所排除的其他特征以不同的方式进行组合以适合各种各样不同的应用。
示例实施例1包括一种集成电路结构,所述集成电路结构包括:衬底层;耦合到衬底层的外延层;包括压缩薄膜的鳍修整隔离(FTI)插塞;以及FTI插塞和外延层之间的栅极间隔物层。
示例实施例2包括示例实施例1或者本文中别的示例的集成电路结构,其中FTI插塞的压缩薄膜要施加从FTI插塞向外的压缩应变。
示例实施例3包括示例实施例1或者本文中别的示例的集成电路结构,其中压缩薄膜包括:SiGe、SiO、SiN或AlN。
示例实施例4包括示例实施例1或者本文中别的示例的集成电路结构,其中集成电路结构包括非平面晶体管。
示例实施例5包括示例实施例4或者本文中别的示例的集成电路结构,其中非平面晶体管是鳍式场效应晶体管(FinFET)、叉片式晶体管或全环绕栅极(GAA)晶体管。
示例实施例6包括示例实施例5或者本文中别的示例的集成电路结构,其中集成电路结构进一步包括耦合到外延层的硅沟道。
示例实施例7包括示例实施例6或者本文中别的示例的集成电路结构,其中非平面晶体管是叉片式晶体管或GAA晶体管,并且其中集成电路结构进一步包括耦合到硅沟道的功函数金属。
示例实施例8包括示例实施例7或者本文中别的示例的集成电路结构,进一步包括耦合到功函数金属的高k介电材料。
示例实施例9包括示例实施例8或者本文中别的示例的集成电路结构,其中高k介电材料包括:HfO2、ZrO2或者TiO2。
示例实施例10包括一种集成电路结构,所述集成电路结构包括:衬底层;耦合到衬底层的第一外延层;耦合到衬底层的第二外延层;包括压缩薄膜的第一鳍修整隔离(FTI)插塞;包括压缩薄膜的第二FTI插塞;以及第一外延层和第二外延层之间的硅沟道,其中第一外延层在第一FTI插塞和硅沟道之间,并且其中第二外延层在第二FTI插塞和硅沟道之间。
示例实施例11包括示例实施例10或者本文中别的示例的集成电路结构,其中第一FTI插塞和第二FTI插塞的压缩薄膜要施加从相应的FTI插塞向外的相应压缩应变。
示例实施例12包括示例实施例10或者本文中别的示例的集成电路结构,其中压缩薄膜包括:SiGe、SiO、SiN或AlN。
示例实施例13包括示例实施例10或者本文中别的示例的集成电路结构,其中集成电路结构包括非平面晶体管,所述非平面晶体管是鳍式场效应晶体管(FinFET)、叉片式晶体管或全环绕栅极(GAA)晶体管。
示例实施例14包括示例实施例13或者本文中别的示例的集成电路结构,其中非平面晶体管是GAA或叉片式晶体管,并且其中集成电路结构进一步包括耦合到硅沟道的功函数金属。
示例实施例15包括示例实施例14或者本文中别的示例的集成电路结构,进一步包括耦合到功函数金属的高k介电材料。
示例实施例16包括示例实施例15或者本文中别的示例的集成电路结构,其中高k介电材料包括:HfO2、ZrO2或者TiO2。
示例实施例17包括一种计算装置,所述计算装置包括:板;以及耦合到板的部件,部件包括集成电路结构,所述集成电路结构包括:衬底层;耦合到衬底层的外延层;包括压缩薄膜的鳍修整隔离(FTI)插塞;以及FTI插塞和外延层之间的栅极间隔物层。
示例实施例18包括了示例实施例17或者本文中别的示例的计算装置,进一步包括:耦合到板的处理器、耦合到板的通信芯片或者耦合到板的相机。
示例实施例19包括一种计算装置,所述计算装置包括:板;以及耦合到板的部件,部件包括集成电路结构,所述集成电路结构包括:衬底层;耦合到衬底层的第一外延层;耦合到衬底层的第二外延层;包括压缩薄膜的第一鳍修整隔离(FTI)插塞;包括压缩薄膜的第二FTI插塞;以及第一外延层和第二外延层之间的硅沟道,其中第一外延层在第一FTI插塞和硅沟道之间,并且其中第二外延层在第二FTI插塞和硅沟道之间。
示例实施例20包括示例实施例19或者本文中别的示例的计算装置,进一步包括:耦合到板的处理器、耦合到板的通信芯片或者耦合到板的相机。
Claims (20)
1.一种集成电路结构,所述集成电路结构包括:
衬底层;
耦合到所述衬底层的外延层;
包括压缩薄膜的鳍修整隔离(FTI)插塞;以及
所述FTI插塞和所述外延层之间的栅极间隔物层。
2.如权利要求1所述的集成电路结构,其中,所述FTI插塞的所述压缩薄膜要施加从所述FTI插塞向外的压缩应变。
3.如权利要求1所述的集成电路结构,其中,所述压缩薄膜包括:SiGe、SiO、SiN或AlN。
4.如权利要求1所述的集成电路结构,其中,所述集成电路结构包括非平面晶体管。
5.如权利要求4所述的集成电路结构,其中,所述非平面晶体管是鳍式场效应晶体管(FinFET)、叉片式晶体管或全环绕栅极(GAA)晶体管。
6.如权利要求5所述的集成电路结构,其中,所述集成电路结构进一步包括耦合到所述外延层的硅沟道。
7.如权利要求6所述的集成电路结构,其中,所述非平面晶体管是叉片式晶体管或GAA晶体管,并且其中,所述集成电路结构进一步包括耦合到所述硅沟道的功函数金属。
8.如权利要求7所述的集成电路结构,进一步包括耦合到所述功函数金属的高k介电材料。
9.如权利要求8所述的集成电路结构,其中,所述高k介电材料包括:HfO2、ZrO2或TiO2。
10.一种集成电路结构,所述集成电路结构包括:
衬底层;
耦合到所述衬底层的第一外延层;
耦合到所述衬底层的第二外延层;
包括压缩薄膜的第一鳍修整隔离(FTI)插塞;
包括所述压缩薄膜的第二FTI插塞;以及
所述第一外延层和所述第二外延层之间的硅沟道,其中,所述第一外延层在所述第一FTI插塞和所述硅沟道之间,并且其中,所述第二外延层在所述第二FTI插塞和所述硅沟道之间。
11.如权利要求10所述的集成电路结构,其中,所述第一FTI插塞和所述第二FTI插塞的所述压缩薄膜要施加从相应的FTI插塞向外的相应压缩应变。
12.如权利要求10所述的集成电路结构,其中,所述压缩薄膜包括:SiGe、SiO、SiN或AlN。
13.如权利要求10所述的集成电路结构,其中,所述集成电路结构包括非平面晶体管,所述非平面晶体管是鳍式场效应晶体管(FinFET)、叉片式晶体管或全环绕栅极(GAA)晶体管。
14.如权利要求13所述的集成电路结构,其中,所述非平面晶体管是GAA或叉片式晶体管,并且其中,所述集成电路结构进一步包括耦合到所述硅沟道的功函数金属。
15.如权利要求14所述的集成电路结构,进一步包括耦合到所述功函数金属的高k介电材料。
16.如权利要求15所述的集成电路结构,其中,所述高k介电材料包括:HfO2、ZrO2或TiO2。
17.一种计算装置,所述计算装置包括:
板;以及
耦合到所述板的部件,所述部件包括集成电路结构,所述集成电路结构包括:
衬底层;
耦合到所述衬底层的外延层;
包括压缩薄膜的鳍修整隔离(FTI)插塞;以及
所述FTI插塞和所述外延层之间的栅极间隔物层。
18.如权利要求17所述的计算装置,进一步包括:耦合到所述板的处理器、耦合到所述板的通信芯片或者耦合到所述板的相机。
19.一种计算装置,所述计算装置包括:
板;以及
耦合到所述板的部件,所述部件包括集成电路结构,所述集成电路结构包括:
衬底层;
耦合到所述衬底层的第一外延层;
耦合到所述衬底层的第二外延层;
包括压缩薄膜的第一鳍修整隔离(FTI)插塞;
包括所述压缩薄膜的第二FTI插塞;以及
所述第一外延层和所述第二外延层之间的硅沟道,其中,所述第一外延层在所述第一FTI插塞和所述硅沟道之间,并且其中,所述第二外延层在所述第二FTI插塞和所述硅沟道之间。
20.如权利要求19所述的计算装置,进一步包括:耦合到所述板的处理器、耦合到所述板的通信芯片或者耦合到所述板的相机。
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