CN116344292A - Vacuum device and preparation method thereof - Google Patents

Abstract

The invention provides a vacuum device and a preparation method thereof, wherein the method comprises the following steps: patterning the SOI substrate to form a nano narrow structure comprising a position with the smallest radial dimension; the gate dielectric layer wraps the nano narrow structure; and (3) carrying out hydrogen annealing to break the position with the smallest radial dimension to form a cross section structure for separating the top semiconductor layer into an anode region and a cathode region, and forming a closed cavity by the gate dielectric layer and the nano narrow structure to form a vacuum device. According to the invention, a nano narrow structure is arranged, and a section structure is formed by hydrogen annealing, so that a vacuum device with a nano-scale cathode-anode interval is obtained, and a larger field intensity and a larger conduction current are formed; meanwhile, a vacuum device with stronger control capability and full surrounding grid is realized by utilizing a nano cantilever structure; in addition, the cavity under the nano cantilever structure is only arranged on the top semiconductor layer, so that the interval between the anode and the cathode is further reduced; finally, the spacing between the anode and the cathode is further reduced by rounding and thinning the nano cantilever structure.

Description

Vacuum device and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a vacuum device and a preparation method thereof.

Background

As integrated circuit fabrication technology enters the 5 nm technology node, the feature size of semiconductor devices continues to shrink, having come to physical limits on size. Limited carrier mobility in silicon-based solid state devices is inherently affected by lattice scattering or impurities, and silicon-based devices are no longer able to meet the growing demands in terms of high frequency or fast response. The vacuum conditions enable ballistic transport of electrons without collisions or scattering, which results in faster carrier transport than is the case in solid state devices.

Nanoscale vacuum channel transistors since the first time proposed, mechanisms that have been used to implement nanoscale vacuum channel transistors include field emission, two-dimensional electron gas emission in schottky diodes, and low-dimensional carbon material thermionic emission, among others. Among them, vacuum transistor devices formed of low-dimensional materials, such as fully-surrounding gate nano-vacuum channel transistors, have received much attention due to their characteristics of high drive current and good radiation immunity.

Vacuum devices often require extremely short anode-cathode spacing to create a large field strength and to create a large on-current. However, it is difficult to manufacture a vacuum device having a nano-scale cathode-anode pitch by using a photolithography technique commonly used in the prior art, and thus a vacuum device capable of realizing a nano-scale source-drain pitch is desired.

It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art, and is not to be construed as merely illustrative of the background art section of the present application.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a vacuum device and a method for manufacturing the same, which are used for solving the problem that the distance between the cathode and the anode of the vacuum device cannot be reduced in the prior art.

In order to achieve the above object, the present invention provides a method for manufacturing a vacuum device, the method comprising:

providing an SOI substrate which sequentially comprises a substrate layer, an oxygen-buried layer and a top semiconductor layer from bottom to top; patterning the SOI substrate to form a nano narrow structure, wherein the nano narrow structure is provided with a position with a minimum radial dimension;

a gate dielectric layer is arranged on the exposed surface of the nano narrow structure and the surface of the top semiconductor layer, the nano narrow structure is wrapped by the gate dielectric layer, and a first gate electrode layer is arranged on the surface of the gate dielectric layer;

annealing the structure obtained in the way, namely, breaking the position with the smallest radial dimension of the nano narrow structure to form a cross-section structure, wherein the cross-section structure divides the top semiconductor layer into an anode region and a cathode region, and the gate dielectric layer and the nano narrow structure wrapping the cross-section structure form a closed cavity;

and arranging an anode contact electrode in the anode region, arranging a cathode contact electrode in the cathode region, and arranging a grid contact electrode in the first grid electrode layer so as to form the vacuum device.

Optionally, the radial dimension of the nano-narrow structure increases gradually from the cross-sectional structure to both sides thereof.

Optionally, the nano narrow structure is a nano cantilever structure, and a position with a minimum distance between the nano cantilever structure and the upper surface of the top semiconductor layer is a position with a minimum radial dimension; a cavity is arranged below the nano cantilever structure and is only arranged on the top semiconductor layer; or the cavity is only arranged on the oxygen burying layer; or the cavity is arranged on the top semiconductor layer and extends into the oxygen-buried layer.

Optionally, the nano narrow structure is a base on which a groove with a preset gradient is arranged on the top semiconductor layer, the bottom surface of the groove is higher than the bottom surface of the top semiconductor layer, and the position with the minimum distance between the bottom surface of the groove and the oxygen burying layer forms the position with the minimum radial dimension of the nano narrow structure.

Optionally, after the nano narrow structure is formed, annealing the nano narrow structure in a hydrogen-containing atmosphere to circularly thin the nano narrow structure, and reducing the radial dimension of the position with the minimum radial dimension.

Optionally, after forming the nano-narrow structure or/and after forming the cross-section structure, doping two sides of the position with the smallest radial dimension of the nano-narrow structure as the cathode region and the anode region.

Optionally, after the section structure is formed, removing the first gate electrode layer, and arranging a second gate electrode layer on the gate dielectric layer; or disposing the second gate electrode layer directly on the first gate electrode layer; the gate contact electrode is disposed on the second gate electrode layer.

Optionally, the annealing temperature at which the annealing in the hydrogen-containing atmosphere is performed to form the cross-sectional structure is 500-1300 ℃.

Optionally, after the vacuum device is formed, patterning the SOI substrate of the vacuum device, providing an insulating layer on the surface of the vacuum device, forming a back gate electrode in the insulating layer, and patterning the insulating layer to expose the back gate electrode, the gate contact electrode, the anode contact electrode and the cathode contact electrode, wherein the back gate electrode cooperates with the gate electrode layer to regulate and control the electrical characteristics of the vacuum device.

The invention also provides a vacuum device which is obtained by adopting any one of the preparation methods, and comprises an SOI substrate, wherein the SOI substrate comprises a substrate layer, a buried oxide layer and a top semiconductor layer;

the buried oxide layer is arranged on the substrate layer, and the top semiconductor layer is arranged on the buried oxide layer;

the top semiconductor layer is internally provided with a nanometer narrow structure, a section structure is arranged at the position with the smallest radial dimension of the nanometer narrow structure, the section structure divides the top semiconductor layer into a cathode area and an anode area, and the section structure is obtained through an annealing process in hydrogen atmosphere;

the periphery of the cross section structure is wrapped by a gate dielectric layer, the wrapped gate dielectric layer of the cross section structure and the nano narrow structure enable the cross section structure to form a closed cavity, and the surface of the gate dielectric layer is wrapped by a first gate electrode layer or/and a second gate electrode layer.

As described above, the vacuum device and the method for manufacturing the same of the present invention have the following beneficial effects:

according to the invention, a nano narrow structure is arranged, and a section structure is formed by hydrogen annealing, so that a vacuum device with a nano-scale cathode-anode interval is obtained, and a larger field intensity and a larger conduction current are formed;

the invention utilizes the nano cantilever structure to realize the vacuum device of the full-surrounding grid with stronger control capability;

the cavity under the nano cantilever structure is only arranged on the top semiconductor layer, so that the interval between the anode and the cathode is further reduced;

the invention further reduces the interval between the anode and the cathode by rounding and thinning the nano cantilever structure.

Drawings

Fig. 1 is a schematic top view showing a nano-cantilever structure formed in step 1 according to a first embodiment of the present invention.

Fig. 2 is a schematic front view showing a nano-cantilever structure formed in step 1 according to a first embodiment of the present invention.

Fig. 3 is a schematic diagram showing a cut-away view of a nano-cantilever structure formed in step 1 according to a first embodiment of the present invention.

Fig. 4 is a schematic top view showing a rounded nano-cantilever structure in an alternative example of step 1 in the first embodiment of the present invention.

Fig. 5 shows a schematic view of a front view of a rounded nano-cantilever structure according to an alternative example of step 1 in accordance with an embodiment of the present invention.

Fig. 6 shows a schematic view of a left-hand cut surface of the rounded nano-cantilever structure in an alternative example of step 1 in accordance with the first embodiment of the present invention.

Fig. 7 is a schematic top view showing the arrangement of the gate dielectric layer and the first gate electrode layer in step 2 according to the first embodiment of the present invention.

Fig. 8 is a schematic diagram showing a front view of the gate dielectric layer and the first gate electrode layer disposed in step 2 according to the first embodiment of the present invention.

Fig. 9 is a schematic diagram showing a left-hand section of the gate dielectric layer and the first gate electrode layer disposed in step 2 according to the first embodiment of the present invention.

Fig. 10 is a schematic top view showing a cross-sectional structure formed in step 3 according to the first embodiment of the present invention.

FIG. 11 is a schematic view showing a front view of a cross-sectional structure formed in step 3 according to the first embodiment of the present invention.

Fig. 12 is a schematic view showing a left-hand cut surface of the cross-sectional structure formed in step 3 in the first embodiment of the present invention.

Fig. 13 is a schematic top view showing the formation of the contact electrode in step 4 in the first embodiment of the present invention.

Fig. 14 is a schematic view showing a front view of the contact electrode formed in step 4 in the first embodiment of the present invention.

Fig. 15 is a schematic view showing a left-hand cut surface of the contact electrode formed in step 4 in the first embodiment of the present invention.

Fig. 16 is a schematic top view showing the formation of the groove in S1 in the second embodiment of the invention.

Fig. 17 is a schematic front view showing a groove formed in S1 in the second embodiment of the invention.

Fig. 18 is a schematic diagram showing a cut-away view of a groove formed in S1 in the second embodiment of the invention.

Fig. 19 shows a schematic view of a left-hand section of the rounded base in the alternative S1 in the second embodiment of the present invention.

Fig. 20 is a schematic top view showing the arrangement of the gate dielectric layer and the first gate electrode layer in S2 in the second embodiment of the present invention.

Fig. 21 is a schematic diagram showing a front view of a gate dielectric layer and a first gate electrode layer disposed in S2 in a second embodiment of the present invention.

Fig. 22 is a schematic view showing a left-hand section of the second embodiment S2 of the present invention where a gate dielectric layer and a first gate electrode layer are disposed.

Fig. 23 is a schematic top view showing a cross-sectional structure formed in S3 in the second embodiment of the invention.

Fig. 24 is a schematic view showing a front view of a cross-sectional structure formed in S3 in the second embodiment of the present invention.

Fig. 25 is a schematic view showing a left-hand section of the cross-sectional structure formed in S3 in the second embodiment of the present invention.

Fig. 26 is a schematic top view showing the formation of the contact electrode in S4 in the second embodiment of the invention.

Fig. 27 is a schematic view showing a front view of a contact electrode formed in S4 in the second embodiment of the present invention.

Fig. 28 is a schematic view showing a left-hand cut surface of the contact electrode formed in S4 in the second embodiment of the present invention.

Fig. 29 is a schematic top view showing an alternative example of S4 in the second embodiment of the present invention, where a back gate electrode is disposed.

Fig. 30 is a schematic view showing a front view of an alternative example of S4 in the second embodiment of the present invention, where a back gate electrode is disposed.

Fig. 31 is a schematic view showing a left-hand cut surface of an alternative example of S4 in the second embodiment of the present invention.

Description of element reference numerals

100. A substrate layer; 200. an oxygen burying layer; 300. a top semiconductor layer; 310. a nano cantilever structure; 321. a base; 322. a groove; 323. a cavity; 330. the radial dimension is the smallest; 340. a cross-sectional structure; 350. a closed cavity; 411. a cathode region; 412. a cathode contact electrode; 421. an anode region; 422. an anode contact electrode; 431. a gate dielectric layer; 432. a first gate electrode layer; 433. a second gate electrode layer; 434. a gate contact electrode; 435. a back gate electrode; 436. an insulating layer.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

As described in detail in the embodiments of the present invention, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.

In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Embodiment one:

as shown in fig. 1 to 15, the present invention provides a method for manufacturing a vacuum device, which includes:

step 1: providing an SOI substrate, wherein the SOI substrate comprises a substrate layer 100, an oxygen-buried layer 200 and a top semiconductor layer 300 from bottom to top in sequence; patterning the SOI substrate to form a nanoribbon structure having a radial minimum dimension 330; the nano narrow structure is a nano cantilever structure 310, a position with a minimum distance between the nano cantilever structure 310 and the upper surface of the top semiconductor layer 300 is a position 330 with a minimum radial dimension, and a cavity 323 is arranged below the nano cantilever structure 310;

step 2: a gate dielectric layer 431 is disposed on the exposed surface of the nano-scale narrow structure and the surface of the top semiconductor layer 300, the gate dielectric layer 431 wraps the nano-cantilever structure 310, and a first gate electrode layer 432 is disposed on the surface of the gate dielectric layer 431;

step 3: annealing the structure obtained in this way in a hydrogen-containing atmosphere to break the position 330 with the smallest radial dimension of the nano-cantilever structure 310, so as to form a cross-section structure 340, wherein the cross-section structure 340 separates the top semiconductor layer 300 into an anode region 421 and a cathode region 411, and the gate dielectric layer 431 wrapping the cross-section structure 340 and the nano-cantilever structure 310 form a closed cavity 350 in the cross-section structure 340;

step 4: an anode contact electrode 422 is disposed in the anode region 421, a cathode contact electrode 412 is disposed in the cathode region 411, and a gate contact electrode 434 is disposed in the first gate electrode layer 432, thereby forming a vacuum device.

The method for manufacturing a vacuum device according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the sequence of the method for manufacturing a vacuum device according to the present invention, and those skilled in the art may vary depending on the actual manufacturing steps.

Firstly, as shown in fig. 1 to 3, step 1 is performed, wherein fig. 2 is a front view cut along line AA 'in fig. 1, and fig. 3 is a left view cut along line BB' in fig. 1, providing an SOI substrate comprising, in order from bottom to top, a substrate layer 100, a buried oxide layer 200 and a top semiconductor layer 300; patterning the SOI substrate to form a nanoribbon structure having a radial minimum dimension 330; the nano narrow structure is a nano cantilever structure 310, a position with a minimum distance between the nano cantilever structure 310 and the upper surface of the top semiconductor layer 300 is a position 330 with a minimum radial dimension, and a cavity 323 is arranged below the nano cantilever structure 310.

The present invention sets the nano cantilever structure 310 to make the minimum radial dimension 330 be in nano dimension, so that the subsequent minimum cathode-anode distance can be formed, and the larger field intensity and current intensity of the vacuum device can be realized. Specifically, other structures may be used to realize a micro-sized nano narrow structure, where the nano cantilever structure 310 may realize a device with a full surrounding gate while realizing a smaller cathode-anode spacing, so as to obtain a high-performance device with a stronger gate control capability.

In one embodiment, the cavity 323 under the nano-cantilever structure 310 is provided only to the top semiconductor layer 300; or the cavity 323 is provided only in the buried oxide layer 200; or the cavity 323 is disposed in the top semiconductor layer 300 and extends into the buried oxide layer 200.

The invention further reduces the size of the nano-cantilever structure 310 by arranging the cavity 323 only on the top semiconductor layer 300, thereby further reducing the cathode-anode spacing of the vacuum device

In one embodiment, as shown in fig. 4-6, where fig. 5 is a front view taken along line AA 'in fig. 4, and fig. 6 is a left view taken along line BB' in fig. 4, after the nano-cantilever structure 310 is formed, the nano-cantilever structure 310 is annealed in a hydrogen-containing atmosphere to round and thin the nano-cantilever structure 310, and the radial dimension of the minimum radial dimension 330 is reduced.

According to the invention, the nano suspended beam structure 310 is annealed in the hydrogen-containing atmosphere to circularly thin the nano suspended beam structure 310, so that the cathode-anode distance of a vacuum device can be further reduced.

Then, as shown in fig. 7 to 9, step 2 is performed, where fig. 8 is a front view taken along line AA 'in fig. 7, fig. 9 is a left view taken along line BB' in fig. 7, a gate dielectric layer 431 is disposed on the exposed surface of the nano-scale structure and the surface of the top semiconductor layer 300, the gate dielectric layer 431 wraps the nano-cantilever structure 310, and a first gate electrode layer 432 is disposed on the surface of the gate dielectric layer 431.

Next, as shown in fig. 10 to 12, step 3 is performed, wherein fig. 11 is a front view taken along line AA 'in fig. 10, fig. 12 is a left view taken along line BB' in fig. 10, and the thus obtained structure is annealed in a hydrogen-containing atmosphere to break the radial dimension minimum 330 of the nano-cantilever structure 310 and form a cross-section structure 340, the cross-section structure 340 separates the top semiconductor layer 300 into an anode region 421 and a cathode region 411, and the gate dielectric layer 431 surrounding the cross-section structure 340 and the nano-cantilever structure 310 form a closed cavity 350 in the cross-section structure 340.

In one embodiment, the radial dimension of the nano-cantilever structure 310 increases gradually from the cross-sectional structure 340 to both sides thereof.

Specifically, the nano-cantilever structure 310 is formed by the previous process, so as to realize a form that the nano-cantilever structure 310 gradually increases from the minimum radial dimension 330 to two sides, and a radial dimension of a small dimension is obtained, so as to obtain a closed cavity 350 formed by a subsequent small-dimension cross-section structure 340, and the dimension is the cathode-anode spacing of the vacuum device.

In one embodiment, after forming the nano-cantilever structure 310 or/and after forming the cross-section structure 340, both sides of the radial dimension minimum 330 of the nano-cantilever structure 310 are doped as the cathode region 411 and the anode region 421.

In one embodiment, after the cross-section structure 340 is formed, the first gate electrode layer 432 is removed, and a second gate electrode layer 433 is disposed on the gate dielectric layer 431; or disposing the second gate electrode layer 433 directly on the first gate electrode layer 432; the gate contact electrode 434 is disposed on the second gate electrode layer 433.

Specifically, the material of the first gate electrode layer 432 is a material through which hydrogen easily permeates, and the material of the second gate electrode layer 433 is used to improve the performance of the vacuum device, such as protecting the vacuum degree of the closed cavity 350 and improving the electrical performance.

The present invention realizes that the hydrogen annealing process for forming the cross-section structure 340 is smoothly performed while ensuring excellent device performance after the annealing process is finished by replacing or adding the second gate electrode layer 433.

In one embodiment, after forming the first gate electrode layer 432 or/and the second gate electrode layer 433, a passivation layer may be disposed at a region other than the nano-cantilever structure 310.

In one embodiment, the annealing temperature at which the hydrogen-containing atmosphere is performed to form the cross-sectional structure 340 is 500-1300 ℃.

In one embodiment, the annealing time for forming the cross-section structure 340 may be 10 seconds to 1 hour, and specifically adjusted according to the material type, thickness, size of the minimum radial dimension 330, hydrogen concentration, and other parameters of the gate dielectric layer 431.

Finally, as shown in fig. 13-15, step 4 is performed, wherein fig. 14 is a front view taken along line AA 'in fig. 13, fig. 15 is a left view taken along line BB' in fig. 13, an anode contact electrode 422 is disposed in the anode region 421, a cathode contact electrode 412 is disposed in the cathode region 411, and a gate contact electrode 434 is disposed in the first gate electrode layer 432, so as to form a vacuum device.

Specifically, when the second gate electrode layer 433 is provided, the gate contact electrode 434 is provided on the second gate electrode layer 433.

The invention also provides a vacuum device which is obtained by adopting any one of the preparation methods, and comprises an SOI substrate, wherein the SOI substrate comprises a substrate layer 100, a buried oxide layer 200 and a top semiconductor layer 300;

the buried oxide layer 200 is disposed on the substrate layer 100, and the top semiconductor layer 300 is disposed on the buried oxide layer 200;

the top semiconductor layer 300 is provided with a nano cantilever structure 310, a position 330 with the smallest radial dimension of the nano cantilever structure 310 is provided with a cross-section structure 340, the cross-section structure 340 divides the top semiconductor layer 300 into a cathode region 411 and an anode region 421, and the cross-section structure 340 is obtained by an annealing process in a hydrogen atmosphere;

the periphery of the cross-section structure 340 is wrapped by a gate dielectric layer 431, the wrapped gate dielectric layer 431 of the cross-section structure 340 and the nano cantilever structure 310 form a closed cavity 350 in the cross-section structure 340, and the surface of the gate dielectric layer 431 is wrapped by a first gate electrode layer 432 or/and a second gate electrode layer 433.

Embodiment two:

the present invention provides a method for manufacturing a vacuum device, which is similar to other features of the method for manufacturing the first embodiment, and is not described herein, and the method for manufacturing the vacuum device is different from the method for manufacturing the vacuum device, and includes:

s1: providing an SOI substrate, wherein the SOI substrate comprises a substrate layer 100, an oxygen-buried layer 200 and a top semiconductor layer 300 from bottom to top in sequence; patterning the SOI substrate to form a nanoribbon structure having a radial minimum dimension 330; the nano-scale structure is a base 321 provided with a groove 322 with a preset gradient on the top semiconductor layer 300, the bottom surface of the groove 322 is higher than the bottom surface of the top semiconductor layer 300, and a position with the smallest distance between the bottom surface of the groove 322 and the oxygen-buried layer 200 forms a position 330 with the smallest radial dimension of the base 321;

s2: a gate dielectric layer 431 is disposed on the exposed surface of the nano-scale structure and the surface of the top semiconductor layer 300, the gate dielectric layer 431 wraps the base 321, and a first gate electrode layer 432 is disposed on the surface of the gate dielectric layer 431;

s3: annealing the structure obtained in this way in a hydrogen-containing atmosphere to break the position 330 with the smallest radial dimension of the base 321, so as to form a cross-section structure 340, wherein the cross-section structure 340 separates the top semiconductor layer 300 into an anode area 421 and a cathode area 411, and the gate dielectric layer 431 wrapping the cross-section structure 340 and the base 321 form a closed cavity 350 in the cross-section structure 340;

s4: an anode contact electrode 422 is disposed in the anode region 421, a cathode contact electrode 412 is disposed in the cathode region 411, and a gate contact electrode 434 is disposed in the first gate electrode layer 432, thereby forming a vacuum device.

The method for manufacturing a vacuum device according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the sequence of the method for manufacturing a vacuum device according to the present invention, and those skilled in the art may vary depending on the actual manufacturing steps.

First, as shown in fig. 16 to 18, S1 is performed, wherein fig. 17 is a front view cut along line AA 'in fig. 16, and fig. 18 is a left view cut along line BB' in fig. 16, providing an SOI substrate comprising, in order from bottom to top, a substrate layer 100, a buried oxide layer 200, and a top semiconductor layer 300; patterning the SOI substrate to form a nanoribbon structure having a radial minimum dimension 330; the nano-scale structure is a base 321 with a groove 322 with a preset gradient disposed on the top semiconductor layer 300, the bottom surface of the groove 322 is higher than the bottom surface of the top semiconductor layer 300, and a position with the smallest distance between the bottom surface of the groove 322 and the oxygen-buried layer 200 forms a position 330 with the smallest radial dimension of the nano-scale structure.

According to the invention, the base 321 is arranged, so that the position 330 with the smallest radial dimension is in a nano-scale dimension, and the subsequent extremely small cathode-anode distance can be formed, so that the larger field intensity and current intensity of the vacuum device are realized.

Specifically, the cross section of the groove 322 with the preset gradient may be in different forms such as V-shape, semi-circle shape, semi-ellipse shape, etc., so that the base 321 under the groove 322 may form a structure with a minimum radial dimension 330.

In one embodiment, as shown in fig. 19, fig. 19 is a left-hand cut view taken along line BB', after the base 321 is formed, the base 321 is annealed in a hydrogen-containing atmosphere to round and thin the base 321, and reduce the radial dimension of the minimum radial dimension 330.

Next, as shown in fig. 20 to 22, S2 is performed, where fig. 21 is a front view taken along line AA 'in fig. 20, fig. 22 is a left view taken along line BB' in fig. 20, a gate dielectric layer 431 is disposed on the exposed surface of the nano-scale structure and the surface of the top semiconductor layer 300, the gate dielectric layer 431 wraps the base 321, and a first gate electrode layer 432 is disposed on the surface of the gate dielectric layer 431.

Next, as shown in fig. 23 to 25, S3 is performed, wherein fig. 24 is a front view taken along line AA 'in fig. 23, fig. 25 is a left view taken along line BB' in fig. 23, the structure thus obtained is annealed in a hydrogen-containing atmosphere to break the portion 330 of the base 321 having the smallest radial dimension, so as to form a cross-sectional structure 340, the cross-sectional structure 340 separates the top semiconductor layer 300 into an anode region 421 and a cathode region 411, and the gate dielectric layer 431 surrounding the cross-sectional structure 340 and the base 321 form a closed cavity 350 in the cross-sectional structure 340.

In one embodiment, after the cross-section structure 340 is formed, the first gate electrode layer 432 is removed, and a second gate electrode layer 433 is disposed on the gate dielectric layer 431; or disposing the second gate electrode layer 433 directly on the first gate electrode layer 432; the gate contact electrode 434 is disposed on the second gate electrode layer 433.

Finally, as shown in fig. 26 to 28, S4 is performed, wherein fig. 27 is a front view taken along line AA 'in fig. 26, and fig. 28 is a left view taken along line BB' in fig. 26, an anode contact electrode 422 is disposed in the anode region 421, a cathode contact electrode 412 is disposed in the cathode region 411, and a gate contact electrode 434 is disposed in the first gate electrode layer 432, so that a vacuum device is formed.

In one embodiment, as shown in fig. 29-31, where fig. 30 is a front view taken along line AA 'in fig. 29, fig. 31 is a left view taken along line BB' in fig. 29, after forming the vacuum device, patterning the SOI substrate of the vacuum device, disposing an insulating layer 436 on the surface of the vacuum device, forming a back gate electrode 435 in the insulating layer 436, patterning the insulating layer 436 to expose the back gate electrode 435, the gate contact electrode 434, the anode contact electrode 422 and the cathode contact electrode 412, and the back gate electrode 435 cooperates with the gate electrode layer to regulate the electrical characteristics of the vacuum device.

The invention can assist in controlling the control device by additionally arranging the back gate electrode 435 so as to improve the control capability of the gate to the device operation.

In summary, the vacuum device and the preparation method thereof can obtain the vacuum device with the cathode-anode interval of nanometer level by arranging the nanometer narrow structure and forming the section structure through hydrogen annealing so as to form larger field intensity and on current; meanwhile, a vacuum device with stronger control capability and full surrounding grid is realized by utilizing a nano cantilever structure; in addition, the cavity under the nano cantilever structure is only arranged on the top semiconductor layer, so that the interval between the anode and the cathode is further reduced; finally, the spacing between the anode and the cathode is further reduced by rounding and thinning the nano cantilever structure.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method of manufacturing a vacuum device, the method comprising:

providing an SOI substrate which sequentially comprises a substrate layer, an oxygen-buried layer and a top semiconductor layer from bottom to top; patterning the SOI substrate to form a nano narrow structure, wherein the nano narrow structure is provided with a position with a minimum radial dimension;

a gate dielectric layer is arranged on the exposed surface of the nano narrow structure and the surface of the top semiconductor layer, the nano narrow structure is wrapped by the gate dielectric layer, and a first gate electrode layer is arranged on the surface of the gate dielectric layer;

annealing the structure obtained in the way, namely, breaking the position with the smallest radial dimension of the nano narrow structure to form a cross-section structure, wherein the cross-section structure divides the top semiconductor layer into an anode region and a cathode region, and the gate dielectric layer and the nano narrow structure wrapping the cross-section structure form a closed cavity;

and arranging an anode contact electrode in the anode region, arranging a cathode contact electrode in the cathode region, and arranging a grid contact electrode in the first grid electrode layer so as to form the vacuum device.

2. The method of manufacturing a vacuum device according to claim 1, wherein the radial dimension of the nanonarrowing structure increases gradually from the cross-sectional structure to both sides thereof.

3. The method of manufacturing a vacuum device according to claim 1, wherein the nano-scale narrow structure is a nano-cantilever structure, and a position of the nano-cantilever structure having a smallest distance from the upper surface of the top semiconductor layer is a position of the smallest radial dimension;

a cavity is arranged below the nano cantilever structure and is only arranged on the top semiconductor layer; or the cavity is only arranged on the oxygen burying layer; or the cavity is arranged on the top semiconductor layer and extends into the oxygen-buried layer.

4. The method of claim 1, wherein the nano-scale structure is a base on which a groove with a predetermined gradient is formed on the top semiconductor layer, the bottom surface of the groove is higher than the bottom surface of the top semiconductor layer, and the position with the smallest distance between the bottom surface of the groove and the buried oxide layer forms the position with the smallest radial dimension of the nano-scale structure.

5. The method of manufacturing a vacuum device according to claim 1, further comprising: and after the nano narrow structure is formed, annealing the nano narrow structure in a hydrogen-containing atmosphere to circularly thin the nano narrow structure and reduce the radial dimension of the position with the minimum radial dimension.

6. The method according to claim 1, wherein after forming the nanonarrowing structure or/and after forming the cross-sectional structure, both sides of the portion where the radial dimension of the nanonarrowing structure is smallest are doped as the cathode region and the anode region.

7. The method of manufacturing a vacuum device according to claim 1, further comprising: removing the first gate electrode layer after the section structure is formed, and arranging a second gate electrode layer on the gate dielectric layer; or (b)

Disposing the second gate electrode layer directly on the first gate electrode layer;

the gate contact electrode is disposed on the second gate electrode layer.

8. The method of manufacturing a vacuum device according to claim 1, wherein an annealing temperature at which annealing of a hydrogen-containing atmosphere is performed to form the cross-sectional structure is 500-1300 ℃.

9. The method of manufacturing a vacuum device according to claim 1, further comprising: after the vacuum device is formed, patterning the SOI substrate of the vacuum device, arranging an insulating layer on the surface of the vacuum device, forming a back gate electrode in the insulating layer, patterning the insulating layer to expose the back gate electrode, the gate contact electrode, the anode contact electrode and the cathode contact electrode, and regulating and controlling the electrical characteristics of the vacuum device by the back gate electrode matched with the gate electrode layer.

10. A vacuum device manufactured by the method of manufacturing a vacuum device according to any one of claims 1 to 9, characterized in that the vacuum device comprises an SOI substrate comprising a substrate layer, a buried oxide layer and a top semiconductor layer;

the buried oxide layer is arranged on the substrate layer, and the top semiconductor layer is arranged on the buried oxide layer;

the top semiconductor layer is internally provided with a nanometer narrow structure, a section structure is arranged at the position with the smallest radial dimension of the nanometer narrow structure, the section structure divides the top semiconductor layer into a cathode area and an anode area, and the section structure is obtained through an annealing process in hydrogen atmosphere;

the periphery of the cross section structure is wrapped by a gate dielectric layer, the wrapped gate dielectric layer of the cross section structure and the nano narrow structure enable the cross section structure to form a closed cavity, and the surface of the gate dielectric layer is wrapped by a first gate electrode layer or/and a second gate electrode layer.

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