CN116343849B - Method, device, storage medium and equipment for improving SSD hybrid read-write performance - Google Patents
Method, device, storage medium and equipment for improving SSD hybrid read-write performance Download PDFInfo
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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Abstract
The application relates to the technical field of data storage, and provides a method, a device, a storage medium and equipment for improving SSD hybrid read-write performance, wherein the method comprises the following steps: acquiring the writing bandwidth of NAND flash memory writing data of an SSD and the number of die of the NAND flash memory, which are currently executing reading, writing and erasing commands concurrently; calculating the total balance coefficient of all die of the concurrent execution commands of the NAND flash memory at the current statistical moment according to the number of die of the concurrent execution commands in the flash memory and the balance coefficient corresponding to the read, write and erase commands, and matching the balance coefficient threshold corresponding to the concurrent execution of the read, write and erase commands of the NAND flash memory according to the write bandwidth; and determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value so as to ensure that the total equalization coefficient of the NAND flash memory at the next statistics time is smaller than or equal to the equalization coefficient threshold value. The application can reduce the probability of the same die of the read command, thereby reducing the delay and improving the QoS.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a method, an apparatus, a storage medium, and a device for improving SSD hybrid read/write performance.
Background
SSD (Solid State Drive, solid state disk) performance metrics generally include IOPS (input output operations per second, which reflects random read and write performance), throughput (MB/s, which reflects sequential read and write performance), response time/latency. Access patterns are considered in performance test design: (1) random (random) and continuous (sequential) data command requests: it is indicated that the LBAs (logical addresses) of the two commands are not consecutive, the consecutive addresses become sequential, and the discontinuous addresses are called random. (2) Block size (Block size): i.e., the data size of a single command transfer, the performance test varies from 4KB to 512KB. Random testing typically uses small blocks of data, such as 4KB; continuous testing typically uses large blocks of data, such as 512KB. The smaller the response time, i.e., the response time required for each command to be issued to completion. For quality of service indicators (Quality of Service, qos), expressed is a latency "confidence level", using the largest of 2 (99%) to 5 (99.999%) percent of commands, i.e., the slowest response time of that command, the smaller the latency of an SSD, the better as a whole.
One NAND flash memory chip in the SSD has several die (or lun), which is the smallest independent unit in the flash memory that can execute commands and report its own status. NAND flash memory generally supports concurrent operations of multiple die, that is, each die can execute NAND commands such as read, write, erase, etc., but only one command can be executed on one die at a time, for example, a die is performing a write operation, and at this time, a read command hits the die, and the read and write commands cannot be performed simultaneously. In order to improve the sequential read-write performance of the SSD, multiple die are generally selected to concurrently execute commands such as read-write erase.
When mixed read-write is performed, the read-write erasing command hits the same die with a high probability, and especially when GC garbage is recovered, command queuing waiting occurs, so that QoS is poor, and user experience is poor. In order to avoid command waiting, in the prior art, data is generally rebuilt through RAID, and a read request can be responded in time, but in the case of high-pressure IO, a situation that multiple die are occupied by other commands may be encountered in the data rebuilding, so that the technical problem of QoS degradation caused when the commands are executed concurrently by multiple die cannot be completely solved in RAID rebuilding.
Disclosure of Invention
The present application has been made in view of the above problems, and provides a method, apparatus, storage medium, and device for improving SSD hybrid read-write performance, which overcome or at least partially solve the above problems.
In one aspect of the present application, a method for improving SSD hybrid read-write performance is provided, the method comprising:
acquiring the writing bandwidth of NAND flash memory writing data of an SSD and the number of die of the NAND flash memory, which are currently executing reading, writing and erasing commands concurrently;
according to the number of die for executing the read, write and erase commands in the NAND flash memory and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, calculating the total balance coefficient WEIGHT of all die for executing the read, write and erase commands in the NAND flash memory at the current statistical moment, wherein a calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW;
matching corresponding equalization coefficient threshold values when the NAND flash memory concurrently executes read, write and erase commands according to the write bandwidth;
and determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value so as to ensure that the total equalization coefficient of all die for concurrently executing the read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the equalization coefficient threshold value.
Optionally, the read equalization coefficient is inversely proportional to the weight value of the number of die of the concurrent execution read command and the total number of die in the NAND flash memory, the write equalization coefficient is inversely proportional to the weight value of the number of die of the concurrent execution write command and the total number of die in the NAND flash memory, and the erase equalization coefficient is inversely proportional to the weight value of the number of die of the concurrent execution erase command and the total number of die in the NAND flash memory.
Optionally, the acquiring the write bandwidth of the NAND flash write data of the SSD includes:
and acquiring the total bandwidth of host write operation and GC garbage collection mechanism corresponding write operation on the NAND flash memory of the SSD.
Optionally, matching the equalization coefficient threshold corresponding to the NAND flash memory when the read, write and erase commands are concurrently executed according to the write bandwidth includes:
judging a bandwidth threshold interval to which the write bandwidth belongs;
and searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
Optionally, the larger the bandwidth threshold interval to which the write bandwidth belongs, the larger the equalization coefficient threshold corresponding to the bandwidth threshold interval.
Optionally, the method further comprises:
and configuring a read equalization coefficient, a write equalization coefficient, an erase equalization coefficient, an equalization coefficient threshold and a matching relation of the equalization coefficient threshold and a write bandwidth according to the power consumption consumed when the NAND flash memory executes the read, write and erase commands.
In a second aspect, the present application further provides an apparatus for improving SSD hybrid read-write performance, the apparatus including:
the monitoring module is used for acquiring the writing bandwidth of the NAND flash memory writing data of the SSD and the number of die of the NAND flash memory for executing the reading, writing and erasing commands concurrently at present;
the calculation module is used for calculating the total balance coefficient WEIGHT of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the current statistical moment according to the number of die of the NAND flash memory for concurrently executing the read, write and erase commands and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, and the calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW;
the matching module is used for matching the corresponding equalization coefficient threshold value when the NAND flash memory concurrently executes the read, write and erase commands according to the write bandwidth;
and the control module is used for determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value so as to ensure that the total equalization coefficient of all die for concurrently executing the read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the equalization coefficient threshold value.
Optionally, the matching module includes:
the judging unit is used for judging a bandwidth threshold interval to which the writing bandwidth belongs;
and the matching unit is used for searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
In a third aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of improving the hybrid read-write performance of an SSD as described above.
In a fourth aspect, the present application also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the steps of the method for improving the hybrid read/write performance of an SSD as described above are implemented when the processor executes the computer program.
According to the method, the device, the storage medium and the equipment for improving the SSD hybrid read-write performance, the total balance coefficient of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the current statistical moment is calculated according to the write bandwidth of write data on the NAND flash memory, the number of die of the concurrent executing read, write and erase commands in the NAND flash memory and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, the total balance coefficient of all die of the concurrent executing read, write and erase commands of the NAND flash memory is determined according to the difference value of the total balance coefficient and the balance coefficient threshold value matched with the write bandwidth, so that the total balance coefficient of all die of the actual concurrent executing read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the balance coefficient threshold value, the balance issuing control of the read, write and erase commands is realized, the probability of the same die in the read command is reduced, and accordingly delay is reduced, and QoS is improved.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a flowchart of a method for improving SSD hybrid read/write performance according to an embodiment of the present application;
fig. 2 is a block diagram of an apparatus for improving SSD hybrid read/write performance according to an embodiment of the application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
FIG. 1 schematically illustrates a flow chart of a method of improving SSD hybrid read-write performance in accordance with one embodiment of the present application. Referring to fig. 1, the method for improving SSD hybrid read-write performance according to the embodiment of the application specifically includes the following steps:
s11, acquiring the writing bandwidth of NAND flash memory writing data of the SSD and the number of die of the NAND flash memory for executing the reading, writing and erasing commands concurrently at present;
in this embodiment, the write data operation includes a host write operation and a GC garbage collection mechanism corresponding write operation. The step S11 of obtaining the write bandwidth of the current write data of the NAND flash memory of the SSD specifically includes: and acquiring the total bandwidth of host write operation and GC garbage collection mechanism corresponding write operation on the NAND flash memory of the SSD.
S12, calculating a total balance coefficient WEIGHT of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the current statistical moment according to the number of die of the current concurrent executing read, write and erase commands in the NAND flash memory and a preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, wherein a calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW.
In the embodiment of the application, when the die and/or the die quantity of the concurrent execution read, write and erase commands are updated and changed, or the statistics of the total equalization coefficient is carried out in real time.
And S13, matching the corresponding equalization coefficient threshold value when the NAND flash memory concurrently executes the read, write and erase commands according to the write bandwidth.
In this embodiment, the read equalization coefficient, the write equalization coefficient, the erase equalization coefficient, the equalization coefficient threshold, and the matching relationship between the equalization coefficient threshold and the write bandwidth are configured in advance according to the power consumption consumed when the NAND flash memory executes the read, write, and erase commands.
The type values of different nands are different from each other for RW, WW and EW, and the main basis is the power consumption consumed by the nands when executing the read-write erase command, which can be understood as the execution time of executing the read-write erase command, such as the longest erase command time, the fastest read command execution, and the minimum power consumption of the command. Because the execution time of the erasing command is long, that is, the time of occupying die is longest, other commands cannot be executed in the period, the erasing equilibrium coefficient EW is the largest, the number of die occupied as much as possible is small, and other commands can be executed in other die which are not occupied. Different nand models are different in time for executing commands, so that specific values are preset according to actual test conclusions and experience values.
The equalization coefficient threshold is mainly determined according to the power consumption, bandwidth requirement and performance of nand, if the equalization coefficient threshold is set too large, concurrent erase commands will be many when writing is only performed, the nand busy time is too long, the power consumption will be high, and meanwhile, qos will be pulled to be large when mixed reading and writing is performed. Setting the equalization coefficient threshold too small affects the read-write performance, mainly the write performance, and the die data of concurrent execution commands at the same time becomes small, which can reduce the bandwidth. Therefore, the application can preset the equalizing coefficient threshold and the matching relation between the equalizing coefficient threshold and the writing bandwidth according to experimental data so as to ensure that the power consumption of nand, the bandwidth requirement and the comprehensive performance can meet the requirement.
S14, determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value, so as to ensure that the total equalization coefficient of all die for concurrently executing the read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the equalization coefficient threshold value.
In this embodiment, the issuing control of the read, write and erase commands may be implemented according to the following discriminant model, that is, when the SSD is running, the number of die executed by each command on the nand needs to conform to the following discriminant model. When a read-write-erase mixed command is received on the nand, the number of concurrent die of different commands is balanced according to the principle, and a discrimination model is as follows:
RW x+wwy+ew z < = equalization coefficient threshold;
wherein x, y and z are the number of die actually occupied by the read, write and erase commands on the nand during normal operation of the SSD disk, for example, in the read-write mixed IO stream, the write command actually sent to the nand has 2 die, the erase command has 3 die, i.e. at this time, the state on the nand is that 2 die are occupied by the write command, and 3 die are occupied by the erase command. At this time, the discrimination model is:
RW 0+ww2+ew 3< = equalization coefficient threshold; in one specific example, rw=1, ww=3, ew=4, and equalization coefficient threshold=20; the current state is 1*0 + 3*2 + 4*3 < 20, and at this time, only the read command can be issued again on nand, i.e. the number of die for executing the read command is increased, and no other command satisfies the condition.
According to the method for improving the SSD hybrid read-write performance, the write bandwidth of write data on the NAND flash memory is monitored and obtained, the total balance coefficient of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the current statistical moment is calculated according to the number of die of the NAND flash memory for concurrently executing the read, write and erase commands and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, the type of the operation command to be executed next and the number of die of the corresponding operation command to be executed are determined according to the difference value of the total balance coefficient and the balance coefficient threshold value matched with the write bandwidth, so that the total balance coefficient of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the next statistical moment is smaller than or equal to the balance coefficient threshold value, balance issuing control of the read, write and erase commands is achieved, the probability of the same die in the command is reduced, and QoS is improved.
In a specific embodiment, the read equalization coefficient is inversely proportional to the weight value of the number of die that concurrently executes the read command and the total number of die in the NAND flash memory, the write equalization coefficient is inversely proportional to the weight value of the number of die that concurrently executes the write command and the total number of die in the NAND flash memory, and the erase equalization coefficient is inversely proportional to the weight value of the number of die that concurrently executes the erase command and the total number of die in the NAND flash memory.
In another embodiment of the present application, the step S13 matches the equalization coefficient threshold corresponding to the NAND flash memory when the read, write, erase command is concurrently executed according to the write bandwidth, and specifically includes the following sub-steps not shown in the drawings:
s131, judging a bandwidth threshold interval to which the write bandwidth belongs;
and S132, searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
The larger the bandwidth threshold interval to which the write bandwidth belongs, the larger the equalization coefficient threshold corresponding to the bandwidth threshold interval.
The technical scheme of the application is clearly and completely explained below through a specific example.
In this embodiment, the read equalization coefficient, the write equalization coefficient, the erase equalization coefficient corresponding to the various commands of the read, write, and erase commands are preset, and the equalization coefficient threshold corresponding to the total equalization coefficient of all die in nand for executing the read, write, and erase commands concurrently.
The specific implementation method is as follows:
(1) setting READ equalization coefficients, WRITE equalization coefficients and ERASE equalization coefficients of READ, WRITE and ERASE commands on nand as Read_WEIGHT (RW), write_WEIGHT (WW) and Erase_WEIGHT (EW) respectively; setting a rule of RW < WW < EW;
(2) the total equalization coefficient of all die for executing the read, write and erase commands in nand is WEIGHT, and three equalization coefficient thresholds are set, and in this embodiment, the three equalization coefficient thresholds are respectively: WEIGHT_THRESHOLD1, WEIGHT_THRESHOLD2, WEIGHT_THRESHOLD3; the setting principle is as follows: WEIGHT_THRESHOLD1< WEIGHT_THRESHOLD2 < WEIGHT_THRESHOLD3;
(3) monitoring bandwidth BW of write data (including host write and GC write) on nand, and setting bandwidth thresholds TH1, TH2 and TH3; and TH 1< TH2 < TH3, can divide into three bandwidth threshold intervals according to three bandwidth thresholds;
(4) when the bandwidth BW of the write data is smaller than TH1, the equalization coefficient THRESHOLD matched with the total equalization coefficients of all die for executing the read, write and erase commands on nand is set as WEIGHT_THRESHOLD1; when TH 1< = BW < TH2, setting the equalization coefficient THRESHOLD of total equalization coefficient matching of all die actually executing the read, write, erase commands concurrently on nand to WEIGHT_THRESHOLD2; when TH2 < = BW, setting an equalization coefficient THRESHOLD value of total equalization coefficient matching of all die actually executing the read, write, erase commands concurrently on nand to WEIGHT_THRESHOLD3;
(5) the discrimination model for executing command equilibrium distribution on nand is as follows:
RW x+wwy+ew z < = equalization coefficient threshold;
when the read-write-erase mixed command is received on the nand, the number of concurrent die of different commands can be balanced according to the principle.
(6) When the write bandwidth BW on nand is < TH1, the discrimination model corresponding to the above step (5) is to conform to:
RW*x + WW*y + EW*z <= WEIGHT_THRESHOLD1;
when the write bandwidth TH 1< = BW < TH2 on nand, the discrimination model corresponding to the above step (5) should conform to:
RW*x + WW*y + EW*z <= WEIGHT_THRESHOLD2;
when the write-on bandwidth BW > =th2, the discrimination model corresponding to the above step (5) is to conform to:
RW*x + WW*y + EW*z <= WEIGHT_THRESHOLD3;
above, when the write bandwidth on the nand is smaller, the write bandwidth requirement can be met without more die concurrent execution commands, so the total equalization coefficient is smaller, and the number of die of concurrent execution commands of write and erase commands is smaller because RW < WW < EW, the number of die of command execution is more prone to read commands, and the die of other commands is reduced when the read commands hit the die of other commands.
According to the technical scheme, the number of die which is executed concurrently by the write command is reduced when the read-write command is in light-weight writing when the read-write command is mixed, so that the die which is busy in the command is reduced, the read command is responded more quickly, qoS is improved, and the write command is not influenced. As the proportion of the write command in the mixed read-write command increases, the corresponding total weight threshold value also increases to increase the number of die for concurrent execution of the write and erase commands, so that the write command responds faster, and simultaneously, as the proportion of the read command decreases, no more die for concurrent execution is needed.
The technical scheme of the application has at least the following beneficial effects:
1. according to different IO streams, the application controls the die quantity of nand concurrent execution commands, and can reduce delay and improve Qos while meeting the throughput requirement.
2. The application sets different equalization coefficients for different commands, and the read equalization coefficient is minimum, so that the read priority principle can be ensured, and the read command delay is reduced.
3. According to the application, by monitoring the write bandwidth on the NAND, the corresponding equalization coefficient threshold value is adaptively selected when the NAND flash memory matched with the write bandwidth concurrently executes the read, write and erase commands, so that the QoS of the read command is improved while the executing efficiency of the GC and host write is ensured.
For the purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated by one of ordinary skill in the art that the methodologies are not limited by the order of acts, as some acts may, in accordance with the methodologies, take place in other order or concurrently. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the application.
In addition, the embodiment of the application also provides a device for improving the SSD hybrid read-write performance, which comprises a functional module for realizing the method for improving the SSD hybrid read-write performance. Fig. 2 schematically illustrates a structural diagram of an apparatus for improving SSD hybrid read-write performance according to an embodiment of the application. Referring to fig. 2, the device for improving SSD hybrid read-write performance according to the embodiment of the application specifically includes a monitor module 201, a calculation module 202, a matching module 203, and a control module 204, where:
the monitoring module 201 is configured to obtain a write bandwidth of NAND flash write data of the SSD and a number of die of the NAND flash that currently executes a read, write, and erase command concurrently;
the calculating module 202 is configured to calculate, according to the number of die of the NAND flash memory that currently executes the read, write and erase commands concurrently and the preset read equalization coefficient RW, write equalization coefficient WW and erase equalization coefficient EW corresponding to the read, write and erase commands, a total equalization coefficient weiht of all die of the NAND flash memory that currently executes the read, write and erase commands concurrently at the current statistical moment, where a calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW;
the matching module 203 is configured to match, according to the write bandwidth, an equalization coefficient threshold corresponding to when the NAND flash memory concurrently executes a read, write, erase command;
and the control module 204 is configured to determine, according to a difference between the total equalization coefficient and the equalization coefficient threshold, a type of a next operation command to be executed and a number of die for executing the corresponding operation command, so as to ensure that a total equalization coefficient of all die for concurrently executing the read, write and erase commands by the NAND flash memory at a next statistical moment is less than or equal to the equalization coefficient threshold.
In the embodiment of the present application, the matching module 203 includes a judging unit and a matching unit, where: the judging unit is used for judging a bandwidth threshold interval to which the writing bandwidth belongs; and the matching unit is used for searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
For the device embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant points refer to the part of the description of the method embodiment, and have corresponding technical effects.
In addition, the embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, the computer program is executed by a processor to realize the steps of the method for improving the SSD hybrid read-write performance.
In this embodiment, the method for improving the SSD hybrid read-write performance may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
In addition, the embodiment of the application also provides electronic equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the steps of the method for improving the SSD hybrid read-write performance are realized when the processor executes the computer program. Such as steps S11-S14 shown in fig. 1. Alternatively, the processor may implement the functions of each module/unit in the embodiment of the device for improving the SSD hybrid read/write performance when executing the computer program, for example, the monitoring module 201, the calculating module 202, the matching module 203, and the control module 204 shown in fig. 2.
In a particular embodiment, the electronic device may be an SSD device.
According to the method, the device, the storage medium and the equipment for improving the SSD hybrid read-write performance, the write bandwidth of write data on the NAND flash memory is monitored and obtained, according to the quantity of die of the current concurrent execution read, write and erase commands in the NAND flash memory and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, the total balance coefficient of all die of the NAND flash memory for concurrent execution read, write and erase commands at the current statistical moment is calculated, the type of the operation command to be executed next and the quantity of die of the corresponding operation command are determined according to the difference value of the total balance coefficient and the balance coefficient threshold value matched with the write bandwidth, so that the total balance coefficient of all die of the current concurrent execution read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the balance coefficient threshold value, balance issuing control of the read, write and erase commands is realized, the probability of the same die in the read command is reduced, and QoS is improved.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, any of the claimed embodiments can be used in any combination.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A method for improving SSD hybrid read-write performance, the method comprising:
acquiring the writing bandwidth of NAND flash memory writing data of an SSD and the number of die of the NAND flash memory, which are currently executing reading, writing and erasing commands concurrently;
according to the number of die of the current concurrent execution of the read, write and erase commands in the NAND flash memory and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, calculating the total balance coefficient WEIGHT of all die of the current concurrent execution of the read, write and erase commands in the NAND flash memory at the current statistical moment, wherein a calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW;
matching corresponding equalization coefficient threshold values when the NAND flash memory concurrently executes read, write and erase commands according to the write bandwidth;
and determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value so as to ensure that the total equalization coefficient of all die for concurrently executing the read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the equalization coefficient threshold value.
2. The method of claim 1, wherein the read equalization coefficient is inversely proportional to a weight value of a number of die concurrently executing the read command to a total number of die in the NAND flash memory, the write equalization coefficient is inversely proportional to a weight value of a number of die concurrently executing the write command to a total number of die in the NAND flash memory, and the erase equalization coefficient is inversely proportional to a weight value of a number of die concurrently executing the erase command to a total number of die in the NAND flash memory.
3. The method of claim 1, wherein the obtaining the write bandwidth of NAND flash write data of the SSD comprises:
and acquiring the total bandwidth of host write operation and GC garbage collection mechanism corresponding write operation on the NAND flash memory of the SSD.
4. The method of claim 1, wherein matching corresponding equalization coefficient thresholds for concurrent execution of read, write, erase commands by the NAND flash memory according to the write bandwidth comprises:
judging a bandwidth threshold interval to which the write bandwidth belongs;
and searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
5. The method of claim 4, wherein the larger the bandwidth threshold interval to which the write bandwidth belongs, the larger the equalization coefficient threshold corresponding to the bandwidth threshold interval.
6. The method according to claim 1, wherein the method further comprises:
and configuring a read equalization coefficient, a write equalization coefficient, an erase equalization coefficient, an equalization coefficient threshold and a matching relation of the equalization coefficient threshold and a write bandwidth according to the power consumption consumed when the NAND flash memory executes the read, write and erase commands.
7. An apparatus for improving SSD hybrid read-write performance, the apparatus comprising:
the monitoring module is used for acquiring the writing bandwidth of the NAND flash memory writing data of the SSD and the number of die of the NAND flash memory for executing the reading, writing and erasing commands concurrently at present;
the calculation module is used for calculating the total balance coefficient WEIGHT of all die of the NAND flash memory for concurrently executing the read, write and erase commands at the current statistical moment according to the number of die of the current concurrent executing read, write and erase commands in the NAND flash memory and the preset read balance coefficient RW, write balance coefficient WW and erase balance coefficient EW corresponding to the read, write and erase commands, and the calculation model is as follows:
RW x+wwy+ew z=weight, where x, y, z are the number of die currently executing read, write, and erase commands concurrently in NAND flash, respectively, RW < WW < EW;
the matching module is used for matching the corresponding equalization coefficient threshold value when the NAND flash memory concurrently executes the read, write and erase commands according to the write bandwidth;
and the control module is used for determining the type of the next operation command to be executed and the number of die for executing the corresponding operation command according to the difference value between the total equalization coefficient and the equalization coefficient threshold value so as to ensure that the total equalization coefficient of all die for concurrently executing the read, write and erase commands of the NAND flash memory at the next statistical moment is smaller than or equal to the equalization coefficient threshold value.
8. The apparatus of claim 7, wherein the matching module comprises:
the judging unit is used for judging a bandwidth threshold interval to which the writing bandwidth belongs;
and the matching unit is used for searching an equalization coefficient threshold corresponding to the current bandwidth threshold interval according to the bandwidth threshold interval to which the write bandwidth belongs.
9. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any of claims 1-6.
10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1-6 when the computer program is executed.
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