CN116341479A - Remapping method based on routability and integrated circuit - Google Patents
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Abstract
The application discloses a remapping method and an integrated circuit based on a routability, comprising the following steps: performing global layout on the whole netlist; global wiring is carried out on the whole netlist; extracting a sub-netlist of wiring congestion; performing incremental remapping on the sub-netlist, and rewriting the sub-netlist by using the incremental remapping result; performing incremental global layout on the rewritten sub-netlist; and incremental global routing is carried out on the rewritten sub-netlist. Through the design, the local congestion can be relieved, and the distributability is improved. Time may also be improved by minimizing congestion. Integrating congestion minimization into the area and delay metrics trades off the impact between area, delay, and congestion minimization, reduces congestion without breaking delay constraints, and increases the area in only a very small fraction.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a remapping method based on routability and an integrated circuit.
Background
For digital circuit design processes at the VLSI (very large scale integration) level, designers often employ computer-aided techniques. Standard languages, such as Hardware Description Language (HDL), have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. A variety of hardware description languages such as VHDL and Verilog have become industry standards. VHDL and Verilog are generic hardware description languages that allow the use of abstract data types to define hardware models at the chip raw level, register Transfer Level (RTL), or behavioral level. As device technology continues to advance, various product design tools have been developed to adapt HDL for use in new devices and design styles.
In designing an integrated circuit using HDL code, the code is first written and the written code is compiled by an HDL compiler. HDL source code describes circuit elements at a layer and a compiler generates an RTL netlist (nestlist) through the compilation. The RTL netlist is made up of a plurality of RTL objects or components and a plurality of networks (nets), which are signal connections between the components. The RTL netlist is typically a technology-independent netlist in that it is independent of the technology or architecture of a particular vendor's integrated circuit, such as a Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC). The RTL netlist corresponds to a schematic representation (as compared to a behavioral representation) of circuit elements. Mapping operations are then performed to transition from the technology-independent RTL netlist to a technology-specific netlist that can be used to create circuits in a vendor technology or architecture, including laying out instances (instances) and routing interconnections so that the circuits meet given timing, spacing, and power constraints.
Electronic Design Automation (EDA) software tools provide various functions related to the design, simulation, analysis, verification, and fabrication of Integrated Circuits (ICs). Advances in computing speed and power and memory capacity have reduced the time required to accomplish such functions. At the same time, the increased design complexity (number of devices and interconnections between devices) and faster design cycles have made IC designers more dependent on EDA software tools to produce IC layouts that can be properly executed while meeting time-to-market goals.
Process mapping uses logic cells provided in a process library (standard cell library) to implement an internal representation of the design, i.e., the design will be mapped to the target process. In the mapping process, some local optimizations must also be performed to meet timing, area, and power consumption constraints. The process mapping is an important step of connecting the front end and the back end of EDA, and only through the process mapping, we can really convert the logic circuit into a physical circuit which is actually used. Conventional process mapping generally comprises three steps, node cutting and cutting equation calculation, boolean matching and coverage, wherein the boolean matching step generates a solution space, which is a crucial step.
Conventional process mapping only considers delay and area constraints when selecting the best boolean match, and does not consider routability (degree of congestion). The routability plays a critical role in the subsequent place and route stage. How to avoid two units far apart from each other from being connected together, thereby improving the utilization of wiring resources is a technical problem to be solved.
The description of the background art is only for the purpose of facilitating an understanding of the relevant art and is not to be taken as an admission of prior art.
Disclosure of Invention
Therefore, the embodiment of the invention provides a process mapping method which can relieve local congestion, improve the wiring property and improve the wiring resource utilization rate.
In a first aspect, an embodiment of the present invention provides a method for remapping based on a routability, including the steps of: performing global layout on the whole netlist; global wiring is carried out on the whole netlist; extracting a sub-netlist of wiring congestion; performing incremental remapping on the sub-netlist, and rewriting the sub-netlist by using the incremental remapping result; performing incremental global layout on the rewritten sub-netlist; and incremental global routing is carried out on the rewritten sub-netlist.
Optionally, after the incremental global routing step, determining whether there is a sub-netlist with routing congestion.
Optionally, the incremental remapping includes the steps of: inputting a congested sub-netlist;
decomposing the congested sub-netlist into a NAND graph; performing routability driven process mapping on the NAND graph to form a new netlist; returning to the new netlist.
Optionally, decomposing the congested sub-netlist into a nand graph includes the steps of: performing topological ordering on the nodes; performing a prescribed operation on each node in the topology sequence; judging whether the current node is the last node or not; judging whether the current node has two inputs or not; taking out two inputs of the current node and decomposing the two inputs to generate a new node; connecting the output of the new node to the current node; and calculating the position of the new node.
Optionally, the steps of claim 4 are repeatedly performed with only two inputs to the current node.
Optionally, the routability driven process map includes the steps of: calculating the cutting of the nodes from bottom to top; calculating a truth table of the cut; traversing each node from bottom to top; judging whether the current node is the last node or not; traversing each cut of the current node; judging whether the current cutting is the last cutting or not; traversing each gate that matches the current cut truth table; judging whether the current matched gate is the last matched gate or not; calculating the coordinates of the current matching gate; calculating the area and the arrival time of the current matching gate; updating the area and time delay matching gate of the current node; the match gates for each node are selected top-down to cover the entire netlist.
Optionally, the method is characterized in that the coordinates of the matching door are obtained through the gravity centers of the fan-in connection object and the fan-out connection object of the matching door; the fan-in connection object is a matched door of a fan-in node; the fan-out connection object is a fan-out node. Optionally, the total area of the matching gate is the sum of the area of the matching gate and the area of the line length multiplied by a coefficient; the area of the matching gate is the sum of the areas of the matching gates of the current matching gate and the fan-in node divided by the number of fan-out nodes; the line length area is the sum of the distance between the matching gate of the fan-in node and the current matching gate and the line length area of the fan-in node divided by the fan-out number.
Optionally, the matching gate arrival time includes: the arrival time of the input pin of the matching gate and the arrival time of the output pin of the matching gate; the arrival time of the input pin is obtained through the arrival time of a fan-in node connected with the input pin and the time delay of a line; the arrival time of the output pin is obtained by the arrival time of the input pin and the delay from the input pin to the output pin.
In a second aspect, an embodiment of the invention provides an integrated circuit, characterized in that the integrated circuit is configured to use the method of any of claims 1-9 when performing a process mapping operation.
Additional optional features and technical effects of embodiments of the invention are described in part below and in part will be apparent from reading the disclosure herein.
Drawings
Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, wherein like or similar reference numerals denote like or similar elements, and wherein:
FIG. 1 illustrates a prior art schematic diagram of a routing method for designing an integrated circuit;
FIG. 2 illustrates a flow diagram of a routing method in which embodiments of the present invention may be implemented;
FIG. 3 illustrates a flow diagram of an incremental remapping method in which embodiments of the invention may be implemented;
FIG. 4 illustrates a flow diagram of a method for decomposing a netlist into NAND diagrams in which embodiments of the present invention may be implemented;
FIG. 5 illustrates a flow diagram of a process mapping method that may be used to implement an embodiment of the invention;
FIG. 6a illustrates a schematic diagram of an area-minimization-based process mapping method in which embodiments of the present invention may be implemented;
FIG. 6b shows a schematic diagram of a remapping-based method in which embodiments of the invention may be implemented.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. The exemplary embodiments of the present invention and the descriptions thereof are used herein to explain the present invention, but are not intended to limit the invention.
The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
In the embodiment of the invention, the process mapping method can relieve local congestion, improve the routability and improve the utilization rate of wiring resources.
In some embodiments, the present invention provides a re-mapping method based on a routability, which can combine the features of the integrated circuit of any of the embodiments, and vice versa, and is not repeated herein.
FIG. 1 shows a schematic diagram of a prior art wiring method for designing an integrated circuit, such as the prior art of FIG. 1, in which HDL code is synthesized after the HDL code is prepared to produce a netlist that is typically optimized by performing logic optimization. After this, a mapping process maps the netlist to a specific target technology/architecture. After step 101 ends, the synthesis has completed and a netlist specific to the technology/architecture used in the vendor's IC can now be provided. The netlist is effectively at the gate level and the timing analysis is estimated by using a statistical model of interconnect properties based on pre-layout information (e.g., fan-out counts, or connected component types and sizes). After synthesis, conventional layout operations may be performed on the logic circuits at step 102 and local changes may be made to the netlist (only at the chip raw level, cell level, or gate level) at step 103 to meet timing performance. Thereafter, conventional routing operations are performed at step 104 to create a circuit design in each IC. If there are some unsatisfied constraints, the process is modified by loop iteration (iteration).
In the element plane placement (floorplanning) technique, a design is divided into a plurality of areas on a chip, and layout-based interconnect estimation is used for the inter-area interconnect while estimating the interconnect within the areas by using a statistical model. The component placement may be used early in the RTL phase or after initial integrated operation. The element floor plan may be extended to divide, replicate, and cut the RTL assembly into multiple zones, and combined with the RTL level timing and region model.
How to avoid two regions that are far apart from each other to be connected together, thereby improving the utilization of wiring resources, is not solved by the prior art.
FIG. 2 shows a schematic flow diagram of a routing method in which an embodiment of the present invention may be implemented, as shown in FIG. 2, in order to evaluate routing congestion, a global layout is performed on the entire netlist in step 201; global routing the entire netlist to determine the locations of the cells and extract the regions of congestion at step 202; in step 203, it is determined whether there is a wiring congestion, and if there is no congestion area, the incremental flow is ended and step 208 is executed; extracting a sub-netlist in step 204; in step 205, incremental remapping is performed on the extracted sub-netlist, and the sub-netlist is rewritten by the remapped result and then is put back into the original sub-netlist; performing incremental global placement on the updated netlist in step 206; performing incremental global routing on the updated netlist in step 207; returning to step 203 after step 207 to judge whether the updated netlist has a congestion area, and ending the incremental flow if the updated netlist has no congestion area; otherwise, the steps in the above embodiment will be continued until no congestion area exists to end the incremental flow.
When the method flow is executed for the first time in the above embodiment, step 203 is not judged, and step 204 is directly executed.
FIG. 3 illustrates a flow diagram of an incremental remapping method in which embodiments of the present invention may be implemented, as shown in FIG. 3, by inputting a congested netlist in step 301; decomposing the netlist into a nand diagram at step 302; performing routability driven process mapping on the nand map at step 303 to form a new netlist; the mapped new netlist is returned in step 304. And performing congestion judgment on the new netlist according to the embodiment. The embodiment of fig. 3 is a refinement of step 205 of the embodiment of fig. 2.
FIG. 4 illustrates a flow diagram of a method for decomposing a netlist into NAND diagrams in which embodiments of the present invention may be implemented. The nodes are topologically arranged in step 401 as shown in fig. 4; performing a provisioning operation for each node v in the topology sequence in step 402, the provisioning operation being a subsequent processing step in the embodiment shown in fig. 4; in step 403, it is determined whether node v is the last node; determining in step 404 whether node v has only two inputs; in step 405, two inputs of node v are fetched and decomposed to generate a new node; connecting the output of the new node to node v in step 406; calculating the position of the new node in step 407; the process of decomposing the netlist into a nand-graph method ends in step 408.
In the embodiment shown in fig. 4, the current node decomposition process is a recursive operation, and each multi-input node is decomposed according to the topological order, so that the fan-in node of the current node is ensured to be decomposed. Each node combines the inputs in sequence to decompose new two-input nodes, then connects the outputs of the new two-input nodes to the original node, and then decomposes the original node until the original node has only two inputs. In this process, the coordinates of the newly resolved node are defined as the center of gravity of the node to which it is connected by fan-in and fan-out. The coordinates of the newly decomposed nodes are obtained by the formula (1):
where pos_x (v) is the x-coordinate of the node, pos_y (v) is the y-coordinate of the node, fanin is the fan-in node, fanout is the fan-out node.
The embodiment shown in fig. 4 is a refinement of step 302 in the embodiment shown in fig. 3.
FIG. 5 illustrates a flow diagram of a process mapping method that may be used to implement an embodiment of the invention; the cut of nodes is computed bottom-up in step 501 as shown in fig. 5; calculating a truth table for the cut in step 502; traversing each node v from bottom up in step 503; determining in step 504 whether node v is the last node; traversing each cut c of node v in step 505; determining if cut c is the last cut in step 506; traversing each gate g matching the cut c truth table in step 506; determining whether the matched gate g is the last gate matched to the cut c truth table in step 508; calculating the coordinates of the matching gate in step 509; calculating the area and arrival time of the matched gate in step 510; updating the optimal area and delay matching gate of the current node v in step 511; the best match gate for each node is selected top-down in step 512 to cover the entire netlist; the flow of the routable process mapping method ends in step 510.
The process mapping method of the routability shown in fig. 5 is mainly divided into three parts: calculation of cut and truth tables, boolean and coverage. The cut calculation generates for each node all possible cuts of no more than 6 in size from bottom up, while calculating the truth table for each cut. The overlay step is to select the best match gate for all primary output nodes from top to bottom, and then select the best match gate for the fan-in nodes of these match gates until the primary input node is reached. The calculation of the truth table and the overlaying step may be performed using the prior art, and are not particularly limited in this application. The flow shown in fig. 5 includes three loops: the first loop traverses each node from the bottom up, the second loop traverses each cut generated by the node, and the third loop traverses the same matching gate for each truth table and the cut truth table. These three loops would generate four best match gates for each node, i.e., each node ultimately retains four possible solutions. In the third cycle, for each matching gate, the coordinate position of the current matching gate is calculated according to the center of gravity of the fan-in and fan-out connection objects of the matching gate. The fanout node of the current node has not calculated its best match gate because it is the best match gate for each node from the bottom up. Therefore, when the coordinates are calculated, the fan-in connection object is the best matching gate of the fan-in node, and the fan-out connection object is the fan-out node. The calculation of the matching gate is shown in the formula (3) and the formula (4):
and after the coordinates of the current matching gate are calculated, calculating the total area and the arrival time of the considered line length of the matching gate by using the coordinates of the matching gate. The total area of the matched gates is defined as the area of the matched gate plus the line length area multiplied by a factor. The coefficient may be obtained empirically or theoretically, and is not particularly limited in this application. The area of the matching gate is the sum of the areas of the best matching gates that calculate the current matching gate and its fan-in node divided by the number of fan-out nodes. The line length area is defined as the sum of the distances of the best match of the fan-in node and the current matched gate, plus the sum of the line length areas of the fan-in node, divided by the number of fan-outs. The area_cost (m, v) refers to the total area, and is composed of the area of the matching gate and the line length area. area (m, v) represents the area of the current matching gate, m represents the current matching gate, fanin (m, v) represents the fan-in node of the current matching gate, area (v) i ) Representing node v i Is a good match for the gate area. wire (m, v) represents the line length area, match (v) i ) Representing node v i Is used for the matching of the gate of the (c),pos (m, v) represents the position of the matching gate of the current node v.
The calculation formula of the total area is shown in formula (5):
area_cost(m，v)＝area(m，v)+k*wire(m，v) (5)
the area calculation formula of the current matching gate is shown as formula (6):
the calculation formula of the line length area is shown as formula (7):
the calculation formula of the distance between the best matching gate and the current matching gate is shown as formula (8)
dist((x 1 ，y 1 )，(x 2 ，y 2 ))＝|x 1 -x 2 |+|y 1 -y 2 | (8)
Wherein x is 1 ，y 1 For the coordinates of the current matching gate, x 2 ，y 2 Is the coordinate of the best matching gate.
The delay of the matched gate is measured in terms of arrival time. Each matching gate needs to calculate the arrival time of the input pin and the arrival time of the output pin. The arrival time of the matching gate is the arrival time of the output pin. The arrival time of an input pin is the arrival time of the best match gate of the fan-in node corresponding to that pin plus the line length delay times a factor. The arrival time of the output pins is the maximum of the arrival time of the input pins of the match gate plus the sum of their delays to the output pins. The arrival time of the input pin is expressed as arrival time (fanin driver pin), which represents the arrival time of the fan-in node connected with the input pin, wrie_delay represents the time delay of the line, estimated by Manhattan distance, and the arrival time of the input pin is calculated as shown in formula (9):
the arrival time of the output pin being arrival time (f) represents the arrival time of the ith input pin;
pin to pin delay represents the i-th input pin to output pin delay, and is determined by the attribute of the matching gate itself. The arrival time calculation formula of the output pins is shown as formula (10)
arrival time out＝max i∈input pin (arrival time(i)+pin to pin delay) (10)
After the total area and time delay of the gates are calculated, comparing the matched gate with the best matched gate of the current node, and if the area is smaller, updating the minimum matching of the area; if the arrival time is earlier, the delay best match is updated.
FIG. 6a illustrates a schematic diagram of an area-minimization-based process mapping method in which embodiments of the present invention may be implemented. G as shown in FIG. 6a 5 Is a four-input gate, the four inputs are g respectively 1 、g 2 、g 3 、g 4 . It can be seen in the embodiment shown in fig. 6a that g is the result of the mapping method based on area minimization using the prior art 5 G is present in four inputs of (2) 3 To g 5 Is a pin g 4 To g 5 Is a "long wire" of two connections to the other pin of (a).
FIG. 6b shows a schematic diagram of a remapping-based method in which embodiments of the invention may be implemented. As shown in FIG. 6b, g will be the time of the remapping process mapping method provided by the above embodiment of the present application 5 Is decomposed into g 6 、g 7 、g 8 Three logic gates. Wherein g 6 Connected to the original logic gate g 1 And original logic gate g 2 Applying; g 7 Connected to the original logic gate g 3 And original logic gate g 4 And (3) upper part. It can be seen from the embodiment shown in fig. 6b that the remapping method provided by the present application eliminates the presence of "long lines", the length of the connection between logic gates becomes smaller, and congestion is improved. The remapping method provided by the embodiment of the application can enable one toThe individual cells are connected with adjacent cells as much as possible, and the occurrence of a long line phenomenon can be avoided in subsequent wiring.
From the above embodiments, it can be seen that the incremental remapping method provided in the embodiments can alleviate local congestion and improve the routability. By minimizing congestion, time is improved. The incremental remapping method provided by the embodiment of the application integrates congestion minimization into the area and the time delay index, balances the influence among the area, the time delay and the congestion minimization, reduces the congestion under the condition of not damaging the time delay constraint, and only has a small part of area increase. The initial input of the new incremental remapping proposed by the incremental remapping method provided by the embodiment of the application is based on the result after wiring, so that the accuracy of congestion degree evaluation in the remapping process is improved, and the remapping result is more feasible.
While most embodiments of the present invention are intended for use in HDL design synthesis software programs, the present invention is not necessarily limited to such applications. Other languages and computer programs may be used (e.g., a computer program may be written to describe hardware such that the computer program may be considered an expression in HDL form and may be compiled, or in some embodiments, the invention may allocate and reallocate logical representations, e.g., netlists, created without using HDL), although embodiments of the invention are in use in HDL synthesis systems. As is well known, the target architecture is typically determined by the programmable IC vendor. One example of a target architecture is a programmable look-up table of an integrated circuit and associated logic. Other examples of target architectures/techniques include those well known in field programmable gate arrays and complex programmable logic devices. For certain embodiments, the invention may also be used in Application Specific Integrated Circuits (ASICs).
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Thus, it will be apparent to those skilled in the art that the functional modules/units or controllers and associated method steps set forth in the above embodiments may be implemented in software, hardware, and a combination of software/hardware.
The acts of the methods, procedures, or steps described in accordance with the embodiments of the present invention do not have to be performed in a specific order and still achieve desirable results unless explicitly stated. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Various embodiments of the invention are described herein, but for brevity, description of each embodiment is not exhaustive and features or parts of the same or similar between each embodiment may be omitted. Herein, "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that it is applicable to at least one embodiment or example, but not all embodiments, according to the present invention. The above terms are not necessarily meant to refer to the same embodiment or example. Those skilled in the art may combine and combine the features of the different embodiments or examples described in this specification and of the different embodiments or examples without contradiction.
The exemplary systems and methods of the present invention have been particularly shown and described with reference to the foregoing embodiments, which are merely examples of the best modes for carrying out the systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein in practicing the systems and/or methods without departing from the spirit and scope of the invention as defined in the following claims.
Claims (10)
1. A method of remapping based on a routability, comprising the steps of:
performing global layout on the whole netlist;
global wiring is carried out on the whole netlist;
extracting a sub-netlist of wiring congestion;
performing incremental remapping on the sub-netlist, and rewriting the sub-netlist by using the incremental remapping result;
performing incremental global layout on the rewritten sub-netlist;
and incremental global routing is carried out on the rewritten sub-netlist.
2. The routability based remapping method of claim 1, wherein a determination is made after the incremental global routing step as to whether there is a child netlist of routing congestion.
3. The routability based remapping method according to claim 1, wherein the incremental remapping comprises the steps of:
inputting a congested sub-netlist;
decomposing the congested sub-netlist into a NAND graph;
performing routability driven process mapping on the NAND graph to form a new netlist;
returning to the new netlist.
4. A routability based remapping method according to claim 3, wherein decomposing the congested sub-netlist into a nand graph comprises the steps of:
performing topological ordering on the nodes;
performing a prescribed operation on each node in the topology sequence;
judging whether the current node is the last node or not;
judging whether the current node has two inputs or not;
taking out two inputs of the current node and decomposing the two inputs to generate a new node;
connecting the output of the new node to the current node;
and calculating the position of the new node.
5. The method of re-mapping based on routability according to claim 4, characterized in that the steps of claim 4 are repeatedly performed with only two inputs to the current node.
6. A routability based remapping method according to claim 3, wherein the routability driven process map comprises the steps of:
calculating the cutting of the nodes from bottom to top;
calculating a truth table of the cut;
traversing each node from bottom to top;
judging whether the current node is the last node or not;
traversing each cut of the current node;
judging whether the current cutting is the last cutting or not;
traversing each gate that matches the current cut truth table;
judging whether the current matched gate is the last matched gate or not;
calculating the coordinates of the current matching gate;
calculating the area and the arrival time of the current matching gate;
updating the area and time delay matching gate of the current node;
the match gates for each node are selected top-down to cover the entire netlist.
7. The routability based remapping method of claim 6, wherein the coordinates of the matching gate are obtained by a center of gravity of a fan-in connection object and a fan-out connection object of the matching gate;
the fan-in connection object is a matched door of a fan-in node;
the fan-out connection object is a fan-out node.
8. The method of re-mapping based on routability according to claim 6, wherein the total area of the matching gate is the sum of the area of the matching gate and the area of the line length multiplied by a factor;
the area of the matching gate is the sum of the areas of the matching gates of the current matching gate and the fan-in node divided by the number of fan-out nodes;
the line length area is the sum of the distance between the matching gate of the fan-in node and the current matching gate and the line length area of the fan-in node divided by the fan-out number.
9. The routability based remapping method of claim 6, wherein matching gate arrival times includes: the arrival time of the input pin of the matching gate and the arrival time of the output pin of the matching gate;
the arrival time of the input pin is obtained through the arrival time of a fan-in node connected with the input pin and the time delay of a line;
the arrival time of the output pin is obtained by the arrival time of the input pin and the delay from the input pin to the output pin.
10. An integrated circuit, characterized in that the integrated circuit is configured to use the method of any of claims 1-9 when performing a process mapping operation.
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