CN116340210A - Communication method and device, communication bus circuit, control cabinet and readable storage medium - Google Patents

Communication method and device, communication bus circuit, control cabinet and readable storage medium Download PDF

Info

Publication number
CN116340210A
CN116340210A CN202310005748.XA CN202310005748A CN116340210A CN 116340210 A CN116340210 A CN 116340210A CN 202310005748 A CN202310005748 A CN 202310005748A CN 116340210 A CN116340210 A CN 116340210A
Authority
CN
China
Prior art keywords
clock signal
signal
communication
serial bus
communication chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310005748.XA
Other languages
Chinese (zh)
Inventor
陈陇飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KUKA Robot Manufacturing Shanghai Co Ltd
KUKA Robotics Guangdong Co Ltd
Original Assignee
KUKA Robot Manufacturing Shanghai Co Ltd
KUKA Robotics Guangdong Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KUKA Robot Manufacturing Shanghai Co Ltd, KUKA Robotics Guangdong Co Ltd filed Critical KUKA Robot Manufacturing Shanghai Co Ltd
Priority to CN202310005748.XA priority Critical patent/CN116340210A/en
Publication of CN116340210A publication Critical patent/CN116340210A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a communication method and device, a communication bus circuit, a control cabinet and a readable storage medium. The communication method comprises the following steps: the serial bus is applied to the serial bus, the serial bus comprises a master communication chip and at least one slave communication chip, and the communication method comprises the following steps: reducing the duty ratio of the clock signal of the serial bus to obtain a target clock signal; and controlling the serial bus to communicate according to the target clock signal so as to enable the data receiving and transmitting frequencies of the master communication chip and at least one slave communication chip to be consistent.

Description

Communication method and device, communication bus circuit, control cabinet and readable storage medium
Technical Field
The invention relates to the technical field of robots, in particular to a communication method and device, a communication bus circuit, a control cabinet and a readable storage medium.
Background
In the process of communication by the synchronous serial bus, a longer PCB (Printed Circuit Board ) trace is often arranged between the master communication chip and the slave communication chip, and in order to ensure the communication quality, a signal processing device such as a buffer, a filter, etc. needs to be arranged between the master communication chip and the slave communication chip. However, more signal processing devices and PCB traces may delay the timing signals of the communications, so that the MISO (Master Input Slave Output, master input and slave output) signals of the serial bus are not established for a sufficient time and cannot be correctly latched by the master communication chip, which reduces the communication rate of the serial bus.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art or related art.
To this end, a first aspect of the invention is directed to a communication method.
A second aspect of the present invention is directed to a communication device.
A third aspect of the present invention is directed to another communication apparatus.
A fourth aspect of the invention is directed to a communication bus circuit.
A fifth aspect of the present invention is directed to a control cabinet.
A sixth aspect of the invention is directed to a readable storage medium.
In view of this, according to one aspect of the present invention, there is provided a communication method applied to a serial bus including a master communication chip and at least one slave communication chip, the communication method including: reducing the duty ratio of the clock signal of the serial bus to obtain a target clock signal; and controlling the serial bus to communicate according to the target clock signal so as to enable the data receiving and transmitting frequencies of the master communication chip and at least one slave communication chip to be consistent.
The execution subject of the technical scheme of the communication method provided by the invention can be a communication bus circuit, a communication device or a determination according to actual use requirements, and is not particularly limited herein. In order to more clearly describe the communication method provided by the present invention, the following description will be made with the execution subject of the communication method as a communication device.
The communication method provided by the invention is used for controlling the serial bus to communicate, so that when the time sequence signal of the serial bus is delayed, the influence of the delay of the time sequence signal on the serial bus communication is reduced under the condition that the internal circuit structure of the serial bus is not changed, namely, the structures such as PCB wiring, a buffer, a filter and the like in the serial bus are not reduced, and the communication rate of the serial bus is improved.
The serial bus may be a synchronous serial bus, and the serial bus includes at least one slave communication chip and one master communication chip. In an actual application process, the serial bus may be a synchronous serial bus, such as an SPI (Serial Peripheral Interface ) bus, an I2C (Inter-Integrated Circuit) bus, etc., which requires a clock signal to participate in data transceiving and timing synchronization, which is not particularly limited herein.
Specifically, in the communication method provided by the invention, in the process of communication through the synchronous serial bus, the communication device adjusts the signal establishment time and the signal holding time of the clock signal of the serial bus in each signal period, thereby reducing the duty ratio of the clock signal and obtaining the target clock signal. On the basis, the communication device controls the slave communication chip and the master communication chip in the serial bus to synchronously communicate according to the target clock signal obtained after the duty ratio is adjusted so as to keep the data receiving and transmitting frequencies of the slave communication chip and the master communication chip consistent. In this way, the slave communication chip and the master communication chip in the serial bus are controlled to synchronously communicate by the target clock signal obtained after the signal duty ratio is reduced, on one hand, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal is ensured to be correctly latched by the master communication chip, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
The above communication method according to the present invention may further have the following additional technical features:
in the above technical solution, reducing the duty cycle of the clock signal of the serial bus includes: the set-up time of the clock signal is kept unchanged, and the hold time of the clock signal is reduced to reduce the duty cycle and the signal period of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus, the set-up time of the clock signal in each clock cycle can be kept unchanged, and only the hold time of the clock signal in each clock cycle is reduced. That is, the low-level duration of the clock signal in each clock cycle is kept unchanged, while the high-level duration of the clock signal in each signal cycle is only reduced. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is reduced when the period duration of the high level duration in each clock period of the clock signal is reduced to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
In any of the above solutions, reducing the duty cycle of the clock signal of the serial bus includes: in the case of keeping the signal period of the clock signal unchanged, the setup time of the clock signal is increased, and the hold time of the clock signal is reduced to reduce the duty ratio of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus, the method can particularly shorten the holding time of the clock signal in each clock period while prolonging the establishing time of the clock signal in each clock period on the premise of keeping the period duration of the clock signal unchanged. That is, the low level duration of the clock signal in each clock cycle is lengthened, and the high level duration of the clock signal in each signal cycle is shortened. In this way, the duty cycle of the clock signal is reduced, i.e. the duty cycle of the low level duration in each clock cycle of the clock signal is increased to the duration of the whole clock cycle. Therefore, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal can still be ensured to be correctly latched by the main communication chip, and the communication rate of the serial bus is improved.
In any of the above solutions, reducing the duty cycle of the clock signal of the serial bus includes: the signal period of the clock signal is reduced, and the setup time of the clock signal is increased, and the hold time of the clock signal is reduced to reduce the duty cycle of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus, the time for establishing the clock signal in each clock period can be prolonged, and the time for keeping the clock signal in each clock period can be shortened while the period duration of the clock signal is reduced. That is, on the premise of integrally reducing the period duration of the clock signal, the low-level duration of the clock signal in each clock period is prolonged, and the high-level duration of the clock signal in each signal period is shortened. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is shortened when the period duration of the low level duration in each clock period of the clock signal is increased to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
According to a second aspect of the present invention, there is provided a communication device applied to a serial bus including a master communication chip and at least one slave communication chip, the communication device comprising: the processing unit is used for reducing the duty ratio of the clock signal of the serial bus to obtain a target clock signal; and the communication unit is used for controlling the serial bus to communicate according to the target clock signal so as to keep the data receiving and transmitting frequencies of the master communication chip and at least one slave communication chip consistent.
The communication device provided by the invention is used for controlling the serial bus to communicate, so that when the time sequence signal of the serial bus is delayed, the influence of the delay of the time sequence signal on the serial bus communication is reduced under the condition that the internal circuit structure of the serial bus is not changed, namely, the structures such as PCB wiring, a buffer, a filter and the like in the serial bus are not reduced, and the communication rate of the serial bus is improved.
The serial bus may be a synchronous serial bus, and the serial bus includes at least one slave communication chip and one master communication chip. In the practical application process, the serial bus may be specifically a synchronous serial bus such as an SPI bus, an I2C bus, etc. that requires a clock signal to participate in data transceiving and timing synchronization, which is not limited herein.
Specifically, the communication device provided by the invention comprises a processing unit and a communication unit, wherein the processing unit adjusts the signal establishment time and the signal holding time of a clock signal of a synchronous serial bus in each signal period in the process of communication through the synchronous serial bus, so that the duty ratio of the clock signal is reduced, and a target clock signal is obtained. On the basis, the communication device controls the slave communication chip and the master communication chip in the serial bus to carry out synchronous communication according to the target clock signal obtained after the duty ratio is adjusted so as to keep the data receiving and transmitting frequencies of the slave communication chip and the master communication chip consistent. In this way, the slave communication chip and the master communication chip in the serial bus are controlled to synchronously communicate by the target clock signal obtained after the signal duty ratio is reduced, on one hand, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal is ensured to be correctly latched by the master communication chip, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
The above communication method according to the present invention may further have the following additional technical features:
in the above technical solution, the processing unit is specifically configured to: the set-up time of the clock signal is kept unchanged, and the hold time of the clock signal is reduced to reduce the duty cycle and the signal period of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus by the processing unit, the establishment time of the clock signal in each clock cycle can be kept unchanged, and the reduction processing is only carried out on the maintenance time of the clock signal in each clock cycle. That is, the processing unit keeps the low-level duration of the clock signal in each clock cycle unchanged, and only reduces the high-level duration of the clock signal in each signal cycle. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is reduced when the period duration of the high level duration in each clock period of the clock signal is reduced to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
In any of the above technical solutions, the processing unit is specifically configured to: in the case of keeping the signal period of the clock signal unchanged, the setup time of the clock signal is increased, and the hold time of the clock signal is reduced to reduce the duty ratio of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus by the processing unit, the time for establishing the clock signal in each clock period is prolonged and the time for keeping the clock signal in each clock period is shortened on the premise of keeping the period duration of the clock signal unchanged. That is, the processing unit lengthens the low-level duration of the clock signal in each clock cycle, and shortens the high-level duration of the clock signal in each signal cycle. In this way, the processing unit reduces the duty ratio of the clock signal, that is, increases the duty ratio of the low level duration in each clock cycle of the clock signal to the duration of the whole clock cycle. Therefore, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal can still be ensured to be correctly latched by the main communication chip, and the communication rate of the serial bus is improved.
In any of the above technical solutions, the processing unit is specifically configured to: the signal period of the clock signal is reduced, and the setup time of the clock signal is increased, and the hold time of the clock signal is reduced to reduce the duty cycle of the clock signal.
In the technical scheme, in the process of reducing the duty ratio of the clock signal of the serial bus by the processing unit, the time for establishing the clock signal in each clock period can be prolonged and the time for keeping the clock signal in each clock period can be shortened while the period duration of the clock signal is reduced. That is, the processing unit lengthens the low-level duration of the clock signal in each clock period and shortens the high-level duration of the clock signal in each signal period on the premise of integrally reducing the period duration of the clock signal. In this way, the processing unit reduces the duty ratio of the clock signal, that is, shortens the period duration of the clock signal while increasing the duty ratio of the low level duration in each clock period of the clock signal to the duration of the whole clock period, and can further reduce the influence of time sequence signal delay on communication, thereby improving the communication rate of the serial bus.
According to a third aspect of the present invention, there is provided another communication apparatus comprising: a memory storing a program or instructions; a processor, wherein the processor executes the program or instructions to implement the steps of the communication method as described in any of the above claims. Therefore, the communication device according to the third aspect of the present invention has all the advantages of the communication method according to any one of the first aspect, and will not be described herein.
According to a fourth aspect of the present invention, there is provided a communication bus circuit comprising: the communication device in the third aspect; a main communication chip; at least one slave communication chip connected with the master communication chip through a communication device; and the signal processing circuit is arranged between the master communication chip and the at least one slave communication chip and is used for processing communication signals of the master communication chip and the at least one slave communication chip.
A fourth aspect of the present invention provides a communication bus circuit including the communication device according to the third aspect. Therefore, the communication bus circuit according to the fourth aspect of the present invention has all the advantages of the communication device according to the third aspect, and will not be described herein.
In the working process of the communication bus circuit, the communication device adjusts the duty ratio of the clock signal of the master communication chip to reduce the duty ratio of the clock signal, obtain a target clock signal, and then control the slave communication chip and the master communication chip in the serial bus to carry out synchronous communication according to the target clock signal obtained after the duty ratio is adjusted, so that the data receiving and transmitting frequencies of the slave communication chip and the master communication chip are kept consistent. In this way, the slave communication chip and the master communication chip in the serial bus are controlled to synchronously communicate by the target clock signal obtained after the signal duty ratio is reduced, on one hand, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal is ensured to be correctly latched by the master communication chip, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
According to a fifth aspect of the present invention, there is provided a control cabinet comprising: the communication bus circuit in the fourth aspect. A control cabinet according to a fifth aspect of the present invention includes the communication bus circuit in the fourth aspect. Therefore, the control cabinet according to the fifth aspect of the present invention has all the advantages of the communication bus circuit in the fourth aspect, and will not be described herein.
According to a sixth aspect of the present invention, there is provided a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement a communication method as in any of the above-mentioned aspects. Therefore, the readable storage medium according to the sixth aspect of the present invention has all the advantages of the communication method according to any one of the first aspect, and will not be described herein.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 shows one of the flow diagrams of a communication method of an embodiment of the present invention;
FIG. 2 is a second flow chart of a communication method according to an embodiment of the invention;
FIG. 3 is a third flow chart of a communication method according to an embodiment of the invention;
FIG. 4 shows a fourth flow chart of a communication method according to an embodiment of the present invention;
FIG. 5 shows one of the schematic diagrams of the communication method of an embodiment of the present invention;
FIG. 6 shows a second schematic diagram of a communication method according to an embodiment of the present invention;
FIG. 7 shows a third schematic diagram of a communication method of an embodiment of the present invention;
FIG. 8 shows a fourth schematic diagram of a communication method of an embodiment of the present invention;
FIG. 9 shows a fifth schematic diagram of a communication method of an embodiment of the present invention;
FIG. 10 is a diagram showing a communication method according to an embodiment of the present invention
Fig. 11 shows one of the block diagrams of the communication apparatus of the embodiment of the present invention;
FIG. 12 shows a second block diagram of a communication device according to an embodiment of the present invention;
FIG. 13 shows a block diagram of a communication bus circuit of an embodiment of the invention;
fig. 14 shows a block diagram of a control cabinet according to an embodiment of the invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present invention and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and the scope of the invention is therefore not limited to the specific embodiments disclosed below.
The following describes in detail, with reference to fig. 1 to 14, a communication method and apparatus, a communication bus circuit, a control cabinet, and a readable storage medium provided in the embodiments of the present application through specific embodiments and application scenarios thereof.
In one embodiment of the present invention, as shown in fig. 1, the communication method may specifically include the following steps 102 and 104:
step 102, reducing the duty ratio of a clock signal of a serial bus to obtain a target clock signal;
step 104, controlling the serial bus to communicate according to the target clock signal.
The communication method provided by the invention is used for controlling the serial bus to communicate, so that when the time sequence signal of the serial bus is delayed, the influence of the delay of the time sequence signal on the serial bus communication is reduced under the condition that the internal circuit structure of the serial bus is not changed, namely, the structures such as PCB wiring, a buffer, a filter and the like in the serial bus are not reduced, and the communication rate of the serial bus is improved.
The serial bus may be a synchronous serial bus, and the serial bus includes at least one slave communication chip and one master communication chip. In the practical application process, the serial bus may be specifically a synchronous serial bus such as an SPI bus, an I2C bus, etc. that requires a clock signal to participate in data transceiving and timing synchronization, which is not limited herein.
Specifically, in the communication method provided by the invention, in the process of communication through the synchronous serial bus, the communication device adjusts the signal establishment time and the signal holding time of the clock signal of the serial bus in each signal period, thereby reducing the duty ratio of the clock signal and obtaining the target clock signal. On the basis, the communication device controls the slave communication chip and the master communication chip in the serial bus to synchronously communicate according to the target clock signal obtained after the duty ratio is adjusted so as to keep the data receiving and transmitting frequencies of the slave communication chip and the master communication chip consistent.
It will be appreciated that in the process of synchronous communication through the synchronous serial bus, as shown in fig. 8, the master communication chip is provided with an SCK signal generating port, a MOSI (Master Output Slave Input, master output-slave input) port and a MISO port, and the slave communication chip is also provided with an SCK signal receiving port, a MOSI port and a MISO port. Further, a longer PCB trace is provided between the master communication chip and the slave communication chip, and in order to ensure that the master communication chip and the slave communication chip are compatible with each other in the communication process, a buffer and a filter are often provided between the master communication chip and the slave communication chip, so as to perform processing such as filtering on communication signals between the master communication chip and the slave communication chip.
On the basis, in the process of communication through the synchronous serial bus, the master communication chip is an initiator of communication, and the master communication chip can send clock signals to the slave communication chip, so that the slave communication chip regularly outputs communication signals to the master communication chip according to the clock signals of the master communication chip and corresponding time sequences. In the master communication chip, the MOSI port is a signal output port, the MISO port is a signal input port, and in the slave communication chip, the MOSI port is a signal input port, and the MISO port is a signal output port. Specifically, in the process of communication through the synchronous serial bus, as shown in fig. 9, at each falling edge of the SCK signal, the master communication chip and the slave communication chip output data signals in the role of the sender, and at the next rising edge of the SCK signal, the master communication chip and the slave communication chip act as receivers of the data signals and latch the data signals on the MISO port and the MOSI port, respectively, so that synchronous communication between the master communication chip and the slave communication chip is realized.
However, in the practical application process, as shown in fig. 10, because a longer PCB trace, a buffer, a filter, and other devices are disposed between the master communication chip and the slave communication chip, a delay occurs in the timing signal of the communication, so that a phase difference, i.e., a time difference, occurs between the MISO signal and the MOSI signal. In particular, the delay of the MISO signal with respect to the SCK signal is more serious than that of the MOSI signal, resulting in a problem that the setup time of the MISO signal is insufficient at the rising edge of the SCK signal. It will be appreciated that the set-up time of the MISO signal is more stringent for the master communication chip than for the MISO signal. In the case that the MISO signal is delayed with respect to the SCK signal, as shown in fig. 10, the set-up time T of the MISO signal corresponding to the rising edge of the SCK signal is delayed and compressed, and when the set-up time T after the delay and compression is smaller than the shortest set-up time required by the master communication chip, the MISO signal cannot be correctly latched by the master communication chip, thereby limiting the communication rate of the serial bus.
Therefore, in the communication method proposed by the present invention, the time-duration duty ratio of the signal setup time of the clock signal in each signal period to the entire signal period is increased by decreasing the duty ratio of the clock signal in each signal period. In this way, under the condition that the time sequence signal of the serial bus for communication is delayed, namely under the condition that the MISO signal is delayed relative to the clock signal, even if the establishment time of the MISO signal corresponding to the rising edge of the SCK signal is delayed and compressed, the signal establishment time after the delay and compression still can meet the minimum requirement of the main communication chip on the establishment time, thereby ensuring that the MISO signal can be correctly latched by the main communication chip and ensuring the communication rate of the serial bus.
In summary, according to the communication method provided by the invention, the slave communication chip and the master communication chip in the serial bus are controlled to perform synchronous communication by the target clock signal obtained after the signal duty ratio is reduced, so that on one hand, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal is ensured to be correctly latched by the master communication chip, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
In an embodiment of the present invention, further, as shown in fig. 2, the step 102 may specifically include the following step 102a:
step 102a, keeping the set-up time of the clock signal of the serial bus unchanged, and reducing the hold time of the clock signal to obtain the target clock signal.
In this embodiment, in reducing the duty ratio of the clock signal of the serial bus, the setup time of the clock signal in each clock cycle may be kept unchanged, and only the hold time of the clock signal in each clock cycle is subjected to the reduction process. That is, the low-level duration of the clock signal in each clock cycle is kept unchanged, while the high-level duration of the clock signal in each signal cycle is only reduced. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is reduced when the period duration of the high level duration in each clock period of the clock signal is reduced to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
Specifically, as shown in fig. 5, the original clock signal SCK is maintained 1 The duration of the low level in each clock cycle is unchanged, reducing the original clock signal SCK 1 The duration of the high level in each signal period is reduced to reduce the original clock signal SCK 1 Duty cycle and period length of (a) to obtain a new clock signal SCK 2 . On the basis of this, the MISO signal is delayed relative to the clock signal to become MISO delay In the case of signals, corresponding to clock signal SCK 2 The signal setup time T of the rising edge still meets the minimum requirement of the main communication chip on the setup time after being delayed and compressed, thereby ensuring MISO delay The signal can be correctly latched by the main communication chip, so that the communication rate of the serial bus is ensured.
For an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, with the low-level duration and the high-level duration each occupying 100ns in each signal period. On the basis of this, the communication device adjusts the duty ratio of the SCK signal, specifically, the communication device maintains the low-level duration in each signal period to be constant at 100ns, and reduces the high-level duration in each signal period to be 25ns. At this time, the signal period of the SCK signal becomes 125ns, and the signal frequency of the SCK signal becomes 8MHz, which is 3MHz higher than the previous signal frequency.
In an embodiment of the present invention, further, as shown in fig. 3, the step 102 may specifically include the following step 102b:
step 102b, keeping the signal period of the clock signal of the serial bus unchanged, increasing the setup time of the clock signal, and decreasing the hold time of the clock signal to obtain the target clock signal.
In this embodiment, in the process of reducing the duty ratio of the clock signal of the serial bus, the hold time of the clock signal in each clock cycle can be shortened while the setup time of the clock signal in each clock cycle is prolonged, with the period duration of the clock signal maintained unchanged. That is, the low level duration of the clock signal in each clock cycle is lengthened, and the high level duration of the clock signal in each signal cycle is shortened. In this way, the duty cycle of the clock signal is reduced, i.e. the duty cycle of the low level duration in each clock cycle of the clock signal is increased to the duration of the whole clock cycle. Therefore, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal can still be ensured to be correctly latched by the main communication chip, and the communication rate of the serial bus is improved.
Specifically, as shown in fig. 6, the original clock signal SCK is maintained 1 The period duration of (1) is unchanged, the original clock signal SCK is increased 1 Low duration in each clock cycle and reduced raw clock signal SCK 1 The duration of the high level in each signal period is reduced to reduce the original clock signal SCK 1 To obtain a new clock signal SCK 3 . On the basis of this, the MISO signal is delayed relative to the clock signal to become MISO delay In the case of signals, corresponding to clock signal SCK 3 The signal setup time T of the rising edge still meets the minimum requirement of the main communication chip on the setup time after being delayed and compressed, thereby ensuring MISO delay The signal can be correctly latched by the main communication chip, so that the communication rate of the serial bus is ensured.
For an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, with the low-level duration and the high-level duration each occupying 100ns in each signal period. On the basis of this, the communication device adjusts the duty ratio of the SCK signal, specifically, the communication device lengthens the low-level duration in each signal period to 150ns and shortens the high-level duration in each signal period to 50ns. At this time, the signal period of the SCK signal is still 200ns, but the duty ratio of the SCK signal is reduced, so that the influence of time sequence signal delay on communication can be reduced, and the communication rate of the serial bus is ensured.
In an embodiment of the present invention, further, as shown in fig. 4, the step 102 may specifically include the following step 102c:
step 102c, decreasing the signal period of the clock signal, increasing the setup time of the clock signal, and decreasing the hold time of the clock signal to obtain the target clock signal.
In this embodiment, in reducing the duty cycle of the clock signal of the serial bus, it is possible to lengthen the setup time of the clock signal in each clock cycle and shorten the hold time of the clock signal in each clock cycle, while specifically reducing the period duration of the clock signal. That is, on the premise of integrally reducing the period duration of the clock signal, the low-level duration of the clock signal in each clock period is prolonged, and the high-level duration of the clock signal in each signal period is shortened. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is shortened when the period duration of the low level duration in each clock period of the clock signal is increased to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
Specifically, as shown in fig. 7, the original clock signal SCK is shortened 1 While increasing the period duration of the original clock signal SCK 1 Low duration in each clock cycle and reduced raw clock signal SCK 1 The duration of the high level in each signal period is reduced to reduce the original clock signal SCK 1 Is a new clock signal SCK 4 . On the basis of this, the MISO signal is delayed relative to the clock signal to become MISO delay In the case of signals, corresponding to clock signal SCK 4 The signal setup time T of the rising edge still meets the minimum requirement of the main communication chip on the setup time after being delayed and compressed, thereby ensuring MISO delay The signal can be correctly latched by the main communication chip, so that the communication rate of the serial bus is ensured.
For an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, with the low-level duration and the high-level duration each occupying 100ns in each signal period. On the basis of this, the communication device adjusts the duty ratio of the SCK signal, specifically, the communication device lengthens the low-level duration in each signal period to 110ns and shortens the high-level duration in each signal period to 15ns. At this time, the signal period of the SCK signal becomes 125ns, and the signal frequency of the SCK signal becomes 8MHz, which is 3MHz higher than the previous signal frequency.
In one embodiment of the present invention, a communication apparatus is also presented. As shown in fig. 11, fig. 11 shows a block diagram of a communication apparatus 1100 according to an embodiment of the present invention. The communication device 1100 may specifically include the following processing unit 1102 and communication unit 1104:
a processing unit 1102, configured to reduce a duty cycle of a clock signal of the serial bus to obtain a target clock signal;
and a communication unit 1104 for controlling the serial bus to communicate according to the target clock signal so as to keep the data transceiving frequencies of the master communication chip and the at least one slave communication chip consistent.
The communication device 1100 provided by the embodiment of the invention is used for controlling the serial bus to communicate, so that when the time sequence signal of the serial bus is delayed, the influence of the delay of the time sequence signal on the serial bus communication is reduced under the condition that the internal circuit structure of the serial bus is not changed, namely, the structures of a PCB (printed circuit board), a buffer, a filter and the like in the serial bus are not reduced, and the communication rate of the serial bus is improved.
The serial bus may be a synchronous serial bus, and the serial bus includes at least one slave communication chip and one master communication chip. In the practical application process, the serial bus may be specifically a synchronous serial bus such as an SPI bus, an I2C bus, etc. that requires a clock signal to participate in data transceiving and timing synchronization, which is not limited herein.
Specifically, the communication device 1100 provided by the present invention includes a processing unit 1102 and a communication unit 1104, where in the process of communicating through a synchronous serial bus, the processing unit 1102 adjusts the signal setup time and the signal hold time of the clock signal of the serial bus in each signal period, so as to reduce the duty ratio of the clock signal, and obtain the target clock signal. Based on this, the communication unit 1104 controls the slave communication chip and the master communication chip in the serial bus to perform synchronous communication according to the target clock signal obtained after the duty ratio is adjusted, so that the data transmission/reception frequencies of the slave communication chip and the master communication chip are kept consistent.
It can be understood that in the process of synchronous communication through the synchronous serial bus, the master communication chip is provided with an SCK signal generating port, a MOSI port and a MISO port, and the slave communication chip is also provided with an SCK signal receiving port, a MOSI port and a MISO port. Further, a longer PCB trace is provided between the master communication chip and the slave communication chip, and in order to ensure that the master communication chip and the slave communication chip are compatible with each other in the communication process, a buffer and a filter are often provided between the master communication chip and the slave communication chip, so as to perform processing such as filtering on communication signals between the master communication chip and the slave communication chip.
On the basis, in the process of communication through the synchronous serial bus, the master communication chip is an initiator of communication, and the master communication chip can send clock signals to the slave communication chip, so that the slave communication chip regularly outputs communication signals to the master communication chip according to the clock signals of the master communication chip and corresponding time sequences. In the master communication chip, the MOSI port is a signal output port, the MISO port is a signal input port, and in the slave communication chip, the MOSI port is a signal input port, and the MISO port is a signal output port. Specifically, in the process of communication through the synchronous serial bus, at each falling edge of the SCK signal, the master communication chip and the slave communication chip output data signals in the role of a sender, and at the next rising edge of the SCK signal, the master communication chip and the slave communication chip serve as receivers of the data signals and latch the data signals on the MISO port and the MOSI port respectively, so that synchronous communication between the master communication chip and the slave communication chip is realized.
However, in the practical application process, because the devices such as the longer PCB trace, the buffer, the filter and the like are arranged between the master communication chip and the slave communication chip, the time sequence signal of the communication is delayed, so that the phase difference, that is, the time difference, occurs between the MISO signal and the MOSI signal. In particular, the delay of the MISO signal with respect to the SCK signal is more serious than that of the MOSI signal, resulting in a problem that the setup time of the MISO signal is insufficient at the rising edge of the SCK signal. It will be appreciated that the set-up time of the MISO signal is more stringent for the master communication chip than for the MISO signal. Under the condition that the MISO signal is delayed relative to the SCK signal, the setup time of the MISO signal corresponding to the rising edge of the SCK signal is delayed and compressed, and when the setup time after the delay and compression is smaller than the shortest setup time required by the main communication chip, the MISO signal cannot be correctly latched by the main communication chip, so that the communication rate of the serial bus is limited.
Therefore, the communication device 1100 according to the present invention increases the duty ratio of the signal setup time of the clock signal in each signal period to the whole signal period by the processing unit 1102 decreasing the duty ratio of the clock signal in each signal period. In this way, under the condition that the time sequence signal of the serial bus for communication is delayed, namely under the condition that the MISO signal is delayed relative to the clock signal, even if the establishment time of the MISO signal corresponding to the rising edge of the SCK signal is delayed and compressed, the signal establishment time after the delay and compression still can meet the minimum requirement of the main communication chip on the establishment time, thereby ensuring that the MISO signal can be correctly latched by the main communication chip and ensuring the communication rate of the serial bus.
In summary, in the communication device 1100 provided by the present invention, the slave communication chip and the master communication chip in the serial bus are controlled to perform synchronous communication by the target clock signal obtained after the signal duty ratio is reduced, on one hand, under the condition that the time sequence signal of the serial bus for communication is delayed, it is ensured that the communication signal can be correctly latched by the master communication chip, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
In the embodiment of the present invention, further, the processing unit 1102 is specifically configured to: the set-up time of the clock signal of the serial bus is kept unchanged, and the hold time of the clock signal is reduced to obtain a target clock signal.
In this embodiment, during the process of the processing unit 1102 reducing the duty ratio of the clock signal of the serial bus, the setup time of the clock signal in each clock cycle may be kept unchanged, and only the hold time of the clock signal in each clock cycle is subjected to the reduction process. That is, the processing unit 1102 keeps the low-level duration of the clock signal in each clock cycle unchanged, and only reduces the high-level duration of the clock signal in each signal cycle. Therefore, the duty ratio of the clock signal is reduced, namely, the period duration of the clock signal is shortened while the period duration of the clock signal is reduced when the period duration of the high level duration in each clock period of the clock signal is reduced to occupy the period duration of the whole clock period, so that the influence of time sequence signal delay on communication can be further reduced, and the communication rate of the serial bus is improved.
For example, for an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, wherein the low level duration and the high level duration each occupy 100ns in each signal period. On this basis, the processing unit 1102 adjusts the duty cycle of the SCK signal, specifically, the processing unit 1102 maintains the low-level duration in each signal period to be constant at 100ns, and reduces the high-level duration in each signal period to be 25ns. At this time, the signal period of the SCK signal becomes 125ns, and the signal frequency of the SCK signal becomes 8MHz, which is 3MHz higher than the previous signal frequency.
In the embodiment of the present invention, further, the processing unit 1102 is specifically configured to: the signal period of the clock signal of the serial bus is kept unchanged, the set-up time of the clock signal is increased, and the holding time of the clock signal is reduced, so that the target clock signal is obtained.
In this embodiment, in the process of the processing unit 1102 reducing the duty ratio of the clock signal of the serial bus, the hold time of the clock signal in each clock cycle may be shortened while the setup time of the clock signal in each clock cycle is prolonged, with the period duration of the clock signal maintained unchanged. That is, the processing unit 1102 lengthens the low-level period of the clock signal in each clock cycle, and shortens the high-level period of the clock signal in each signal cycle. In this way, the processing unit 1102 decreases the duty cycle of the clock signal, that is, increases the duty cycle of the low-level duration of each clock cycle of the clock signal over the whole clock cycle. Therefore, under the condition that the time sequence signal of the serial bus for communication is delayed, the communication signal can still be ensured to be correctly latched by the main communication chip, and the communication rate of the serial bus is improved.
For an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, with the low-level duration and the high-level duration each occupying 100ns in each signal period. On this basis, the processing unit 1102 adjusts the duty ratio of the SCK signal, specifically, the processing unit 1102 lengthens the low-level duration in each signal period to 150ns and shortens the high-level duration in each signal period to 50ns. At this time, the signal period of the SCK signal is still 200ns, but the duty ratio of the SCK signal is reduced, so that the influence of time sequence signal delay on communication can be reduced, and the communication rate of the serial bus is ensured.
In the embodiment of the present invention, further, the processing unit 1102 is specifically configured to: the signal period of the clock signal is reduced, the set-up time of the clock signal is increased, and the hold time of the clock signal is reduced to obtain the target clock signal.
In this embodiment, in the process of the processing unit 1102 reducing the duty cycle of the clock signal of the serial bus, the setup time of the clock signal in each clock cycle may be prolonged, and the hold time of the clock signal in each clock cycle may be shortened, while the period duration of the clock signal is reduced. That is, the processing unit 1102 lengthens the low-level duration of the clock signal in each clock cycle and shortens the high-level duration of the clock signal in each signal cycle on the premise of reducing the cycle duration of the clock signal as a whole. In this way, the processing unit 1102 reduces the duty ratio of the clock signal, that is, reduces the period duration of the clock signal while increasing the duty ratio of the low level duration in each clock period of the clock signal to the duration of the whole clock period, and can further reduce the influence of the delay of the timing signal on communication, thereby improving the communication rate of the serial bus.
For an SCK signal with a signal frequency of 5MHz, the signal period of the SCK signal is 200ns, with the low-level duration and the high-level duration each occupying 100ns in each signal period. On this basis, the processing unit 1102 adjusts the duty ratio of the SCK signal, specifically, the processing unit 1102 lengthens the low-level duration in each signal period to 110ns and shortens the high-level duration in each signal period to 15ns. At this time, the signal period of the SCK signal becomes 125ns, and the signal frequency of the SCK signal becomes 8MHz, which is 3MHz higher than the previous signal frequency.
In one embodiment of the present invention, another communication apparatus is also presented. As shown in fig. 12, fig. 12 shows a block diagram of a communication apparatus 1200 according to an embodiment of the present invention. Wherein, this communication device 1200 includes:
a memory 1202, the memory 1202 having stored thereon programs or instructions;
the processor 1204, when executing the program or instructions, implements the steps of the communication method in any of the embodiments described above.
The communication device 1200 provided in this embodiment includes a memory 1202 and a processor 1204, and when the program or the instructions in the memory 1202 are executed by the processor 1204, the steps of the communication method in any of the above embodiments are implemented, so that the communication device 1200 has all the advantages of the communication method in any of the above embodiments, which are not described herein.
In particular, the memory 1202 and the processor 1204 may be connected by a bus or other means. The processor 1204 may include one or more processing units, and the processor 1204 may be a chip such as a central processing unit (Central Processing Unit, CPU), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA), or the like.
In one embodiment of the invention, a communication bus circuit is also presented. As shown in fig. 13, fig. 13 shows a block diagram of a communication bus circuit 1300 according to an embodiment of the present invention. The communication bus circuit 1300 includes the communication device 1200, the master communication chip 1302, at least one slave communication chip 1304, and the signal processing circuit 1306 in the above embodiments.
The communication bus circuit 1300 according to the fourth embodiment of the present invention includes the communication device 1200 according to the third embodiment. Thus, the fourth aspect of the invention is provided by embodiments
The communication bus circuit 1300 of (a) has all the technical effects of the communication device 1200 in the above embodiment, and 5 is not described herein.
Further, at least one slave communication chip 1304 is connected to the master communication chip 1302 via the communication device 1200, and a signal processing circuit 1306 is disposed between the master communication chip 1302 and the at least one slave communication chip 1304, where the signal processing circuit 1306 is configured to process communication signals of the master communication chip 1302 and the at least one slave communication chip 1304.
0 during the operation of the communication bus circuit 1300, the communication device 1200 adjusts the duty ratio of the clock signal of the master communication chip 1302 to reduce the duty ratio of the clock signal, obtain the target clock signal, and further control the slave communication chip 1304 and the master communication chip 1302 to perform synchronous communication according to the target clock signal obtained after the duty ratio is adjusted, so that the slave communication chip 1304 and the master communication chip
The data transmission/reception frequency of 1302 is kept uniform. In this way, the slave communication chip 1304 and the master communication chip 1302 are controlled to perform synchronous communication by the target 5 clock signal obtained by reducing the signal duty ratio, and one of them
In the case that the time sequence signal of the serial bus for communication is delayed, the communication signal is ensured to be correctly latched by the main communication chip 1302, and the communication rate of the serial bus is improved; on the other hand, the influence of the time sequence signal delay on communication is reduced only by reducing the duty ratio of the clock signal, and the internal structure of the serial bus is not required to be adjusted, so that the hardware cost of the serial bus is reduced.
0 in one embodiment of the invention, a control cabinet is also presented. As shown in fig. 14, fig. 14 shows a block diagram of a control cabinet 1400 provided by an embodiment of the present invention. Wherein the control cabinet 1400 includes the communication bus circuit 1300 in the fourth aspect embodiment described above.
The control cabinet 1400 according to the fifth aspect of the present invention includes the fourth embodiment
The communication bus circuit 1300 of (a). Therefore, the control cabinet 1400,5 according to the fifth aspect of the present invention has all the advantages of the communication bus circuit 1300 according to the fourth embodiment, here
And will not be described in detail.
An embodiment of a sixth aspect of the present invention proposes a readable storage medium. On which a program or instructions is stored which, when executed by a processor, implement the steps of the communication method as in any of the embodiments described above.
The readable storage medium according to the embodiments of the present invention may implement the steps of the communication method according to any of the embodiments described above when the stored program or instructions are executed by the processor. Therefore, the readable storage medium has all the advantages of the communication method in any of the above embodiments, and will not be described herein.
In particular, the above-described readable storage medium may include any medium capable of storing or transmitting information. Examples of readable storage media include electronic circuitry, semiconductor Memory devices, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), compact-disk Read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), flash Memory, erasable ROM (EROM), magnetic tape, floppy disk, optical disk, hard disk, fiber optic media, radio Frequency (RF) links, optical data storage devices, and the like. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
In the description of the present specification, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance unless explicitly specified and limited otherwise; the terms "coupled," "mounted," "secured," and the like are to be construed broadly, and may be fixedly coupled, detachably coupled, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, the terms "one embodiment," "some embodiments," "particular embodiments," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the technical solutions, and when the technical solutions are contradictory or cannot be implemented, the combination of the technical solutions should be considered as not existing, and not falling within the scope of protection claimed by the present invention.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A communication method applied to a serial bus including a master communication chip and at least one slave communication chip, the communication method comprising:
reducing the duty ratio of the clock signal of the serial bus to obtain a target clock signal;
and controlling the serial bus to communicate according to the target clock signal so as to keep the data receiving and transmitting frequencies of the master communication chip and the at least one slave communication chip consistent.
2. The communication method according to claim 1, wherein the reducing the duty cycle of the clock signal of the serial bus comprises:
the set-up time of the clock signal is kept unchanged, and the hold time of the clock signal is reduced to reduce the duty cycle and the signal period of the clock signal.
3. The communication method according to claim 1, wherein the reducing the duty cycle of the clock signal of the serial bus comprises:
Increasing the setup time of the clock signal and decreasing the hold time of the clock signal to decrease the duty cycle of the clock signal while keeping the signal period of the clock signal unchanged.
4. A communication method according to any one of claims 1 to 3, wherein said reducing the duty cycle of the clock signal of the serial bus comprises:
decreasing the signal period of the clock signal and increasing the setup time of the clock signal, and decreasing the hold time of the clock signal to decrease the duty cycle of the clock signal.
5. A communication device, characterized by being applied to a serial bus including a master communication chip and at least one slave communication chip, the communication device comprising:
the processing unit is used for reducing the duty ratio of the clock signal of the serial bus to obtain a target clock signal;
and the communication unit is used for controlling the serial bus to communicate according to the target clock signal so as to keep the data receiving and transmitting frequencies of the master communication chip and the at least one slave communication chip consistent.
6. The communication device according to claim 5, wherein the processing unit is specifically configured to:
The set-up time of the clock signal is kept unchanged, and the hold time of the clock signal is reduced to reduce the duty cycle and the signal period of the clock signal.
7. The communication device according to claim 5, wherein the processing unit is specifically configured to:
increasing the setup time of the clock signal and decreasing the hold time of the clock signal to decrease the duty cycle of the clock signal while keeping the signal period of the clock signal unchanged.
8. The communication device according to any of the claims 5 to 7, characterized in that the processing unit is specifically configured to:
decreasing the signal period of the clock signal and increasing the setup time of the clock signal, and decreasing the hold time of the clock signal to decrease the duty cycle of the clock signal.
9. A communication device, comprising:
a memory storing a program or instructions;
a processor which when executing the program or instructions carries out the steps of the communication method according to any one of claims 1 to 4.
10. A communication bus circuit, comprising:
the communication device of claim 9;
A main communication chip;
at least one slave communication chip connected to the master communication chip through the communication device;
and the signal processing circuit is arranged between the master communication chip and the at least one slave communication chip and is used for processing communication signals of the master communication chip and the at least one slave communication chip.
11. A control cabinet, characterized by comprising:
the communication bus circuit of claim 10.
12. A readable storage medium having stored thereon a program or instructions, which when executed by a processor, implement the steps of the communication method according to any of claims 1 to 4.
CN202310005748.XA 2023-01-04 2023-01-04 Communication method and device, communication bus circuit, control cabinet and readable storage medium Pending CN116340210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310005748.XA CN116340210A (en) 2023-01-04 2023-01-04 Communication method and device, communication bus circuit, control cabinet and readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310005748.XA CN116340210A (en) 2023-01-04 2023-01-04 Communication method and device, communication bus circuit, control cabinet and readable storage medium

Publications (1)

Publication Number Publication Date
CN116340210A true CN116340210A (en) 2023-06-27

Family

ID=86879704

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310005748.XA Pending CN116340210A (en) 2023-01-04 2023-01-04 Communication method and device, communication bus circuit, control cabinet and readable storage medium

Country Status (1)

Country Link
CN (1) CN116340210A (en)

Similar Documents

Publication Publication Date Title
EP3414668A1 (en) Multiprotocol i3c common command codes
US20170041086A1 (en) Data transmission apparatus for changing clock signal at runtime and data interface system including the same
WO2017065923A1 (en) Methods to avoid i2c void message in i3c
JP2008535334A (en) Method and apparatus for transmitting a sequence of transmission bursts
US8718116B2 (en) Scheduled gain control in collocated wireless receivers using forward timed signal strength predictions
JPWO2012132217A1 (en) CAN communication system, CAN transmission device, CAN reception device, and CAN communication method
CN101604182A (en) Automatically adjust the method and the clock frequency regulating circuit of clock frequency
CN116340210A (en) Communication method and device, communication bus circuit, control cabinet and readable storage medium
CN112585913A (en) Communication device, communication method, and communication program
CN108429597A (en) Electronic equipment, method for synchronizing time and module
US7432770B2 (en) Signal transmission device
US7489915B2 (en) Squelch circuit and communication apparatus used with the same
US20100080332A1 (en) Clock-synchronous communication apparatus and communication system
US8605744B2 (en) Semiconductor integrated circuit device
JP2007274028A (en) Preemphasis adjustment system
CN110221996B (en) Controller configuration method and device in main control chip
US7058149B2 (en) System for providing a calibrated clock and methods thereof
CN113204514B (en) Method for improving SPI interface frequency of chip
US7882384B2 (en) Setting and minimizing a derived clock frequency based on an input time interval
US7555669B2 (en) Timing vector program mechanism
US7184361B2 (en) Method and apparatus for avoiding bi-directional signal fighting of serial interface
CN112737573A (en) Clock skew calibration system, method and equipment based on daisy chain and computer storage medium
JP3097688B2 (en) Image output device controller, image output device, and method of controlling image output device
CN215416438U (en) CPU clock adjusting circuit and system based on hardware implementation
US20080002479A1 (en) Data transfer system and data processing apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination