CN116340201A - Thread storage position allocation method, device, chip, device and storage medium - Google Patents

Abstract

The present invention relates to the field of memory data processing technologies, and in particular, to a method, an apparatus, a chip, a computing device, and a computer readable storage medium for allocating thread storage locations. The method comprises the following steps: virtual caches are allocated for threads; calculating the access frequency of the physical memory area in a preset time period; selecting a low access frequency physical memory area in a first preset range according to the order from small to large of access frequency; determining a low access frequency virtual cache according to the mapping relation; increasing the value of a low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount; ordering the virtual caches in order of the low access frequency counter value from small to large; at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area. By the method, a proper physical memory area can be allocated for the virtual cache, so that the occupied area of the memory, the access power consumption and the time delay are considered.

Description

Thread storage position allocation method, device, chip, device and storage medium

Technical Field

The present invention relates to the field of memory data processing technologies, and in particular, to a method, an apparatus, a chip, a computing device, and a computer readable storage medium for allocating thread storage locations.

Background

In the existing operating system, the memory is managed through a memory management unit (Memory Management Unit, MMU), in order to improve the utilization rate of the physical memory, when a user accesses the memory, the MMU can allocate a virtual cache for a thread accessed by the user and translate the virtual cache into an actual physical memory area, so that after the system operates for a period of time, the problem of memory management fragmentation caused by frequent memory application and release is prevented by adjusting the mapping relation between the virtual cache and the actual physical memory area, and meanwhile, the MMU can also control the access of the physical memory area, thereby improving the security of the operating system.

Further, for the actual physical memory, the larger the single block capacity is, the larger the power consumption in the read-write access is, the higher the delay is, and if the single block capacity is smaller, the smaller the power consumption in the read-write access is, and the lower the delay is. However, on the premise that the capacity of the single physical memory is the same as the total capacity of the plurality of physical memories, the area occupied by the single physical memory is smaller than the total area occupied by the plurality of physical memories.

At present, the mapping relationship between the virtual cache and the actual physical memory area is adjusted by mapping the virtual cache set to one or more actual physical memory areas, so that the subsequent virtual cache can apply for a physical memory with continuous enough addresses. The method can only solve the problem of memory management fragmentation, but cannot allocate a proper physical memory area for the virtual cache corresponding to the thread according to the conditions of the occupied area, access power consumption, time delay and the like of the physical memory.

Disclosure of Invention

Based on the above-mentioned current situation, a main object of the present invention is to provide a method, an apparatus, a chip, a computing device and a computer readable storage medium for allocating a suitable physical memory area for a virtual cache, so as to take account of the occupied area of a memory, access power consumption and delay.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

according to an aspect of the embodiments of the present application, there is provided a thread storage location allocation method, including: virtual caches are allocated for threads; the number of the virtual caches is multiple, a mapping relation is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of the single first memory hardware is smaller than that of the single second memory hardware; calculating the access frequency of each physical memory area in each preset time period; according to the order of the access frequency from small to large, selecting a physical memory area in a first preset range before as a low access frequency physical memory area; according to the mapping relation, determining the virtual cache corresponding to the low access frequency physical memory area as a low access frequency virtual cache; increasing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value; ordering the virtual caches in order of the low access frequency counter value from small to large; at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area.

Preferably, before ordering the virtual caches in order of the low access frequency counter value from small to large, the method further comprises: judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value; if yes, executing the step of sequencing the virtual caches in the order from the low access frequency counter value to the high access frequency counter value; if not, the mapping relation is established between the virtual cache and the first physical memory area.

Preferably, before ordering the virtual caches in order of the low access frequency counter value from small to large, the method includes: the same virtual cache as that in the previous application is allocated for the thread which applies for the cache again; at least one virtual buffer memory in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer memory and the first physical memory area, wherein the method comprises the following steps: judging whether the virtual cache corresponding to the thread applying for the cache again is located in a first preset range of sequencing; if so, establishing a mapping relation between the virtual cache corresponding to the thread of the application cache and the first physical memory area.

Preferably, at least one virtual buffer in a second preset range before the sorting is selected, and a mapping relation is established between the virtual buffer and the first physical memory area, including: when the system is in an idle state, a virtual cache which does not perform direct memory operation is selected from the virtual caches in a first preset range, and a mapping relation is established between the virtual cache and the first physical memory area.

Preferably, when the system is in an idle state, selecting a virtual cache that does not perform direct memory operation from virtual caches in a second preset range, and establishing a mapping relationship with the first physical memory area, where the method includes: when the system is in an idle state, judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value; if not, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the previous second preset range, and establishing a mapping relation with the first physical memory area.

Preferably, after ordering the virtual caches in order of the low access frequency counter value from small to large, the method further comprises: at least one virtual cache in a third preset range after sequencing is selected, and a mapping relation is established between the virtual cache and the second physical memory area.

Preferably, at least one virtual cache in the third preset range after the sorting is selected, and a mapping relation is established between the virtual cache and the second physical memory area, including: when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in a third preset range, and establishing a mapping relation between the virtual cache and the second physical memory area.

Preferably, the number of low access frequency counters is fixed; at least one virtual cache in a third preset range after the sorting is selected, and after the mapping relation is established between the virtual cache and the second physical memory area, the method further comprises the steps of: marking the selected virtual cache which establishes a mapping relation with the second physical memory area; releasing the corresponding relation between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread in the subsequent step, and sorting the low access frequency counter of which the correspondence is not released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual caches in the order of the low access frequency counter value from small to large is performed in the subsequent step, and selecting at least one from the virtual caches in a first second preset range of the sorting when the step of establishing a mapping relationship with the first physical memory area is performed in the subsequent step, wherein the first second preset range of the sorting includes each part of the two separated sorting.

Preferably, the number of low access frequency counters is fixed; at least one virtual buffer in a second preset range before sequencing is selected, and after a mapping relation is established between the virtual buffer and the first physical memory area, the method further comprises the steps of: marking the selected virtual cache which establishes a mapping relation with the first physical memory area; releasing the corresponding relation between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread in the subsequent step, and sorting the low access frequency counter of which the correspondence is not released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual caches in the order of the low access frequency counter value from small to large is performed in the subsequent step, and selecting at least one from the virtual caches in a first second preset range of the sorting when the step of establishing a mapping relationship with the first physical memory area is performed in the subsequent step, wherein the first second preset range of the sorting includes each part of the two separated sorting.

Preferably, the pre-establishing a condition of the low access frequency counter for the virtual cache includes: the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or, in a preset time period, the application number of the virtual cache is greater than or equal to a preset number; and/or, in the preset time period, the total time length of the virtual buffer occupying the physical memory area is greater than or equal to the preset time length.

Preferably, after increasing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: the value of the low access frequency counter is recorded so that when the same step is executed again after the next power-on, accumulation is carried out on the basis of the recorded value of the low access frequency counter.

Preferably, the method further comprises: the value of the low access frequency counter is restored to the initial value every time the power is turned on.

According to another aspect of the embodiments of the present application, there is provided a thread storage location allocation apparatus, including: the first allocation module is used for allocating virtual caches for the threads; the number of the virtual caches is multiple, a mapping relation is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of the single first memory hardware is smaller than that of the single second memory hardware; the computing module is used for computing the access frequency of each physical memory area in each preset time period; the selecting module is used for selecting the physical memory area in the first preset range as the low access frequency physical memory area according to the order of the access frequency from small to large; the determining module is used for determining the virtual cache corresponding to the low access frequency physical memory area as a low access frequency virtual cache according to the mapping relation; the increasing module is used for increasing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value; the ordering module is used for ordering the virtual caches according to the order of the low access frequency counter from small to large; the first mapping module is used for selecting at least one from the virtual caches in the second preset range before sequencing, and establishing a mapping relation with the first physical memory area.

Preferably, the apparatus further comprises: the judging module is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value; the control module is used for controlling the ordering module to execute the step of ordering the virtual caches according to the sequence from the low access frequency counter value to the high value when the judgment module judges that the virtual caches are yes; and the second mapping module is used for establishing a mapping relation between the virtual cache and the first physical memory area when the judging module judges that the virtual cache is not in the first physical memory area.

Preferably, the apparatus further comprises: the second allocation module is used for allocating the same virtual cache as the thread which applies for the cache again in the previous application; the first mapping module includes: the first judging submodule is used for judging whether the virtual cache corresponding to the thread for applying for the cache again is located in a first and second preset range of sequencing; and the first mapping sub-module is used for establishing a mapping relation between the virtual cache corresponding to the thread which applies for the cache again and the first physical memory area when the judging sub-module judges that the thread is yes.

Preferably, the first mapping module includes: and the second mapping sub-module is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in a second preset range when the system is in an idle state, and establishing a mapping relation with the first physical memory area.

Preferably, the first mapping module further comprises: the judging unit is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value when the system is in an idle state; and the control unit is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges and establishing a mapping relation with the first physical memory area when the judging unit judges that the virtual cache is not in the second preset range.

Preferably, the device comprises: and the third mapping module is used for selecting at least one from the virtual caches in the third preset range after the sorting and establishing a mapping relation with the second physical memory area.

Preferably, the third mapping module includes: and the third mapping sub-module is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in a third preset range after the system is in an idle state, and establishing a mapping relation with the second physical memory area.

Preferably, the number of low access frequency counters is fixed; the apparatus further comprises: the first marking module is used for marking the selected virtual cache which is in a mapping relation with the second physical memory area after the second mapping module performs the step of selecting at least one from the virtual caches in the third preset range after the sorting and establishing the mapping relation with the second physical memory area; the first releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter; a first resetting module, configured to reset a value of the low access frequency counter of the de-correspondence relationship to an initial value, for establishing a correspondence relationship with a virtual cache corresponding to a newly applied thread in a subsequent step, and separate the low access frequency counter of the non-de-correspondence relationship from the de-correspondence virtual cache when the subsequent step of ordering the virtual caches in order of decreasing the value of the low access frequency counter is performed by the subsequent ordering module, and select at least one from the virtual caches in a first second preset range of the ordering when the subsequent step of establishing a mapping relationship with the first physical memory area is performed by the subsequent first mapping module, where the first second preset range of the ordering includes each of the two separate orderings.

Preferably, the number of low access frequency counters is fixed; the apparatus further comprises: the second marking module is used for selecting at least one from the virtual caches in the second preset range before the first mapping module is ordered, and marking the selected virtual cache which has the mapping relation with the first physical memory area after the first mapping module establishes the mapping relation with the first physical memory area; the second releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter; and a second resetting module for resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with the virtual cache corresponding to the newly applied thread in the subsequent step, and separating the low access frequency counter of which the correspondence is not released from the virtual cache of which the correspondence is released when the subsequent step of ordering the virtual caches in the order of the low access frequency counter value from small to large is performed by the subsequent ordering module, and selecting at least one from the virtual caches in a previous second preset range of the ordering when the step of establishing the mapping relationship with the first physical memory area is performed by the subsequent first mapping module, wherein the previous second preset range of the ordering comprises each part of the separated two orderings.

Preferably, the pre-establishing a condition of the low access frequency counter for the virtual cache includes: the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or, in a preset time period, the application number of the virtual cache is greater than or equal to a preset number; and/or, in the preset time period, the total time length of the virtual buffer occupying the physical memory area is greater than or equal to the preset time length.

Preferably, the apparatus further comprises: the recording module is used for recording the value of the low access frequency counter so as to accumulate the value of the low access frequency counter when the same step is executed again after the next power-on.

Preferably, the apparatus further comprises: and the recovery module is used for recovering the value of the low access frequency counter to an initial value at each start-up.

According to another aspect of the embodiments of the present application, there is also provided a method for allocating thread storage locations, including: virtual caches are allocated for threads; the number of the virtual caches is multiple, a mapping relation is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of the single first memory hardware is smaller than that of the single second memory hardware; calculating the access frequency of each physical memory area in each preset time period; according to the order of the access frequency from small to large, selecting a physical memory area in a first preset range before as a low access frequency physical memory area; according to the mapping relation, determining the virtual cache corresponding to the low access frequency physical memory area as a low access frequency virtual cache; reducing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value; ordering the virtual caches in the order of the low access frequency counter from high to low; at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area.

Preferably, before ordering the virtual caches in order of the value of the low access frequency counter from large to small, the method further comprises: judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value; if yes, executing the step of sequencing the virtual caches according to the sequence from the high value to the low value of the low access frequency counter; if not, the mapping relation is established between the virtual cache and the first physical memory area.

Preferably, before ordering the virtual caches in order of the value of the low access frequency counter from large to small, the method includes: the same virtual cache as that in the previous application is allocated for the thread which applies for the cache again; at least one virtual buffer memory in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer memory and the first physical memory area, wherein the method comprises the following steps: judging whether the virtual cache corresponding to the thread applying for the cache again is located in a first preset range of sequencing; if so, establishing a mapping relation between the virtual cache corresponding to the thread of the application cache and the first physical memory area.

Preferably, at least one virtual buffer in a second preset range before the sorting is selected, and a mapping relation is established between the virtual buffer and the first physical memory area, including: when the system is in an idle state, a virtual cache which does not perform direct memory operation is selected from the virtual caches in a first preset range, and a mapping relation is established between the virtual cache and the first physical memory area.

Preferably, when the system is in an idle state, selecting a virtual cache that does not perform direct memory operation from virtual caches in a second preset range, and establishing a mapping relationship with the first physical memory area, where the method includes: when the system is in an idle state, judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value; if not, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the previous second preset range, and establishing a mapping relation with the first physical memory area.

Preferably, after ordering the virtual caches in order of the value of the low access frequency counter from large to small, the method further comprises: at least one virtual cache in a third preset range after sequencing is selected, and a mapping relation is established between the virtual cache and the second physical memory area.

Preferably, at least one virtual cache in the third preset range after the sorting is selected, and a mapping relation is established between the virtual cache and the second physical memory area, including: when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in a third preset range, and establishing a mapping relation between the virtual cache and the second physical memory area.

Preferably, the number of low access frequency counters is fixed; at least one virtual cache in a third preset range after the sorting is selected, and after the mapping relation is established between the virtual cache and the second physical memory area, the method further comprises the steps of: marking the selected virtual cache which establishes a mapping relation with the second physical memory area; releasing the corresponding relation between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread in the subsequent step, and sorting the low access frequency counter of which the correspondence is not released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual caches in the order of the low access frequency counter value from small to large is performed in the subsequent step, and selecting at least one from the virtual caches in a first second preset range of the sorting when the step of establishing a mapping relationship with the first physical memory area is performed in the subsequent step, wherein the first second preset range of the sorting includes each part of the two separated sorting.

Preferably, the number of low access frequency counters is fixed; at least one virtual buffer in a second preset range before sequencing is selected, and after a mapping relation is established between the virtual buffer and the first physical memory area, the method further comprises the steps of: marking the selected virtual cache which establishes a mapping relation with the first physical memory area; releasing the corresponding relation between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread in the subsequent step, and sorting the low access frequency counter of which the correspondence is not released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual caches in the order of the low access frequency counter value from small to large is performed in the subsequent step, and selecting at least one from the virtual caches in a first second preset range of the sorting when the step of establishing a mapping relationship with the first physical memory area is performed in the subsequent step, wherein the first second preset range of the sorting includes each part of the two separated sorting.

Preferably, the pre-establishing a condition of the low access frequency counter for the virtual cache includes: the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or, in a preset time period, the application number of the virtual cache is greater than or equal to a preset number; and/or, in the preset time period, the total time length of the virtual buffer occupying the physical memory area is greater than or equal to the preset time length.

Preferably, after reducing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: the value of the low access frequency counter is recorded so that when the same step is executed again after the next power-on, accumulation is carried out on the basis of the recorded value of the low access frequency counter.

Preferably, the method further comprises: the value of the low access frequency counter is restored to the initial value every time the power is turned on.

According to another aspect of the embodiments of the present application, a system-in-chip is provided, which includes a memory management unit, a first memory hardware and a second memory hardware, where a capacity of a single first memory hardware is smaller than a capacity of a single second memory hardware, and when the system-in-chip runs a thread, the memory management unit can allocate a memory location of the thread by using any one of the two thread memory location allocation methods.

According to another aspect of embodiments of the present application, there is provided a computing device comprising: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface are communicated with each other through the communication bus; the memory is used to store executable instructions that cause the processor to perform either of the two thread storage location allocation methods described above.

According to another aspect of the embodiments of the present application, there is provided a computer-readable storage medium having an execution program stored thereon, the execution program when executed implementing any one of the two thread storage location allocation methods described above.

According to the thread storage position allocation method provided by the embodiment of the application, the access frequency of the physical memory area is calculated once every preset time period, after the physical memory area is ordered based on the access frequency, the low access frequency virtual cache corresponding to a part of the physical memory area with lower access frequency in the virtual cache is selected, the value of the low access frequency counter of the low access frequency virtual cache is increased by a preset unit quantity, the number of times of counting is increased as time is accumulated, finally, threads with low access frequency and threads with high access frequency can be accurately determined, and after a mapping relation is established between at least one virtual cache with lower value of the low access frequency counter and the first physical memory area according to the determined result, the system operation power consumption can be effectively reduced, the system operation smoothness is improved, and meanwhile, the occupied area of memory hardware is ensured to be proper.

Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.

Drawings

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:

FIG. 1 is a flowchart illustrating a method for allocating thread storage locations according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a mapping relationship between virtual caches and physical memory according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a correspondence relationship between a physical memory area and a counter according to an embodiment of the present invention;

FIG. 4 is a flowchart illustrating a portion of steps in a method for allocating a thread storage location according to an embodiment of the present invention;

FIG. 5 is a flowchart illustrating a portion of steps in a method for allocating a thread storage location according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating sub-steps of step 174 in a method for allocating thread storage locations according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating steps following step 160 in the method for allocating thread storage locations according to an embodiment of the present invention;

FIG. 8 is a flowchart illustrating steps following step 170 in a method for allocating thread storage locations according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a modular structure of a thread storage location allocation apparatus according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a modular structure of a system-on-chip provided by an embodiment of the present invention;

FIG. 11 is a schematic diagram of a modular architecture of a computing device according to an embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the present invention, and in order to avoid obscuring the present invention, well-known methods, procedures, flows, and components are not presented in detail.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

A System on Chip (SoC) that is memory managed by a memory management unit MMU when operating. The MMU mainly has the following functions: virtual address translation, access rights control, and extended physical memory management. The virtual address translation is to translate a virtual cache address accessed by a user into an actual physical address when the user accesses the memory, so that the system can access the actual physical address. Access right control refers to access right control on some virtual cache addresses so as to manage access right and scope of a user program, for example, a code segment is generally set to be read-only, and if the user program writes the code segment, the system triggers an exception. The extended physical memory management refers to managing physical memory resources of the system, and providing operation interfaces such as application, release, etc. of physical memory for user programs.

In the running process of the system, the thread can continuously apply and release the memory according to task demands, so that the memory fragmentation can be caused, and the mapping relation between the virtual cache and the physical memory area can be adjusted through the MMU, so that the thread storage is more centralized, and the memory with continuous addresses and enough large enough is reserved for the subsequent thread application storage.

For the hardware of the actual physical memory, the larger the single block capacity is, the larger the power consumption in the read-write access is, the higher the delay is, and if the single block capacity is smaller, the smaller the power consumption in the read-write access is, and the lower the delay is. However, under the premise of the same capacity, that is, the same bit number, the occupied area of the single physical memory is smaller than the sum of the occupied areas of the plurality of physical memories.

At present, the MMU adjusts the mapping relation between the virtual cache and the physical memory area only to solve the problem of memory management fragmentation, but cannot allocate a more proper physical memory area for the virtual cache corresponding to the thread according to the conditions of the occupied area of the physical memory, access power consumption, time delay and the like.

Since the operating system generally allocates virtual caches for threads randomly, if it is desired to reduce system power consumption by allocating threads with high access frequency to a memory region with small capacity, it is difficult to determine whether a thread or its corresponding virtual cache is with high access frequency or low access frequency by allocating threads with low access frequency to a memory region with large capacity to save the area occupied by physical memory.

Based on this, the inventor thinks that the access frequency of each physical memory area can be calculated first, and then all virtual caches mapped by the physical memory area with high access frequency and threads corresponding to the partial virtual caches are determined as high access frequency by combining the mapping relation between the physical memory area and the virtual caches. However, since a mapping relationship is generally established between one physical memory area and a plurality of virtual caches, when the access frequency calculated for a certain physical memory area is high, a part of the plurality of virtual caches corresponding to the physical memory area may be truly high access frequency, and another part may be actually low access frequency, and if all virtual caches corresponding to the physical memory area are directly determined to be high access frequency, a part of virtual caches with low access frequency are determined to be high access frequency, resulting in inaccurate determination results.

In order to solve the above problems, the present inventors found through research that when the access frequency of the physical memory area obtained by calculation is low, all virtual caches corresponding to the physical memory area have a low access frequency. Based on the above, the inventor of the present application adopts reverse thinking, finds out the physical memory area with low access frequency through calculation, and then determines all virtual caches corresponding to the physical memory area with low access frequency and threads corresponding to the virtual caches as low access frequency, thereby effectively eliminating the situation that the determination result is inaccurate.

To further exclude contingencies, such as when a thread is actually a thread of high access frequency, but is in a dormant state when it is computed, there is no real commissioning, resulting in a situation where it is determined to be of low access frequency, contingencies can be excluded by computing once every predetermined period of time, accumulating over time and computing times. And for statistics, a low access frequency counter is established for the virtual cache, the value of the low access frequency counter corresponding to all virtual caches mapped by the physical memory address with lower access frequency obtained by each calculation is changed by a preset unit amount (for example, 1 can be added), the virtual cache with smaller value of the low access frequency counter can be determined along with the accumulation of time, and the higher access frequency is, otherwise, the lower access frequency is.

After accurately obtaining the threads with low access frequency and the threads with high access frequency, the operating system maps at least part of virtual caches with high access frequency to the first physical memory area so as to achieve the aims of taking the occupied area of the physical memory, the access power consumption and the time delay into consideration.

The thread storage location allocation method provided by the embodiment of the application comprises, but is not limited to, intelligent electronic devices such as mobile phones, computers and servers.

Based on the foregoing, according to an aspect of an embodiment of the present application, a method for allocating thread storage locations is provided, and referring specifically to fig. 1, a flow of the method provided by an embodiment of the present application is shown in the drawings. The method is performed by a computing device, which may be, for example, a cell phone, a computer, a server, etc. As shown in the figure, the method comprises:

step 110: virtual caches are allocated for threads; the number of the virtual caches is multiple, a mapping relation is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of the single first memory hardware is smaller than that of the single second memory hardware.

In this step, when the system is started up and running, the thread accesses and applies for the memory. It is to be appreciated that the thread may be the first application or the second application. The thread can be one thread, and a plurality of virtual caches are allocated for the thread for the first application; the thread may also be multiple and at least one virtual cache may be allocated for one thread.

When the thread applies for the memory, the operating system allocates a virtual buffer (i.e. a virtual memory area) for the thread, and a mapping relationship is established between the virtual buffer random and the physical memory area, and the operating system knows the mapping relationship.

Because the capacity of the first memory hardware is smaller than that of the second memory hardware, the first physical memory area has lower power consumption and shorter time delay when being accessed than the second physical memory area, but if the same capacity is achieved, the area occupied by the total amount of the first memory hardware is larger than that occupied by the total amount of the second memory hardware.

Referring to fig. 2, which illustrates a correspondence between threads, virtual caches, and physical memory areas in one embodiment provided herein, taking the embodiment shown in the figure as an example, the system includes a first memory hardware (SmallRam, R for short) of 32k as a single block _s ) And a second memory hardware (BigRam, R for short) with a monolithic capacity of 64k _b )，R _s Every 8k is divided into a first physical memory area, and the total of 4 first physical memory areas is R _b Every 8k is divided into a second physical memory area, and the total of 8 second physical memory areas is 8. The system matches the virtual cache for the thread after it receives it, in the figure, pageT0, pageT1, Page T2 … PageTn is expressed as a thread-matched virtual cache, page0, page1, page2 … Page are expressed as physical memory addresses corresponding to the physical memory regions, and mapping relations are established between virtual caches Page T0, page T1, page T2 … PageTn and physical memory addresses Page0, page1, page2 … Page through the MMU.

Step 120: and calculating the access frequency of each physical memory area in each preset time period.

As shown in fig. 3, in this step, an access counter may be allocated to each physical memory area, and if the physical memory area is accessed once, the value of the corresponding access counter is increased by 1. The predetermined time period may be, for example, 1 second, and the access frequency F of each physical memory area is obtained by recording the access times of each physical memory area in each 1 second interval by using an access counter, and calculating the ratio between the access times of each physical memory area and the sum of the access times of all physical memory areas in 1 second. It should be noted that, since the access frequency of each physical memory area is calculated once in each predetermined period, after the calculation of a single predetermined period is completed, all the counters may be cleared, so as to facilitate the calculation of the access frequency in the next predetermined period.

It will be appreciated that the access frequency of the physical memory area may also be implemented by existing digital circuits, such as an infinite impulse response filter, etc., and will not be described in detail herein.

Step 130: and selecting the physical memory area in the first preset range as the low access frequency physical memory area according to the order of the access frequency from small to large.

It should be noted that in this step, the sorting and selecting are performed once every predetermined period of time described in the step 120.

Taking fig. 3 as an example, if the values of the counters of the physical memory area from bottom to top are 9, 5, 1, 12, 3, 6, 0, 4, 0, 2, 5, 3, respectively, the corresponding access frequencies are f0=0.18, f1=0.1, f2=0.02, f3=0.24, f4=0.06, f5=0.12, f6=0, f7=0.08, f8=0, f9=0.04, f10=0.1, f11=0.06, and the corresponding access frequencies are f6=f8 < f2< f9< f4< f11< f7< f1=f10 < f5< f0< f3 in order from small to large. The first preset range may be 25% of the total number of physical memory areas, that is, 0.25×12=3, and the selected low access frequency physical memory areas are the second physical memory areas corresponding to F6 and F8 and the first physical memory area corresponding to F2.

Step 140: and determining the virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache according to the mapping relation.

Referring to fig. 2 and 3 in combination, if the physical memory addresses of the second physical memory area corresponding to F6 and F8 are Page300-Page350 and Page400-Page450, and the physical memory address of the first physical memory area corresponding to F2 is Page50-Page100, the virtual cache mapped with Page300-Page350, page400-Page450, page50-Page100 may be, for example, page 2, page 7, page10, page 12, page 16, page 17, page 22, page 25, page 26, and Page 28, and the virtual caches Page 2, page 7, page10, page 12, page 16, page 17, page 22, page 25, page 26, and Page 28 are virtual caches with low access frequency.

It should be noted that, in this step, the low access frequency virtual cache is also determined every predetermined period of time.

Step 150: and increasing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value.

As shown in fig. 2, a specific way to pre-establish the low access frequency counter for the virtual cache may be to count the virtual cache by software, specifically, the low access frequency counter corresponding to the virtual cache PageT0 and PageT1 matched by the Thread0 is denoted as Thread0_lfp_cnt0 and Thread0_lfp_cnt1, respectively, and the access frequency counter corresponding to the virtual cache PageT2 matched by the Thread1 is denoted as Thread1 LFP cnt2.

The initial value of the low access frequency counter is a preset minimum value, namely, the value of the low access frequency counter only increases and does not decrease in the working process, and in the working process, when the value of the low access frequency counter increases to a certain degree, if a reset condition is met, the value of the low access frequency counter can be reinitialized to the preset minimum value, so that the initial value is always the minimum value in all values of the whole working process of the low access frequency counter. The preset minimum value may be, for example, 0, 1, 10, etc., and the specific value is not limited herein. The purpose of setting the initial value of the low access frequency counter to the minimum value is to allow the value of the subsequent low access frequency counter to be increased widely in order to perform sufficient counting.

It should be noted that in some embodiments, the low access frequency counter may be pre-established for all virtual caches at a time, and in this embodiment, the step of pre-establishing the low access frequency counter for all virtual caches has no sequential relationship with steps 110-140.

In other embodiments, the low access frequency counter may be pre-established only for the low access frequency virtual cache determined in step 140, and the low access frequency counter may be pre-established for the new low access frequency virtual cache after the next predetermined period of time is determined, for which embodiment the step of pre-establishing the low access frequency counter for all virtual caches may be performed after step 140.

In this step, the increment of the value of the low access frequency counter by the preset unit amount may specifically be to increment the value of the low access frequency counter corresponding to the low access frequency virtual cache by 1.

As shown in fig. 2, for example, when the low access frequency virtual cache determined for a certain unit time is PageT2, pageT7, pageT10, pageT12, pageT16, pageT17, pageT22, pageT25, pageT26, and PageT28, wherein the threads corresponding to PageT2, pageT7, pageT10, pageT12, pageT16, pageT17 are Thread1, when PageT22, pageT25, pageT26 and PageT28 correspond to Thread2, then the low access frequency counters Ther1_LFP_cnt 2, ther1_LFP_cnt 7, ther1_LFP_cnt 10, ther1_LFP_cnt 12, ther1_LFP_cnt 16, ther1_LFP_cnt 17, ther2_LFP_cnt 22, ther1_LFP_cnt 25, ther1_LFP_cnt 26 and Ther1_LFP_cnt 28 are all incremented by 1.

It should be noted that, the steps 130 to 150 are all performed once for each predetermined period, so that as time is accumulated, the value of the low access frequency counter corresponding to the low access frequency virtual cache will be larger and larger, and further the system can accurately determine which threads are threads with low access frequency and which threads are threads with high access frequency according to the value of the low access frequency counter corresponding to each virtual cache.

Step 160: the virtual caches are ordered in order of the value of the low access frequency counter from small to large.

In this step, the virtual caches are ordered in the order of the low access frequency counter value from small to large, which is equivalent to ordering the threads corresponding to the virtual caches from high to low according to the actual access frequency.

Step 170: at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area.

The second preset range may take 30% of the total number of virtual caches, for example, when the total number of virtual caches is 10, the first three virtual caches with high access frequency are taken according to the order.

After the threads corresponding to the virtual caches are sequenced from high to low according to the actual access frequency, in this step, at least one virtual cache corresponding to the thread with a smaller value of the low access frequency counter (i.e. higher access frequency) is adjusted to be mapped to the first physical memory area, so that the thread with a high access frequency is stored in the first physical memory area with relatively lower power consumption and delay on the premise of ensuring that the occupied area of the memory hardware is proper, the running power consumption of the system is further reduced, and the fluency is improved.

It should be noted that, in step 170, if the system finds that the virtual cache matched with the current thread is mapped to the second physical memory area through the mapping relationship table, it adjusts and maps the virtual cache to the first physical memory area; if the virtual cache matched with the current thread is found to be mapped to the first physical memory area, the adjustment is not performed.

According to the thread storage position allocation method provided by the embodiment of the application, the access frequency of the physical memory area is calculated once every preset time period, after the physical memory area is ordered based on the access frequency, the low access frequency virtual cache corresponding to a part of the physical memory area with lower access frequency in the virtual cache is selected, the value of the low access frequency counter of the low access frequency virtual cache is increased by a preset unit quantity, the number of times of counting is increased as time is accumulated, finally, threads with low access frequency and threads with high access frequency can be accurately determined, and after a mapping relation is established between at least one virtual cache with lower value of the low access frequency counter and the first physical memory area according to the determined result, the system operation power consumption can be effectively reduced, the system operation smoothness is improved, and meanwhile, the occupied area of memory hardware is ensured to be proper.

The embodiment of the present application further provides another method for allocating thread storage locations, specifically, the step 150 is replaced by the following steps: and reducing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value. The above step 160 is replaced with the following steps: the virtual caches are ordered in order of the value of the low access frequency counter from large to small. The remaining steps remain consistent with the thread storage location allocation method provided by the above embodiments.

It will be appreciated that the step 150 of decreasing the value of the low access frequency counter whose pre-established initial value is the preset maximum value by a preset unit amount and ordering the virtual caches in the order from the high value to the low value of the low access frequency counter increases the value of the low access frequency counter whose pre-established initial value is the preset minimum value by a preset unit amount and the step 160 of ordering the virtual caches in the order from the low value to the high value are the same as the functions performed in the corresponding scheme. Counting the low access frequency counter by adopting a mode of increasing a preset unit amount and a mode of reducing the preset unit amount, and sequencing the virtual caches according to the sequence of the values of the low access frequency counter from big to small by adopting the mode of reducing the preset unit amount, so that the higher the sequencing is, the higher the access frequency of the virtual cache corresponding to the low access frequency counter. In the manner of step 150, the virtual caches are sorted in the order of the low access frequency counter from the low access frequency counter to the high access frequency counter in step 160, and the higher the access frequency of the virtual caches corresponding to the low access frequency counter in the middle of the sorting is, the higher the access frequency of the virtual caches corresponding to the low access frequency counter is. Therefore, the two are mutually corresponding technical characteristics, and the same technical problems are solved in the corresponding scheme.

And it should also be noted that, the initial value of the low access frequency counter is a preset maximum value, which is just opposite to the preset minimum value described above, that means that the value of the low access frequency counter is only reduced and not increased in the working process, and the initial value is always the maximum in all the values of the low access frequency counter in the whole working process. Specifically, the preset maximum value may be 999, 9999, 99999, or the like, for example, and the specific value is not limited herein.

In order to ensure smooth adjustment of the mapping relationship, an implementation manner is provided in the present application, and referring to fig. 4 specifically, a further partial step flow of the thread storage location allocation method provided in the embodiment of the present application is shown in the figure. As shown in the figure, before step 160, the following steps are further included:

step 1501: and judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value.

The preset capacity value is a reserved exchange area capacity value preset by the first physical memory area, and aims to continuously provide storage for the running thread in the first physical memory area through the reserved exchange area when the residual capacity of the first physical memory area is insufficient. The preset capacity value may be set correspondingly according to the total capacity of all the first physical memory areas, taking the total capacity of all the first physical memories shown in fig. 3 as 32k as an example, and the preset capacity value may be set to 8k.

If step 1501 is yes, step 160 is executed.

If step 1501 is negative, step 1503 is executed: and establishing a mapping relation between the virtual cache and the first physical memory area.

In this embodiment, when the remaining total capacity of all the first physical memory areas is greater than the preset capacity value, virtual caches matched by any threads are mapped into the first physical memory areas, that is, all threads are stored into the first physical memory areas, and based on the characteristics of low access power consumption and short delay of the first physical memory areas, the system power consumption can be sufficiently reduced, and the running smoothness of the system can be improved. When the residual total capacity of all the first physical memory areas is smaller than or equal to the preset capacity value, sequencing the virtual caches, selecting at least one virtual cache with high access frequency from the sequencing, and mapping and storing the virtual cache to the first physical memory areas, so that the system can still keep lower power consumption and shorter delay.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application. However, in the case of further embodiments of the method for allocating thread storage locations, the steps 150 and 160 mentioned in the embodiments are correspondingly modified to the steps of the method for allocating thread storage locations instead of the steps 150 and 160, and the same shall apply hereinafter.

For the situation that the memory is applied again after the thread is released, an implementation manner is provided in the present application, and specifically please refer to fig. 5, which illustrates a further partial step flow of the thread storage location allocation method provided in the embodiment of the present application. As shown in the figure, prior to step 160, the method further comprises:

step 1502: the thread which applies for the cache again is allocated with the same virtual cache as the thread which applies for the cache in the previous time.

When the same thread accesses at different time, the MMU is the same as the virtual cache matched with the thread, namely when the thread applies for accessing the memory for the first time, the MMU firstly matches the virtual cache with the thread, and when the thread releases and applies for accessing the memory again, the MMU matches the virtual cache which is the same as the virtual cache applied for last time.

In the subsequent step 160, after the system allocates the same virtual cache for the reapplied thread, the virtual cache is ordered according to the value counted in the steps 120 to 150 by the low access frequency counter corresponding to the virtual cache.

Step 170 comprises the steps of:

step 171: judging whether the virtual cache corresponding to the thread applying for the cache again is located in the first preset range of the sequencing.

If the determination in step 171 is yes, step 173 is executed: and establishing a mapping relation between the virtual cache corresponding to the thread which applies for the cache again and the first physical memory area.

In this step, according to the ordering condition, if the virtual cache corresponding to the reapplied thread is located in the first second preset range in the ordering, the thread is indicated to be a high access frequency thread, and the mapping relationship is established between the virtual cache corresponding to the thread and the first physical memory area, so that the system power consumption can be effectively reduced, and the smoothness of system operation can be improved.

In this embodiment, a mapping relationship is established between the virtual cache corresponding to the reapplied high-access-frequency thread and the first physical memory area, so that it is ensured that the virtual cache corresponding to the high-access-frequency thread can be mapped to the first physical memory area in time, and further power consumption and delay can be reduced in time.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

Referring to fig. 6, a substep flow of step 170 is shown. As shown in the figures, in some embodiments, step 170 includes the steps of:

Step 174: when the system is in an idle state, a virtual cache which does not perform direct memory operation is selected from the virtual caches in a first preset range, and a mapping relation is established between the virtual cache and the first physical memory area.

Direct memory operations (Direct Memory Access, DMA for short), also known as burst data transfer. DMA operations do not save site, resume site, or the like during data transfer, and DMA operations are independent of CPU access, thus forcing data handling, which can result in data inconsistencies.

The idle state in this step refers to a state when the system has no thread task execution requirements.

In this embodiment, when the system is in an idle state, a virtual cache that does not perform direct memory operation is selected from the virtual caches in the previous second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area, so that system power consumption is reduced and access delay is shortened on the premise of ensuring that handling data is not lost.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

With continued reference to FIG. 6, in some embodiments, the steps at 174 include the steps of:

Step 1741: and when the system is in an idle state, judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value.

If step 1741 is no, the following steps are performed:

step 1743: and selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first preset range, and establishing a mapping relation with the first physical memory area.

It can be understood that the virtual buffer can be carried only when the remaining total capacity of the first physical memory area meets the capacity required after the virtual buffer is carried, otherwise, the virtual buffer may have discontinuous storage data addresses, resulting in data loss and other situations.

Therefore, in this embodiment, when the system is in an idle state, it is first determined whether the total remaining capacity of all the first physical memory areas meets the storage requirement of the virtual cache to be carried, and when the storage requirement is met, the virtual cache is carried, so as to ensure that the data can be completely carried, and prevent situations such as data loss.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

Referring to fig. 7, a flow of steps following step 160 is shown. As shown in the figure, in some embodiments, the following steps are further included after step 160:

Step 1601: at least one virtual cache in a third preset range after sequencing is selected, and a mapping relation is established between the virtual cache and the second physical memory area.

The third preset range may specifically be 30% of the total number of virtual caches.

In this embodiment, the access frequency of the virtual caches in the third preset range after the ordering is lower, so that after the mapping relationship between at least one virtual cache and the second physical memory area is established, the power consumption and the delay are not too much increased, and a certain space can be further vacated by the first physical memory area to store threads with high access frequency, so that the power consumption, the delay and the occupied area of memory hardware are simultaneously considered.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In some embodiments, the step of selecting at least one from the virtual caches in the third predetermined range after the sorting, and establishing a mapping relationship with the second physical memory area includes:

when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in a third preset range, and establishing a mapping relation between the virtual cache and the second physical memory area.

In this embodiment, when the system is in an idle state, a virtual cache that does not perform direct memory operation is selected from virtual caches in a third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area, so that the low-access-frequency virtual cache is carried on the premise that carrying data is not lost.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

Referring again to fig. 7, in some embodiments, the number of low access frequency counters is fixed, and after step 1601, the method further comprises the steps of:

step 1603: and marking the virtual cache which is selected and establishes a mapping relation with the second physical memory area.

Step 1605: and releasing the corresponding relation between the marked virtual cache and the low access frequency counter.

It should be noted that, the marked virtual cache will not have a low access frequency counter corresponding to the marked virtual cache.

It can be understood that in the actual running process, the operating system applies for and releases a large number of virtual caches, and if a large number of low-access frequency counters are established for the virtual caches, more running memory of the operating system is occupied, so that the computing power of the operating system is affected. Based on this, by setting the number of low access frequency counters to a fixed value, for example, 50, 100, 500, or the like, it is ensured that the low access frequency counter is in a reasonable range for memory occupancy.

Considering that the fixed number of low access frequency counters cannot count more virtual caches, for virtual caches that are carried to the second physical memory area, it can be basically determined that the corresponding thread is a low access frequency thread, so that the significance of counting the threads by the low access frequency counter is not great.

Therefore, in steps 1603 to 1605, the virtual cache carried to the second physical memory area is marked, and the corresponding relation between the marked virtual cache and the low access frequency counter is released, so that on one hand, the low access frequency counter is ensured not to be allocated to the marked virtual cache, on the other hand, the low access frequency counter which is released from the corresponding relation is released, so that the count statistics can be performed for the virtual cache corresponding to the thread of the new application, and further, the access frequency of the thread corresponding to more virtual caches can be determined.

Step 1607: the value of the low access frequency counter that is de-mapped is reset to an initial value for establishing a correspondence subsequently to the virtual cache corresponding to the newly applied thread, and the low access frequency counter that is not de-mapped and the low access frequency counter that is de-mapped are sorted separately at the subsequent execution of step 160, and the first second preset range of sorting comprises a portion of each of the two separate sorting at the subsequent execution of step 170.

In this step, the value of the low access frequency counter, which is released from the correspondence, is reset to an initial value, so that it is ready for counting the virtual cache corresponding to the newly applied thread. Further, since only a part of the low access frequency counters are de-mapped and reset, another part of the low access frequency counters remain as previously recorded values. Based on this, if all the low access frequency counter values are still sorted in a unified manner when step 160 is performed subsequently, there is no reference value in sorting due to the fact that there is no comparability in the values between the low access frequency counter whose correspondence is released and the low access frequency counter whose correspondence is not released. Therefore, when step 160 is executed thereafter, the low access frequency counter which is not de-mapped and the virtual cache which is de-mapped are sorted separately, so as to ensure that the subsequent result is accurate and reliable.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

Referring to fig. 8, a flow of steps following step 170 is shown. As shown in the figure, in some embodiments, the number of low access frequency counters is fixed, and following step 170, the following steps are also included:

Step 1701: and marking the virtual cache which is selected and establishes a mapping relation with the first physical memory area.

Step 1703: and releasing the corresponding relation between the marked virtual cache and the low access frequency counter.

It should be noted that, the marked virtual cache will not have a low access frequency counter corresponding to the marked virtual cache.

Step 1705: the value of the low access frequency counter that is de-mapped is reset to an initial value for establishing a correspondence subsequently to the virtual cache corresponding to the newly applied thread, and the low access frequency counter that is not de-mapped and the low access frequency counter that is de-mapped are sorted separately at the subsequent execution of step 160, and the first second preset range of sorting comprises a portion of each of the two separate sorting at the subsequent execution of step 170.

It is understood that the actions of steps 1701 to 1705 are the same as those of steps 1603 to 1607, except that steps 1701 to 1705 release the low access frequency counter corresponding to the virtual cache transferred to the first physical memory area, and steps 1603 to 1607 release the low access frequency counter corresponding to the virtual cache transferred to the second physical memory area, and the other operations are substantially the same, and are not repeated herein.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In some embodiments of the present application, pre-establishing the condition of the low access frequency counter for the virtual cache includes: the capacity of the virtual cache application is greater than or equal to a preset threshold.

Specifically, the process of pre-establishing the low access frequency counter for the virtual cache may include the steps of:

judging whether the capacity of the virtual cache application is larger than or equal to a preset threshold value;

if the judgment result is yes, a low access frequency counter is established for the virtual cache.

The preset threshold may be set to 1kB, for example. I.e. a virtual cache counter is established and a low access frequency value count is performed for the virtual cache application only if its capacity is greater than 1kB. It can be appreciated that, because the number of virtual caches is large during the running process of the system, if the low-frequency access counter is built for all virtual caches and the low-frequency access value count is performed, a large amount of memory space and computation are occupied. Based on the method, the occupation of memory space and calculation power can be reduced by establishing the low access frequency counter for the virtual cache with the application capacity larger than the preset threshold value.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In some embodiments of the present application, pre-establishing the condition of the low access frequency counter for the virtual cache includes: and in a preset time period, the application times of the virtual cache are larger than or equal to preset times.

Specifically, the process of pre-establishing the low access frequency counter for the virtual cache may include the steps of:

respectively recording the application times and/or release times of each virtual cache in a preset time period through a counter;

and establishing a low access frequency counter for the virtual cache corresponding to the counter with the count value larger than or equal to the preset times.

Wherein the predetermined period of time may be 1 second, 1 minute, 1 hour, or the like. The preset number of times may be, for example, 10, 20, 50, 100, etc.

Likewise, by establishing a low access frequency counter for a virtual cache having a number of applications and/or releases greater than or equal to a preset number of times within a predetermined period of time, memory space and computational effort may be reduced.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In some embodiments of the present application, pre-establishing the condition of the low access frequency counter for the virtual cache includes: and within a preset time period, the total time length of the virtual cache occupying the physical memory area is greater than or equal to the preset time length.

Specifically, the process of pre-establishing the low access frequency counter for the virtual cache may include the steps of:

recording a time node of each application and release of the virtual cache;

obtaining the time length of each occupying physical memory area of the virtual cache by differentiating the time node at each application time and the time node at release time;

summing the time length of each virtual buffer occupying the physical memory area in a preset time period to obtain the total time length of each virtual buffer occupying the physical memory area in the preset time period;

and establishing a low access frequency counter for the virtual cache which occupies the total time length of the physical memory area and is longer than or equal to the preset time length.

The predetermined period of time may be 1 second, 1 minute, 1 hour, or the like, and the preset period of time may be 10 milliseconds, 10 seconds, 10 minutes, or the like, respectively.

Likewise, memory space and computational effort may be reduced by establishing a low access frequency counter for a virtual cache that occupies a total time period of the physical memory area for a predetermined period of time that is greater than or equal to a predetermined time period.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

It should be noted that, for the above-mentioned conditions of pre-establishing the low access frequency counter for the virtual cache, an application may be selected, or multiple conditions may be combined, that is, the low access frequency counter may be established for the virtual cache when the virtual cache simultaneously satisfies multiple conditions.

In some embodiments, after step 150 above, the method further comprises the steps of:

the value of the low access frequency counter is recorded for accumulation based on the recorded value of the low access frequency counter when step 150 is executed again after the next power-on.

Specifically, the system can set a power-down data cache space, for example, through a flash disk (flash), so that the low access frequency value is stored when power is lost.

By recording and retaining the value of the low access frequency counter before the last power-off and accumulating the value of the low access frequency counter when the system is started next time, the memory allocation after the next power-on can be more accurate and reasonable, and the low power consumption management capability of the system is improved.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In some embodiments, the method further comprises the steps of: and restoring the value of the low access frequency counter to an initial value every time the power-on is started.

Specifically, for the embodiment where the system is not provided with the power-down data cache space, the value of the low access frequency counter becomes a random number at each power-on, and if the random number is used for accumulation, the calculation result is inaccurate. Therefore, when the computer is started up each time, the values of all the low access frequency counters are cleared to enable the values of all the low access frequency counters to be increased by a preset unit amount on the basis of zero, so that the accuracy of a calculation result is ensured, and the high access frequency virtual cache and the low access frequency virtual cache are accurately determined.

It will be appreciated that this embodiment is equally applicable to another method of allocating thread storage locations provided in the embodiments of the present application.

In accordance with one aspect of an embodiment of the present application, a thread storage location allocation apparatus is provided, and in particular, reference is made to fig. 9, which illustrates a structure of the thread storage location allocation apparatus. As shown in the figure, the thread storage location allocation apparatus 200 includes a first allocation module 210, a calculation module 220, a selection module 230, a determination module 240, an augmentation module 250, a ranking module 260, and a first mapping module 270. The first allocation module 210 is configured to allocate a virtual cache for a thread; the number of the virtual caches is multiple, a mapping relation is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of the single first memory hardware is smaller than that of the single second memory hardware. The calculation module 220 is configured to calculate the access frequency of each physical memory area during each predetermined period. The selecting module 230 is configured to select, according to the order from the smaller access frequency to the larger access frequency, the physical memory area within the first preset range before the first preset range as the physical memory area with the lower access frequency. The determining module 240 is configured to determine, according to the mapping relationship, the virtual cache corresponding to the low access frequency physical memory area as the low access frequency virtual cache. The increasing module 250 is configured to increase a value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, where an initial value of the low access frequency counter is a preset minimum value. The ordering module 260 is configured to order the virtual caches in order of the low access frequency counter value from small to large. The first mapping module 270 is configured to select at least one from the virtual caches in the second predetermined range before the ordering, and establish a mapping relationship with the first physical memory area.

According to another aspect of the embodiments of the present application, another thread storage location allocation apparatus is provided, and specifically, the increasing module 250 is replaced by a decreasing module, where the decreasing module is configured to decrease a value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, where an initial value of the low access frequency counter is a preset maximum value. The role of the ordering module 260 described above is also replaced with ordering the virtual caches in order of the value of the low access frequency counter from large to small. The function of the remaining modules remains the same.

In some embodiments, the apparatus further comprises a determination module, a control module, and a second mapping module. The judging module is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value. The control module is used for controlling the ordering module to execute the step of ordering the virtual caches according to the order of the values of the low access frequency counter from small to large when the judgment module judges that the virtual caches are yes. And the second mapping module is used for establishing a mapping relation between the virtual cache and the first physical memory area when the judging module judges that the virtual cache is not in the first physical memory area.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the apparatus further includes a second allocation module, where the second allocation module is configured to allocate the same virtual cache for the thread that applied for caching again as it applied for previously. The first mapping module comprises a first judging sub-module and a first mapping sub-module. The first judging submodule is used for judging whether the virtual cache corresponding to the thread for applying for the cache again is located in a first preset range of sequencing. And the first mapping submodule is used for establishing a mapping relation between the virtual cache corresponding to the thread which applies for the cache again and the first physical memory area when the judging submodule judges that the thread is yes.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the first mapping module includes a second mapping sub-module, where the second mapping sub-module is configured to, when the system is in an idle state, select a virtual cache that does not perform a direct memory operation from virtual caches in a first second preset range, and establish a mapping relationship with the first physical memory area.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the second mapping submodule includes: a judging unit and a control unit. The judging unit is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value when the system is in an idle state. And the control unit is used for selecting a virtual cache which is not subjected to direct memory operation from the virtual caches in the second preset range and establishing a mapping relation with the first physical memory area when the judging unit judges that the virtual cache is not subjected to direct memory operation.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the apparatus includes a third mapping module, where the third mapping module is configured to select at least one from virtual caches in a third predetermined range after the ordering, and establish a mapping relationship with the second physical memory area.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the third mapping module includes a third mapping sub-module, where the third mapping sub-module is configured to, when the system is in an idle state, select a virtual cache that does not perform a direct memory operation from virtual caches in a third preset range, and establish a mapping relationship with the second physical memory area.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the number of low access frequency counters is fixed; the apparatus further comprises: the device comprises a first marking module, a first releasing module and a first resetting module. The first marking module is used for marking the selected virtual cache which is in mapping relation with the second physical memory area after the second mapping module performs the step of selecting at least one from the virtual caches in the third preset range after the sorting and establishing the mapping relation with the second physical memory area. The first releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter. The first reset module is configured to reset a value of the low access frequency counter from which the correspondence is released to an initial value, for establishing a correspondence with a virtual cache corresponding to a newly applied thread in a subsequent step, and separate the low access frequency counter from the virtual cache from which the correspondence is released when the subsequent step of ordering the virtual caches in order of decreasing the value of the low access frequency counter is performed by the subsequent ordering module, and select at least one from the virtual caches in a preceding second preset range of ordering when the subsequent step of establishing a mapping relationship with the first physical memory region is performed by the subsequent first mapping module, the preceding second preset range of ordering including each of the two separate orderings.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the number of low access frequency counters is fixed; the apparatus further comprises: the device comprises a second marking module, a second releasing module and a second resetting module. The second marking module is used for selecting at least one from the virtual caches in the second preset range before the first mapping module is ordered, and marking the selected virtual cache which is in the mapping relation with the first physical memory area after the virtual cache is in the mapping relation with the first physical memory area. The second releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter. The second resetting module is configured to reset a value of the low access frequency counter from which the correspondence is released to an initial value, so as to be used for establishing a correspondence with a virtual cache corresponding to a newly applied thread in a subsequent step, and separate the low access frequency counter from the virtual cache from which the correspondence is released when the subsequent step of ordering the virtual caches in order of the low access frequency counter from a small value to a large value is performed by the subsequent ordering module, and select at least one from the virtual caches in a first second preset range before the ordering when the subsequent step of establishing a mapping relationship with the first physical memory area is performed by the first mapping module, where the first second preset range before the ordering includes each of the two separate orderings.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, pre-establishing the low access frequency counter for the virtual cache conditions includes: the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or, in a preset time period, the application number of the virtual cache is greater than or equal to a preset number; and/or, in the preset time period, the total time length of the virtual buffer occupying the physical memory area is greater than or equal to the preset time length.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the apparatus further includes a recording module, where the recording module is configured to record a value of the low access frequency counter, so that when the same step is performed again after the next power-on, the recording module accumulates the value of the low access frequency counter.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In some embodiments, the apparatus further comprises: and the recovery module is used for recovering the value of the low access frequency counter to an initial value at each start-up.

It will be appreciated that this embodiment is equally applicable to another thread storage location allocation apparatus provided in the embodiments of the present application.

In accordance with an aspect of the present embodiment, a System On Chip (SOC) Chip is also provided, and referring to fig. 10 specifically, the System on Chip 300 includes a memory management unit 310, a first memory hardware 320 and a second memory hardware 330. Wherein the capacity of the monolithic first memory hardware 320 is smaller than the capacity of the monolithic second memory hardware 330, when the system-on-chip 300 runs a thread, the memory management unit 310 can allocate a memory location of the thread by using any one of the two thread memory location allocation methods provided in the above embodiments.

According to an aspect of the embodiments of the present application, there is further provided a computing device, where the embodiments of the present application do not limit a specific implementation manner of the computing device, and referring specifically to fig. 11, a structure of the computing device is shown.

As shown in fig. 11, the computing device may include: a processor 402, a communication interface (Communications Interface) 404, a memory 406, and a communication bus 408.

Wherein: processor 402, communication interface 404, and memory 406 communicate with each other via communication bus 408. A communication interface 404 for communicating with network elements of other devices, such as clients or other servers. The processor 402 is configured to execute the program 410, and may specifically perform relevant steps in any one of the two thread storage location allocation methods provided in the foregoing embodiments.

In particular, program 410 may include program code including computer-executable instructions.

The processor 402 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors included by the computing device may be the same type of processor, such as one or more CPUs; but may also be different types of processors such as one or more CPUs and one or more ASICs.

Memory 406 for storing programs 410. Memory 406 may comprise high-speed RAM memory or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.

The embodiment of the invention also provides a computer readable storage medium, such as an optical disc, on which an execution program is stored, and the execution program when executed implements any one of the two thread storage location allocation methods provided in the above embodiment.

The computer readable storage medium according to the embodiments of the present disclosure is not limited to the above-described embodiments, and may be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In an embodiment of the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

In which the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures, for example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. The numbering of the steps herein is for convenience of illustration and reference only and is not intended to limit the order in which the steps are performed, the particular order of execution being determined by the technology itself, and the skilled artisan can determine various allowable, reasonable orders based on the technology itself.

It should be noted that step numbers (letter or number numbers) are used in the present invention to refer to certain specific method steps for convenience and brevity only, and are not intended to limit the order of the method steps by letter or number in any way. It will be apparent to those skilled in the art that the sequence of steps of the relevant method should be determined by the technique itself, should not be unduly limited by the presence of step numbers, and that one skilled in the art can determine various allowable, reasonable sequences of steps based on the technique itself.

It should be noted that, the specific values, the relationships between the values, and the selection of the value intervals, not only require the inventor to have a theoretical basis far exceeding the level of those skilled in the art, but also require creative attempts and selections according to the expected target design result, and are aided with several difficult experiments, so that the expected target result can be obtained finally. The determination of this value is never available to those of ordinary skill in the art, and first, the initial selection interval of these proportional relationships is (O, +_j) and only those having ordinary skill in the art cannot narrow the initial selection interval to determine the approximate range for selection by subsequent tests, and further, they do not have the creative ability to construct a viable test to accurately obtain the specific final selected value interval of the best effect within this narrowed approximate range.

Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.

It will be understood that the above-described embodiments are merely illustrative and not restrictive, and that all obvious or equivalent modifications and substitutions to the details given above may be made by those skilled in the art without departing from the underlying principles of the invention, are intended to be included within the scope of the appended claims.

Claims (39)

1. A thread storage position allocation method is characterized in that: comprising the following steps:

virtual caches are allocated for threads; the number of the virtual caches is multiple, a mapping relation is established between the virtual caches and a plurality of physical memory areas, wherein the physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of first memory hardware is smaller than that of a single piece of second memory hardware;

calculating the access frequency of each physical memory area in each preset time period;

selecting a physical memory area in a first preset range as a low access frequency physical memory area according to the order of the access frequency from small to large;

According to the mapping relation, determining the virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache;

increasing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value;

ordering the virtual caches in order of the low access frequency counter value from small to large;

at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area.

2. The thread storage location allocation method of claim 1, wherein prior to ordering the virtual caches in order of the low access frequency counter value from small to large, the method further comprises:

judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value;

if yes, executing the step of sequencing the virtual caches in the order from the low access frequency counter to the high access frequency counter;

if not, establishing a mapping relation between the virtual cache and the first physical memory area.

3. The thread storage location allocation method according to claim 1, wherein before ordering the virtual caches in order of the low access frequency counter value from small to large, comprising: the same virtual cache as that in the previous application is allocated for the thread which applies for the cache again;

at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area, wherein the method comprises the following steps: judging whether the virtual cache corresponding to the thread applying for cache again is located in the first preset range of sequencing; if yes, establishing a mapping relation between the virtual cache corresponding to the thread applying for the cache again and the first physical memory area.

4. The method for allocating thread storage locations according to claim 1, wherein selecting at least one from virtual caches within a second predetermined range before ordering, and establishing a mapping relationship with the first physical memory area, includes:

when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges, and establishing a mapping relation with the first physical memory area.

5. The method for allocating thread storage locations according to claim 4, wherein when the system is in an idle state, selecting a virtual cache that does not perform a direct memory operation from the virtual caches in the second preset range, and establishing a mapping relationship with the first physical memory area, includes:

when the system is in an idle state, judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value;

if not, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges, and establishing a mapping relation with the first physical memory area.

6. The thread storage location allocation method according to claim 1, wherein after said ordering of said virtual caches in order of the value of said low access frequency counter from small to large, said method further comprises:

and selecting at least one from the virtual caches in the third preset range after sequencing, and establishing a mapping relation with the second physical memory area.

7. The method for allocating thread storage locations according to claim 6, wherein selecting at least one from the virtual caches in the third predetermined range after the ordering, and establishing a mapping relationship with the second physical memory area, includes:

And when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the rear third preset range, and establishing a mapping relation with the second physical memory area.

8. The thread storage location allocation method according to claim 6, wherein the number of low access frequency counters is fixed;

at least one virtual cache in a third preset range after the sorting is selected, and after the mapping relation is established between the virtual cache and the second physical memory area, the method further comprises the steps of:

marking the selected virtual cache which establishes a mapping relation with the second physical memory area;

releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread, and sorting the low access frequency counter not of which the correspondence is released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual cache in order of the low access frequency counter value from small to large is performed subsequently, and selecting at least one from the virtual caches in a second preset range before sorting, wherein the second preset range before sorting comprises a part of each of the two separated sorting when the step of establishing a mapping relationship with the first physical memory area is performed subsequently.

9. The thread storage location allocation method according to any one of claims 1 to 8, wherein the number of low access frequency counters is fixed;

at least one virtual buffer in the second preset range before the sorting is selected, and after the mapping relation is established between the virtual buffer and the first physical memory area, the method further comprises the steps of:

marking the selected virtual cache which establishes a mapping relation with the first physical memory area;

releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread, and sorting the low access frequency counter not of which the correspondence is released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual cache in order of the low access frequency counter value from small to large is performed subsequently, and selecting at least one from the virtual caches in a second preset range before sorting, wherein the second preset range before sorting comprises a part of each of the two separated sorting when the step of establishing a mapping relationship with the first physical memory area is performed subsequently.

10. The thread storage location allocation method according to any one of claims 1 to 8, wherein the pre-establishing a low access frequency counter condition for the virtual cache comprises:

the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or the number of the groups of groups,

in a preset time period, the application times of the virtual cache are larger than or equal to preset times; and/or the number of the groups of groups,

and within a preset time period, the total time length of the virtual cache occupying the physical memory area is greater than or equal to a preset time length.

11. The thread storage location allocation method according to any one of claims 1 to 8, wherein after the increasing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method comprises:

and recording the value of the low access frequency counter so as to accumulate the value of the low access frequency counter when the same step is executed again after the next power-on.

12. The thread storage location allocation method of any of claims 1-8, wherein the method further comprises:

and restoring the value of the low access frequency counter to an initial value every time the power-on is started.

13. A thread storage location allocation apparatus, comprising:

the first allocation module is used for allocating virtual caches for the threads; the number of the virtual caches is multiple, a mapping relation is established between the virtual caches and a plurality of physical memory areas, wherein the physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of first memory hardware is smaller than that of a single piece of second memory hardware;

the computing module is used for computing the access frequency of each physical memory area in each preset time period;

the selecting module is used for selecting the physical memory area in the first preset range as the low access frequency physical memory area according to the order from the small access frequency to the large access frequency;

the determining module is used for determining the virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache according to the mapping relation;

an increasing module, configured to increase a value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, where an initial value of the low access frequency counter is a preset minimum value;

The sorting module is used for sorting the virtual caches according to the order of the low access frequency counter from small to large;

the first mapping module is used for selecting at least one from the virtual caches in the second preset range before sequencing, and establishing a mapping relation with the first physical memory area.

14. The thread storage location allocation apparatus of claim 13 wherein said apparatus further comprises:

the judging module is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value;

the control module is used for controlling the sorting module to execute the step of sorting the virtual caches in the order from the low access frequency counter to the high when the judgment module judges that the virtual caches are the virtual caches;

and the second mapping module is used for establishing a mapping relation between the virtual cache and the first physical memory area when the judging module judges that the virtual cache is not in the first physical memory area.

15. The thread storage location allocation apparatus of claim 13 wherein said apparatus further comprises: the second allocation module is used for allocating the same virtual cache as the thread which applies for the cache again in the previous application;

The first mapping module includes: the first judging submodule is used for judging whether the virtual cache corresponding to the thread applying for cache again is located in the ordered first and second preset ranges or not; and the first mapping sub-module is used for establishing a mapping relation between the virtual cache corresponding to the thread applying for cache again and the first physical memory area when the judging sub-module judges that the thread applying for cache again is yes.

16. The thread storage location allocation apparatus of claim 13 wherein the first mapping module comprises:

and the second mapping sub-module is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges when the system is in an idle state, and establishing a mapping relation with the first physical memory area.

17. The thread storage location allocation apparatus of claim 16 wherein the second mapping submodule comprises:

the judging unit is used for judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value when the system is in an idle state;

and the control unit is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges and establishing a mapping relation with the first physical memory area when the judging unit judges that the virtual cache is not in the second preset range.

18. The thread storage location allocation apparatus of claim 13 wherein said apparatus comprises:

and the third mapping module is used for selecting at least one from the virtual caches in a third preset range after sequencing and establishing a mapping relation with the second physical memory area.

19. The thread storage location allocation apparatus of claim 18 wherein said third mapping module comprises:

and the third mapping sub-module is used for selecting a virtual cache which does not perform direct memory operation from the virtual caches in the third preset range when the system is in an idle state, and establishing a mapping relation with the second physical memory area.

20. The thread storage location allocation apparatus of claim 18 wherein the number of low access frequency counters is fixed;

the apparatus further comprises:

the first marking module is used for marking the virtual cache which is selected and has the mapping relation with the second physical memory area after the second mapping module executes the step of selecting at least one from the virtual caches in the third preset range after the sorting and establishing the mapping relation with the second physical memory area;

The first releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

a first resetting module, configured to reset a value of a low access frequency counter from which a correspondence is released to an initial value, so as to be used for establishing a correspondence with a virtual cache corresponding to a newly applied thread in a subsequent step, and when the sorting module performs the step of sorting the virtual caches in order of the low access frequency counter from small to large, sorting is performed between the low access frequency counter from which the correspondence is not released and the virtual cache from which the correspondence is released, and when the first mapping module performs the step of selecting at least one from virtual caches in a first second preset range of sorting, and establishing a mapping relationship with the first physical memory area in the first preset range of sorting, the first second preset range of sorting includes each part of two separated sorting.

21. The thread storage location allocation apparatus of any of claims 13-20 wherein the number of low access frequency counters is fixed;

the apparatus further comprises:

The second marking module is used for marking the virtual cache which is selected and has the mapping relation with the first physical memory area after the first mapping module executes the at least one virtual cache which is selected from the virtual caches in the second preset range before the ordering and has the mapping relation with the first physical memory area;

the second releasing module is used for releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

and a second resetting module, configured to reset a value of the low access frequency counter from which the correspondence is released to an initial value, so as to be used for establishing a correspondence with a virtual cache corresponding to a newly applied thread in a subsequent step, and when the sorting module performs the step of sorting the virtual caches in order of the low access frequency counter from a small value to a large value in the subsequent step, sort the low access frequency counter not from which the correspondence is released and the virtual cache from which the correspondence is released separately, and when the first mapping module performs the step of selecting at least one from the virtual caches in a first second preset range of sorting, and establishes a mapping relationship with the first physical memory area in the previous second preset range of sorting, each part of the two separated sorting steps is included in the previous second preset range of sorting.

22. The thread storage location allocation apparatus according to any one of claims 13 to 20, wherein pre-establishing a low access frequency counter condition for the virtual cache comprises:

the capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or the number of the groups of groups,

in a preset time period, the application times of the virtual cache are larger than or equal to preset times; and/or the number of the groups of groups,

and within a preset time period, the total time length of the virtual cache occupying the physical memory area is greater than or equal to a preset time length.

23. The thread storage location allocation apparatus of any of claims 13-20, wherein the apparatus further comprises:

and the recording module is used for recording the value of the low access frequency counter so as to accumulate the value of the low access frequency counter when the same step is executed again after the next power-on.

24. The thread storage location allocation apparatus of any of claims 13-20, wherein the apparatus further comprises:

and the recovery module is used for recovering the value of the low access frequency counter to an initial value when the computer is started each time.

25. A thread storage position allocation method is characterized in that: comprising the following steps:

Virtual caches are allocated for threads; the number of the virtual caches is multiple, a mapping relation is established between the virtual caches and a plurality of physical memory areas, wherein the physical memory areas comprise a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of first memory hardware is smaller than that of a single piece of second memory hardware;

calculating the access frequency of each physical memory area in each preset time period;

selecting a physical memory area in a first preset range as a low access frequency physical memory area according to the order of the access frequency from small to large;

according to the mapping relation, determining the virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache;

reducing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value;

ordering the virtual caches in the order of the low access frequency counter from high to low;

At least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area.

26. The thread storage location allocation method according to claim 25, wherein before said ordering of said virtual caches in order of the value of said low access frequency counter from higher to lower, said method further comprises:

judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value;

if yes, executing the step of sequencing the virtual caches according to the sequence from the high value to the low value of the low access frequency counter;

if not, establishing a mapping relation between the virtual cache and the first physical memory area.

27. The thread storage location allocation method according to claim 25, wherein before said ordering said virtual caches in order of the value of said low access frequency counter from high to low, comprising: the same virtual cache as that in the previous application is allocated for the thread which applies for the cache again;

at least one virtual buffer in a second preset range before sequencing is selected, and a mapping relation is established between the virtual buffer and the first physical memory area, wherein the method comprises the following steps: judging whether the virtual cache corresponding to the thread applying for cache again is located in the first preset range of sequencing; if yes, establishing a mapping relation between the virtual cache corresponding to the thread applying for the cache again and the first physical memory area.

28. The method for allocating thread storage locations according to claim 25, wherein selecting at least one from among virtual caches within a second predetermined range before ordering, and establishing a mapping relationship with the first physical memory area, comprises:

when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges, and establishing a mapping relation with the first physical memory area.

29. The method for allocating thread storage locations according to claim 28, wherein when the system is in an idle state, selecting a virtual cache that does not perform a direct memory operation from the virtual caches in the second preset range, and establishing a mapping relationship with the first physical memory area, includes:

when the system is in an idle state, judging whether the residual total capacity of all the first physical memory areas is smaller than or equal to a preset capacity value;

if not, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the first and second preset ranges, and establishing a mapping relation with the first physical memory area.

30. The thread storage location allocation method according to claim 25, wherein after said ordering of said virtual caches in order of the value of said low access frequency counter from higher to lower, said method further comprises:

and selecting at least one from the virtual caches in the third preset range after sequencing, and establishing a mapping relation with the second physical memory area.

31. The method for allocating thread storage locations according to claim 30, wherein selecting at least one from among virtual caches within a third predetermined range after ordering, and establishing a mapping relationship with the second physical memory area, includes:

and when the system is in an idle state, selecting a virtual cache which does not perform direct memory operation from the virtual caches in the rear third preset range, and establishing a mapping relation with the second physical memory area.

32. The thread storage location allocation method of claim 30 wherein the number of low access frequency counters is fixed;

at least one virtual cache in a third preset range after the sorting is selected, and after the mapping relation is established between the virtual cache and the second physical memory area, the method further comprises the steps of:

Marking the selected virtual cache which establishes a mapping relation with the second physical memory area;

releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread, and sorting the low access frequency counter not of which the correspondence is released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual cache in order of the low access frequency counter value from small to large is performed subsequently, and selecting at least one from the virtual caches in a second preset range before sorting, wherein the second preset range before sorting comprises a part of each of the two separated sorting when the step of establishing a mapping relationship with the first physical memory area is performed subsequently.

33. The thread storage location allocation method of any of claims 25-32 wherein the number of low access frequency counters is fixed;

at least one virtual buffer in the second preset range before the sorting is selected, and after the mapping relation is established between the virtual buffer and the first physical memory area, the method further comprises the steps of:

Marking the selected virtual cache which establishes a mapping relation with the first physical memory area;

releasing the corresponding relation between the marked virtual cache and the low access frequency counter;

resetting the value of the low access frequency counter of which the correspondence is released to an initial value for establishing a correspondence with a virtual cache corresponding to a newly applied thread, and sorting the low access frequency counter not of which the correspondence is released and the low access frequency counter of which the correspondence is released separately when the step of sorting the virtual cache in order of the low access frequency counter value from small to large is performed subsequently, and selecting at least one from the virtual caches in a second preset range before sorting, wherein the second preset range before sorting comprises a part of each of the two separated sorting when the step of establishing a mapping relationship with the first physical memory area is performed subsequently.

34. The thread storage location allocation method of any of claims 25-32, wherein pre-establishing a low access frequency counter condition for the virtual cache comprises:

The capacity of the virtual cache application is larger than or equal to a preset threshold value; and/or the number of the groups of groups,

in a preset time period, the application frequency and/or the release frequency of the virtual cache are/is greater than or equal to the preset frequency; and/or the number of the groups of groups,

and within a preset time period, the total time length of the virtual cache occupying the physical memory area is greater than or equal to a preset time length.

35. The thread storage location allocation method according to any one of claims 25 to 32, wherein after the reducing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method comprises:

and recording the value of the low access frequency counter so as to accumulate the value of the low access frequency counter when the same step is executed again after the next power-on.

36. The thread storage location allocation method of any of claims 25-32, wherein the method further comprises:

and restoring the value of the low access frequency counter to an initial value every time the power-on is started.

37. A system-on-chip comprising a memory management unit, first memory hardware and second memory hardware, wherein the capacity of a single block of the first memory hardware is smaller than the capacity of a single block of the second memory hardware, the memory management unit being capable of allocating memory locations of threads using the thread memory location allocation method of any one of claims 1-12 or the thread memory location allocation method of any one of claims 25-36 when the system-on-chip is running threads.

38. A computing device, comprising: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus;

the memory is configured to store executable instructions that cause the processor to perform the thread storage location allocation method of any one of claims 1-12 or the thread storage location allocation method of any one of claims 25-36.

39. A computer-readable storage medium, wherein an execution program is stored on the computer-readable storage medium, the execution program when executed implementing the thread storage location allocation method according to any one of claims 1 to 12 or the thread storage location allocation method according to any one of claims 25 to 36.

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