CN116340074A - Hardware-in-loop test system and test method of multi-core processor system-on-chip - Google Patents
Hardware-in-loop test system and test method of multi-core processor system-on-chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/71—Version control; Configuration management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention provides a hardware-in-loop test system and a test method of a multi-core processor system-on-chip, wherein the system comprises the following steps: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; a code warehouse is arranged in the first server, and the code warehouse stores test codes of different versions; after receiving the target instruction, the first server analyzes the target instruction to obtain a compiling instruction; after receiving the compiling instruction, the second server acquires a corresponding first target code from the first server according to the compiling instruction; compiling second object code for the processor system and the programmable logic unit according to the first object code; the processor system writes and configures the programmable logic unit according to the second target code, outputs a test result according to actual result data output by the configured programmable logic unit, and returns the test result to the user terminal, so that the automatic test of the multi-core processor system on chip can be realized.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a hardware-in-loop testing system and a testing method of a multi-core processor system-on-chip.
Background
System-on-chip refers to the technique of integrating a complete system on a single chip, grouping all or part of the necessary electronic circuitry into packets. So-called complete systems typically include a central processing unit, memory, peripheral circuits, etc. The system-on-chip of the multi-core processor refers to a system-on-chip in which a central processor is a multi-core processor.
The multi-core processor system-on-a-chip may include a processor system and a programmable logic unit; version iterations of a multi-core processor system-on-a-chip are long (typically requiring several hours to tens of hours) in both the processor system and the compilation time of the programmable logic units; in addition, in order to ensure the effectiveness of the multi-core processor system on chip, when the versions of the processor system and the programmable logic unit are changed, testing of the corresponding versions is needed; thus, testing and version management are the most important parts of the multi-core processor system on a chip for the current technology.
Disclosure of Invention
In view of the above, it is proposed to provide a hardware-in-loop test system and a test method of a multi-core processor system-on-chip that overcomes or at least partially solves the above-mentioned problems, comprising:
A hardware-in-the-loop test system, the system comprising: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; the multi-core processor system-on-chip comprises a processor system and a programmable logic unit;
the user terminal is used for responding to user operation and outputting a target instruction to the first server; obtaining a test result generated for the target instruction;
a code warehouse is arranged in the first server, and the code warehouse stores test codes of different versions; the first server is used for judging whether the target instruction is a test instruction or not after receiving the target instruction; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction;
the second server is used for acquiring a corresponding first target code from the first server according to the compiling instruction after receiving the compiling instruction; and compiling second object code for the processor system and the programmable logic unit from the first object code;
the processor system is used for programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
Optionally, the system further comprises a network sharing folder;
the network sharing folder is used for sharing the second target code uploaded by the second server and returning the second target code to the processor system in response to the access of the processor system.
Optionally, the processor system is configured to run an application test program according to the second object code; the application test program is used for programming and configuring the programmable logic unit, starting the programmed and configured programmable logic unit, and generating the test result by comparing actual result data and expected result data output by the programmed and configured programmable logic unit; and outputting the test result.
Optionally, the programmable logic unit is configured to write the actual result data at a preset storage address in a running process; and upon ending operation, sending an interrupt notification to the processor system;
the processor system is used for responding to the interrupt notification and reading the actual result data from the preset storage address.
Optionally, the system further comprises a user defect management system;
The processor system is used for returning the test result to the user terminal and/or sending the test result to the user defect management system;
and the user defect management system is used for feeding back to the user terminal according to the test result.
Optionally, the first server includes: a first sub-server and a second sub-server; the first sub-server is deployed with the code warehouse;
the first sub-server is used for judging whether the target instruction is a test instruction or not; if the target instruction is a test instruction, the target instruction is sent to the second sub-server;
the second sub-server is configured to parse the target instruction to obtain a compiling instruction, and send the compiling instruction to the second server.
The embodiment of the invention also provides a testing method of the multi-core processor system-on-chip, which is applied to the system described in any one of the above, and comprises the following steps:
responding to user operation, judging whether a target instruction received by a first server is a test instruction;
if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction;
Acquiring a first target code corresponding to a compiling instruction, and compiling a second target code for the processor system and the programmable logic unit according to the first target code;
and programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
The embodiment of the invention also provides a testing device of the multi-core processor system-on-chip, which is applied to the system described in any one of the above, and comprises:
the judging module is used for responding to the user operation and judging whether the target instruction received by the first server is a test instruction or not;
the analysis module is used for analyzing the target instruction to obtain a compiling instruction if the target instruction is a test instruction;
the compiling module is used for acquiring a first target code corresponding to the compiling instruction and compiling a second target code aiming at the processor system and the programmable logic unit according to the first target code;
and the test module is used for programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
The embodiment of the invention also provides electronic equipment, which comprises a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein the computer program realizes the test method of the multi-core processor system-on-chip when being executed by the processor.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes the testing method of the multi-core processor system-on-chip when being executed by a processor.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides a hardware-in-loop test system, which comprises: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; the multi-core processor system-on-chip comprises a processor system and a programmable logic unit; the user terminal is used for responding to the user operation and outputting a target instruction to the first server; obtaining a test result generated for the target instruction; a code warehouse is arranged in the first server, and the code warehouse stores test codes of different versions; the first server is used for judging whether the target instruction is a test instruction or not after receiving the target instruction; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction; the second server is used for acquiring a corresponding first target code from the first server according to the compiling instruction after receiving the compiling instruction; compiling second object code for the processor system and the programmable logic unit according to the first object code; and the processor system is used for programming and configuring the programmable logic unit according to the second target code and outputting a test result according to the actual result data output by the programmed and configured programmable logic unit. The system provided by the embodiment of the invention can realize automatic test of the multi-core processor system on chip.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the description of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a hardware-in-the-loop test system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another hardware-in-the-loop test system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a process of data interaction according to an embodiment of the present invention;
FIG. 4 is a flow chart of steps of a method for testing a system-on-chip of a multi-core processor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a testing apparatus for a system-on-chip of a multi-core processor according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, a schematic structural diagram of a hardware-in-the-loop test system according to an embodiment of the present invention is shown, including: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; the multi-core processor system-on-a-chip may include a processor system and a programmable logic unit.
In one embodiment of the present invention, the user terminal is configured to output a target instruction to the first server in response to a user operation; and acquiring a test result generated for the target instruction.
In practical application, when the versions of the processor system and the programmable logic unit change, testing of the corresponding versions is needed; at this time, the user may perform a user operation on the user terminal, which may include an operation of selecting a version to be tested.
In response to the user operation, the user terminal may output a target instruction to the first server to drive the subsequent detection process.
As an example, the user terminal may also receive a test result generated by the hardware-in-the-loop test system based on the target instruction; after receiving the test result, the user terminal can display the test result to the user so that the user knows the test result.
In an embodiment of the present invention, a code repository is provided in the first server, the code repository storing test codes of different versions; the first server is used for judging whether the target instruction is a test instruction or not after receiving the target instruction; and if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction.
In practical applications, the iteration of the version of the test code may cause different custom circuit structures generated by the programmable logic units in the multi-core processor system, in order to test the custom logic circuits with different structures, a code repository may be set in advance in the first server, where the code repository may store different versions of the test code, the first server may be used to perform version management on the test code, and different versions of the test code may be used to test the programmable logic units of different custom logic circuits in the multi-core processor system.
As an example, after receiving the target instruction, the first server may first determine whether the target instruction is a test instruction; if the target instruction is a test instruction, the first server may parse it to obtain a compiled instruction, and send the compiled instruction to the second server. The compilation instructions may be used to instruct the second server to compile the code.
And if the target instruction is not a test instruction, the first server will act as a corresponding process for the target instruction, such as: and displayed on the interface corresponding to the first server, which is not limited in the embodiment of the present invention.
In practical applications, the first server may be used to implement persistent integration; specifically, the method can be used for being responsible for the automatic control of the whole flow; for example: the instruction is parsed, the pull code is controlled, the result returned by the user defect management system is controlled, and the like, which is not limited by the embodiment of the invention.
In an embodiment of the present invention, the second server is configured to obtain, after receiving the compiling instruction, a corresponding first object code from the first server according to the compiling instruction; and compiling second object code for the processor system and the programmable logic unit from the first object code.
After receiving the compiling instruction, the second server can acquire a corresponding first target code from the first server according to the compiling instruction; the first object code may be obtained based on the version currently required to be detected.
The second server may then compile second object code for testing the processor system and the programmable logic unit based on the first object code.
In an embodiment of the present invention, the processor system is configured to write and configure the programmable logic unit according to the second object code, and output the test result according to the actual result data output by the programmed and configured programmable logic unit.
After compiling to obtain the second target code, the second server can send the second target code to a processor system of the multi-core processor system on chip; after receiving the second target code, the processor system can write and configure the programmable logic unit based on the second target code so as to write and configure the programmable logic unit based on the version specified by the target instruction, thereby completing the writing and configuration of the programmable logic unit under the version specified by the target instruction.
After programming and configuring the programmable logic unit are completed, the programmable logic unit after programming and configuring can be started; at this time, recording may be performed based on the running programmable logic unit to obtain actual result data.
As an example, the processor system may also output test results based on actual result data output by the programmed and configured programmable logic units; thereby completing the testing of the processor system and programmable logic units under the version specified by the target instruction.
After obtaining the actual result data output by the programmed and configured programmable logic unit, the processor system can generate a test result according to the actual result data; meanwhile, the processor system may feed back the test result to the user terminal, which is not limited in the embodiment of the present invention.
In one embodiment of the invention, the processor system is configured to run an application test program according to the second object code; the application test program is used for programming and configuring the programmable logic unit, starting the programmed and configured programmable logic unit, and generating a test result by comparing actual result data and expected result data output by the programmed and configured programmable logic unit; and outputting a test result.
As an example, the processor system, upon receiving the second object code, may compile software test case code, which may be used to run the application test program.
After the application test program is run, the programmable logic unit can be programmed and configured; and, the programmable logic unit after programming and configuration can be started after programming and configuration are completed, which is not limited by the embodiment of the invention.
In one embodiment of the present invention, the programmable logic unit is configured to write actual result data at a preset storage address during an operation process; and upon ending the run, sending an interrupt notification to the processor system.
When the programmable logic unit ends operation, an interrupt notification may be sent to the processor system to notify the processor system that the test is complete.
And the processor system is used for responding to the interrupt notification and reading actual result data from a preset storage address.
After receiving the interrupt notification, the processor system can respond to the interrupt notification to read actual result data from a preset storage address; in order to avoid the timeout from being blocked when the actual result data is read, a timeout waiting time can be set, and when the actual result data is not acquired after the timeout waiting time is exceeded, the acquisition is ended, and error information is returned to the user terminal and/or the user defect management system.
As an example, after receiving the interrupt notification, the application test program running in the processor system may read the actual result data from the preset memory address in response to the interrupt notification, which is not limited by the embodiment of the present invention.
After reading the actual result data, the processor system may generate a test result by comparing the actual result data output by the programmed and configured programmable logic unit with the expected result data. The expected result data may be indicative of the result data expected for the current test.
In an embodiment of the present invention, the system further comprises a user defect management system;
and the processor system is used for returning the test result to the user terminal and/or sending the test result to the user defect management system.
And the user defect management system is used for feeding back to the user terminal according to the test result.
In practical application, the hardware-in-the-loop test system may also include a user defect management system; after the processor system obtains the test results, the test results may be sent to the user defect management system.
After receiving the test result, the user defect management system can feed back to the user terminal according to the test result.
Alternatively, the processor system may also directly return to the user terminal after obtaining the test result, which is not limited in the embodiment of the present invention.
In one embodiment of the present invention, a first server includes: a first sub-server and a second sub-server; the first sub-server is deployed with a code repository.
As an example, the first server may include a first sub-server and a second sub-server; the first sub-server can be deployed with a code warehouse, and the second sub-server can be used for analyzing target instructions.
The first sub-server is used for judging whether the target instruction is a test instruction or not; and if the target instruction is a test instruction, sending the target instruction to the second sub-server.
In practical application, the user terminal may send the target instruction to the first sub-server; after receiving the target instruction, the first sub-server may first determine whether the target instruction is a test instruction.
If the target instruction is a test instruction, the first sub-server may send the target instruction to the second sub-server for resolution.
And if the target instruction is not a test instruction, the first sub-server may perform a corresponding operation in response to the target instruction, for example: the target instruction is displayed on the interface corresponding to the first sub-server, which is not limited in the embodiment of the present invention.
And the second sub-server is used for analyzing the target instruction, pulling codes from a code warehouse of the first sub-server and the like, obtaining a compiling instruction, and sending the compiling instruction to the second server.
After receiving the target instruction, the second sub-server can analyze the target instruction to obtain a compiling instruction contained in the target instruction; the parsed compiled instructions may then be sent to a second server.
In addition, the second sub-server can also be used to implement persistent integration; specifically, the method can be used for being responsible for the automatic control of the whole flow; for example: the instruction is parsed, the pull code is controlled, the result returned by the user defect management system is controlled, and the like, which is not limited by the embodiment of the invention.
In one embodiment of the present invention, the system further comprises a network sharing folder;
and the network sharing folder is used for sharing the second target code uploaded by the second server and returning the second target code to the processor system in response to the access of the processor system.
In practical application, the hardware-in-the-loop test system may further include a network sharing folder; files of hardware among units in the ring test system can be transmitted in a network sharing folder mounting mode.
In particular, the second server may move the second object code to the network shared folder for access by the processor system.
The processor system may obtain the second object code by accessing a network shared folder. In particular, the processor system may read the second object code directly from the network shared folder, as embodiments of the invention are not limited in this respect.
Referring to fig. 2, a schematic diagram of another hardware-in-the-loop test system according to an embodiment of the present invention may include a user terminal, a GitLab server (i.e., the first sub-server above), a Jenkins server (i.e., the second sub-server above), a company server (i.e., the second server above), and Xilinx MPSoC (Multi Processor System on Chip, multi-core processor system-on-a-chip) devices. The Xilinx MPSoC device may be deployed on an FPGA (Field Programmable Gate Array ) computing board card. The main control chip on the FPGA computing board is a Xilinx MPSoC device, and MPSoC comprises a PS (processor system, processing System) part and a PL (programmable logic unit, programmable Logic) part; wherein PS runs linux and PL runs programmable logic custom circuits of the DUT.
Meanwhile, in order to ensure the normal operation of the system on a chip of the multi-core processor, peripheral circuits such as: flash, EMMC (Embedded Multi Media Card )/SD (Secure Digital card), DRAM (Dynamic Random Access Memory ), etc., as embodiments of the present invention are not limited in this respect.
(1) User terminal: and starting hardware in-loop test and obtaining test results.
(2) GitLab server: and running the git service, wherein the server is used as a code warehouse to carry out the version management of codes.
(3) Jenkins server: the server runs Jenkins service and is responsible for continuous integration work of codes.
(4) Compile server: the server is provided with a development environment corresponding to the MPSoC device and login information of the MPSoC, is responsible for compiling the code to be tested, and sends the compiled configuration file to the MPSoC. Meanwhile, the FPGA computer board is responsible for receiving the test result through a network, and sending the test result to a GitLab server or informing a user through a defect tracking management system.
(5) FPGA computing board card: and the Xilinx MPSoC device is deployed, and the test object and the test program finally run on the Xilinx MPSoC device. The Xilinx MPSoC device comprises two parts PS and PL. A PL section internally generates a custom logic circuit generated from a user code to be tested as a DUT (Design Under Test, test object); the PS part runs a Linux operating system customized by the Xilinx Petalinux development suite, and a test application program runs on the operating system for completing programming of the PL part, configuration and status reading of the DUT, and network communication with a Jenkins server, a Compile server and the like.
Through the assembly, the system construction of the hardware-in-the-loop test method is realized. The code to be tested is deployed on an FPGA computing board card by means of a GitLab code management tool (or other similar tools), a continuous integration tool (Jenkins or other similar tools), an Xilinx compiling tool and the like, testing is performed on the board card in real time, and finally a user is informed of the test result through a user defect management system (for example, jira) or GitLab and the like.
FIG. 3 is a schematic diagram of a data interaction process according to an embodiment of the present invention:
the first stage is that the user designates the code branches used by PS and PL according to the test requirement, sends the command of the comment test under the corresponding test PL code branch on the GitLab, and starts the test. The command may be based on the code/engineering custom regular expression to be tested, e.g., may include information such as the PL code version number to be tested, the PS application code version number to be tested, etc.
The second stage is that the GitLab server sends a command for the command test to the Jenkins server when determining the command for the test.
The third stage is to send compiling command through the Jenkins server; at this time, the Jenkins server may feed back a message to the user terminal to inform the user that the test is started normally.
Compiling the PL side and PS side designs for a Compile server to generate configuration files;
and the fifth stage is on-board testing of the FPGA, and PS and PL interactive testing.
The sixth stage is to collect test information and inform the user of the test information through a user defect management system (Jira) or GitLab or the like.
Specific:
1. according to the test requirement, the user carries out the comment on the corresponding branch of the corresponding test PL code on the interface of the GitLab through the user terminal, and starts the test.
The user can select the hardware code branch to be tested in the hardware code warehouse of the PL part to be tested of the GitLab, and according to the test requirement, the user can carry out the comment according to the designed instruction format, and start the test. The interface of the GitLab is updated synchronously.
The command may be in a custom format according to the code/project to be tested, for example, may include information such as the project version number of the PL code to be tested, the code version number of the PS application to be tested, and the like.
2. After the user performs the comment on the interface of the GitLab, the GitLab server judges whether the comment content is a test instruction according to the customized comment instruction regular expression.
If the test instruction is the test instruction, the test instruction is sent to the Jenkins server. And notifying the Jenkins server to analyze the test instruction, analyzing out a corresponding compiling instruction and sending the compiling instruction to the Compile server.
If the test instruction is not the test instruction, the GitLab server processes the test instruction as common comment information and displays the common comment information on a GitLab interface.
And after receiving the compiling instruction, the Compile server pulls the software codes and the hardware codes of the designated branches according to the comment information to generate a PL configuration code stream, compiles and generates boot. Bin files by using customized Linux, pulls the application software test case codes of the designated branches, and moves the boot. Bin files and the corresponding application software test case codes to the shared network folder.
The Compile server adopts an automation script to pull codes from Git, and generates a configuration code stream of a programmable logic part by utilizing MPSoC compiling software Vivado according to engineering automation script in the codes.
Meanwhile, the xsa design description file of the PS design output standard is used for compiling and generating equipment tree pointing to the Linux at the PS side. The project of MPSoC is built by using script according to the Tcl command supported by Xilinx. The user only needs to update the design code and then execute the script, so that the iterative updating of the design can be completed. The hardware-in-the-loop test method integrates this mode into the test flow, constructing a standardized test flow. The standardized test flow enables the hardware IP test flow and the platform to be relatively independent in change, and is very important for the division of functional design and the positioning of defects.
The Compile server pulls petrinux engineering codes from the GitLab server through an automation script, and generates files such as customized boot. Bin, image mirror Image and the like with specific equipment trees through a customized Linux compiling tool Petaliinux provided by an MPSoC provider by using the generated information such as xsa description files, configuration code streams and the like.
After the PS receives the configuration code stream, the PL portion is re-programmed through the fpga manager interface. After the programming is completed, compiling software Test case codes to generate a software Test case Test app.
The test case code is pulled from the GitLab server by an automation script and synchronized to the MPSoC through a network sharing folder. The PS part compiles the Test case code to generate a Test app of the Test application program
Test app starts a PL test program, configures a PL part of hardware test object DUT, and the DUT programmable logic customizing circuit starts to run and generates a result; after the DUT finishes testing, sending an interrupt notification to the Test app; after the Test app receives the interrupt notification, reading a preset storage address to collect actual result data from the preset storage address, and obtaining a Test result according to the actual result data and expected result data; and then, synchronizing the test result to the Jenkins server through the network sharing folder.
PS burns PL through FPGA_manager.
The PS executes the application Test app to complete configuration and start up of the DUT custom logic. After the DUT is completed, the DUT informs the Test app through an interrupt, and the Test app is required to read the storage space of the DUT execution result data and compare with expected result data, so that a Test result is obtained. The user may define a timeout period as needed and return an error if the DUT is running timeout.
The Test app and the Jenkins server also use a network sharing folder for communication.
The Jenkins server gathers log information and informs the user of the test information through a user defect management system (e.g., jira) or GitLab, etc.
The Jenkins server gathers log information and informs the user of the test information via a user defect management system (e.g., jira or otherwise), gitLab, etc.
The communication between the server and the MPSOC adopts network sharing folder mount for communication, and the file server places the files such as boot. Bin, image mirror Image and the like and software test case codes in the sharing folder, and the MPSOC is accessed through nfs (network file system) network sharing folder mount.
The embodiment of the invention provides a hardware-in-loop test system, which comprises: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; the multi-core processor system-on-chip comprises a processor system and a programmable logic unit; the user terminal is used for responding to the user operation and generating a target instruction; obtaining a test result generated for the target instruction; a code warehouse is arranged in the first server, and the code warehouse stores test codes of different versions; the first server is used for judging whether the target instruction is a test instruction or not after receiving the target instruction; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction; the second server is used for acquiring a corresponding first target code from the first server according to the compiling instruction after receiving the compiling instruction; compiling second object code for the processor system and the programmable logic unit according to the first object code; and the processor system is used for programming and configuring the programmable logic unit according to the second target code and outputting a test result according to the actual result data output by the programmed and configured programmable logic unit. The system provided by the embodiment of the invention can realize automatic test of the multi-core processor system on chip.
Referring to fig. 4, a flowchart illustrating steps of a method for testing a system on a chip of a multi-core processor according to an embodiment of the present invention may be applied to the hardware-in-loop test system as described above.
Specifically, the method comprises the following steps:
In practical application, when the versions of the processor system and the programmable logic unit change, testing of the corresponding versions is needed; at this time, the user may perform a user operation on the user terminal, which may include an operation of selecting a version to be tested.
In response to the user operation, the user terminal may send a target instruction to the first server to drive the subsequent detection process.
After receiving the target instruction, the first server may first determine whether the target instruction is a test instruction.
And step 402, if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction.
If the target instruction is a test instruction, the first server may parse it to obtain a compiled instruction, and send the compiled instruction to the second server.
And if the target instruction is not a test instruction, the first server will act as a corresponding process for the target instruction.
After receiving the compiling instruction, the second server may obtain the corresponding first object code from the first server according to the compiling instruction.
The second server may then compile second object code for testing the processor system and the programmable logic unit based on the first object code.
And 404, programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to the actual result data output by the programmed and configured programmable logic unit.
After compiling to obtain the second target code, the second server can send the second target code to a processor system of the multi-core processor system on chip; after receiving the second target code, the processor system can write and configure the programmable logic unit based on the second target code so as to write and configure the programmable logic unit based on the version specified by the target instruction, thereby completing the writing and configuration of the programmable logic unit under the version specified by the target instruction.
After programming and configuring the programmable logic unit are completed, the programmable logic unit after programming and configuring can be started; at this time, recording may be performed based on the running programmable logic unit to obtain actual result data.
As an example, the processor system may also obtain actual result data output by the programmed and configured programmable logic unit after operation; to complete testing of the processor system and programmable logic units under the version specified by the target instruction.
After obtaining the actual result data, the processor system can output a test result according to the actual result data; meanwhile, the processor system may feed back the test result to the user terminal, which is not limited in the embodiment of the present invention.
In the embodiment of the invention, whether the target instruction received by the first server is a test instruction is judged in response to user operation; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction; acquiring a first target code corresponding to the compiling instruction, and compiling a second target code for the processor system and the programmable logic unit according to the first target code; and programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit. By the embodiment of the invention, the automatic test of the multi-core processor system-on-chip is realized.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Referring to fig. 5, a schematic structural diagram of a testing apparatus of a system on a chip of a multi-core processor according to an embodiment of the present invention is shown, which may be applied to the hardware-in-loop testing system as described above.
Specifically, the method can comprise the following modules:
a judging module 501, configured to respond to a user operation, and judge whether a target instruction received by the first server is a test instruction;
the parsing module 502 is configured to parse the target instruction if the target instruction is a test instruction, so as to obtain a compiled instruction;
a compiling module 503, configured to obtain a first object code corresponding to the compiling instruction, and compile a second object code for the processor system and the programmable logic unit according to the first object code;
And the test module 504 is configured to write and configure the programmable logic unit according to the second object code, and output a test result according to the actual result data output by the programmed and configured programmable logic unit.
In the embodiment of the invention, whether the target instruction received by the first server is a test instruction is judged in response to user operation; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction; acquiring a first target code corresponding to the compiling instruction, and compiling a second target code for the processor system and the programmable logic unit according to the first target code; and programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit. By the embodiment of the invention, the automatic test of the multi-core processor system-on-chip is realized.
The embodiment of the invention also provides electronic equipment, which comprises a processor, a memory and a computer program which is stored in the memory and can run on the processor, wherein the computer program is executed by the processor to realize the test method of the multi-core processor system-on-chip.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the testing method of the multi-core processor system-on-chip.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above provides a detailed description of a hardware-in-loop test system and a test method of a multi-core processor system-on-chip, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A hardware-in-the-loop test system, the system comprising: the system comprises a user terminal, a first server, a second server and a multi-core processor system-on-chip; the multi-core processor system-on-chip comprises a processor system and a programmable logic unit;
the user terminal is used for responding to user operation and outputting a target instruction to the first server; obtaining a test result generated for the target instruction;
a code warehouse is arranged in the first server, and the code warehouse stores test codes of different versions; the first server is used for judging whether the target instruction is a test instruction or not after receiving the target instruction; if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction;
The second server is used for acquiring a corresponding first target code from the first server according to the compiling instruction after receiving the compiling instruction; and compiling second object code for the processor system and the programmable logic unit from the first object code;
the processor system is used for programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
2. The system of claim 1, further comprising a network shared folder;
the network sharing folder is used for sharing the second target code uploaded by the second server and returning the second target code to the processor system in response to the access of the processor system.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the processor system is used for running an application test program according to the second target code; the application test program is used for programming and configuring the programmable logic unit, starting the programmed and configured programmable logic unit, and generating the test result by comparing actual result data and expected result data output by the programmed and configured programmable logic unit; and outputting the test result.
4. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the programmable logic unit is used for writing the actual result data in a preset storage address in the operation process; and upon ending operation, sending an interrupt notification to the processor system;
the processor system is used for responding to the interrupt notification and reading the actual result data from the preset storage address.
5. The system of claim 1, wherein the system further comprises a user defect management system;
the processor system is used for returning the test result to the user terminal and/or sending the test result to the user defect management system;
and the user defect management system is used for feeding back to the user terminal according to the test result.
6. The system of claim 1, wherein the first server comprises: a first sub-server and a second sub-server; the first sub-server is deployed with the code warehouse;
the first sub-server is used for judging whether the target instruction is a test instruction or not; if the target instruction is a test instruction, the target instruction is sent to the second sub-server;
The second sub-server is configured to parse the target instruction to obtain a compiling instruction, and send the compiling instruction to the second server.
7. A method of testing a system on a chip of a multi-core processor, applied to the system of any of claims 1-6, the method comprising:
responding to user operation, judging whether a target instruction received by a first server is a test instruction;
if the target instruction is a test instruction, analyzing the target instruction to obtain a compiling instruction;
acquiring a first target code corresponding to a compiling instruction, and compiling a second target code for the processor system and the programmable logic unit according to the first target code;
and programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
8. A test apparatus for a system on a chip of a multi-core processor, applied to the system of any of claims 1-6, the apparatus comprising:
the judging module is used for responding to the user operation and judging whether the target instruction received by the first server is a test instruction or not;
The analysis module is used for analyzing the target instruction to obtain a compiling instruction if the target instruction is a test instruction;
the compiling module is used for acquiring a first target code corresponding to the compiling instruction and compiling a second target code aiming at the processor system and the programmable logic unit according to the first target code;
and the test module is used for programming and configuring the programmable logic unit according to the second target code, and outputting a test result according to actual result data output by the programmed and configured programmable logic unit.
9. An electronic device comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, the computer program when executed by the processor implementing the method of testing a multi-core processor system-on-chip of claim 7.
10. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, which when executed by a processor implements the method of testing a multi-core processor system-on-chip of claim 7.
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