CN116339024A - Display panel and display terminal - Google Patents

Abstract

The application discloses display panel and display terminal, including array substrate, the opposite direction base plate and press from both sides the display medium layer of locating between array substrate and the opposite direction base plate, display panel still includes scanning drive circuit, many first signal lines and many second signal lines, many first signal lines set up in array substrate and connect scanning drive circuit, first signal line is used for transmitting scanning auxiliary signal to scanning drive circuit, scanning auxiliary signal is used for driving scanning drive circuit and produces and output scanning signal, with the pixel electrode formation electric field in the control display panel, many second signal lines set up in the opposite direction base plate, wherein, many first signal lines are parallelly connected electricity according to the mode of one-to-one with many second signal lines. The parallel signal lines are arranged on the array substrate and the opposite substrate at the same time, so that the line impedance can be effectively reduced, the line heating is reduced, and the driving capability is improved.

Description

Display panel and display terminal

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display terminal.

Background

The Gate Driver Less technology (GDL) is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so as to replace the external integrated circuit board (Integrated Circuit, IC) to complete the driving of the horizontal scanning line. The GDL technology can reduce the welding procedure of an external IC, and can make the liquid crystal display panel more suitable for manufacturing display products with narrow frames or without frames.

Currently, since many traces are provided in the GDL driving circuit, for example, a clock signal line for transmitting a clock signal, a start signal line for transmitting a start signal, and a reset signal line for transmitting a reset signal, the signal line is affected by impedance in the signal line, so that the clock signal is transmitted further and further, the signal attenuation degree is more serious, and thus the signal is unstable, resulting in a reduction in driving capability. Therefore, how to maintain the stability of the signal and improve the driving capability is a problem to be solved.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present application proposes a display panel and a display terminal that can effectively maintain signal stability.

The application provides a display panel which comprises an array substrate, an opposite substrate and a display medium layer clamped between the array substrate and the opposite substrate, wherein an electric field is formed between the array substrate and the opposite substrate so as to drive the display medium layer to transmit light rays to execute image display. The display panel further comprises a scanning driving circuit, a plurality of first signal lines and a plurality of second signal lines, wherein the plurality of first signal lines are arranged on the array substrate and are connected with the scanning driving circuit, the first signal lines are used for transmitting scanning auxiliary signals to the scanning driving circuit, the scanning auxiliary signals are used for driving the scanning driving circuit to generate and output scanning signals, the scanning signals are used for controlling data signals for image display to be transmitted to pixel electrodes in the display panel so as to form an electric field, and the plurality of second signal lines are arranged on the opposite substrate and are electrically connected in parallel in a one-to-one correspondence mode.

Optionally, the plurality of first signal lines and the plurality of second signal lines include a plurality of signal line groups, wherein one signal line group includes one first signal line and one second signal line which are disposed opposite to each other in a thickness direction of the display panel, and the display panel further includes a plurality of first conductors and a plurality of second conductors, and in one signal line group, both ends of the first signal line and the second signal line are connected to one second conductor through one first conductor, respectively, so that one first signal line and one second signal line are electrically connected in parallel.

Optionally, the display panel further includes a timing control circuit, the plurality of first signal lines are electrically connected to the timing control circuit and the scan driving circuit, the timing control circuit is configured to output a scan auxiliary signal, and the scan auxiliary signal is transmitted to the scan driving circuit through the plurality of first conductors and the plurality of signal line groups.

Optionally, the display panel further includes a display area and a non-display area that are adjacently disposed, the display area includes pixel units arranged in an array for performing image display, and the plurality of first signal lines are disposed in the non-display area on both sides of the display area and used for transmitting scan auxiliary signals to a scan driving circuit disposed in the non-display area, and the scan driving circuit outputs the scan signals according to the scan auxiliary signals to control the pixel units to receive data signals for image display and perform image display.

Optionally, the display panel further includes a display area and a non-display area that are adjacently disposed, the display area includes pixel units arranged in an array for performing image display, and the plurality of first signal lines are disposed in the non-display area at one side of the display area and used for transmitting scan auxiliary signals to a scan driving circuit disposed in the non-display area, and the scan driving circuit outputs the scan signals according to the scan auxiliary signals to control the pixel units to receive data signals for image display and perform image display.

Optionally, the opposite substrate includes a common electrode, where the common electrode is disposed at a position of the opposite substrate corresponding to the display area and is used for providing a common voltage for driving the display medium layer for the pixel unit, the common voltage forms an electric field with the data signals in the pixel electrode, and the plurality of second signal lines are disposed at positions of the opposite substrate corresponding to the non-display area and are used for being connected in parallel with the plurality of first signal lines through the first conductors and the second conductors, respectively.

Optionally, the common electrode and the plurality of second signal lines are made of the same material and in the same process.

Optionally, the display panel further includes a plurality of feedback lines, the plurality of feedback lines are connected to the plurality of first conductors and the timing control circuit, and are configured to detect a size of the scan auxiliary signal transmitted in each signal line group and output the feedback signal to the timing control circuit, and the timing control circuit adjusts the scan auxiliary signal output to the signal line group according to the feedback signal, so that the adjusted scan auxiliary signal is within a preset range.

Optionally, the display panel further includes a data driving circuit, the data driving circuit is disposed in the non-display area, and is configured to receive data control signals from the plurality of signal lines, output data signals to the pixel units according to the data control signals, and the pixel units receive the data signals under the control of the scan signals, so as to perform image display.

The application also discloses a display terminal, including power module and foretell display panel, power module sets up in display panel's one side that deviates from the emergent ray for provide driving voltage when carrying out image display for display panel.

Compared with the prior art, the scanning auxiliary signal output by the time sequence control circuit can be transmitted to the scanning drive circuit or other functional modules through the first signal wire and the second signal wire which are connected in parallel, so that the impedance of the signal wires is reduced, the stability of the scanning auxiliary signal is improved, the scanning auxiliary signal in the first signal wire is detected and fed back through the second signal wire, and the scanning auxiliary signal can be output in a preset range in an adjustable mode, so that the stability of the scanning auxiliary signal is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display terminal according to a first embodiment of the present application

FIG. 2 is a schematic side view of the display panel of FIG. 1;

FIG. 3 is a schematic plan view of an array substrate of the display panel shown in FIG. 2;

FIG. 4 is a schematic layout diagram of the array substrate and the opposite substrate in FIG. 3;

fig. 5 is a schematic cross-sectional view of the display panel of fig. 4.

FIG. 6 is a schematic diagram of a circuit layout of the array substrate in FIG. 4;

FIG. 7 is a schematic diagram of a circuit layout of another array substrate shown in FIG. 4;

FIG. 8 is a schematic diagram of the circuit layout of the opposite substrate in FIG. 4;

fig. 9 is a schematic circuit layout diagram of an opposite substrate according to a second embodiment of the present application.

Reference numerals:

the display device comprises a display terminal-100, a display panel-10, a power module-20, a support frame-30, a display area-10 a, a non-display area-10B, m data lines-S1-Sm, n scanning lines-G1-Gn, a pixel unit-P, an array substrate-10C, a counter substrate-10 d, a display medium layer-10 e, a timing control circuit-11, a data driving circuit-12, a scanning driving circuit-13, a backlight module-17, a first direction-F1, a second direction-F2, a horizontal synchronizing signal-Hsyn, a vertical synchronizing signal-Vsyn, a scanning control signal-Cg, a data control signal-Cs, a first signal line-L1, a second signal line-L2, a first conductor-14A, a second conductor-14B, a third conductor-14C, a common electrode-Vcom and a common electrode line-LM.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display terminal according to a first embodiment of the present application. As shown in fig. 1, the display terminal 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on the back surface of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used for providing driving voltage for the display panel 10 to display images, and the supporting frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20. In other embodiments of the present application, the display terminal 100 may not need to be provided with the support frame 30, for example, a portable electronic device, such as a mobile phone, a tablet computer, or the like.

Referring to fig. 2, fig. 2 is a schematic side view of the display panel in fig. 1.

AS shown in fig. 2, the display panel 10 includes an Array Substrate (AS) 10c, an opposite substrate 10d, and a display medium layer 10e interposed between the Array substrate 10c and the opposite substrate 10 d. The array substrate 10c and the opposite substrate 10d are provided with driving elements for generating corresponding electric fields according to the Data signals (Data), so as to drive the display medium layer 10e to emit light rays with corresponding brightness, and image display is performed.

In the exemplary embodiment, the display panel 10 may be a liquid crystal display panel, that is, the display medium layer 10e is a liquid crystal molecule, and may be other types of display panels in other embodiments of the present application, which is not limited in this application. In this embodiment, the driving elements may be a common electrode (not shown) disposed on the opposite substrate 10d and a pixel electrode (not shown) disposed on the array substrate 10c, respectively.

Taking a liquid crystal display panel as an example, the display medium layer 10e is a liquid crystal molecule, and the liquid crystal molecule deflects and transmits light rays with preset brightness, so that image display is performed. The display panel 10 further includes a backlight module 17 (Back light Module, BM), the backlight module 17 is configured to provide display light to the display area 10a of the display panel 10, and the display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. The display panel 10 further includes other elements or components, such as a signal processor module and a signal sensing module.

Referring to fig. 3, fig. 3 is a schematic plan layout of the array substrate in the display panel shown in fig. 2. As shown in fig. 3, the display panel 10 further includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are disposed in the non-display region 10b.

M data lines (Source lines) S1 to Sm and n scanning lines (Gate lines) G1 to Gn are provided in a grid-like arrangement in the display region 10a of the display panel 10. Wherein, m data lines S1-Sm extend along a first direction F1, and n scanning lines G1-Gn extend along a second direction F2. Wherein the first direction F1 and the second direction F2 are perpendicular to each other. The pixel units P are provided at intersections of the n scanning lines G1-Gn and the data lines S1-Sm.

The timing control circuit 11 receives an image signal representing image information, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a clock signal for controlling the scan driving circuit 13, a scan control signal Cg, and a data control signal Cs for controlling the data driving circuit 12.

The m data lines S1 to Sm are connected to the data driving circuit 11 for receiving the data signals stored and transmitted in the form of gray scale values supplied from the data driving circuit 12, and the n scan lines G1 to Gn are connected to the scan driving circuit 13 for receiving the scan signals from the scan driving circuit 13.

Each pixel unit P at least comprises one pixel electrode (not shown), the pixel electrode receives the data voltages corresponding to the gray scale values in the data signals provided by the data lines S1 to Sm in a preset time period under the control of the n scanning lines G1 to Gn, the pixel electrode loaded with the data voltages cooperates with the common electrode loaded with the common voltage to generate a corresponding driving electric field, and the display medium layer 10e is driven to deflect by a corresponding angle according to the electric field, so that the received backlight emits light rays with corresponding brightness according to the deflected corresponding angle, and the light rays with corresponding brightness according to the image signals are emitted for image display.

The scan driving circuit 13 receives the scan control signal Cg output from the timing control circuit 11, and outputs scan signals to the respective scan lines G1 to Gn. The data driving circuit 12 receives the data control signal Cs output from the timing control circuit 11, and outputs data signals for performing image display to the driving elements in the respective pixel units P in the display area 10a to the respective data lines S1 to Sm. Wherein the data signal provided to the display panel 10 is a gray scale voltage in analog form. The scan driving circuit 13 outputs a scan signal to control the pixel unit P to receive the data signal output from the data driving circuit 12, so as to control the pixel unit P to display a corresponding image.

In the present embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the array substrate 10c are fabricated in the same process in the array substrate 10c, i.e. GOA (Gate Driver on Array) technology.

Referring to fig. 4, fig. 4 is a schematic layout diagram of the array substrate and the opposite substrate in fig. 3.

As shown in fig. 4, the display panel 10 further includes a plurality of first signal lines L1 and a plurality of second signal lines L2, wherein the plurality of first signal lines L1 are laid in the non-display area 10b of the array substrate 10c and connected to the scan driving circuit 13, and the first signal lines L1 are used for transmitting scan auxiliary signals to the scan driving circuit 13 to drive the scan driving circuit 13 to generate and output scan signals. The plurality of second signal lines L2 are respectively laid on the opposite substrate 10d, wherein the plurality of second signal lines L2 are respectively and electrically connected in parallel with the plurality of first signal lines L1 in a one-to-one correspondence manner.

The scan auxiliary signal includes a clock signal, a start signal, a reset signal, and a low voltage signal, that is, some of the first signal lines L1 and the second signal lines L2 may be clock signal lines for transmitting the clock signal, may be start signal lines for transmitting the start signal, may be reset signal lines for transmitting the reset signal, and the like to the scan driving circuit 13 and other functional modules.

The display panel 10 further includes a plurality of first conductors 14A and a plurality of second conductors 14B, wherein one of the first conductors 14A and one of the second conductors 14B are disposed at two ends of one of the first signal lines L1 and one of the second signal lines L2, respectively, for connecting the one of the first signal lines L1 and the one of the second signal lines L2 in parallel.

The array substrate 10C further includes a plurality of common electrode lines LM and a plurality of third conductors 14C, and each of the common electrode lines LM is connected to the third conductors 14C at both ends thereof, respectively, and to the common electrode Vcom in the opposite substrate 10d through the third conductors 14C for transmitting a common voltage to the common electrode Vcom. The common voltage in the common electrode Vcom forms an electric field with the pixel voltage in the pixel unit to drive the liquid crystal molecules in the display medium layer 10e to deflect to emit light of a preset brightness, thereby performing image display.

Referring to fig. 5, fig. 5 is a schematic cross-sectional view of the display panel of fig. 4.

As shown in fig. 5, the plurality of first signal lines L1 and the plurality of second signal lines L2 include a plurality of signal line groups, that is, the plurality of first signal lines L1 and the plurality of second signal lines L2 may form a plurality of signal line groups, wherein one signal group includes one first signal line L1 and one second signal line L2 disposed opposite to each other in the thickness direction of the display panel 10. In one signal line group, both ends of the first signal line L1 and the second signal line L2 are connected through one first conductor 14A and one second conductor 14B, respectively, so that one first signal line L1 and one second signal line L2 are electrically connected in parallel.

In an exemplary embodiment, the conductor 14 may be a conductive gold ball (Au dot), or may be configured as other conductors as needed, which is not limited in this application.

Referring to fig. 6, fig. 6 is a circuit layout diagram of the array substrate in fig. 4.

As shown in fig. 6, a plurality of first signal lines L1 and a plurality of common electrode lines LM are respectively laid in the non-display area 10b on both sides of the display area 10a along the first direction F1, the scan driving circuit 13 is respectively disposed in the non-display area 10b on both sides of the display area 10a, the plurality of first signal lines L1 are connected to the scan driving circuit 13 and the timing control circuit 11 for receiving the scan auxiliary signal from the timing control circuit 11 and transmitting the scan auxiliary signal to the scan driving circuit 13 through a plurality of first conductors 14A and a plurality of signal line groups to drive the scan driving circuit 13 to output the scan signal to the pixel units P in the display area 10a, and the pixel units P receive the data signal under the control of the scan signal. The common electrode line LM is connected to the third conductors 14C at both ends thereof, respectively, and to the common electrode Vcom in the opposite substrate 10d through the third conductors 14C for transmitting a common voltage to the common electrode Vcom. The pixel electrode (not shown) in the pixel unit P forms an electric field according to the data signal and the common voltage in the common electrode Vcom, so as to drive the liquid crystal molecules in the display medium layer 10e to deflect, so as to emit light with a preset gray scale, thereby performing image display.

The first signal lines L1 are connected to the timing control circuit 11 via the first conductor 14A at a terminal adjacent to the timing control circuit 11, and are configured to receive the scan auxiliary signal from the timing control circuit 11 and transmit the scan auxiliary signal to the scan driving circuit 13 and other functional modules, and the first signal lines L1 are connected to the second conductor 14B at a terminal far from the timing control circuit 11. Both ends of the second signal line L2 provided in the opposite substrate 10d are connected to the first conductor 14A and the second conductor 14B, respectively, for parallel connection with the first signal line L1.

Referring to fig. 7, fig. 7 is a schematic circuit layout diagram of another array substrate shown in fig. 4.

As shown in fig. 7, the plurality of first signal lines L1 and the plurality of common electrode lines LM are respectively laid in the non-display area 10b on one side of the display area 10a along the first direction F1, the scan driving circuit 13 and the plurality of first signal lines L1 are disposed in the non-display area 10b on the same side of the display area 10a, that is, the plurality of first signal lines L1 are disposed adjacent to the scan driving circuit 13, the plurality of first signal lines L1 are connected to the timing control circuit 11 and the scan driving circuit 13 for receiving the scan auxiliary signal from the timing control circuit 11, and are transmitted to the scan driving circuit 13 through the plurality of first conductors 14A and the plurality of signal line groups to drive the scan driving circuit 13 to output the scan signal to the pixel units P in the display area 10a, and the pixel units P receive the data signal under the control of the scan signal. The common electrode line LM is connected to the third conductors 14C at both ends thereof, respectively, and to the common electrode Vcom in the opposite substrate 10d through the third conductors 14C for transmitting a common voltage to the common electrode Vcom. The pixel electrode (not shown) in the pixel unit P forms an electric field according to the data signal and the common voltage in the common electrode Vcom, so as to drive the liquid crystal molecules in the display medium layer 10e to deflect, so as to emit light with a preset gray scale, thereby performing image display.

The first signal lines L1 are connected to the timing control circuit 11 via the first conductor 14A at a terminal adjacent to the timing control circuit 11, and are configured to receive the scan auxiliary signal from the timing control circuit 11 and transmit the scan auxiliary signal to the scan driving circuit 13 and other functional modules, and the first signal lines L1 are connected to the second conductor 14B at a terminal far from the timing control circuit 11. Both ends of the second signal line L2 provided in the opposite substrate 10d are connected to the first conductor 14A and the second conductor 14B, respectively, for parallel connection with the first signal line L1. That is, the timing control circuit 11 transmits the scan assist signal or the like to the scan driving circuit 13 and other functional blocks through a plurality of signal line groups.

Referring to fig. 8, fig. 8 is a schematic diagram of the circuit layout of the opposite substrate in fig. 4.

As shown in fig. 8, the opposite substrate 10d includes a plurality of second signal lines L2 and a common electrode Vcom, where the plurality of second signal lines L2 are respectively laid in the first direction F1 at positions corresponding to the non-display area 10B in the opposite substrate 10d, and are used for being respectively connected in parallel with the plurality of first signal lines L1 through the first conductors 14A and the second conductors 14B, that is, are respectively arranged in a one-to-one correspondence with the plurality of first signal lines L1. The common electrode Vcom is connected to the common electrode lines LM provided in the array substrate 10C through the third conductive body 14C, for receiving a common voltage from the plurality of common electrode lines LM, for driving the liquid crystal molecules to deflect to emit light in cooperation with the data signals in the pixel unit, thereby performing image display. The common electrode Vcom is a transparent electrode disposed at a position corresponding to the display area 10a in the opposite substrate 10 d. The plurality of second signal lines L2 and the common electrode Vcom are made of the same conductive material and in the same process, in other words, the plurality of second signal lines L2 are formed by cutting the material for making the common electrode Vcom, and the plurality of second signal lines L2 are independent from each other and are not connected to the common electrode Vcom.

One end of the second signal line L2 adjacent to the timing control circuit 11 is connected to the first conductor 14A, and one end of the second signal line L2 far from the timing control circuit 11 is connected to the second conductor 14B, so that the second signal line L2 is connected in parallel with the first signal line L1 through the first conductor 14A and the second conductor 14B disposed on both sides.

When the timing control circuit 11 outputs the scanning auxiliary signal, the scanning auxiliary signal output by the timing control circuit 11 can be transmitted to the scanning driving circuit 13 or other functional modules through the first signal line L1 and the second signal line L2 which are connected in parallel, so that the impedance of the signal lines can be reduced, the stability of the scanning auxiliary signal is maintained, the heating condition of the first signal line and the second signal line is further reduced due to the reduction of the impedance, the influence of the heating of the lines on the liquid crystal is reduced, the display effect is improved, and meanwhile, the heat of the signal lines is radiated through the two side substrates, namely, the heat of the signal lines is radiated through the array substrate 10c and the opposite substrate 10d, and the integral heat radiation capability of the display panel is effectively improved, so that the driving capability of the scanning driving circuit 13 is improved.

Referring to fig. 9, fig. 9 is a schematic diagram of a circuit layout of an opposite substrate according to a second embodiment of the present application. As shown in fig. 9, the opposite substrate 10d includes a plurality of control units FC, a plurality of second signal lines L2, and a common electrode Vcom, wherein the plurality of second signal lines L2 are respectively laid at positions corresponding to the non-display area 10B in the opposite substrate 10d along the first direction F1, the second signal lines L2 are connected to the second electric conductor 14B and to the first electric conductor 14A via the control units FC, and the control units FC are used for controlling the connection and disconnection between the second signal lines L2 and the first electric conductor 14A.

The timing control circuit 11 is connected to the plurality of first conductors 14A and the plurality of control units FC, respectively, and when the control units FC control the second signal lines L2 to be turned on with the first conductors 14A, the second signal lines L2 and the first signal lines L1 are connected in parallel between the first conductors 14A and the second conductors 14B. One end of the second signal line L2 adjacent to the timing control circuit 11 is connected to the first conductor 14A, and one end of the second signal line L2 far from the timing control circuit 11 is connected to the second conductor 14B, so that the second signal line L2 is connected in parallel with the first signal line L1 through the first conductor 14A and the second conductor 14B disposed on both sides.

When the control unit FC controls the second signal line L2 to be disconnected from the first electrical conductor 14A, the second signal line L2 is connected between the second electrical conductor 14B and the control unit FC, and is connected to the timing control circuit 11 via the control unit FC, wherein the first signal line L1, the second electrical conductor 14B, the second signal line L2, and the control unit FC are sequentially connected in series. At this time, the second signal line L2 is a feedback signal line, and is configured to receive a feedback signal from the second electrical conductor 14B and transmit the feedback signal to the timing control circuit 11 through the control unit FC, where the feedback signal is used to characterize the magnitude of the scan auxiliary signal and the potential maintaining time, and the timing control circuit 11 adjusts the output scan auxiliary signal to be in a preset range according to the feedback signal. The potential of the scanning auxiliary signal can be adjusted within a preset range, the output duration of the scanning auxiliary signal is adjusted within the preset range, and when the scanning auxiliary signal is within the preset range, the image display effect of the pixel unit P is in a better state.

The common electrode Vcom is connected to the common electrode lines LM provided in the array substrate 10C through the third conductive body 14C, for receiving a common voltage from the plurality of common electrode lines LM, for driving the liquid crystal molecules to deflect to emit light in cooperation with the data signals in the pixel unit, thereby performing image display. The common electrode Vcom is a transparent electrode disposed at a position corresponding to the display area 10a in the opposite substrate 10 d. The plurality of second signal lines L2 and the common electrode Vcom are made of the same conductive material and in the same process, in other words, the plurality of second signal lines L2 are formed by cutting the material for making the common electrode Vcom, and the plurality of second signal lines L2 are independent from each other and are not connected to the common electrode Vcom.

And, detect the scanning auxiliary signal in the first signal line and transmit the feedback signal to the timing control circuit 11 through the second signal line L2, the timing control circuit 11 adjusts the clock signal that is outputted and other signals are located in the preset range according to the feedback signal, has promoted the stability of clock signal and other signals, thus has promoted the driving capability of the scanning driving circuit.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. A display panel comprises an array substrate, an opposite substrate and a display medium layer clamped between the array substrate and the opposite substrate, wherein an electric field is formed between the array substrate and the opposite substrate so as to drive the display medium layer to transmit light rays to execute image display;

the display panel is characterized by further comprising a scanning driving circuit, a plurality of first signal lines and a plurality of second signal lines, wherein the plurality of first signal lines are arranged on the array substrate and are connected with the scanning driving circuit, the first signal lines are used for transmitting scanning auxiliary signals to the scanning driving circuit, the scanning auxiliary signals are used for driving the scanning driving circuit to generate and output scanning signals, the scanning signals are used for controlling data signals for image display to be transmitted to pixel electrodes in the display panel so as to form an electric field, the plurality of second signal lines are arranged on the opposite substrate, the plurality of first signal lines and the plurality of second signal lines are arranged in a one-to-one correspondence mode and are electrically connected, and the second signal lines are used for transmitting the scanning auxiliary signals together with the first signal lines or for detecting and feeding back the scanning auxiliary signals in the first signal lines.

2. The display panel according to claim 1, further comprising at least one control unit, a plurality of first conductors, and a plurality of second conductors, wherein the first signal lines are connected between the first conductors and the second conductors, the second signal lines are connected to the second conductors, and are connected to the first conductors via the control unit, and the control unit is configured to control on and off between the second signal lines and the first conductors;

when the control unit controls the second signal line to be conducted with the first conductor, the second signal line and the first signal line are connected in parallel between the first conductor and the second conductor;

when the control unit controls disconnection between the second signal wire and the first conductor, the second signal wire is connected between the second conductor and the control unit, and the first signal wire, the second conductor, the second signal wire and the control unit are sequentially connected in series.

3. The display panel according to claim 2, wherein the plurality of first signal lines and the plurality of second signal lines include a plurality of signal line groups, wherein one of the signal line groups includes one of the first signal lines and one of the second signal lines disposed opposite to each other in a thickness direction of the display panel, and when the control unit controls the second signal lines to be conductive with the first conductors, both ends of the first signal lines and the second signal lines are connected to one of the second conductors through one of the first conductors, respectively, such that one of the first signal lines and one of the second signal lines are electrically connected in parallel.

4. The display panel of claim 3, wherein,

the display panel further comprises a time sequence control circuit, the time sequence control circuit is respectively connected with the first conductors and the control units, the first signal lines are electrically connected with the scanning drive circuit and are electrically connected with the time sequence control circuit through the first conductors, the time sequence control circuit is used for outputting the scanning auxiliary signals through the first conductors, when the control units control the second signal lines to be conducted with the first conductors, the scanning auxiliary signals are transmitted to the scanning drive circuit through the first conductors and the signal line groups, and when the control units control the second signal lines to be disconnected with the first conductors, the scanning auxiliary signals are transmitted to the scanning drive circuit through the first conductors and the first signal lines.

5. The display panel according to claim 4, wherein when the control unit controls the second signal line to be disconnected from the first conductive body, the second signal line receives a feedback signal from the second conductive body and transmits the feedback signal to the timing control circuit via the control unit, and the timing control circuit adjusts the scan auxiliary signal to be within a preset range according to the feedback signal.

6. The display panel according to claim 5, further comprising a display area and a non-display area which are adjacently arranged, wherein the display area comprises pixel units arranged in an array for performing image display, the plurality of first signal lines are arranged in the non-display area at both sides of the display area for transmitting the scan auxiliary signal to the scan driving circuit arranged in the non-display area, and the scan driving circuit outputs a scan signal according to the scan auxiliary signal to control the pixel units to receive a data signal for image display and perform image display.

7. The display panel according to claim 5, further comprising a display area and a non-display area disposed adjacently, wherein the display area includes pixel units arranged in an array for performing image display, the plurality of first signal lines are disposed in the non-display area on one side of the display area for transmitting the scan auxiliary signal to the scan driving circuit disposed in the non-display area, and the scan driving circuit outputs a scan signal according to the scan auxiliary signal to control the pixel units to receive a data signal for image display and perform image display.

8. The display panel according to claim 6 or 7, wherein the counter substrate includes a common electrode provided at a position of the counter substrate corresponding to the display region for supplying a common voltage for driving the display medium layer to the pixel unit, the common voltage forming the electric field with the data signal in the pixel electrode, and the plurality of second signal lines are provided at positions of the counter substrate corresponding to the non-display region for respectively connecting in parallel with the plurality of first signal lines through the first electric conductor and the second electric conductor.

9. The display panel of claim 8, wherein the common electrode and the plurality of second signal lines are made of the same material and in the same process.

10. A display terminal, comprising a power module and the display panel according to any one of claims 1-9, wherein the power module is disposed on a side of the display panel facing away from the emergent light, and is configured to provide a driving voltage for displaying images on the display panel.

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