CN116318167A - Device and method for converting direct current B code into pulse signal by double-channel signal hot standby input - Google Patents
Device and method for converting direct current B code into pulse signal by double-channel signal hot standby input Download PDFInfo
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Abstract
The invention discloses a device and a method for converting direct current B code into pulse signals by double-channel signal hot standby input, and belongs to the technical field of time synchronization. The device comprises: a code element identification module, a B code information analysis module, a second punctual edge extraction module, a 1PPS generation module, a 1PPM generation module, a B code effectiveness detection module and a pulse signal selection module which are realized based on a programmable logic device; the invention adopts the programmable logic device to realize the conversion of direct current B code into pulse signals with double-channel signal hot standby input, and can realize the expansion output of the pulse signals with high stability.
Description
Technical Field
The invention belongs to the technical field of time synchronization, and particularly relates to a device and a method for converting direct current B code into pulse signals through double-channel signal hot standby input.
Background
IRIG is an acronym for the subordinate institutional range instrumentation group of the united states department of range commander (Inter-Range Instrumentation Group). IRIG serial time code has six formats, namely A, B, D, E, G, H, wherein IRIG-B format time code (hereinafter abbreviated as B code) is most widely used. The time frame rate of the B code is 1 frame/s, and the B code comprises 100 bits of information which respectively represent BCD time information and control function information, and can extract 1Hz and 100Hz pulse signals.
lPPS (pulse per second), a time reference signal, one pulse per second, the rising edge of the pulse marks the beginning of the second.
lPPM (pulse per minute), a time reference signal, one pulse per minute, marks the start of the pulse rising edge division.
The direct current B code and the pulse signals (1 PPS, 1 PPM) are the common time setting mode of the power system, and the common characteristics are that: the interface is simple, and the precision is high (better than 1 mu s).
In the transformer substation time synchronization service, a time signal expansion device is often used to realize expansion of a pulse signal multipath interface, the input sources of the signal expansion device are usually two, and when one source is abnormal, the device can be switched to the other source. Because the detection of the signal quality of the input source requires a certain time, when the input source of the signal expansion device is switched, a pulse signal is lost, so that the time synchronization abnormal alarm is sent out by the time service equipment at the later stage.
Disclosure of Invention
Aiming at the problem that an output pulse signal is lost when an input source of a time signal expansion device is switched, the invention provides a device and a method for converting direct current B codes into pulse signals by double-channel signal hot standby input. The invention adopts the programmable logic device to realize the conversion of direct current B code into pulse signals with double-channel signal hot standby input, and can realize the expansion output of the pulse signals with high stability.
The invention is realized by the following technical scheme:
a device for converting direct current B code into pulse signals by double-channel signal hot standby input comprises: a code element identification module, a B code information analysis module, a second punctual edge extraction module, a 1PPS generation module, a 1PPM generation module, a B code effectiveness detection module and a pulse signal selection module which are realized based on a programmable logic device;
the code element identification module is used for carrying out code element detection and identification on an input direct current B code signal and outputting serial code element information and code element error signals obtained by identification;
the second time edge extraction module is used for extracting a second time edge signal of the direct current B code signal according to the serial code element information;
the B code information analysis module is used for analyzing the direct current B code signal according to the serial code element information and the second punctual edge signal, performing data verification, and outputting second time information and leap second forecast information of the direct current B code signal obtained by analysis and a B code decoding error signal;
the 1PPS generation module is used for delaying the second time edge signal by 100ms and generating a 1PPS signal with a pulse width of 100 ms;
the 1PPM generation module is used for generating a 1PPM signal according to the second time information and the leap second forecast information;
the B code validity detection module is used for judging whether the direct current B code signal is valid or not according to the states of the code element error signal and the B code decoding error signal;
the pulse signal selection module is used for selecting 1PPS signals and 1PPM signals corresponding to the effective direct current B code signals to be used as output according to the validity state of the direct current B code signals.
The invention utilizes the programmable logic device to complete the direct current B code pulse signal input by the two-way signal, solves the problem of losing the output pulse signal when the input source of the time signal expansion device is switched, does not need a CPU, and has simple hardware architecture, low cost and high reliability.
As a preferred embodiment, the device of the present invention further comprises an interface driving circuit;
the interface driving circuit is used for converting the 1PPS signal and the 1PPM signal output by the pulse signal selection module into physical layer interface signals and outputting the physical layer interface signals as pulse signals.
In a preferred embodiment, the symbol recognition module of the present invention determines that the dc B code signal having a symbol width deviation of less than 5% and a symbol high level width deviation of less than 5% is a signal conforming to the characteristics of the dc B code symbol.
As a preferred embodiment, the device of the invention further comprises a thermostatic crystal oscillator;
the constant temperature crystal oscillator provides a 10MHz driving signal for the code element identification module.
As a preferred embodiment, the second on-time edge extracting module of the present invention determines the information position of the symbol P according to the serial symbol information outputted from the symbol identifying module, and when 2 consecutive "P" symbols occur, the rising edge of the "Pr" symbol is the second on-time edge of the direct current B code.
As a preferred embodiment, the strategy of the 1PPM generating module of the present invention for generating the 1PPM signal is specifically:
if the leap second advance notice information is invalid, when the second time information is 59, an output switch is turned on, and a 1PPS signal output by the 1PPS generating module is output as the 1PPM signal;
if the positive leap second forecast in the leap second forecast information is valid, when the second time information is 60, an output switch is turned on, and a 1PPS signal output by the 1PPS generating module is output as the 1PPM signal;
and if the negative leap second forecast in the leap second forecast information is valid, turning on an output switch when the second time information is 58, and outputting the 1PPS signal output by the 1PPS generating module as the 1PPM signal.
As a preferred embodiment, the rule for determining whether the input dc B-code signal is valid by the B-code validity detection module of the present invention is:
and if the code element error signal and the B code decoding error signal are invalid, the corresponding input direct current B code signal is valid, otherwise, the direct current B code signal is invalid.
As a preferred embodiment, the programmable logic device of the present invention is an FPGA.
On the other hand, the invention also provides a method for converting direct current B code into pulse signals by double-channel signal hot standby input, which is realized based on the device provided by the invention, and comprises the following steps:
the direct current B code signals of the two channels are input, and the 1PPS signals and the 1PPM signals of the corresponding channels are respectively processed and generated through a code element identification module, a second time edge extraction module, a B code information analysis module, a 1PPS generation module and a 1PPM generation module;
and selecting 1PPS signals and 1PPM signals of channels corresponding to the effective direct current B code signals as output according to the B code effectiveness detection modules of the two channels to output signal effectiveness states.
As a preferred embodiment, the pulse signal selection module of the present invention selects logic as follows:
if the channel 1 is valid, selecting 1PPS signal and 1PPM signal of the channel 1 to output;
channel 1 is invalid, channel 2 is valid, and then 1PPS signal and 1PPM signal of channel 2 are selected to be output;
and if the channel 1 and the channel 2 are invalid, no signal is output.
The invention has the following advantages and beneficial effects:
the invention adopts a programmable logic device, such as an FPGA, to complete the conversion of direct current B code into pulse signals input by double-channel signal hot standby, realizes the expansion output of pulse signals with high stability, solves the problem of losing output pulse signals when the input source of the time signal expansion device is switched, does not use a CPU, and has simple hardware architecture, low cost and high reliability.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
fig. 1 is a logic block diagram of a dc B-transcoded pulse signal according to an embodiment of the present invention.
Fig. 2 is a schematic symbol diagram of a dc B code according to an embodiment of the present invention.
Fig. 3 is a timing diagram of the extraction of the timing edge of the dc B code according to an embodiment of the invention.
Fig. 4 is a flow chart of a dc B code pulse signal according to an embodiment of the invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Examples
Aiming at the problem that an output pulse signal is lost when an input source of a time signal expansion device is switched, the embodiment provides a device for converting direct current B code into a pulse signal by double-channel signal hot standby input. Wherein the IRIG-B code symbol definition is shown in table 1 below.
TABLE 1IRIG-B code symbol definition
The device of the embodiment comprises: the system comprises a code element identification module, a B code information analysis module, a second time edge extraction module, a 1PPS generation module, a 1PPM generation module, a B code effectiveness detection module, a pulse signal selection module and an interface driving circuit. The other modules except the interface driving circuit are all realized by the FPGA, and the specific modules are shown in figure 1. In the embodiment, the FPGA is adopted to complete direct current B code conversion pulse signals input by the double-channel signal hot standby, so that the pulse signal expansion output with high stability is realized. In this embodiment, the FPGA is taken as an example for illustration, but the present invention is not limited thereto, and in other alternative embodiments, each module may be implemented in other manners.
The code element identification module is used for carrying out code element detection and identification on the input direct current B code signal according to the definition of the B code element signal and outputting serial code element information and code element error signals obtained by identification. If the detection is passed, identifying to obtain serial code element information, wherein the code element error signal output at the moment is in an invalid state; the output symbol error signal is in an active state if the detection fails.
As shown in fig. 2, the symbol width is 10ms, the symbol "0" duty cycle is 20% (high level 2 ms), the symbol "1" duty cycle is 50% (high level 5 ms), and the symbol "P" duty cycle is 80% (high level 8 ms)). The module adopts a 10MHz clock signal provided by a constant temperature crystal oscillator to judge that the code element width deviation is less than 5% (500 mu s) and the code element high level width deviation is less than 5% (the code element '0' deviation is less than 100 mu s, the code element '1' deviation is less than 250 mu s and the code element 'P' deviation is less than 400 mu s) is a signal conforming to the code element characteristics of the direct current B code.
And the B code information analysis module analyzes the direct current B code signal according to the serial code element information output by the code element identification module and the second punctual edge signal output by the second punctual edge extraction module, performs data verification according to the direct current B code coding rule, and outputs time (year, month, day, time, minute and second), leap second forecast and leap second mark and B code decoding error signal in the direct current B code coding information obtained by analysis. And if the verification is not passed, the output B code decoding error signal is in an effective state.
The second on-time edge extraction module judges the information position of the code element P according to the serial code element information output by the code element identification module, and when 2 continuous P code elements (P0 and Pr) appear according to the direct current B code coding rule, the rising edge of the Pr code element is the second on-time edge of the direct current B code, as shown in figure 3.
And the 1PPS generating module is used for generating a 1PPS signal with the pulse width of 100ms by delaying the second on-time edge signal output by the second on-time edge extracting module by 100 ms.
The 1PPM generation module is used for outputting the 1PPS signal output by the 1PPS generation module as a 1PPM signal according to the second time information and leap second forecast information output by the B code information analysis module, if the leap second forecast is invalid and the second information is 59, the output switch is turned on; if the positive leap second forecast is valid, when the second information is 60, an output switch is turned on, and a 1PPS signal output by the 1PPS generating module is output as a 1PPM signal; if the negative leap second announcement is valid, the output switch is turned on when the second information is 58, and the 1PPS signal output by the 1PPS generation module is output as a 1PPM signal.
And the B code validity detection module is used for checking the correctness of the direct current B code according to the serial code element information output by the code element identification module and the second punctual edge signal output by the second punctual edge extraction module and the direct current B code checking rule, and detecting the validity according to the code element of the code element identification module so as to determine the validity of the input direct current B code signal.
The pulse signal selection module selects and outputs pulse signals generated according to the direct current B code input 1 or the direct current B code input 2 signals according to the signal effectiveness output by the B code effectiveness detection module.
And the interface driving circuit converts the 1PPS signal and the 1PPM signal output by the pulse signal selection module into physical layer interface signals and outputs the physical layer interface signals through TTL, RS485, empty contact and an optical fiber interface.
As an alternative embodiment, the symbol recognition module comprises 1 64-bit counter TimeCounter [64], and the 10MHz clock signal provided by 1 constant temperature crystal oscillator drives the 64-bit counter TimeCounter [64] to continuously count from 0, wherein the count can last for 58494 years without overflowing. The code element identification module internally designs 200 64-bit registers BDC_Reg_TS64, records the value of TimeCounter 64 as a signal rising edge timestamp on the signal rising edge of the input direct current B code, and stores the value in an odd-numbered register of the registers BDC_Reg_TS 64; recording the value of TimeCoulter [64] as a signal falling edge timestamp at the signal falling edge of the input direct current B code, and storing the value in the even number of a register BDC_Reg_TS 64; an 8-bit register BDC_Index [8] is set to store the timestamp count value. Designing 100 2-bit registers IRIG_Reg [100] to store symbol types (symbols 0, 1 or P) in the symbol identification module; an 8-bit register irig_index is set to store the symbol count value.
After the device is powered on, a code element identification module initializes all the registers BDC_Reg_TS64[4] to 0, initializes the registers BDC_Index to 1, performs level conversion detection on an input direct current B code signal after the initialization is completed, records the value of a TimeCoulter [64] as a time stamp when the level conversion of the direct current B code is detected, acquires a rising edge time stamp when the rising edge of the signal arrives, judges the value of the BDC_Index at the moment, stores the time stamp into the registers BDC_Reg_TS64[ BDC_Index ] if the value is odd, considers a time sequence error if the time sequence is even, enters an error correction program branch, and restarts the time sequence; when the signal falling edge arrives, a falling edge time stamp is obtained, at this time, the value of BDC_Index is judged, if the signal falling edge comes, the time stamp is stored in a register BDC_Reg_TS64[ BDC_Index ], if the signal falling edge comes, the time stamp is considered to be wrong, and the error correction program branches and restarts the time sequence. When the odd number time stamp is successfully recorded and the serial number BDC_Index is larger than 2, the symbol identification module starts a symbol correctness judging time sequence, the current obtained odd number time stamp is subtracted by the adjacent odd number time stamp (BDC_Reg_TS 64[ BDC_Index ] -BDC_Reg_TS64[ BDC_Index-2 ]) to calculate the symbol width, the previous even number time stamp is subtracted by the previous odd number time stamp (BDC_Reg_TS 64[ BDC_Index-1] -BDC_Reg_TS64[ BDC_Index-2 ]), the symbol high level width is calculated, the error of the symbol width and the error of the symbol high level width are smaller than 5 percent, otherwise, the data error is considered, the error correction program branch is entered, and the time sequence is restarted. The symbol recognition module analyzes the symbol type according to the symbol definition rule (see fig. 2, symbol diagram of direct current B code) of the symbol judged by correctness, and stores the symbol type in IRIG Reg [ IRIG Index ]. The error correction program branch of the symbol recognition module sets a register bdc_index to 1 and outputs a symbol error signal to the B-code validity detection module. In addition, a 9ms counter Time_9ms is arranged in the code element identification module and is used for detecting whether the B code signal is lost, when the input signal 9ms is unchanged, the input signal is considered to be interrupted, and a code element error signal is output to the B code effectiveness detection module.
And the second time edge extraction module starts starting operation when detecting that new data is stored in a register IRIG_Reg [ IRIG_Index ], the module judges whether IRIG_Index is larger than 1, if yes, detects whether IRIG_Reg [ IRIG_Index ] and IRIG_Reg [ IRIG_Index-1] are both code elements P, and if yes, stores a corresponding second time edge timestamp BDC_Reg_TS64[ IRIG_Index 2-1] into BDC_Reg_TS64[1] and sets IRIG_Index as 2.
And when the symbol count value reaches 98, the B code information analysis module starts to analyze the B code information, performs data verification and verifies correctly, and then the module extracts the symbol information according to the bit definition of IRIG-B code symbols in table 1, calculates to obtain second, minute and leap second forecast, leap second mark and time quality information and verifies errors, and then outputs B code decoding error information to the B code effectiveness detection module.
The B code validity detection module judges whether the input B code is valid or not according to the code element error signal state output by the code element identification module and the B code decoding error state output by the B code information analysis module, if the code element error signal and the decoding error signal are invalid, the 1PPS and 1PPM signals generated by the channel of signals are valid and can be used as output, otherwise, the signals are invalid and can not be used for output.
The pulse signal selection module selects 1PPS and 1PPM to be used as output according to the B code validity states of the two channels, and the selection logic is as follows:
(1) If the channel 1 is valid, selecting a channel 1 signal to output;
(2) Channel 1 is invalid, channel 2 is valid, and then channel 2 signal output is selected;
(3) Both channels 1, 2 are inactive, no signal is output.
As shown in fig. 4, the working principle of the device proposed in this embodiment is as follows:
the direct current B code input (namely direct current B code input 1 and direct current B code input 2) of the two channels respectively carries out code element identification by respective code element identification modules; when the B code information conforming to the code element definition rule is identified, the corresponding second time edge extraction module extracts the second time edge signal, otherwise, a code element error signal is output to the corresponding B code effectiveness detection module;
according to the second on-time edge signal output by the second on-time edge extraction module, delaying for 100ms to generate a 1PPS signal with a pulse width of 100 ms;
according to the serial code element information output by the code element identification module and the second punctual edge signal output by the second punctual edge extraction module, carrying out data verification, and if the verification is correct, analyzing second time information and leap second forecast information of the direct current B code coding information according to the direct current B code coding rule; otherwise, outputting B code decoding error information to a B code validity detection module;
generating a 1PPM signal according to the second time information and leap second forecast information output by the B code information analysis module;
judging the validity of the input B code according to the code element error signal state and the B code decoding error information;
selecting 1PPS and 1PPM signals to be used as output according to the B code effectiveness state of the two channels;
and performing physical layer interface signal conversion output on the output 1PPS signal and the 1PPM signal.
The above embodiments are described in further detail for the purpose, technical solution and advantageous effects of the present invention, and it should be understood that the above embodiments are only embodiments of the present invention, and the technical solution disclosed in the present invention may be implemented in other manners. For example, the modules may be divided into only one logic function, and there may be other manners of dividing the modules when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted or not performed. In addition, the communication connection between modules may be an indirect coupling or communication connection via some interfaces, devices or units, and may be in electrical or other forms.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one processing unit. The integrated units may be implemented in hardware or in software functional units.
Wherein the integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Claims (10)
1. The device for converting direct current B code into pulse signals by double-channel signal hot standby input is characterized by comprising the following components: a code element identification module, a B code information analysis module, a second punctual edge extraction module, a 1PPS generation module, a 1PPM generation module, a B code effectiveness detection module and a pulse signal selection module which are realized based on a programmable logic device;
the code element identification module is used for carrying out code element detection and identification on an input direct current B code signal and outputting serial code element information and code element error signals obtained by identification;
the second time edge extraction module is used for extracting a second time edge signal of the direct current B code signal according to the serial code element information;
the B code information analysis module is used for analyzing the direct current B code signal according to the serial code element information and the second punctual edge signal, performing data verification, and outputting second time information and leap second forecast information of the direct current B code signal obtained by analysis and a B code decoding error signal;
the 1PPS generation module is used for delaying the second time edge signal by 100ms and generating a 1PPS signal with a pulse width of 100 ms;
the 1PPM generation module is used for generating a 1PPM signal according to the second time information and the leap second forecast information;
the B code validity detection module is used for judging whether the direct current B code signal is valid or not according to the states of the code element error signal and the B code decoding error signal;
the pulse signal selection module is used for selecting 1PPS signals and 1PPM signals corresponding to the effective direct current B code signals to be used as output according to the validity state of the direct current B code signals.
2. The device for converting direct current B code into pulse signals by two-way signal hot standby input according to claim 1, further comprising an interface driving circuit;
the interface driving circuit is used for converting the 1PPS signal and the 1PPM signal output by the pulse signal selection module into physical layer interface signals and outputting the physical layer interface signals as pulse signals.
3. The apparatus for converting a two-way signal hot standby input direct current B code into a pulse signal according to claim 1 or 2, wherein the symbol recognition module determines that the symbol width deviation is less than 5%, and the direct current B code signal with the symbol high level width deviation of less than 5% is a signal conforming to the symbol characteristics of the direct current B code.
4. The device for converting direct current B code into pulse signals by double-signal hot standby input according to claim 1 or 2, which is characterized by further comprising a constant-temperature crystal oscillator;
the constant temperature crystal oscillator provides a 10MHz driving signal for the code element identification module.
5. The apparatus for converting a direct current B code to a pulse signal according to claim 1 or 2, wherein said second on-time edge extracting module judges the information position of symbol P according to said serial symbol information, and when 2 consecutive "P" symbols occur, the rising edge of "Pr" symbol is the second on-time edge of said direct current B code.
6. The device for converting direct current B code into pulse signal by dual-signal hot standby input according to claim 1 or 2, wherein the strategy for generating 1PPM signal by the 1PPM generating module is specifically as follows:
if the leap second advance notice information is invalid, when the second time information is 59, an output switch is turned on, and a 1PPS signal output by the 1PPS generating module is output as the 1PPM signal;
if the positive leap second forecast in the leap second forecast information is valid, when the second time information is 60, an output switch is turned on, and a 1PPS signal output by the 1PPS generating module is output as the 1PPM signal;
and if the negative leap second forecast in the leap second forecast information is valid, turning on an output switch when the second time information is 58, and outputting the 1PPS signal output by the 1PPS generating module as the 1PPM signal.
7. The apparatus for converting a direct current B-code signal into a pulse signal according to claim 1 or 2, wherein the rule for determining whether the direct current B-code signal is valid by the B-code validity detection module is as follows:
and if the code element error signal and the B code decoding error signal are invalid, the corresponding input direct current B code signal is valid, otherwise, the direct current B code signal is invalid.
8. The device for converting direct current B code into pulse signals according to claim 1 or 2, wherein the programmable logic device is an FPGA.
9. A method for converting direct current B code into pulse signals for dual-signal hot standby input, which is realized based on the device of any one of claims 1-8, and comprises the following steps:
the direct current B code signals of the two channels are input, and the 1PPS signals and the 1PPM signals of the corresponding channels are respectively processed and generated through a code element identification module, a second time edge extraction module, a B code information analysis module, a 1PPS generation module and a 1PPM generation module;
according to the validity states of the B code validity detection modules output signals of the two channels, 1PPS signals and 1PPM signals of the channels corresponding to the valid direct current B code signals are selected to be output.
10. The method according to claim 9, wherein the two channels are channel 1 and channel 2, respectively, and the selecting, according to the validity status of the B-code validity detection module output signals of the two channels, the 1PPS signal and the 1PPM signal of the channel corresponding to the valid direct current B-code signal as the outputs specifically includes:
selecting 1PPS signal and 1PPM signal output of the channel 1 under the condition that the channel 1 is effective and the channel 2 is not effective;
selecting 1PPS signal and 1PPM signal output of the channel 2 under the condition that the channel 1 is invalid and the channel 2 is valid;
in the case where both the channel 1 and the channel 2 are inactive, no signal is output.
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| Publication number | Priority date | Publication date | Assignee | Title |
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