CN116317656A

CN116317656A - Inversion control system and inversion control method

Info

Publication number: CN116317656A
Application number: CN202211462795.9A
Authority: CN
Inventors: 关真希; 高山直树; 迫田友治
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2021-12-10
Filing date: 2022-11-21
Publication date: 2023-06-23
Also published as: JP2023086188A

Abstract

The present invention relates to an inversion control system and an inversion control method. Even if a part of the inverters connected in parallel fails, the operation of the elevator can be continued. An inverter control system for supplying power to a motor for driving an elevator by means of N inverters connected in parallel (N is an integer of 2 or more) and controlling the inverters connected in parallel, the inverter control system comprising: a fault signal receiving unit (192) that receives an abnormality signal of an inverter in a group unit that divides N inverters connected in parallel into a plurality of groups; and a gate command unit (191) that causes the inverter of the group other than the group in which the fault signal reception unit receives the abnormal signal to operate.

Description

Inversion control system and inversion control method

Technical Field

The present invention relates to an inversion control system and an inversion control method.

Background

Elevators such as elevators use an ac motor as a power source. In order to control the operating state of the ac motor, the voltage and frequency of the power supply are converted by an inverter. For example, in the case of an elevator installed in a building, the three-phase ac power supplied from an electric power company is converted into voltage and frequency by an inverter, and then supplied to an ac motor constituting a hoisting machine.

In the case of converting the voltage and frequency of the three-phase ac power supply by an inverter, specifically, a three-phase ac power supply converter (converter) is converted into a dc power supply, and the converted dc power supply is set to an ac power supply of a desired voltage and frequency by the inverter. The converter and the inverter can have the same basic configuration, and in this case, only the operation directions are reversed. In the following description, the inverter will be described as including a converter, except for the case of distinguishing the inverter from the other.

When an inverter is used as a device for controlling the power supply of an elevator or the like, the inverters are connected in parallel in accordance with the required power supply capacity, and the plurality of inverters are simultaneously processed. That is, the inverter is constituted by semiconductor switches such as IGBTs (Insulated Gate Bipolar Transistor: insulated gate bipolar transistors), and a current and a voltage that can pass through 1 semiconductor switch are limited, so that a plurality of parallel connections ensure a necessary power supply capacity. For example, in the case of constituting an inverter with 200kW output, 1 inverter 4 with 50kW output is connected in parallel to ensure 200kW.

Patent document 1 describes the following technique: when an abnormality is detected in any inverter device, the operation of the inverter device in which the abnormality is detected is stopped. In the technique described in patent document 1, abnormality of the transformer is performed for each of the U phase, V phase, and W phase, and abnormality of each phase such as U-phase abnormal signal is detected.

Prior art literature

Patent literature

Patent document 1: JP-A2015-29393

As described in patent document 1, in the case of an inverter device having a structure in which abnormality is performed in each of the U-phase, V-phase, and W-phase, in the case of an inverter device constituted by a plurality of units (units), it is difficult to identify an inverter unit in which a failure has occurred. For example, when an abnormality of the U-phase is detected, it is difficult to determine which unit of the plurality of units the U-phase is abnormal, and it cannot be said that appropriate abnormality detection is performed.

Therefore, the inverter device in which the abnormality is detected cannot be used until the failed semiconductor switch or the like is replaced. For example, when an abnormality occurs in an inverter device that drives an elevator, the elevator is in a disabled state until the corresponding inverter device is recovered from a failure.

Disclosure of Invention

The present invention aims to provide an inverter control system and an inverter control method, which can continue the operation of an elevator even if a part of inverters connected in parallel fails.

In order to solve the above problems, the following configuration is adopted, for example.

The present application includes various means for solving the above-mentioned problems, and as an example thereof, an inverter control system for supplying power to a motor driving a lifter by N (N is an integer of 2 or more) inverters connected in parallel and controlling the inverters connected in parallel, the inverter control system comprising: a fault signal receiving unit that receives an abnormality signal of an inverter in a group unit that divides N inverters connected in parallel into a plurality of groups; and a gate command unit that causes the failure signal receiving unit to operate the inverter of the group other than the group in which the failure signal receiving unit receives the abnormal signal.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present invention, since the abnormality of the inverter is detected in the group unit, the inverter in which the abnormality is not detected can be operated, and even when the abnormality occurs in a part of the inverters, the elevator can be continued to operate.

The problems, structures, and effects other than those described above will be apparent from the following description of the embodiments.

Drawings

Fig. 1 is a diagram showing a schematic configuration of an elevator and a circuit of an inverter device controlled by an inverter control system according to an embodiment of the present invention.

Fig. 2 is a plan view showing an example of the arrangement of the inverter shown in fig. 1.

Fig. 3 is a perspective view showing the shape of 1 unit of an inverter device controlled by an inverter control system according to an embodiment of the present invention.

Fig. 4 is a block diagram showing a configuration example of an inverter control system according to an embodiment of the present invention.

Fig. 5 is a flowchart showing an example of control processing of the inverter control system according to the embodiment of the present invention.

Description of the reference numerals

Three-phase ac power supply, 12..power filter section, 13..reactor, 14..motor, 15..sheave, 16..main rope, 18..load sensor, 19..counterweight, 100..inverter, 101..handle, 102, 103..terminal section, 102U, 102V, 102 w..terminal, 103..terminal section, 103 u..terminal, 104-U, 104-V, 104-W, 105-P, 105-n..terminal, 107..frame, 109..control panel, and power supply. The parallel inverter, 111, 112, 121, 122, 131, 132, 141, 142, the inverter unit, 111-C, 112-U1., the capacitor, 111-F1, 111-F2, 111-F3., the cooling fan, 111-U1, 111-U2, 111-V1, 111-V2, 111-W1, 111-W2, the semiconductor switch, 190, the inverter control device, 191, the gate instruction unit, 192, the fault signal receiving unit, 193, the fault handling unit

Detailed Description

An inverter control system according to an embodiment of the present invention (hereinafter referred to as "this example") will be described below with reference to the drawings.

The inverter control system of this example is a system for an inverter device that supplies power to a hoisting machine of an elevator as a hoist.

[ Structure of inverter ]

Fig. 1 shows a circuit configuration of an inverter 100. Fig. 1 also illustrates a schematic configuration of an elevator to which power is supplied by the inverter 100.

Inverter 100 includes 1 st parallel inverter 110, 2 nd parallel inverters 120, …, and N-th parallel inverter 190 (N is an integer of 2 or more).

2 inverter units are connected in series to each of the parallel inverters 110 to 190. For example, the 1 st parallel inverter 110 connects 2

inverter units

111, 112 in parallel. The inverter unit 111 operates as a converter for converting the three-phase ac power supply 11 into dc, and has 2 semiconductor switches in each of the U-phase, V-phase, and W-phase, and 6 semiconductor switches 111-U1, 111-U2, 111-V1, 111-V2, 111-W1, and 111-W2 in total.

Further, a capacitor 111-C for smoothing the power supply converted into direct current is connected to the inverter unit 111.

A power filter unit 12 is connected between the three-phase ac power supply 11 and the inverter unit 111.

The inverter unit 112 performs an operation of converting the dc power obtained in the inverter unit 111 into a three-phase ac power, and has 2 semiconductor switches in each of the U-phase, V-phase, and W-phase, and 6 semiconductor switches 112-U1, 112-U2, 112-V1, 112-V2, 112-W1, and 112-W2 in total. The capacitor 112-C is also connected to the dc side of the inverter unit 112.

The 2 nd parallel inverter 120 to the N-th parallel inverter 190 are similarly provided with 2

inverter units

121, 122 to 191, 192. For example, the inverter unit 121 of the 2 nd parallel inverter 120 has 6 semiconductor switches 121-U1, 121-U2, 121-V1, 121-V2, 121-W1, 121-W2, and performs an operation of converting a three-phase ac power source into a dc power source. The inverter unit 122 of the 2 nd parallel inverter 120 has 6 semiconductor switches 122-U1, 122-U2, 122-V1, 122-V2, 122-W1, 122-W2, and performs an operation of converting a dc power supply into a three-phase ac power supply.

The inverter unit 191 of the nth parallel inverter 190 has 6 semiconductor switches 191-U1, 191-U2, 191-V1, 191-V2, 191-W1, 191-W2, and performs an operation of converting a three-phase ac power supply into a dc power supply. The inverter unit 192 has 6 semiconductor switches 192-U1, 192-U2, 192-V1, 192-V2, 192-W1, 192-W2, and converts the dc power into three-phase ac power.

The 2 nd parallel inverter 120 to the N-th parallel inverter 190 are also connected to the 2

inverter units

121, 122 to 191, 192, respectively, and the capacitors 121-C, 122-C to 191-C, 192-C are also connected to each other.

The semiconductor switches (121-U1, etc.) disposed in the

inverter units

111, 112 to 191, 192 are formed of semiconductor elements such as IGBTs, and are turned on and off by an inverter control unit 200 (fig. 4) described later. In this case, the on/off control of the inverter units 112 to 192 of the parallel inverters 110 to 190 that obtain the three-phase ac power supply is controlled to set the voltage and frequency for driving the elevator.

The three-phase ac power obtained in the inverter units 112 to 192 of the parallel inverters 110 to 190 is supplied to a motor (for example, a three-phase synchronous motor) 14 as a hoisting machine of an elevator via a reactor 13.

Here, the structure of the elevator side will be briefly described, and the main suspension rope 16 is wound around the sheave 15 that rotates in conjunction with the rotation of the motor 14. The main suspension rope 16 has one end connected to the car 17 and the other end connected to the counterweight 19, and the car 17 is lifted and lowered by rotation of the motor 14. The car 17 is provided with a load sensor 18 as a load detecting unit for detecting the load of the car 17.

The inverter 100 is provided in, for example, a machine room of an elevator.

[ configuration example of inverter ]

Fig. 2 shows an example of the arrangement of the inverter 100 of this example.

The inverter device 100 of the example of fig. 2 is configured to have a 4-parallel configuration of the 1 st to 4 th parallel inverters 110 to 140.

Since each of the parallel inverters 110 to 140 includes 2 inverter units, the total of the parallel inverters includes 8 inverter units 111 to 141 and 112 to 142.

As shown in fig. 2, the inverter device 100 of the present example includes 8 inverter units 111 to 141 and 112 to 142 arranged in a longitudinal direction on the control panel 109. That is, in the example of fig. 2, the

inverter units

111, 121, 131, 141, 112, 122, 132, 142 are arranged in this order from the top. However, the arrangement state of the cells shown in fig. 2 is an example, and other arrangement procedures may be adopted.

Each

inverter unit

111, 112, 121, 122, 131, 132, 141, 142 includes 6 semiconductor switches (not shown in fig. 2), and 3 cooling fans are mounted to each unit

For example, cooling fans 111-F1, 111-F2, 111-F3 are mounted on the inverter unit 111. Similarly, cooling fans shown as "F1, F2, and F3" are also attached to the inverter units 121 to 141 and 112 to 142 at the ends of the reference numerals of the respective units. Further, handles 101 are attached to left and right ends of the inverter units 111 to 142.

The 4

inverter units

111, 121, 131, 141 operating as converters are connected in parallel to the 3

terminals

102U, 102V, 102W of the terminal portion 102. The 3

terminals

102U, 102V, 102W of the terminal portion 102 are connected to the three-phase ac power supply 11 shown in fig. 1.

The 4

inverter units

112, 122, 132, 142 operating as inverters are connected in parallel with the 3

terminals

103U, 103V, 103W of the terminal portion 103. The 3

terminals

103U, 103V, 103W of the terminal portion 103 are connected to the motor 14 side shown in fig. 1.

The maximum currents that can be output by the parallel inverters 110 to 140 are set to the same value.

[ Structure of inverter Unit ]

Fig. 3 is a perspective view showing the structure of 1 inverter unit 111.

The other inverter units 112 to 142 have the same configuration as the inverter unit 111.

The inverter unit 111 is provided with 3 cooling fans 111-F1, 111-F2, 111-F3 on the front side of the frame 107 that doubles as a heat sink. The inverter unit 111 has 6 semiconductor switches 111-U1, 111-U2, 111-V1, 111-V2, 111-W1, and 111-W2. In this example, the inverter unit is configured by using a 2in1 type IGBT module, but 1in1 and 6in1 types may be used. Further, a capacitor 111-C and the like are disposed in the inverter unit 111. Handles 101 are attached to the left and right end portions of the front surface side of the frame 107.

The three-phase ac side terminals 104-U, 104-V, 104-W are arranged on the front side of the upper portion of the frame 107, and the dc side terminals 105-P, 105-N are arranged on the rear side of the upper portion of the frame 107.

In the case of the inverter unit 111 operating as a converter, the three-phase ac side terminals 104-U, 104-V, 104-W are connected to the three-phase ac power supply 11 (fig. 1). In the case of inverter unit 121 operating as an inverter, three-phase ac-side terminals 104-U, 104-V, 104-W are connected to motor 14 side.

The dc-side terminals 105-P, 105-N are connected to dc-side terminals (not shown) of the inverter units 112 of the same parallel inverter 110.

[ control Structure of inverter ]

Fig. 4 shows the configuration of the inverter device 100 and the inverter control unit 200 used in the inverter control system of the present example. The inverter device 100 of the example of fig. 4 has a configuration including 6 parallel inverters 110 to 160. The 6 parallel inverters 110 to 160 are divided into 3 groups.

That is, the 1 st parallel inverter 110 and the 2 nd parallel inverter 120 are set as the 1 st group inverter 100a. The 3 rd parallel inverter 130 and the 4 th parallel inverter 140 are set as the group 2 inverter 100b. Further, the 5 th parallel inverter 150 and the 6 th parallel inverter 160 are set as the 3 rd group inverter 100c.

The semiconductor switches disposed in the parallel inverters 110 to 160 are turned on/off by a command from a gate command unit 191 of the inverter control device 190.

In this case, each of the parallel inverters 110 to 160 is configured to be supplied with a gate command individually via the switches 119 to 169, and the control of the stop operation can be performed for each of the parallel inverters 110 to 160.

The inverter control system of this example further includes a fault signal receiving unit 192 and a fault handling unit 193.

The fault signal receiving unit 192 performs a fault signal receiving process for receiving the abnormal signals of the inverters 110 to 160.

Here, the fault signal receiving unit 192 receives the abnormality signal individually in each group. That is, the fault signal receiving unit 192 receives the abnormality signal when an abnormality has occurred in the group 1 inverter 100a, the abnormality signal when an abnormality has occurred in the group 2 inverter 100b, and the abnormality signal when an abnormality has occurred in the group 3 inverter 100c separately.

The abnormality signals received by the fault signal receiving unit 192 include an abnormality signal indicating that the semiconductor switches of the respective parallel inverters 110 to 160 are not operating, an abnormality signal indicating that the currents and voltages of the respective parallel inverters 110 to 160 are abnormal, an abnormality signal indicating that the temperatures of the respective parallel inverters 110 to 160 are abnormal, and the like.

The fault handling unit 193 determines which group of the parallel inverters 110 to 160 has an abnormality, and supplies information of the determined group in which the abnormality has occurred to the gate command unit 191.

The gate command unit 191, which has received the information of the abnormal group from the failure handling unit 193, performs control processing for turning off the switches of the lines for controlling the parallel inverters of the corresponding group and operating only the parallel inverters of the remaining group. For example, when an abnormality signal is received from the group 1 inverter, the

switches

119 and 129 are turned off, and only the group 2

parallel inverters

130 and 140 and the group 3

parallel inverters

150 and 160 are operated.

The fault handling unit 193 determines the number of parallel inverters that can normally operate except for the abnormal group. Then, the failure handling unit 193 determines the maximum current that can be supplied to the motor 14 (fig. 1) based on the determination, and instructs an elevator control unit, not shown, of limiting the load and speed of the elevator based on the determined maximum current.

In fig. 4, the fault signal receiving unit 192 and the fault handling unit 193 are provided outside the inverter control device 190, but the fault signal receiving unit 192 and the fault handling unit 193 may be provided in the inverter control device 190.

[ control Process of inverter control device ]

Fig. 5 is a flowchart showing an example of processing in the case where the fault signal receiving unit 192 receives the abnormal signal.

First, the fault signal receiving unit 192 determines whether or not an abnormal signal is received (step S11). If the abnormality signal is not received in step S11 (no in step S11), the gate command unit 191 operates all the parallel inverters 110 to 160.

Then, when the fault signal receiving unit 192 receives the abnormality signal in step S11 (yes in step S11), the fault handling unit 193 determines whether or not the fault signal is an abnormality signal of the group 1 inverter 100a (step S12).

In step S12, if the signal is not an abnormal signal of the group 1 inverter 100a (no in step S12), the failure handling unit 193 determines whether the signal is an abnormal signal of the group 2 inverter 100b (step S13).

In step S13, if the abnormal signal of the group 2 inverter 1O0b is not detected (no in step S13), it is determined that the abnormal signal detected in step S11 is an abnormal signal of the group 3 inverter 100c. Then, the gate command unit 191 turns off the

switches

159 and 169 to stop the group 3 inverter 100c (parallel inverters 150 and 160) (step S14).

Then, in the elevator control device, not shown, the operation of the elevator is continued by the power supplied from the 2

group inverters

100a and 100b excluding the stopped 3 rd group inverter 100c in accordance with the instruction from the failure handling unit 193 (step S15). At this time, since the current supplied to the motor 14 is limited, the elevator control unit performs a boarding restriction process and a travel speed restriction process that restrict the loading rate of the car 17 from 100% in the normal state.

In step S12, if the signal is an abnormal signal of the group 1 inverter 100a (yes in step S12), the fault handling unit 193 further determines whether or not the signal is abnormal even for the group 2 inverter 100b (step S16).

In step S16, when the inverter 100b of group 2 does not output an abnormality signal (no in step S16), the failure handling unit 193 also determines whether or not an abnormality signal is being output to the inverter 100c of group 3 (step S17).

In step S17, when the group 3 inverter 100c does not output an abnormality signal (no in step S17), the failure handling unit 193 determines that only the group 1 inverter 100a is abnormal. At this time, the gate command unit 191 stops the group 1 inverter 100a, and stops the supply of electric power by the group 1 inverter 100a (step S18).

That is, in step S18, electric power is supplied to the motor 14 via the group 2 and group 3

inverters

100b, 100c.

Then, the flow proceeds to step S15, and the elevator control device continues the operation of the elevator with the power supplied through the group 2 and group 3

inverters

100b, 100c, after the elevator taking restriction or the speed restriction is performed.

In step S17, when an abnormality signal is being output to the group 3 inverter 100c as well (yes in step S17), the fault handling unit 193 determines that the group 1 inverter 100a and the group 3 inverter 100c are abnormal. At this time, the gate command unit 191 stops the group 1 inverter 100a and the group 3 inverter 100c, and stops the supply of electric power by the group 1 inverter 100a and the group 3 inverter 100c (step S19).

Then, the flow goes to step S15, and the elevator control device continues the operation of the elevator with the power supplied only by the inverter 100b of group 2, after the elevator taking restriction or the speed restriction is performed.

In addition, in step S16, when the inverter 100b of group 2 is outputting an abnormal signal (yes in step S16), it is also determined whether or not the inverter 100c of group 3 is outputting an abnormal signal (step S20).

In step S20, when the inverter 100c of group 3 is outputting an abnormal signal (yes in step S20), the gate command unit 191 stops the supply of electric power to the inverters 100a to 100c of all groups and stops the elevator because the inverters 100a to 100c of all groups output an abnormal signal (step S21).

In step S20, when the group 3 inverter 100c does not output an abnormality signal (no in step S20), the fault handling unit 193 determines that the group 1 inverter 100a and the group 2 inverter 100b are abnormal. At this time, the gate command unit 191 stops the group 1 inverter 100a and the group 2 inverter 100b (step S22).

Then, the flow proceeds to step S15, and the elevator control device continues the operation of the elevator with the power supplied only by the inverter 100c of group 3, after the elevator taking restriction or the speed restriction is performed.

In addition, in step S13, if the signal is an abnormal signal of the group 2 inverter 100b (yes in step S13), the fault handling unit 193 further determines whether or not the abnormal signal is being output to the group 3 inverter 100c (step S23).

In step S23, when the group 3 inverter 100c is outputting an abnormality signal (yes in step S23), the fault handling unit 193 determines that the group 2 inverter 100b and the group 3 inverter 100c are abnormal. At this time, the gate command unit 191 stops the group 2 inverter 100b and the group 3 inverter 100c (step S24).

Then, the flow proceeds to step S15, and the elevator control device continues the operation of the elevator with the power supplied only by the group 1 inverter 100a, after the elevator taking restriction or the speed restriction is performed.

In step S23, when the inverter 100c of group 3 does not output an abnormality signal (no in step S23), the failure handling unit 193 determines that only the inverter 100b of group 2 is abnormal. At this time, the gate command unit 191 stops the inverter 100b of group 2 (step S25).

Then, the flow goes to step S15, and the elevator control device continues the operation of the elevator with the power supplied through the group 1 inverter 100a and the group 3 inverter 100c, after the elevator taking restriction or the speed restriction is performed.

[ Effect of controlling inverter control device ]

Even when a failure occurs in a group of the inverter device 100, the inverter control device 190 of this example continues the power supply to the motor 14 by using the remaining group of inverters, by performing the control process shown in fig. 5. Thus, the elevator can continue to operate even if a part of the inverter fails.

However, when a part of the inverters fail, the maximum current of the power supply to the motor 14 is limited according to the number of remaining normal groups, and therefore, the elevator taking restriction and the speed restriction of the car 17 are performed, but there is an effect that the elevator-based service can be continued.

Further, as shown in fig. 4, by configuring a group for detecting an abnormal signal by a plurality of parallel inverters, the number of sensors for detecting an abnormal signal can be reduced as compared with the number of parallel inverters, and an abnormal signal can be detected with a simple configuration.

When a failure occurs in some of the group inverters, the elevator car 17 is restricted in riding and speed, so that the operating group inverter is not overloaded and the life of the inverter is not shortened by the continuation of the overload operation.

Modification example

The embodiment examples described so far have been described in detail for the purpose of easily understanding the present invention, but are not necessarily limited to the configuration having all the descriptions.

For example, although the process of the case where the parallel inverters 110 to 160 are provided in 6 is described in the flowchart of fig. 5, the present invention can be applied to a process of selecting an inverter to be operated in the same process in a case where the parallel inverters are provided in N (N is an integer of 2 or more).

The arrangement of the inverter units 111 to 142 shown in fig. 2 is an example, and other configurations are also possible.

In the above embodiment, the control of the inverter device that supplies power to the motor of the elevator was applied, but the control may also be applied to motors of elevators other than elevators. For example, the present invention can be applied to control of an inverter device that supplies power to a motor of an elevator such as an escalator.

In the configuration diagram of the control device shown in fig. 4, only control lines and information lines considered to be necessary for explanation are shown, but the configuration diagram is not necessarily limited to showing all of the control lines and information lines. In practice, it is considered that almost all structures are connected to each other.

Claims

1. An inverter control system for supplying power to a motor driving an elevator by N inverters connected in parallel and controlling each of the inverters connected in parallel, wherein N is an integer of 2 or more, the inverter control system comprising:

a fault signal receiving unit that receives an abnormality signal of the inverter in a group unit that divides the N inverters connected in parallel into a plurality of groups; and

and a gate command unit that causes the inverter of the group other than the group in which the fault signal reception unit receives the abnormal signal to operate.

2. The inverter control system according to claim 1, wherein,

the elevator is restricted in speed or limited in elevator riding corresponding to the number of inverters in a group in which the gate command unit operates.

3. The inverter control system according to claim 2, wherein,

the failure signal receiving unit stops the elevator when an abnormality signal is received from the inverters of all groups.

4. The inverter control system according to claim 1, wherein,

each group is provided with 2 inverters connected in parallel.

5. An inverter control method for supplying power to a motor driving an elevator by N inverters connected in parallel and controlling each of the inverters connected in parallel, wherein N is an integer of 2 or more, the inverter control method comprising:

a fault signal receiving process of receiving an abnormality signal of the inverter in units of inverters that divide the N inverters connected in parallel into a plurality of groups; and

and a control process of operating the inverter of the group other than the group in which the abnormal signal is received in the fault signal reception process.