CN116317579A - Logic circuit for DC-DC converter and DC-DC converter - Google Patents

Logic circuit for DC-DC converter and DC-DC converter Download PDF

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Publication number
CN116317579A
CN116317579A CN202310301139.9A CN202310301139A CN116317579A CN 116317579 A CN116317579 A CN 116317579A CN 202310301139 A CN202310301139 A CN 202310301139A CN 116317579 A CN116317579 A CN 116317579A
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China
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signal
output
coupled
trigger
converter
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CN202310301139.9A
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Chinese (zh)
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刘伟波
马梦娇
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Junying Semiconductor Shanghai Co ltd
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Junying Semiconductor Shanghai Co ltd
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Priority to CN202310301139.9A priority Critical patent/CN116317579A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Embodiments of the present disclosure provide a logic circuit for a DC-DC converter and a DC-DC converter. The logic circuit includes: the device comprises a first step detection circuit, an upper pipe turn-off control circuit and a lower pipe turn-off control circuit. The first step detection circuit is configured to: the first step of the output voltage of the DC-DC converter in the soft start stage is detected according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, the feedback voltage of the DC-DC converter and the first reference voltage from the first reference voltage end to generate a first step indication signal. The upper tube turn-off control circuit is configured to: and in the case that the first step indication signal is at an active level, enabling the upper pipe turn-off signal to be at an active level so as to indicate turn-off of the upper pipe of the DC-DC converter. The down tube turn-off control circuit is configured to: in case the first step indication signal is at an active level, the down tube shut down signal is made to be at an active level to indicate to shut down the down tube of the DC-DC converter.

Description

Logic circuit for DC-DC converter and DC-DC converter
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a logic circuit for a DC-DC converter and a DC-DC converter.
Background
DC-DC (direct current-direct current) converters are widely used in various chip-powered applications. The DC-DC converter includes a BUCK converter (BUCK) and a BOOST converter (BOOST). The buck converter may convert a higher dc voltage to a lower dc voltage. The boost converter may convert a lower dc voltage to a higher dc voltage. During the power-up of the DC-DC converter, if its output voltage rises too fast, the DC-DC converter requires a lot of energy to the forward stage (the power supply stage of the DC-DC converter). In order to protect the power supply of the front stage, a soft start process is provided in the power-up process of the DC-DC converter. Soft start enables the output voltage of the DC-DC converter to rise from zero volts to a nominal value at a slower rate. In this way, the DC-DC converter slowly transfers energy without momentarily extracting too much energy from the input (pre-stage) to destroy the pre-stage.
Disclosure of Invention
Embodiments described herein provide a logic circuit for a DC-DC converter and a DC-DC converter.
According to a first aspect of the present disclosure, a logic circuit for a DC-DC converter is provided. The logic circuit includes: the device comprises a first step detection circuit, an upper pipe turn-off control circuit and a lower pipe turn-off control circuit. Wherein the first step detection circuit is configured to: the first step of the output voltage of the DC-DC converter in the soft start stage is detected according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, the feedback voltage of the DC-DC converter and the first reference voltage from the first reference voltage end to generate a first step indication signal. The upper tube turn-off control circuit is configured to: and in the case that the first step indication signal is at an active level, enabling the upper pipe turn-off signal to be at an active level so as to indicate turn-off of the upper pipe of the DC-DC converter. The down tube turn-off control circuit is configured to: in case the first step indication signal is at an active level, the down tube shut down signal is made to be at an active level to indicate to shut down the down tube of the DC-DC converter.
In some embodiments of the present disclosure, a first step detection circuit includes: the device comprises a ramp signal generating circuit, a starting control circuit, a first RS trigger, an error amplifier and an output circuit. Wherein the ramp signal generating circuit is configured to: a ramp signal is generated. The start control circuit is configured to: a start-up detection signal is generated based on the ramp signal and the first reference voltage. The start detection signal is at a first level when the ramp signal is lower than a first reference voltage. The start detection signal is flipped to a second level when the ramp signal rises to the first reference voltage. The set terminal of the first RS flip-flop is provided with a start-up detection signal. The reset terminal of the first RS flip-flop is provided with one of a down tube shutdown signal and an up tube shutdown signal. A first enable signal is output from an output terminal of the first RS flip-flop. A first input of the error amplifier is provided with a ramp signal. A second input of the error amplifier is provided with a feedback voltage. A soft start control signal is output from the output of the error amplifier. The output circuit is configured to: the first step indication signal is made active in case both the soft start control signal and the first enable signal are active.
In some embodiments of the present disclosure, the start-up control circuit includes: a voltage comparator, and a first inverter. Wherein a first input of the voltage comparator is provided with a ramp signal. The second input end of the voltage comparator is coupled with the first reference voltage end. The output end of the voltage comparator is coupled with the input end of the first inverter. The output end of the first inverter is coupled to the set end of the first RS flip-flop.
In some embodiments of the present disclosure, the start-up control circuit includes: a voltage comparator. The first input end of the voltage comparator is coupled to the first reference voltage end. A second input of the voltage comparator is provided with a ramp signal. The output end of the voltage comparator is coupled with the set end of the first RS trigger.
In some embodiments of the present disclosure, a ramp signal generating circuit includes: a first current source, and a first capacitor. Wherein the first current source is configured to: a first current is provided to a first terminal of a first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal. Wherein a ramp signal is generated at a first end of the first capacitor.
In some embodiments of the present disclosure, the output circuit includes: a second inverter, and an and gate. The input end of the second inverter is coupled with the output end of the error amplifier. The output end of the second inverter is coupled to the first input end of the AND gate. The second input of the AND gate is coupled to the output of the first RS flip-flop. And outputting a first step indication signal from an output end of the AND gate.
In some embodiments of the present disclosure, the upper tube shutdown control circuit includes: and a second RS flip-flop. Wherein the set terminal of the second RS flip-flop is provided with a first step indication signal. And outputting an upper tube closing signal from the output end of the second RS trigger.
In some embodiments of the present disclosure, the down tube shutdown control circuit includes: a delay circuit, and a third RS flip-flop. Wherein the delay circuit is configured to: the first step indication signal is delayed to output a delayed first step indication signal. The set terminal of the third RS flip-flop is provided with a delayed first step indication signal. And outputting a down tube turn-off signal from the output end of the third RS trigger.
In some embodiments of the present disclosure, the first RS flip-flop includes: a first nor gate and a second nor gate. Wherein the first input of the first nor gate is provided with a start-up detection signal. The second input end of the first NOR gate is coupled with the output end of the second NOR gate. The output end of the first NOR gate is coupled with the first input end of the second NOR gate. The second input end of the second nor gate is coupled to the output end of the second RS flip-flop. The output of the second nor gate is the output of the first RS flip-flop.
In some embodiments of the present disclosure, the first RS flip-flop includes: a first nor gate and a second nor gate. Wherein the first input of the first nor gate is provided with a start-up detection signal. The second input end of the first NOR gate is coupled with the output end of the second NOR gate. The output end of the first NOR gate is coupled with the first input end of the second NOR gate. The second input end of the second nor gate is coupled to the output end of the third RS flip-flop. The output of the second nor gate is the output of the first RS flip-flop.
In some embodiments of the present disclosure, the second RS flip-flop includes: a third nor gate and a fourth nor gate. Wherein the first input of the third nor gate is provided with a first step indication signal. The second input end of the third nor gate is coupled to the output end of the fourth nor gate. The output end of the third nor gate is coupled to the first input end of the fourth nor gate. The output of the fourth nor gate is the output of the second RS flip-flop.
In some embodiments of the present disclosure, the third RS flip-flop includes: fifth nor gate and sixth nor gate. Wherein the first input of the fifth nor gate is provided with a delayed first step indication signal. The second input terminal of the fifth nor gate is coupled to the output terminal of the sixth nor gate. The output end of the fifth NOR gate is coupled with the first input end of the sixth NOR gate. The output of the sixth nor gate is the output of the third RS flip-flop.
According to a second aspect of the present disclosure, a logic circuit for a DC-DC converter is provided. The logic circuit includes: the circuit comprises a first current source, a first capacitor, a voltage comparator, a first inverter, a second inverter, an AND gate, an error amplifier, a first RS trigger, a second RS trigger, a third RS trigger and a delay circuit. Wherein the first current source is configured to: a first current is provided to a first terminal of a first capacitor. The second terminal of the first capacitor is coupled to the second voltage terminal. The first input terminal of the error amplifier is coupled to the first terminal of the first capacitor. The second input terminal of the error amplifier is coupled to the feedback voltage terminal of the DC-DC converter. The output end of the error amplifier is coupled with the input end of the second inverter. The first input end of the voltage comparator is coupled with the first end of the first capacitor. The second input end of the voltage comparator is coupled with the first reference voltage end. The output end of the voltage comparator is coupled with the input end of the first inverter. The output end of the first inverter is coupled to the set end of the first RS flip-flop. The reset terminal of the first RS flip-flop is coupled to one of the output terminal of the second RS flip-flop and the output terminal of the third RS flip-flop. The output end of the second inverter is coupled to the first input end of the AND gate. The second input of the AND gate is coupled to the output of the first RS flip-flop. The output end of the AND gate is coupled with the set end of the second RS trigger and the delay circuit. And outputting an upper tube closing signal from the output end of the second RS trigger. The delay circuit is configured to: the first step indication signal output from the and gate is delayed to output a delayed first step indication signal. The set terminal of the third RS flip-flop is provided with a delayed first step indication signal. And outputting a down tube turn-off signal from the output end of the third RS trigger. Wherein the active level of the upper tube shut-off signal is used for indicating to shut off the upper tube of the DC-DC converter. The active level of the down tube shutdown signal is used to indicate the shutdown of the down tube of the DC-DC converter.
According to a third aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter includes: logic circuitry according to the first or second aspect of the present disclosure.
According to a fourth aspect of the present disclosure, a chip is provided. The chip comprises a DC-DC converter according to the third aspect of the present disclosure.
According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a chip according to the fourth aspect of the present disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is a basic topology of a buck converter;
FIG. 2 is an exemplary circuit diagram of a soft start circuit;
FIG. 3 is an exemplary timing diagram of a soft start process performed using the soft start circuit shown in FIG. 2;
FIG. 4 is a schematic block diagram of a logic circuit for a DC-DC converter according to an embodiment of the disclosure;
FIG. 5 is a further schematic block diagram of the logic circuit shown in FIG. 4;
FIG. 6 is an exemplary circuit diagram of the logic circuit shown in FIG. 5;
FIG. 7 is an exemplary timing diagram of a soft start process performed using logic circuitry according to an embodiment of the present disclosure; and
fig. 8 is a comparison of the soft start process shown in fig. 3 and 7.
In the drawings, the last two digits are identical to the elements. It is noted that the elements in the drawings are schematic and are not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows a basic topology of a buck converter. In this buck converter, the upper pipe HS and the lower pipe LS are alternately turned on and off under the control of an upper pipe drive signal DH and a lower pipe drive signal DL, respectively. When the upper tube HS is turned on, the inductor current IL rises with a slope of (VIN-VO)/L. When the down tube LS is turned on, the inductor current IL is decreased, and the slope of the inductor current IL is VO/L. Where VIN represents the input voltage, VO represents the output voltage, and L represents the inductance value of the inductor. In fig. 1, the feedback voltage FB is equal to the voltage division of the output voltage VO across the two resistors. The waveform of the feedback voltage FB follows the waveform variation of the output voltage VO. Also shown in fig. 1 are an output capacitor Cout and a load current source Iload.
As described above, there is a soft start process during the power-up of the DC-DC converter. Fig. 2 shows an exemplary circuit diagram of a soft start circuit for a DC-DC converter. During soft start, the first current I1 output by the first current source I1 charges the capacitor CSS, thereby generating the ramp signal VRAMP on the upper plate of the capacitor CSS. The magnitudes of the feedback voltage FB and the ramp signal VRAMP are compared by the error amplifier EA. When the feedback voltage FB is higher than the ramp signal VRAMP, the soft start control signal ss_ctl is at a low level, controlling the down tube LS to be turned on. The down tube LS is turned on until the inductor current IL drops to zero or the ramp signal VRAMP rises to the feedback voltage FB. The feedback voltage FB is not much higher than the ramp signal VRAMP. The upper tube HS is turned on only when the feedback voltage FB is lower than the ramp signal VRAMP, so that the feedback voltage FB and the ramp signal VRAMP can be closely raised during soft start. Since the ramp signal VRAMP is obtained by charging the capacitor CSS having a large capacity with the current I1 having a small amplitude, the feedback voltage FB can be increased slowly, and the output voltage VO can be increased slowly.
In practical applications, the capacitor CSS may be located outside the DC-DC converter. The pin connecting the capacitor CSS is denoted SS. If the upper plate (pin SS) of the capacitor CSS is shorted to ground, the ramp signal VRAMP cannot rise all the time, and if the switching operation of the upper and lower pipes is allowed at this time, various abnormal situations may occur, such as the upper and lower pipes being always switched in the forced continuous conduction mode (FCCM mode), etc. It is necessary to wait for the ramp signal VRAMP to rise to a certain value before starting switching. Therefore, a voltage comparator CMP is provided in the soft start circuit shown in fig. 2. The voltage comparator CMP compares the magnitudes of the ramp signal VRAMP and the reference voltage Vref1 to generate the signal ss_short. The signal ss_short may be provided to circuitry in the DC-DC converter for generating the upper and lower pipe drive signals DH and DL to indicate whether or not to allow switching to begin. When the ramp signal VRAMP rises to the reference voltage Vref1, the signal ss_short toggles high, indicating that switching is allowed to start.
FIG. 3 illustrates an exemplary timing diagram for a soft start process performed using the soft start circuit shown in FIG. 2. As shown in fig. 3, the stepped-up voltage (shown by the dotted line) is the feedback voltage FB, the ramp signal VRAMP, and the saw-tooth current is the inductor current IL.
At time t1, the blocks within the DC-DC converter are enabled and the ramp signal VRAMP begins to rise. At time t2 ramp signal VRAMP rises to a threshold (reference voltage Vref1 in fig. 2) that allows switching to begin, at which time upper tube HS begins to conduct and begin delivering energy to the output of the DC-DC converter. Since the output voltage VO is zero at this time, the slope of the inductor current IL at the rise is very large (equal to VIN/L) and the slope of the inductor current IL at the fall is almost zero (equal to-VO/L). Therefore, the inductor current IL rises quickly. At time t3, the feedback voltage FB rises to be equal to the ramp signal VRAMP, at which time the down tube starts to be turned on. Since the output voltage VO is not very high (e.g., 100mV to 200 mV), the inductor current IL drops relatively slowly. Until time t4, inductor current IL drops to zero. At time t5, ramp signal VRAMP rises above feedback voltage FB, continuing to open up tube HS to deliver energy to the output.
As can be seen from fig. 3, the first step (step before time t 5) of the feedback voltage FB will be much higher than the following steps (steps after time t 5) at the beginning of soft start (especially when the DC-DC converter has a small duty cycle). This is because the inductor current IL has the highest rising slope at the beginning of soft start, and the ramp signal VRAMP needs to rise to a certain value (reference voltage Vref1 in fig. 2) to open the upper tube. Thus, the inductor current IL will be raised very high during the first few cycles. In addition, during the process (between time t3 and time t 4) of the inductor current IL falling after the feedback voltage FB exceeds the ramp signal VRAMP, all energy is delivered to the output terminal, and this energy may cause the feedback voltage FB to rise too much. If the first step of the output voltage VO rises to the turn-on voltage of the next stage circuit at soft start, the next stage circuit will start to operate. And the next stage acts as a load to pull the output voltage VO low. When the output voltage VO is too low, the next stage circuit stops operating again. In this way, there is a risk that the next stage circuit is turned on and off. And there is a risk that the output voltage VO and the inductor current IL will ripple too much at the beginning of a soft start if the DC-DC converter is soft started under load.
Accordingly, embodiments of the present disclosure propose a logic circuit for a DC-DC converter, which aims to reduce the amplitude of the first step of the output voltage in the soft start phase, thereby making the DC-DC converter operate more stably. Fig. 4 shows a schematic block diagram of a logic circuit 400 for a DC-DC converter according to an embodiment of the disclosure. The logic circuit 400 includes: a head step detection circuit 410, an upper pipe shut-off control circuit 420, and a lower pipe shut-off control circuit 430.
The head step detection circuit 410 is coupled to the upper pipe shut-off control circuit 420 and the lower pipe shut-off control circuit 430. The first step detection circuit 410 is configured to: the first step of the output voltage VO of the DC-DC converter during the soft start phase is detected from one of the upper tube shutdown signal close_h output by the upper tube shutdown control circuit 420 and the lower tube shutdown signal close_l output by the lower tube shutdown control circuit 430, the feedback voltage FB of the DC-DC converter, and the first reference voltage Vref1 from the first reference voltage terminal Vref1 to generate the first step indication signal pfm_fir. In case a first step of the output voltage VO is detected, the first step indication signal pfm_fir is flipped to an active level. In some embodiments of the present disclosure, the active level of the first step indication signal pfm_fir is a high level.
The upper pipe turn-off control circuit 420 is coupled to the head step detection circuit 410 and the lower pipe turn-off control circuit 430. The upper pipe shut-off control circuit 420 is configured to: in case the first step indication signal pfm_fir is at an active level, the upper pipe shutdown signal close_h is made at an active level to indicate to shutdown the upper pipe HS of the DC-DC converter. In some embodiments of the present disclosure, the upper tube shutdown control circuit 420 is further configured to: in the case where the first step indication signal pfm_fir is at an inactive level, the upper pipe shut-off signal close_h is controlled according to an upper pipe control signal in the DC-DC converter.
The down tube turn-off control circuit 430 is coupled to the head step detection circuit 410 and the up tube turn-off control circuit 420. The down tube shutdown control circuit 430 is configured to: in case the first step indication signal pfm_fir is at an active level, the down tube shutdown signal close_l is made at an active level to indicate to shut down the down tube LS of the DC-DC converter. In some embodiments of the present disclosure, the down tube shutdown control circuit 430 is further configured to: in the case where the first step indication signal pfm_fir is at an inactive level, the down tube off signal close_l is controlled according to a down tube control signal in the DC-DC converter.
The logic circuit 400 according to an embodiment of the present disclosure controls to turn off both the upper and lower tubes HS and LS of the DC-DC converter when the output voltage VO appears a first step (the feedback voltage FB appears a first step). Referring to fig. 1, in this case, the inductor current IL is discharged through the body diode of the down tube LS, where vo=v SW -0.7V. Wherein V is SW The voltage value at the SW point is indicated. If the lower tube LS is turned on to discharge the inductor current IL, the slope of the inductor current IL is-VO/L, if both the upper tube HS and the lower tube LS are turned off to discharge the inductor current IL, the slope of the inductor current IL is (-V) SW -VO)/L. Thus, the slope of the inductor current IL is increased by several times, and the inductor current IL can be quickly discharged to zero ampere.
Fig. 7 illustrates an exemplary timing diagram of a soft start process performed using logic circuitry according to an embodiment of the present disclosure. Referring to fig. 7, it can be seen that when the feedback voltage FB has a first step (time t 3), the slope of the inductor current IL (time t3 to time t 6) becomes larger, thereby dropping to zero ampere more quickly. At time t7, ramp signal VRAMP rises above feedback voltage FB, continuing to open up tube HS to deliver energy to the output.
In this way, the output voltage VO of the DC-DC converter using the logic circuit 400 of the embodiment of the present disclosure slowly rises, without causing the next stage circuit to be turned on and off at once. In addition the risk of excessive ripple of the output voltage VO and the inductor current IL is avoided.
Fig. 8 shows a comparison of the soft start process shown in fig. 3 and 7. In fig. 8, the inductor current value decreasing from time t3 to time t4 is indicated by a hatched portion. The energy of the shaded portion is not transferred to the output terminal and therefore the first step of the output voltage is significantly reduced. As can be seen from fig. 8, the difference between the first step of the feedback voltage FB and the rise of the ramp signal VRAMP to the threshold value (Vref 1) of the start switch is significantly reduced. The operation is only needed to be carried out once, so that the follow-up soft start and the normal work after the soft start are not affected.
In some embodiments of the present disclosure, the first step detection circuit 410 can control the first step indication signal pfm_fir to remain at an inactive level after the upper pipe shut-off signal close_h or the lower pipe shut-off signal close_l toggles to an active level. In this way, the first step indication signal pfm_fir no longer affects the upper pipe shut-off signal close_h and the lower pipe shut-off signal close_l, thereby making the upper pipe HS and the lower pipe LS normally alternately turned on and off.
Fig. 5 shows a further schematic block diagram of the logic circuit shown in fig. 4. In the logic circuit 500, the first step detection circuit 510 includes: a ramp signal generating circuit 511, a start control circuit 512, a first RS flip-flop 513, an error amplifier EA, and an output circuit 514.
An output terminal of the ramp signal generating circuit 511 is coupled to an input terminal of the start-up control circuit 512 and a first input terminal of the error amplifier EA. The ramp signal generating circuit 511 is configured to: the ramp signal VRAMP is generated.
An input terminal of the start-up control circuit 512 is coupled to the ramp signal generating circuit 511 and a first input terminal of the error amplifier EA. An output terminal of the start control circuit 512 is coupled to the first RS flip-flop 513. The start-up control circuit 512 is also coupled to the first reference voltage terminal Vref1. The start control circuit 512 is configured to: the start detection signal ss_short is generated according to the ramp signal VRAMP and the first reference voltage Vref1. The start detection signal ss_short is at a first level when the ramp signal VRAMP is lower than the first reference voltage Vref1. The start detection signal ss_short is flipped to the second level when the ramp signal VRAMP rises to the first reference voltage Vref1. In some embodiments of the present disclosure, the first level is a high level. The second level is low.
The set terminal of the first RS flip-flop 513 is supplied with the start detection signal ss_short. The reset terminal of the first RS flip-flop 513 is supplied with one of the down tube shutdown signal close_l and the up tube shutdown signal close_h (the reset terminal of the first RS flip-flop 513 is supplied with the down tube shutdown signal close_l in the example of fig. 5, but the reset terminal of the first RS flip-flop 513 may also be supplied with the up tube shutdown signal close_h). The first enable signal EN1 is output from the output terminal of the first RS flip-flop 513. In some embodiments of the present disclosure, the first enable signal EN1 is at an active level in a case where the set terminal of the first RS flip-flop 513 is provided with an active level and the reset terminal of the first RS flip-flop 513 is provided with an inactive level. In the case where the set terminal of the first RS flip-flop 513 is supplied with the inactive level and the reset terminal of the first RS flip-flop 513 is supplied with the active level, the first enable signal EN1 is at the inactive level. In the case where both the set terminal and the reset terminal of the first RS flip-flop 513 are supplied with the inactive level, the level of the first enable signal EN1 remains unchanged. In some embodiments of the present disclosure, the active level of the first RS flip-flop 513 is a high level.
A first input of the error amplifier EA is supplied with a ramp signal VRAMP. A second input of the error amplifier EA is provided with a feedback voltage FB. The soft start control signal ss_ctl is output from the output terminal of the error amplifier EA. In the example of fig. 5, the first input of the error amplifier EA is a non-inverting input and the second input of the error amplifier EA is an inverting input. In some embodiments of the present disclosure, the soft start control signal ss_ctl is at an inactive level when the feedback voltage FB is lower than the ramp signal VRAMP. When the feedback voltage FB rises to the ramp signal VRAMP, the soft start control signal ss_ctl toggles to an active level. In some embodiments of the present disclosure, the active level of the soft start control signal ss_ctl is a low level, and the inactive level of the soft start control signal ss_ctl is a high level.
Two inputs of the output circuit 514 are coupled to the output of the error amplifier EA and the output of the first RS flip-flop 513, respectively. An output terminal of the output circuit 514 is coupled to an upper pipe shut-off control circuit 520 and a lower pipe shut-off control circuit 530. The output circuit 514 is configured to: the first step indication signal pfm_fir is made to be at an active level in the case where both the soft start control signal ss_ctl and the first enable signal EN1 are at active levels. The output circuit 514 is further configured to: the first step indication signal pfm_fir is made to be at an inactive level in the case where at least one of the soft start control signal ss_ctl and the first enable signal EN1 is at an inactive level.
The upper pipe shut-off control circuit 520 includes: a second RS flip-flop 521. Wherein the set terminal of the second RS flip-flop 521 is provided with a first step indication signal pfm_fir. The upper pipe shut-off signal close_h is output from the output terminal of the second RS flip-flop 521. In addition, the set and reset terminals of the second RS flip-flop 521 may be provided with an upper pipe control signal for controlling the normal switching of the upper pipe HS. When the first step indication signal pfm_fir is at an inactive level, the upper pipe control signal can control the second RS flip-flop 521 to normally generate the upper pipe off signal close_h, thereby controlling the upper pipe HS to normally turn on and off.
The down tube shutoff control circuit 530 includes: a delay circuit 531, and a third RS flip-flop 532. Wherein the delay circuit 531 is configured to: the first step indication signal pfm_fir is delayed to output a delayed first step indication signal pfm_fir. The time delay period may be set according to a specific application, to which embodiments of the present disclosure are not limited. The set terminal of the third RS flip-flop 532 is provided with the delayed first step indication signal pfm_fir. The down tube off signal close_l is output from the output terminal of the third RS flip-flop 532. Wherein the delay circuit 531 is used to guarantee dead time of the DC-DC converter. In addition, the set and reset terminals of the third RS flip-flop 532 may be provided with a down tube control signal for controlling the normal switching of the down tube LS. When the first step indication signal pfm_fir is at an inactive level, the down tube control signal can control the third RS flip-flop 532 to normally generate the down tube off signal close_l, thereby controlling the down tube LS to normally turn on and off.
In the example of fig. 5, the initial levels of the upper pipe shut down signal close_h and the lower pipe shut down signal close_l are at an inactive level (e.g., low level). At the start of soft start, the ramp signal VRAMP gradually rises. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the start-up detection signal ss_short is at the first level. The start detection signal ss_short at the first level sets the first RS flip-flop 513 such that the first enable signal EN1 is at an active level. When the ramp signal VRAMP rises to the first reference voltage Vref1, the start-up detection signal ss_short is inverted to the second level. Since the down tube shutdown signal close_l is at the initial inactive level at this time, the first RS flip-flop 513 keeps the first enable signal EN1 unchanged from the previous state (i.e., the first enable signal EN1 is still at the active level). When the feedback voltage FB rises to the ramp signal VRAMP, the soft start control signal ss_ctl output by the error amplifier EA is inverted to an active level. At this time, both the soft start control signal ss_ctl and the first enable signal EN1 are at an active level, and thus the first step indication signal pfm_fir is flipped to an active level. The first step indication signal pfm_fir at an active level causes the upper pipe shut down signal close_h to flip to an active level and causes the lower pipe shut down signal close_l to flip to an active level after a delay. In this case, both the upper tube and the lower tube are turned off, so that the inductor current IL is rapidly discharged.
The down tube off signal close_l flipped to the active level causes the first RS flip-flop 513 to be reset, and thus, the first enable signal EN1 is flipped to the inactive level. At this time, the first step indication signal pfm_fir is inverted to an inactive level. Since the ramp signal VRAMP does not fall below the first reference voltage Vref1, the start-up detection signal ss_short does not flip to the first level. The first RS flip-flop 513 is not set again to control the first enable signal EN1 to flip-flop to the active level. In this way, the first step indication signal pfm_fir will remain at an inactive level all the time, and the upper pipe shut-off signal close_h and the lower pipe shut-off signal close_l are not affected any more, so that the upper pipe HS and the lower pipe LS are normally alternately turned on and off.
Fig. 6 shows an exemplary circuit diagram of the logic circuit shown in fig. 5. In the logic circuit 600, the start control circuit 612 in the first step detection circuit 610 includes: a voltage comparator CMP, and a first inverter NG1. Wherein a first input of the voltage comparator CMP is provided with a ramp signal VRAMP. The second input terminal of the voltage comparator CMP is coupled to the first reference voltage terminal Vref1. The output terminal of the voltage comparator CMP is coupled to the input terminal of the first inverter NG1. The output terminal of the first inverter NG1 is coupled to the set terminal of the first RS flip-flop 613. In the example of fig. 6, the first input of the voltage comparator CMP is a non-inverting input and the second input of the voltage comparator CMP is an inverting input. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the output signal ss_short of the voltage comparator CMP is at a low level and the start-up detection signal ss_short is at a high level. When the ramp signal VRAMP rises to the first reference voltage Vref1, the output signal ss_short of the voltage comparator CMP is inverted to a high level, and the start-up detection signal ss_short is inverted to a low level.
In an alternative embodiment illustrated in fig. 6, the start-up control circuit 612 may include only: a voltage comparator CMP. The first input terminal of the voltage comparator CMP is coupled to the first reference voltage terminal Vref1. A second input terminal of the voltage comparator CMP is supplied with the ramp signal VRAMP. The output terminal of the voltage comparator CMP is coupled to the set terminal of the first RS flip-flop 613. In this alternative embodiment, the first input of the voltage comparator CMP is a non-inverting input and the second input of the voltage comparator CMP is an inverting input. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the start-up detection signal ss_short output by the voltage comparator CMP is at a high level. When the ramp signal VRAMP rises to the first reference voltage Vref1, the start detection signal ss_short output by the voltage comparator CMP is inverted to a low level.
The ramp signal generating circuit 611 includes: a first current source I1, and a first capacitor CSS. Wherein the first current source I1 is powered by a first voltage V1. The first current source I1 is coupled to a first terminal (pin SS) of the first capacitor CSS. The first current source I1 is configured to: the first current I1 is supplied to the first terminal of the first capacitor CSS. The second terminal of the first capacitor CSS is coupled to the second voltage terminal V2. As the charge from the first current I1 is stored in the first capacitor CSS, the ramp signal VRAMP is generated at the first end of the first capacitor CSS.
The output circuit 614 includes: a second inverter NG2, AND an AND gate AND. Wherein the input of the second inverter NG2 is coupled to the output of the error amplifier EA. The output of the second inverter NG2 is coupled to the first input of the AND gate AND. A second input of the AND gate AND is coupled to an output of the first RS flip-flop 613. The first step indication signal pfm_fir is output from the output terminal of the AND gate AND.
In the example of fig. 6, the first RS flip-flop 613 includes: a first NOR gate NOR1 and a second NOR gate NOR2. Wherein a first input of the first NOR gate NOR1 is provided with a start detection signal ss_short. A second input of the first NOR gate NOR1 is coupled to an output of the second NOR gate NOR2. The output of the first NOR gate NOR1 is coupled to a first input of a second NOR gate NOR2. A second input of the second NOR gate NOR2 is coupled to an output of the second RS flip-flop 621. The output of the second NOR gate NOR2 is the output of the first RS flip-flop 613.
In an alternative embodiment illustrated in fig. 6, the second input of the second NOR gate NOR2 in the first RS flip-flop 613 may also be coupled to the output of the third RS flip-flop 632.
The second RS flip-flop 621 in the upper pipe shut-off control circuit 620 includes: a third NOR gate NOR3 and a fourth NOR gate NOR4. Wherein a first input of the third NOR gate NOR3 is provided with a first step indication signal pfm_fir. A second input of the third NOR gate NOR3 is coupled to an output of the fourth NOR gate NOR4. The output of the third NOR gate NOR3 is coupled to a first input of a fourth NOR gate NOR4. The output of the fourth NOR gate NOR4 is the output of the second RS flip-flop 621.
The third RS flip-flop 632 in the down pipe shut down control circuit 630 includes: a fifth NOR gate NOR5 and a sixth NOR gate NOR6. Wherein a first input of the fifth NOR gate NOR5 is provided with a delayed first step indication signal PFM FIR. A second input of the fifth NOR gate NOR5 is coupled to an output of the sixth NOR gate NOR6. The output of the fifth NOR gate NOR5 is coupled to a first input of a sixth NOR gate NOR6. The output of the sixth NOR gate NOR6 is the output of the third RS flip-flop 632.
In the example of fig. 6, a high voltage signal is input from a first voltage terminal V1, and a second voltage terminal V2 is grounded. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 6 based on the above inventive concepts are also within the scope of the present disclosure.
In the example of fig. 6, the initial levels of the upper pipe shut down signal close_h and the lower pipe shut down signal close_l are low. At the start of soft start, the first current I1 starts to charge the first capacitor CSS, and the ramp signal VRAMP gradually rises. When the ramp signal VRAMP is lower than the first reference voltage Vref1, the output signal ss_short of the voltage comparator CMP is at a low level and the start-up detection signal ss_short is at a high level. The start detection signal ss_short at a high level sets the first RS flip-flop 613 so that the first enable signal EN1 is at a high level. When the ramp signal VRAMP rises to the first reference voltage Vref1, the output signal ss_short of the voltage comparator CMP is turned to a high level (allowing the upper pipe HS and the lower pipe LS to start the switching operation), and the start-up detection signal ss_short is turned to a low level. Since the down tube off signal close_l is at an initial low level at this time, the first RS flip-flop 613 keeps the first enable signal EN1 unchanged from the previous state (i.e., the first enable signal EN1 is still at a high level). Referring to fig. 7, when the feedback voltage FB rises to the ramp signal VRAMP (time t 3), the soft start control signal ss_ctl output by the error amplifier EA is inverted to a low level. At this time, both the signal output from the second inverter NG2 and the first enable signal EN1 are at a high level, and thus the first step indication signal pfm_fir is inverted to a high level. The first step indication signal pfm_fir at a high level causes the upper pipe shut down signal close_h to flip to a high level and causes the lower pipe shut down signal close_l to flip to a high level after a delay. In this case, both the upper tube and the lower tube are turned off, so that the inductor current IL is rapidly discharged.
The down tube off signal close_l flipped to the high level causes the first RS flip-flop 613 to be reset, and thus, the first enable signal EN1 is flipped to the low level. At this time, the first step indication signal pfm_fir is inverted to a low level. Since the ramp signal VRAMP does not fall below the first reference voltage Vref1, the start-up detection signal ss_short does not flip to a high level. The first RS flip-flop 613 is not set again to control the first enable signal EN1 to flip-flop high. In this way, the first step indication signal pfm_fir will remain low all the time, and the upper pipe shut-off signal close_h and the lower pipe shut-off signal close_l are not affected any more, so that the upper pipe HS and the lower pipe LS are normally alternately turned on and off.
Embodiments of the present disclosure also provide a DC-DC converter. The DC-DC converter includes logic circuitry according to embodiments of the present disclosure.
The embodiment of the disclosure also provides a chip. The chip includes a DC-DC converter according to an embodiment of the present disclosure. The chip is, for example, a power management type chip.
The embodiment of the disclosure also provides electronic equipment. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is for example a smart terminal device such as a tablet computer, a smart phone or the like.
In summary, the logic circuit according to the embodiment of the present disclosure reduces the amplitude of the first step of the output voltage in the soft start phase by controlling the upper and lower transistors to be fully turned off when the feedback voltage first rises to the ramp voltage. And the operation is only carried out once, and the subsequent soft start and the normal work after the soft start are not affected. According to the DC-DC converter disclosed by the embodiment of the invention, the situations of false start of a next-stage circuit and overlarge ripple during soft start with load can be effectively avoided, and the DC-DC converter can work more stably.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (10)

1. A logic circuit for a DC-DC converter, comprising: a first step detection circuit, an upper pipe turn-off control circuit and a lower pipe turn-off control circuit,
wherein the first step detection circuit is configured to: detecting a first step of an output voltage of the DC-DC converter at a soft start stage according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, a feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal to generate a first step indication signal;
The upper tube turn-off control circuit is configured to: under the condition that the first step indicating signal is at an active level, the upper tube closing signal is at an active level to indicate closing of an upper tube of the DC-DC converter;
the down tube turn-off control circuit is configured to: and under the condition that the first step indicating signal is at an active level, the down pipe closing signal is at an active level so as to indicate closing of the down pipe of the DC-DC converter.
2. The logic circuit of claim 1, wherein the first step detection circuit comprises: a ramp signal generating circuit, a start control circuit, a first RS trigger, an error amplifier, and an output circuit,
wherein the ramp signal generating circuit is configured to: generating a ramp signal;
the start control circuit is configured to: generating a start detection signal according to the ramp signal and the first reference voltage, wherein the start detection signal is at a first level when the ramp signal is lower than the first reference voltage, and the start detection signal is turned to a second level when the ramp signal is increased to the first reference voltage;
the set end of the first RS trigger is provided with the starting detection signal, the reset end of the first RS trigger is provided with one of the lower pipe shut-off signal and the upper pipe shut-off signal, and a first enabling signal is output from the output end of the first RS trigger;
The first input end of the error amplifier is provided with the ramp signal, the second input end of the error amplifier is provided with the feedback voltage, and a soft start control signal is output from the output end of the error amplifier;
the output circuit is configured to: the first step indication signal is made active in case both the soft start control signal and the first enable signal are active.
3. The logic circuit of claim 2, wherein the start-up control circuit comprises: a voltage comparator, and a first inverter,
wherein a first input end of the voltage comparator is provided with the ramp signal, a second input end of the voltage comparator is coupled with the first reference voltage end, and an output end of the voltage comparator is coupled with an input end of the first inverter;
the output end of the first inverter is coupled with the set end of the first RS trigger.
4. The logic circuit of claim 2, wherein the start-up control circuit comprises: the voltage of the voltage-to-voltage converter,
the first input end of the voltage comparator is coupled to the first reference voltage end, the second input end of the voltage comparator is provided with the ramp signal, and the output end of the voltage comparator is coupled to the set end of the first RS trigger.
5. The logic circuit according to claim 2, wherein the ramp signal generating circuit comprises: a first current source and a first capacitor,
wherein the first current source is configured to: providing a first current to a first terminal of the first capacitor;
the second end of the first capacitor is coupled with a second voltage end;
wherein the ramp signal is generated at a first end of the first capacitor.
6. The logic circuit of claim 2, wherein the output circuit comprises: a second inverter, and an and gate,
the input end of the second inverter is coupled with the output end of the error amplifier, and the output end of the second inverter is coupled with the first input end of the AND gate;
the second input end of the AND gate is coupled with the output end of the first RS trigger, and the first step indication signal is output from the output end of the AND gate.
7. The logic circuit according to any one of claims 1 to 6, wherein the upper pipe shut-off control circuit includes: a second RS flip-flop is provided which is configured to be toggled,
the setting end of the second RS trigger is provided with the first step indication signal, and the upper tube turn-off signal is output from the output end of the second RS trigger.
8. The logic circuit according to any one of claims 1 to 6, wherein the down tube shutdown control circuit comprises: a delay circuit, and a third RS flip-flop,
wherein the delay circuit is configured to: delaying the first step indication signal to output a delayed first step indication signal;
the setting end of the third RS trigger is provided with the delayed head step indication signal, and the down tube turn-off signal is output from the output end of the third RS trigger.
9. A logic circuit for a DC-DC converter, comprising: a first current source, a first capacitor, a voltage comparator, a first inverter, a second inverter, an AND gate, an error amplifier, a first RS trigger, a second RS trigger, a third RS trigger, and a delay circuit,
wherein the first current source is configured to: providing a first current to a first terminal of the first capacitor;
the second end of the first capacitor is coupled with a second voltage end;
the first input end of the error amplifier is coupled with the first end of the first capacitor, the second input end of the error amplifier is coupled with the feedback voltage end of the DC-DC converter, and the output end of the error amplifier is coupled with the input end of the second inverter;
The first input end of the voltage comparator is coupled with the first end of the first capacitor, the second input end of the voltage comparator is coupled with the first reference voltage end, and the output end of the voltage comparator is coupled with the input end of the first inverter;
the output end of the first inverter is coupled with the set end of the first RS trigger;
the reset end of the first RS trigger is coupled with one of the output end of the second RS trigger and the output end of the third RS trigger;
the output end of the second inverter is coupled with the first input end of the AND gate;
the second input end of the AND gate is coupled with the output end of the first RS trigger, and the output end of the AND gate is coupled with the setting end of the second RS trigger and the delay circuit;
outputting an upper tube turn-off signal from the output end of the second RS trigger;
the delay circuit is configured to: delaying the first step indication signal output from the and gate to output a delayed first step indication signal;
the setting end of the third RS trigger is provided with the delayed first step indication signal, and a down tube turn-off signal is output from the output end of the third RS trigger;
The effective level of the upper tube turn-off signal is used for indicating turn-off of an upper tube of the DC-DC converter, and the effective level of the lower tube turn-off signal is used for indicating turn-off of a lower tube of the DC-DC converter.
10. A DC-DC converter, comprising: the logic circuit according to any one of claims 1 to 9.
CN202310301139.9A 2023-03-23 2023-03-23 Logic circuit for DC-DC converter and DC-DC converter Pending CN116317579A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310301139.9A CN116317579A (en) 2023-03-23 2023-03-23 Logic circuit for DC-DC converter and DC-DC converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310301139.9A CN116317579A (en) 2023-03-23 2023-03-23 Logic circuit for DC-DC converter and DC-DC converter

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Publication Number Publication Date
CN116317579A true CN116317579A (en) 2023-06-23

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Family Applications (1)

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