CN116314329A - Super-junction trench gate MOSFET and preparation method thereof - Google Patents
Super-junction trench gate MOSFET and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 210000000746 body region Anatomy 0.000 claims abstract description 35
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
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- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract 3
- 239000007924 injection Substances 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
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Abstract
The invention provides a super-junction trench gate MOSFET and a preparation method thereof, wherein the preparation method comprises the following steps: forming an epitaxial layer on a substrate; forming a trench gate structure; performing global ion implantation on the epitaxial layer to form a body region; forming a first heavily doped region; forming a column region, wherein an overlapping region exists between the column region of the terminal region and the trench gate structure; forming a second contact hole; and forming a second heavily doped region and forming a first conductive plug and a second conductive plug. According to the method, the plurality of spaced trench gate structures are introduced into the terminal area, the body area with the injection depth smaller than the depth of the trench gate structures is formed between the trench gate structures through global ion injection, and the column area is formed at the bottom of the trench gate structure of the terminal area, so that the body area of the terminal area is isolated into the independent floating body area, the voltage resistance of the terminal area is improved, the electrical performance of a device is improved, the number of photomasks corresponding to the ion injection of the body area is reduced, the preparation process is simplified, and the manufacturing cost is reduced.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a super-junction trench gate MOSFET and a preparation method thereof.
Background
Trench gate MOSFET devices are widely used in power conversion circuits, and are commonly used in power switching devices. The on-resistance (R_sp) and Breakdown Voltage (BV) of the trench gate are one of important parameter indexes, so that higher breakdown voltage is obtained, and the lower on-resistance can improve the competitiveness of the product. In order to improve the on-resistance of medium-high voltage (50V-200V) trench gates, a superjunction-trench gate concept realized by ion implantation is proposed.
Currently, superjunction trench gate MOSFETs generally comprise: in order to improve the withstand voltage of the termination region, the cell region and the termination region are typically selected to form an independently floating PPL (P-pilar) in the termination region, since the P-Body (P-Body) has a doping concentration of more than 1E17 atoms/cm 3 Therefore, the P-Body is not required to be implanted in the terminal region of the whole device, so that a mask corresponding to the P-Body ion implantation is required to be added, but the addition of a mask layer tends to increase the manufacturing cost of the platform.
Disclosure of Invention
The application provides a super-junction trench gate MOSFET and a preparation method thereof, which can solve at least one of the problems of insufficient withstand voltage of a terminal area of the super-junction trench gate MOSFET, higher manufacturing cost of the super-junction trench gate MOSFET and the like.
In one aspect, an embodiment of the present application provides a method for preparing a super-junction trench gate MOSFET, including:
providing a substrate, wherein the substrate comprises a cell region and a terminal region;
forming an epitaxial layer, wherein the epitaxial layer covers the surface of the substrate;
forming a plurality of trench gate structures which are spaced from each other, wherein the trench gate structures are positioned in the epitaxial layer of the primordial cell region and the epitaxial layer of the terminal region;
performing global ion implantation on the epitaxial layer to form a body region between the trench gate structures of the cell region and at the bottom of the trench gate structure of the terminal region, wherein the depth of the trench gate structure is greater than the implantation depth of the body region;
performing selective ion implantation on the epitaxial layer to form a plurality of first heavily doped regions in the body region of the cell region;
performing selective ion implantation on the epitaxial layer to form a plurality of column regions in the epitaxial layer between the trench gate structures, wherein an overlapping region exists between the column regions of the terminal region and the trench gate structures;
etching the first heavily doped region of the cell region and the column region with partial thickness to form a plurality of first contact holes, and simultaneously, etching the top end of the trench gate structure of the cell region to form a plurality of second contact holes;
ion implantation is carried out on the bottom of the contact hole so as to form a plurality of second heavily doped regions between the first heavily doped region and the column region; the method comprises the steps of,
and forming a first conductive plug and a second conductive plug, wherein the first conductive plug fills the first contact hole, and the second conductive plug fills the second contact hole.
Optionally, in the method for manufacturing a super junction trench gate MOSFET, a distance from a center of a trench gate structure in the cell region near the termination region to a center of a trench gate in the termination region near the cell region is greater than a distance between centers of two adjacent trench gate structures in the cell region.
Optionally, in the method for manufacturing a super-junction trench gate MOSFET, the step of forming a plurality of trench gate structures spaced apart from each other includes:
etching a part of the epitaxial layer to form a plurality of grooves in the epitaxial layer of the cell region and the epitaxial layer of the terminal region;
forming a gate dielectric layer, wherein the gate dielectric layer covers the side wall and the bottom wall of the groove;
and forming a polysilicon gate, wherein the polysilicon gate covers the gate dielectric layer and fills the residual space of the trench.
Optionally, in the method for manufacturing the super junction trench gate MOSFET, the step of forming the first conductive plug and the second conductive plug includes:
forming a first metal layer, wherein the first metal layer covers the side wall and the bottom wall of the first contact hole and the side wall and the bottom wall of the second contact hole;
forming a second metal layer, wherein the second metal layer covers the first metal layer;
performing a thermal annealing process;
forming a third metal layer which covers the second metal layer and fills the residual spaces of the first contact hole and the second contact hole;
and removing the first metal layer, the second metal layer and the third metal layer which exceed the surfaces of the first contact hole, the second contact hole and the epitaxial layer to obtain the first conductive plug in the first contact hole and obtain the second conductive plug in the second contact hole.
Optionally, in the preparation method of the super-junction trench gate MOSFET, the first metal layer is a titanium layer; the second metal layer is a titanium nitride layer; the third metal layer is a tungsten layer.
On the other hand, the embodiment of the application also provides a super-junction trench gate MOSFET, which comprises:
a substrate comprising a cell region and a termination region;
an epitaxial layer, wherein the epitaxial layer covers the surface of the substrate;
a plurality of trench gate structures spaced apart from one another, the trench gate structures being located in the epitaxial layer of the cell region and in the epitaxial layer of the termination region;
the body region is positioned in the epitaxial layer between the trench gate structures and is obtained by carrying out global ion implantation on the epitaxial layer, wherein the depth of the trench gate structure is larger than the implantation depth of the body region;
a plurality of first heavily doped regions located in the body region of the primordial region;
the column regions are positioned at the bottoms of the first heavily doped regions of the primordial cell regions and the bottoms of the trench gate structures of the terminal regions;
the second heavily doped regions are positioned at the bottoms of the first heavily doped regions of the primordial cell regions; the method comprises the steps of,
a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are positioned in the first heavily doped region of the cell region and the column region with partial thickness, and the second conductive plugs are positioned at the top end of the trench gate structure of the cell region.
Optionally, in the super junction trench gate MOSFET, a distance from a center of a trench gate structure in the cell region near the termination region to a center of a trench gate in the termination region near the cell region is greater than a distance between centers of two adjacent trench gate structures in the cell region.
Optionally, in the super junction trench gate MOSFET, the super junction trench gate MOSFET further includes: and a plurality of trenches in the epitaxial layer of the cell region and in the epitaxial layer of the termination region.
Optionally, in the super junction trench gate MOSFET, the trench gate structure includes: the gate dielectric layer covers the side wall and the bottom wall of the groove, and the polysilicon gate electrode covers the gate dielectric layer and fills the residual space of the groove.
The technical scheme of the application at least comprises the following advantages:
according to the method, the body region is formed in the epitaxial layer between the trench gate structures of the cell region and the terminal region through global ion implantation, the depth of the trench gate structure is larger than the implantation depth of the body region, and then a plurality of column regions are formed at the bottom of the first heavily doped region of the cell region and the bottom of the trench gate structure of the terminal region, so that the body region of the terminal region is isolated into an independent floating body block by the trench gate structure and the column regions, the voltage resistance of the terminal region is improved, the electrical property of a device is improved, the photomask corresponding to the ion implantation of the body region is reduced, the preparation process is simplified, and the manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method of fabricating a superjunction trench-gate MOSFET according to an embodiment of the present invention;
FIGS. 2-4 are schematic views of a semiconductor structure at various process steps in the fabrication of a super junction trench gate MOSFET in accordance with an embodiment of the present invention;
wherein reference numerals are as follows:
101-substrate, 102-epitaxial layer, 103-column region, 104-gate dielectric layer, 105-polysilicon gate, 106-body region, 107-second heavily doped region, 108-first heavily doped region, 109-second conductive plug, 110-first conductive plug.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
The embodiment of the application provides a preparation method of a super-junction trench gate MOSFET, referring to FIG. 1, FIG. 1 is a flowchart of the preparation method of the super-junction trench gate MOSFET, and the preparation method of the super-junction trench gate MOSFET comprises the following steps:
referring to fig. 2-4, fig. 2-4 are schematic views of a semiconductor structure at various process steps in the preparation of a super junction trench gate MOSFET according to an embodiment of the invention.
First, step S10 is performed: as shown in fig. 2, a substrate 101 is provided, the substrate 101 including a cell region and a terminal region.
The substrate 101 may be N-type highly doped or P-type highly doped.
In this embodiment, an N-type superjunction-trench gate is taken as an example, so the substrate 101 is a highly doped N-type substrate.
Then, step S20 is performed: as shown in fig. 2, an epitaxial layer 102 is formed, and the epitaxial layer 102 covers the surface of the substrate 101.
The epitaxial layer 102 may also be referred to as a drift region, and in this embodiment, the doped ions in the epitaxial layer 102 are N-type. The doping concentration of ions in the epitaxial layer 102 is 5E15atoms/cm 3 ～1E17atoms/cm 3 。
Next, step S30 is performed: as shown in fig. 2, a plurality of trench gate structures are formed spaced apart from each other, the trench gate structures being located in the epitaxial layer 102 of the cell region and in the epitaxial layer 102 of the termination region.
Specifically, the step of forming a plurality of trench gate structures spaced apart from one another includes:
step S30.1: etching a portion of the thickness of the epitaxial layer 102 to form a plurality of trenches in the epitaxial layer 102 of the cell region and in the epitaxial layer 102 of the termination region;
step S30.2: forming a gate dielectric layer 104, wherein the gate dielectric layer 104 covers the side wall and the bottom wall of the groove;
step S30.3: a polysilicon gate 105 is formed, the polysilicon gate 105 covering the gate dielectric layer 104 and filling the remaining space of the trench.
Preferably, a distance (L) from a center of the trench gate structure in the cell region closest to the terminal region to a center of the trench gate in the terminal region closest to the cell region 2 ) Is greater than the distance (L) between the centers of two adjacent trench gate structures in the primordial region 1 )。
Further, the width W of the trench gate structure of the termination region in the transverse direction T The width of the trench gate structure in the transverse direction is larger than or equal to that of the cell region.
In another embodiment, the width W of the trench gate structure of the termination region in the lateral direction T The width of the trench gate structure in the transverse direction is smaller than that of the cell region.
Next, step S40 is performed: as shown in fig. 3, the epitaxial layer 102 is subjected to a one-time global ion implantation to form a body region 106 in the epitaxial layer 102 between the cell region and the trench gate structure of the termination region.
Preferably, the depth of the trench gate structure is greater than the implantation depth of the body region 106.
In this embodiment, the depth of the polysilicon gate 105 is greater than the implantation depth of the body region 106.
In this embodiment, the body region 106 is a P-type body region.
Next, step S50 is performed: as shown in fig. 3, the epitaxial layer 102 is subjected to a selective ion implantation to form a plurality of first heavily doped regions 108 in the body region 106 of the cell region.
In this embodiment, the first heavily doped region 108 is an N-type heavily doped region.
It is noted that no selective ion implantation to form the first heavily doped region is performed in the body region 106 between the two trench gate structures at the interface of the cell region and the termination region.
Step S60: as shown in fig. 3, the epitaxial layer 102 is selectively ion-implanted to form a plurality of column regions 103 at the bottom of the first heavily doped region 108 of the cell region and at the bottom of the trench gate structure of the termination region.
Preferably, the column region 103 of the termination region penetrates through the trench gate structure of the termination region, and an overlapping region exists between the column region 103 of the termination region and the trench gate structure.
In this embodiment, the pillar region 103 is a P-type pillar region.
Wherein the column region 103 is used to assist the depletion of the N-type epitaxial layer 102 (drift region).
It is noted that a selective ion implantation is performed in the body region 106 between the two trench gate structures at the interface of the cell region and the termination region to form the column region 103.
In this embodiment, the width W of the trench gate structure of the termination region in the lateral direction T A width W of the column region 103 in the lateral direction smaller than the terminal region P 。
In another embodiment, the width W of the trench gate structure of the termination region in the lateral direction T A width W of the column region 103 in the lateral direction greater than or equal to the termination region P 。
Step S70: as shown in fig. 4, the first heavily doped region 108 of the cell region and a portion of the thickness of the column region 103 are etched to form a plurality of first contact holes, and simultaneously, the top ends of the trench gate structures of the cell region are etched to form a plurality of second contact holes.
It is noted that etching of the pillar region 103 with a partial thickness is performed in the body region 106 between the two trench gate structures at the boundary position of the cell region and the terminal region to form a corresponding first contact hole.
Step S80: as shown in fig. 4, ion implantation is performed on the contact hole bottom to form a plurality of second heavily doped regions 107 between the first heavily doped regions 108 and the column regions 103.
It is noted that ion implantation is performed to form a corresponding second heavily doped region 107 at the bottom of the first contact hole between the two trench gate structures at the boundary position of the cell region and the terminal region.
In this embodiment, the second heavily doped region 107 is a P-type heavily doped region.
Step S90: as shown in fig. 4, a first conductive plug 110 and a second conductive plug 109 are formed, the first conductive plug 110 filling the first contact hole, and the second conductive plug 109 filling the second contact hole.
The step of forming the first conductive plugs 110 and the second conductive plugs 109 may specifically include:
forming a first metal layer, wherein the first metal layer covers the side wall and the bottom wall of the first contact hole and the side wall and the bottom wall of the second contact hole;
forming a second metal layer, wherein the second metal layer covers the first metal layer;
performing a thermal annealing process to alloy the first/second metal layers with the epitaxial layer 102 and with the polysilicon gate 105;
forming a third metal layer which covers the second metal layer and fills the residual spaces of the first contact hole and the second contact hole;
and removing the first metal layer, the second metal layer and the third metal layer beyond the first contact hole, the second contact hole and the surface of the epitaxial layer to obtain the first conductive plug 110 in the first contact hole and obtain the second conductive plug 109 in the second contact hole.
The first conductive plug 110 is used to lead out the source (heavily doped region) and the body region, and the second conductive plug 109 is used to lead out the polysilicon gate 105.
Preferably, the first metal layer is a titanium layer; the second metal layer is a titanium nitride layer; the third metal layer is a tungsten layer.
Based on the same inventive concept, the embodiments of the present application further provide a super junction trench gate MOSFET, as shown in fig. 4, including:
a substrate 101, the substrate 101 comprising a cell region and a termination region;
an epitaxial layer 102, wherein the epitaxial layer 102 covers the surface of the substrate 101;
a plurality of spaced trench gate structures located in the epitaxial layer 102 of the cell region and in the epitaxial layer 102 of the termination region;
the body region 106 is located in the epitaxial layer 102 between the trench gate structures, the body region 106 is obtained by performing global ion implantation on the epitaxial layer 102, and the depth of the trench gate structures is greater than the implantation depth of the body region 106;
a plurality of first heavily doped regions 108, the first heavily doped regions 108 being located in the body region 106 of the cell region;
a plurality of column regions 103, wherein the column regions 103 are located at the bottom of the first heavily doped region 108 of the cell region and at the bottom of the trench gate structure of the termination region;
a plurality of second heavily doped regions 107, wherein the second heavily doped regions 107 are located at the bottom of the first heavily doped regions 108 of the cell region; the method comprises the steps of,
a plurality of first conductive plugs 110 and a plurality of second conductive plugs 109, the first conductive plugs 110 being located in the first heavily doped regions 108 and a portion of the thickness of the column regions 103 of the cell region, the second conductive plugs 109 being located at the top of the trench gate structure of the cell region.
Preferably, a distance (L) from a center of the trench gate structure in the cell region closest to the terminal region to a center of the trench gate in the terminal region closest to the cell region 2 ) Is greater than the distance (L) between the centers of two adjacent trench gate structures in the primordial region 1 )。
Preferably, the super junction trench gate MOSFET further includes: a plurality of trenches are located in the epitaxial layer 102 of the cell region and in the epitaxial layer 102 of the termination region.
Further, the trench gate structure includes: the gate dielectric layer 104 and the polysilicon gate 105, wherein the gate dielectric layer 104 covers the side wall and the bottom wall of the trench, and the polysilicon gate 105 covers the gate dielectric layer 104 and fills the residual space of the trench.
In the application, a plurality of spaced trench gate structures are introduced into a cell region and a terminal region, and a body region 106 is formed in an epitaxial layer 102 between the trench gate structures of the cell region and the terminal region through global ion implantation, the depth of the trench gate structure is larger than the implantation depth of the body region 106, then a plurality of column regions 103 are formed at the bottom of a first heavily doped region 108 of the cell region and the bottom of the trench gate structure of the terminal region, so that the body region 106 of the terminal region is isolated into an independent floating body block by the trench gate structure and the column regions 103, the voltage resistance of the terminal region is improved, the electrical performance of a device is improved, a photomask corresponding to the body region ion implantation is reduced, the preparation process is simplified, and the manufacturing cost is reduced.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (9)
1. The preparation method of the super-junction trench gate MOSFET is characterized by comprising the following steps of:
providing a substrate, wherein the substrate comprises a cell region and a terminal region;
forming an epitaxial layer, wherein the epitaxial layer covers the surface of the substrate;
forming a plurality of trench gate structures which are spaced from each other, wherein the trench gate structures are positioned in the epitaxial layer of the primordial cell region and the epitaxial layer of the terminal region;
performing global ion implantation on the epitaxial layer to form a body region in the epitaxial layer between the trench gate structures, wherein the depth of the trench gate structures is greater than the implantation depth of the body region;
performing selective ion implantation on the epitaxial layer to form a plurality of first heavily doped regions in the body region of the cell region;
performing selective ion implantation on the epitaxial layer to form a plurality of column regions at the bottom of the first heavily doped region of the cell region and the bottom of the trench gate structure of the terminal region, wherein an overlapping region exists between the column region of the terminal region and the trench gate structure;
etching the first heavily doped region of the cell region and the column region with partial thickness to form a plurality of first contact holes, and simultaneously, etching the top end of the trench gate structure of the cell region to form a plurality of second contact holes;
ion implantation is carried out on the bottom of the contact hole so as to form a plurality of second heavily doped regions between the first heavily doped region and the column region; the method comprises the steps of,
and forming a first conductive plug and a second conductive plug, wherein the first conductive plug fills the first contact hole, and the second conductive plug fills the second contact hole.
2. The method of fabricating a superjunction trench-gate MOSFET of claim 1, wherein a distance from a center of a trench-gate structure in the cell region near the termination region to a center of a trench-gate in the termination region near the cell region is greater than a distance between centers of two adjacent trench-gate structures in the cell region.
3. The method of fabricating a superjunction trench-gate MOSFET of claim 1, wherein the step of forming a plurality of spaced apart trench-gate structures comprises:
etching a part of the epitaxial layer to form a plurality of grooves in the epitaxial layer of the cell region and the epitaxial layer of the terminal region;
forming a gate dielectric layer, wherein the gate dielectric layer covers the side wall and the bottom wall of the groove;
and forming a polysilicon gate, wherein the polysilicon gate covers the gate dielectric layer and fills the residual space of the trench.
4. The method of fabricating a superjunction trench-gate MOSFET of claim 1, wherein the step of forming the first conductive plug and the second conductive plug comprises:
forming a first metal layer, wherein the first metal layer covers the side wall and the bottom wall of the first contact hole and the side wall and the bottom wall of the second contact hole;
forming a second metal layer, wherein the second metal layer covers the first metal layer;
performing a thermal annealing process;
forming a third metal layer which covers the second metal layer and fills the residual spaces of the first contact hole and the second contact hole;
and removing the first metal layer, the second metal layer and the third metal layer which exceed the surfaces of the first contact hole, the second contact hole and the epitaxial layer to obtain the first conductive plug in the first contact hole and obtain the second conductive plug in the second contact hole.
5. The method of manufacturing a superjunction trench-gate MOSFET of claim 4, wherein the first metal layer is a titanium layer; the second metal layer is a titanium nitride layer; the third metal layer is a tungsten layer.
6. A superjunction trench gate MOSFET comprising:
a substrate comprising a cell region and a termination region;
an epitaxial layer, wherein the epitaxial layer covers the surface of the substrate;
a plurality of trench gate structures spaced apart from one another, the trench gate structures being located in the epitaxial layer of the cell region and in the epitaxial layer of the termination region;
the body region is positioned in the epitaxial layer between the trench gate structures and is obtained by carrying out global ion implantation on the epitaxial layer, wherein the depth of the trench gate structure is larger than the implantation depth of the body region;
a plurality of first heavily doped regions located in the body region of the primordial region;
the column regions are positioned at the bottoms of the first heavily doped regions of the primordial cell regions and the bottoms of the trench gate structures of the terminal regions;
the second heavily doped regions are positioned at the bottoms of the first heavily doped regions of the primordial cell regions; the method comprises the steps of,
a plurality of first conductive plugs and a plurality of second conductive plugs, wherein the first conductive plugs are positioned in the first heavily doped region of the cell region and the column region with partial thickness, and the second conductive plugs are positioned at the top end of the trench gate structure of the cell region.
7. The superjunction trench-gate MOSFET of claim 6, wherein a distance from a center of a trench-gate structure in the cell region near the termination region to a center of a trench-gate in the termination region near the cell region is greater than a distance between centers of two adjacent trench-gate structures in the cell region.
8. The superjunction trench-gate MOSFET of claim 6, further comprising: and a plurality of trenches in the epitaxial layer of the cell region and in the epitaxial layer of the termination region.
9. The superjunction trench-gate MOSFET of claim 8, wherein the trench-gate structure comprises: the gate dielectric layer covers the side wall and the bottom wall of the groove, and the polysilicon gate electrode covers the gate dielectric layer and fills the residual space of the groove.
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