CN116314298A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN116314298A CN116314298A CN202310312017.XA CN202310312017A CN116314298A CN 116314298 A CN116314298 A CN 116314298A CN 202310312017 A CN202310312017 A CN 202310312017A CN 116314298 A CN116314298 A CN 116314298A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- conductive layer
- top surface
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 230000004888 barrier function Effects 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000011049 filling Methods 0.000 claims description 6
- 230000001965 increasing effect Effects 0.000 abstract description 11
- 230000006870 function Effects 0.000 description 61
- 230000008569 process Effects 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 238000002161 passivation Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 239000000306 component Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000737 periodic effect Effects 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- -1 phosphorus ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000032750 Device leakage Diseases 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method of forming the same, the semiconductor structure comprising: a gate trench formed on a substrate; a gate dielectric layer, a barrier layer and a conductive layer which are sequentially formed in the gate trench; the conductive layer comprises a first conductive layer and a second conductive layer, a first gap is formed between the edge of the first conductive layer and the inner wall of the gate trench, a second gap is formed between the edge of the second conductive layer and the inner wall of the gate trench, and the second gap is larger than the first gap; the dielectric layer covers the surface of the second conductive layer and fills the second gap. The semiconductor structure is provided by the disclosure, the lateral dimension between the conducting layer and the inner wall of the grid electrode groove in the semiconductor structure is increased, and the dielectric layer is filled between the conducting layer and the inner wall of the grid electrode groove, so that the insulativity between the conducting layer and the drain electrode is improved, the gate induced drain leakage current is reduced, the power consumption of a device is reduced, the reliability of the device is improved, and the yield of the device is further improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method of forming the same.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) has been widely used in smart devices such as mobile phones and tablet computers due to its small size, fast data transmission speed, and high integration level. The word line structure is used as a core component of the dynamic random access memory and is mainly used for controlling the on and off of the transistor. The gate induced leakage current generated when the transistor is in the off or standby state constrains the size of the transistor and causes an increase in the static power of the transistor, reducing the reliability of the device.
At present, the thickness of a gate dielectric layer is often increased to reduce the gate-induced drain leakage current, but the method leads to the increase of the device turn-on voltage and power consumption, which limits the performance of the semiconductor device.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure aims to overcome the shortcomings of the prior art, and provides a semiconductor structure and a forming method thereof, which can effectively improve the phenomenon of gate induced drain leakage current in a semiconductor device, so as to improve the reliability of the device and facilitate the improvement of the overall performance of the device.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:
a substrate comprising a source region, a drain region, and a gate trench between the source region and the drain region;
the conductive layer comprises a first conductive layer and a second conductive layer which are sequentially stacked from bottom to top along the depth direction of the grid groove, a first gap is formed between the edge of the first conductive layer and the inner wall of the grid groove in the direction parallel to the substrate, a second gap is formed between the edge of the second conductive layer and the inner wall of the grid groove, and the second gap is larger than the first gap;
the grid dielectric layer covers the inner wall of the grid groove and is at least positioned between the first conductive layer and the inner wall of the grid groove;
a barrier layer located between the gate dielectric layer and the first conductive layer, the barrier layer filling the first gap;
and the dielectric layer covers the surface of the second conductive layer and fills the second gap.
In some embodiments of the present disclosure, based on the foregoing aspect, the semiconductor structure further includes a work function adjusting layer, the work function adjusting layer being located on a surface of the dielectric layer.
In some embodiments of the present disclosure, based on the foregoing, a top surface of the gate dielectric layer is flush with a top surface of the second conductive layer.
In some embodiments of the disclosure, based on the foregoing scheme, a top surface of the dielectric layer is higher than a top surface of the gate dielectric layer, and the dielectric layer covers surfaces of the second conductive layer and the barrier layer.
In some embodiments of the disclosure, based on the foregoing solution, the top surface of the dielectric layer is higher than the top surface of the gate dielectric layer, and the dielectric layer covers the surface of the structure formed by the gate dielectric layer, the barrier layer, and the conductive layer together.
According to another aspect of the present disclosure, there is provided a method of forming a semiconductor structure, the method comprising:
providing a substrate, forming a source region, a drain region and a gate trench between the source region and the drain region on the substrate;
forming a gate dielectric layer on the inner wall of the gate trench;
forming a barrier layer on the gate dielectric layer;
Forming a conductive layer on the barrier layer, wherein the top surface of the conductive layer is higher than the top surface of the barrier layer, the conductive layer higher than the top surface of the barrier layer is a second conductive layer, the conductive layer lower than the top surface of the barrier layer is a first conductive layer, a first gap is formed between the edge of the first conductive layer and the inner wall of the gate trench, and a second gap is formed between the edge of the second conductive layer and the inner wall of the gate trench;
removing a portion of the second conductive layer in a direction parallel to the substrate so that the second gap is larger than the first gap;
and forming a dielectric layer on the second conductive layer, and enabling the dielectric layer to fill the second gap.
In some embodiments of the present disclosure, after forming the dielectric layer, based on the foregoing scheme, the method further includes:
and doping part of the dielectric layer from the top surface of the dielectric layer to the direction of the substrate so as to form a work function adjusting layer in the dielectric layer.
In some embodiments of the present disclosure, based on the foregoing scheme, a work function adjusting layer is formed within the dielectric layer, the method comprising:
and adjusting the doping concentration of the dielectric layer to adjust the work function of the work function adjusting layer.
In some embodiments of the present disclosure, based on the foregoing scheme, a dielectric layer is formed, the method comprising:
and enabling the dielectric layer to cover the surfaces of the second conductive layer and the barrier layer, wherein the top surface of the dielectric layer is higher than the top surface of the gate dielectric layer.
In some embodiments of the present disclosure, based on the foregoing scheme, a dielectric layer is formed, the method comprising:
and enabling the dielectric layer to cover the surface of the structure formed by the gate dielectric layer, the barrier layer and the conductive layer together, wherein the top surface of the dielectric layer is higher than the top surface of the gate dielectric layer.
According to the semiconductor structure, the lateral dimension between the conducting layer and the inner wall of the grid electrode groove in the semiconductor structure is increased, and the dielectric layer is filled between the conducting layer and the inner wall of the grid electrode groove, so that the insulativity between the conducting layer and the drain electrode is improved, the gate-induced drain leakage current in the semiconductor structure is reduced, the power consumption is reduced, the reliability of a device is further improved, and the yield of a product is improved; on the other hand, the semiconductor provided by the disclosure has a simple structure, a film layer in a process is not required to be added to achieve the purpose of improving the formation of a device, and the increase of the transverse dimension between the conductive layer and the inner wall of the grid electrode groove does not affect the conductive function of the structure;
Another aspect of the present disclosure provides a method for forming a semiconductor structure, which increases a distance between a sidewall of a conductive layer and a drain electrode by increasing a lateral dimension between an edge of the conductive layer and an inner wall of a gate trench, and fills a dielectric layer between the conductive layer and the inner wall of the gate trench, thereby improving insulation between the conductive layer and the drain electrode, and further reducing gate-induced drain leakage current, reducing power consumption, increasing reliability of a device, and improving yield of a product.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a flow chart illustrating a method of forming a semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 2 is a schematic structural view of a substrate in an exemplary embodiment of the present disclosure.
Fig. 3 is a partial schematic structure diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.
Fig. 4-6 are schematic structural diagrams in a semiconductor structure forming step in an exemplary embodiment of the present disclosure.
Fig. 7-9 are schematic structural diagrams in another semiconductor structure forming step in an exemplary embodiment of the present disclosure.
Wherein reference numerals are as follows:
100: a substrate; 101: a source region; 102: a drain region; 103: a gate trench; 200: a gate dielectric layer; 300: a barrier layer; 400: a conductive layer; 410: a first conductive layer; 420: a second conductive layer; 500: a dielectric layer; 600: a work function adjusting layer; 700: a passivation layer; a1: a first gap; a2: and a second gap.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.
In the related art, a memory device mainly includes a substrate, a word line structure, a bit line structure, a storage capacitor and a transistor, wherein the bit line structure is connected with a drain electrode on the substrate, the word line structure controls the on or off of the transistor, and the storage capacitor is communicated with a source electrode of the transistor.
The word line structure mainly comprises a gate oxide layer formed on the inner wall of the gate trench, an interface layer and a conductive layer filled in the gate trench. The process of forming the word line structure generally includes the steps of: slotting the substrate to form a gate trench on the substrate; filling a gate oxide layer, an interface layer and a conductive layer in the gate trench; an insulating layer filling the gate trench is formed on the conductive layer. However, due to the size limitation of the word line structure, the distance between the conductive layer of the word line structure and the drain electrode on the substrate is relatively short, which results in a large Gate-induced drain leakage current (Gate-induced Drain Leakage, GIDL) generated by the word line structure during operation, which can seriously affect the performance and reliability of the device.
Accordingly, the present disclosure provides a semiconductor structure to reduce gate induced drain leakage current in a word line structure in a device, and to improve the reliability of the device.
Embodiments of the present disclosure provide a semiconductor structure, as shown in fig. 2-4, comprising: substrate 100, conductive layer 400, gate dielectric layer 200, barrier layer 300, and dielectric layer 500.
The substrate 100 includes a source region 101, a drain region 102, and a gate trench 103 between the source region 101 and the drain region 102; the conductive layer 400 includes a first conductive layer 410 and a second conductive layer 420 sequentially stacked from bottom to top along a depth direction of the gate trench 103, a first gap A1 is provided between an edge of the first conductive layer 410 and an inner wall of the gate trench 103 in a direction parallel to the substrate 100, a second gap A2 is provided between an edge of the second conductive layer 420 and the inner wall of the gate trench 103, and the second gap A2 is greater than the first gap A1; the gate dielectric layer 200 covers the inner wall of the gate trench 103 and is at least located between the first conductive layer 410 and the inner wall of the gate trench 103; the barrier layer 300 is located between the gate dielectric layer 200 and the first conductive layer 410, and the barrier layer 300 fills the first gap A1; the dielectric layer 500 covers the surface of the second conductive layer 420 and fills the second gap A2.
The semiconductor structure provided by the present disclosure includes a conductive layer, the conductive layer includes a first conductive layer 410 and a second conductive layer 420, which have a first gap A1 and a second gap A2 with an inner wall of the gate trench 103, respectively, the second gap A2 is larger than the first gap A1, and a dielectric layer 500 is formed on the conductive layer 400, and the dielectric layer 500 fills the second gap A2. The lateral dimension between the conductive layer 400 and the inner wall of the gate trench 103 is increased, and the dielectric layer 500 is filled in the second gap A2, so that the insulativity between the conductive layer 400 and the drain is increased, the gate-induced drain leakage current is further reduced, and the limitation of the gate-induced drain leakage current on the structure and the dimension of the device is further reduced, so that the reliability of the device is increased, and the yield of the device is improved.
The following describes a semiconductor structure in an embodiment of the present disclosure in detail with reference to the accompanying drawings:
as shown in fig. 2, in an embodiment provided by the present disclosure, a semiconductor structure includes a substrate 100, the substrate 100 including a source region 101, a drain region 102, and a gate trench 103 between the source region 101 and the drain region 102.
The material of the substrate 100 may be silicon or other semiconductor materials, and the substrate 100 may be circular, triangular or square, and the shape and material of the substrate 100 are not particularly limited in this disclosure. Other structures such as shallow trench isolation structures and well regions may be formed on the substrate 100, and structures not shown in the drawings provided in the present disclosure may be adjusted or designed according to actual manufacturing processes of the semiconductor, which is not particularly limited in the present disclosure.
The substrate 100 may be of a P-type, which may include source and drain regions 101 and 102 disposed at intervals, and the source and drain regions may be formed by doping the source and drain regions 101 and 102. For example, the source region 101 and the drain region 102 may be n-doped so that the source region 101 and the drain region 102 form an n-type semiconductor, and the doping material may be an element in the V main group in the periodic table, for example, the doping material may be phosphorus, or may be a material of other elements, which is not specifically described herein. Alternatively, the substrate 100 may be N-type, and the doping of the corresponding source region 101 and drain region 102 may be adaptively adjusted, and the formation method is similar to that of P-type doping, which is not described herein.
In the embodiment provided in the present disclosure, the source region 101 and the drain region 102 may be implanted with phosphorus ions by using an ion implantation method, and of course, the source region 101 and/or the drain region 102 may be doped by using other processes, which is not limited herein. It should be noted that, between the source region 101 and the drain region 102, a channel region may be formed, where the channel region may have a gate trench 103, and a buried word line structure may be formed in the gate trench 103, where the word line structure is used as a gate of a transistor, and may control the transistor to be turned on or off.
In the embodiments provided in the present disclosure, the sidewall of the gate trench 103 may extend in a direction perpendicular to the substrate 100, the bottom of the gate trench 103 may be arc-shaped, the arc center thereof may be located in the gate trench 103, the sidewall of the gate trench 103 may be connected with both ends of the arc shape, the gate trench 103 may have a symmetry axis in the direction perpendicular to the substrate 100, and the gate trench 103 may be symmetrical along the symmetry axis thereof. Of course, due to the limitation of the process, the gate trench 103 may have a non-axisymmetric structure and may be adjusted according to the actual situation of the process.
The depth of the gate trench 103 may be 100nm to 300nm, for example, may be 100nm, 150nm, 200nm, 250nm, or 300nm; the width of the gate trench 103 may be 10nm to 50nm, for example, 10nm, 20nm, 30nm, 40nm, or 50nm, and the width of the gate trench 103 may be a lateral dimension between sidewalls of the gate trench 103 in a direction parallel to the substrate 100. Of course, the gate trench 103 may have other different dimensions, and the dimensions of the gate trench 103 may be tailored according to the design requirements of the semiconductor device, which is not particularly limited herein.
In the embodiment provided in the present disclosure, as shown in fig. 3, in conjunction with fig. 4, the semiconductor structure includes a gate dielectric layer 200, a barrier layer 300, and a conductive layer 400 sequentially formed within a gate trench 103, and a dielectric layer 500 on the conductive layer 400.
Wherein, the gate dielectric layer 200, the barrier layer 300 and the conductive layer 400 are sequentially formed in the gate trench 103, the gate dielectric layer 200 may be a film layer attached to the side wall and the bottom wall of the gate trench 103, and the gate dielectric layer 200 covers the inner wall of the gate trench 103; a barrier layer 300 is formed on a side of the gate dielectric layer 200 facing away from the substrate 100; a conductive layer 400 is formed on a side of the barrier layer 300 facing away from the substrate 100, the conductive layer 400 filling the gate trench 103.
The gate dielectric layer 200 may be an insulating layer, for example, the gate dielectric layer 200 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or other high-K dielectric materials, or may be a combination of the above materials, and the thickness of the gate dielectric layer 200 may be 1nm to 7nm, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, or 7nm, or of course, may be other thicknesses, which are not specifically mentioned herein.
A barrier layer 300 is disposed between the gate dielectric layer 200 and the conductive layer 400, the barrier layer 300 wraps the bottom wall and a portion of the sidewall of the conductive layer 400, and is attached to the gate dielectric layer 200, and the barrier layer 300 is used for isolating the conductive layer 400 from the gate dielectric layer 200 and preventing the conductive layer 400 from diffusing in the process. The barrier layer 300 may be a conductive material such as titanium nitride, and the barrier layer 300 may be a part of a conductive structure in a semiconductor structure, and has a conductive effect. The thickness of the barrier layer 300 may be 0.5nm to 2nm, for example, 0.5nm, 1nm, 1.5nm or 2nm, although other thicknesses are also possible.
The conductive layer 400 may include a first conductive layer 410 and a second conductive layer 420, and the top surface of the barrier layer 300 is defined as a boundary, the conductive layer higher than the top surface of the barrier layer 300 is the second conductive layer 420, and the conductive layer lower than the top surface of the barrier layer 300 is the first conductive layer 410, i.e. the conductive layer 400 includes the first conductive layer 410 and the second conductive layer 420 stacked sequentially from bottom to top along the depth direction of the gate trench 103. In a direction parallel to the substrate 100, a first gap A1 is formed between an edge of the first conductive layer 410 and an inner wall of the gate trench 103, and a second gap A2 is formed between the second conductive layer 420 and the inner wall of the gate trench 103, wherein the second gap A2 is larger than the first gap A1. In the present disclosure, the gate dielectric layer 200 is at least between the first conductive layer 410 and the inner wall of the gate trench 103, the barrier layer 300 is between the gate dielectric layer 200 and the first conductive layer 410, and the barrier layer 300 fills the first gap A1.
Wherein the second conductive layer 420 may be formed by etching a portion of the conductive layer. Specifically, after the conductive layer 400 is formed on the barrier layer 300, the conductive layer 400 is etched in a direction from the top surface thereof to the substrate 100, that is, a portion of the conductive layer 400 near the top surface is etched to reduce the size of the upper end of the conductive layer 400 in a direction parallel to the substrate 100, thereby forming the second conductive layer 420.
In the present disclosure, the first conductive layer 410 and the second conductive layer 420 may be the same conductive layer, only to distinguish the process forming steps, the conductive layer 400 is divided into the first conductive layer 410 and the second conductive layer 420, and in the present disclosure, the first conductive layer 410 and the second conductive layer 420 may be two portions of the same film layer; or the first conductive layer 410 and the second conductive layer 420 may be two different conductive layers, and after the second conductive layer 420 is formed on the first conductive layer 410, the first conductive layer 410 and the second conductive layer 420 form the conductive layer 400, and the structure of the conductive layer 400 may be adjusted according to actual process requirements.
The second gap A2 is larger than the first gap A1, i.e. the orthographic projection of the maximum width of the second conductive layer 420 on the substrate 100 is located within the orthographic projection of the maximum width of the first conductive layer 410 on the substrate 100. Specifically, the area of the orthographic projection of the maximum width of the second conductive layer 420 onto the substrate 100 is at least three-fifths of the area of the orthographic projection of the maximum width of the first conductive layer 410 onto the substrate 100. In addition, the second conductive layer 420 may be symmetrical along a central axis of the gate trench 103 (the central axis is perpendicular to the substrate 100), when the second conductive layer 420 is formed, the conductive layer 400 may be symmetrically etched along the central axis of the gate trench 103, so that etched portions of the conductive layer 400 are symmetrically distributed on two sides of the central axis of the gate trench 103, so that the second conductive layer 420 has a symmetrical structure, for example, the conductive layer 400 having a width of one fifth may be removed on two sides of the top of the conductive layer 400 along the symmetry axis of the gate trench 103, so as to form the second conductive layer 420, and an orthographic projection of a maximum width of the second conductive layer 420 on the substrate 100 is three fifths of an orthographic projection of the maximum width of the second conductive layer 420 on the substrate 100. Of course, the conductive layer 400 may also be asymmetrically etched, and the specific structure of the conductive layer 400 may be adaptively adjusted according to the process requirements.
In a specific embodiment, the second gap A2 may be 6nm to 10nm, for example, may be 6nm, 7nm, 8nm, 9nm or 10nm; the first gap A1 may be 4nm to 7nm, for example, may be 4nm, 5nm, 6nm or 7nm, and the second gap A2 needs to be ensured to be larger than the first gap A1.
The semiconductor structure provided by the present disclosure further includes a dielectric layer 500, where the dielectric layer 500 is formed on the top surface of the conductive layer 400. Specifically, the dielectric layer 500 covers the second conductive layer 420 and fills the second gap A2. The material of the dielectric layer 500 may be silicon oxide, silicon nitride or silicon oxynitride, etc., preferably, the dielectric layer 500 is an undoped silicon dioxide layer; the thickness thereof may be 10nm to 20nm, for example, 10nm, 13nm, 15nm, 17nm, 19nm or 20nm. The material and thickness of the dielectric layer 500 may be adjusted according to the actual process, and are not particularly limited herein. The dielectric layer 500 may be formed by atomic layer deposition, chemical vapor deposition, or the like.
The materials of the gate dielectric layer 200 and the dielectric layer 500 may be the same, for example, the gate dielectric layer 200 and the dielectric layer 500 may be made of undoped silicon dioxide, further, in order to distinguish the gate dielectric layer 200 and the dielectric layer 500, the gate dielectric layer 200 may be made of silicon dioxide with a density greater than that of the dielectric layer 500, for example, after the gate dielectric layer 200 is formed, the gate dielectric layer 200 may be made denser by a method such as thermal annealing.
In the embodiment provided in the present disclosure, the top surface of the gate dielectric layer 200 is flush with the top surface of the second conductive layer 420, and as illustrated in fig. 4-6, the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, and the dielectric layer 500 covers the surfaces of the second conductive layer 420 and the barrier layer 300; or as shown in fig. 7-9, the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, and the dielectric layer 500 covers the surface of the structure formed by the gate dielectric layer 200, the barrier layer 300 and the conductive layer 400. The adaptive deformation structure for the semiconductor structure in the above two embodiments, which are shown as examples only, is also applicable to the present disclosure.
As shown in fig. 5 and 8, the semiconductor structure provided in the present disclosure further includes a work function adjusting layer 600, where the work function adjusting layer 600 is located on the surface of the dielectric layer 500. The work function adjusting layer 600 may be formed by forming a film layer to be doped on the dielectric layer 500, and forming the work function adjusting layer 600 by doping the film layer to be doped; alternatively, the work function adjusting layer 600 is a portion of the dielectric layer 500 formed by a doping process, and the work function adjusting layer 600 is a portion of the dielectric layer 500 away from the substrate 100.
For the first embodiment, the film to be doped may be made of the same material as the dielectric layer 500, for example, the film to be doped may be an undoped silicon dioxide film, and the film to be doped is doped from top to bottom along the depth direction of the gate trench 103 to form the work function adjusting layer 600. For the second embodiment described above, when forming the dielectric layer 500, a portion of the total dielectric layer may be doped downward and upward in the depth direction of the gate trench 103 according to the sum of the thicknesses of the preset dielectric layer 500 and the work function adjusting layer 600 as the formation thickness of the total dielectric layer when the work function adjusting layer 600 is not formed, so as to form the work function adjusting layer 600 of the preset thickness on the total dielectric layer. The two embodiments may be performed alone, or may be performed in combination, or the work function adjusting layer 600 may be formed by both of the modifications and combinations thereof, which are not particularly limited herein.
It should be noted that, due to the limitation of the doping process, the doping concentration or the doping thickness of the work function adjusting layer 600 along the depth direction of the gate trench 103 may be the same or different, for example, the bottom surface of the work function adjusting layer 600 is formed to be in contact with the top surface of the dielectric layer 500, and both surfaces may be completely parallel to the top surface direction of the substrate 100; or the work function adjusting layer 600 is formed to be partially in contact with the top surface of the gate dielectric layer 200. The semiconductor structure of the present disclosure may further control the magnitude of the work function by adjusting the work function adjusting layer 600, thereby controlling the magnitude of the gate-induced drain leakage current.
The work function adjusting layer 600 may be an N-type doped film or a P-type doped film. When the work function adjusting layer 600 is an N-type doped film, the doping ions may be elements of main group v of the periodic table, for example, phosphorus and the like; when the work function adjusting layer 600 is a P-type doped film, the dopant ions may be elements of main group iii of the periodic table, for example, boron. Of course, work function tuning layer 600 may be other doped structures. The thickness of the work function adjusting layer 600 may be 10nm to 20nm, for example, 10nm, 12 nm, 14nm, 16nm, 18nm, 20nm, or the like.
The ion doping concentration of the work function adjusting layer 600 can be adjusted, and the work function of the work function adjusting layer 600 can be adjusted by adjusting the doping concentration, so that the work function of the work function adjusting layer 600 is reduced, tunneling electrons in the work function adjusting layer 600 are reduced, and then the gate-induced drain leakage current is reduced in a preset doping concentration range; on the other hand, the work function adjusting layer 600 is located on the surface of the dielectric layer, so that a potential barrier can be increased, and parasitic capacitance of the device can be reduced, so that performance of the device can be improved.
As shown in fig. 6 and 9, the semiconductor structure further includes a passivation layer 700, the passivation layer 700 is located on the surface of the work function adjusting layer 600, and the passivation layer 700 fills between the inner walls of the gate trench 103, and the top surface of the passivation layer 700 may be flush with the top surface of the gate trench 103. In the embodiments provided by the present disclosure, the resistivity of the passivation layer 700 is less than or equal to the resistivity of the dielectric layer 500. The resistivity of the dielectric layer 500 may be 10 14 Ω·㎝～10 16 The resistivity of the material can be 10 cm 14 Ω·㎝、10 15 Omega. Cm or 10 cm 16 Omega. Cm, etc., for example, dielectric layer 500 is an undoped silicon dioxide layer having a resistivity of 10 15 Omega. Cm; the resistivity of the passivation layer 700 may be 10 13 Ω·㎝～10 15 The resistivity of the material can be 10 cm 13 Ω·㎝、10 14 Omega. Cm or 10 cm 15 Omega·cm, etc., for example, passivation layer 700 is a silicon nitride layer having a resistivity of 10 14 Omega. Cm. Low resistivity in passivation layer 700When the resistivity of the dielectric layer 500 is higher, the dielectric layer 500 has a higher resistivity, so that the dielectric layer 500 has better insulating property and isolation property than the passivation layer 700, and the occurrence of the device leakage phenomenon is effectively prevented.
The embodiment of the disclosure provides a method for forming a semiconductor structure, as shown in fig. 1, the method comprises the following steps:
step S10: providing a substrate, forming a source region, a drain region and a gate trench between the source region and the drain region on the substrate;
step S20: forming a gate dielectric layer on the inner wall of the gate trench;
step S30: forming a barrier layer on the gate dielectric layer;
step S40: forming a conductive layer on the barrier layer, wherein the top surface of the conductive layer is higher than the top surface of the barrier layer, the conductive layer higher than the top surface of the barrier layer is a first conductive layer, the conductive layer lower than the top surface of the barrier layer is a second conductive layer, a first gap is formed between the edge of the first conductive layer and the inner wall of the gate trench, and a second gap is formed between the edge of the second conductive layer and the inner wall of the gate trench;
Step S50: removing a portion of the second conductive layer in a direction parallel to the substrate such that the second gap is greater than the first gap;
step S60: and forming a dielectric layer on the second conductive layer, and filling the second gap with the dielectric layer.
According to the method for forming the semiconductor structure, the lateral dimension between the edge of the conductive layer and the inner wall of the grid groove is increased, the distance between the side wall of the conductive layer and the drain electrode is increased, the dielectric layer is filled between the conductive layer and the inner wall of the grid groove, the insulativity between the conductive layer and the drain electrode is improved, the gate-induced drain leakage current is further reduced, the power consumption is reduced, the reliability of a device is improved, and the yield of a product is improved. Wherein in step S10 a substrate is provided, on which a source region, a drain region and a gate trench between the source region and the drain region are formed.
The following describes in detail a method for forming a semiconductor structure provided in the present disclosure with reference to the accompanying drawings:
as shown in fig. 2, the substrate 100 may be of a P-type, which may include source and drain regions 101 and 102 disposed at intervals, and the source and drain regions may be formed by doping the source and drain regions 101 and 102. For example, the source region 101 and the drain region 102 may be n-doped so that the source region 101 and the drain region 102 form an n-type semiconductor, and the doping material may be an element in the V main group in the periodic table, for example, the doping material may be phosphorus, or may be a material of other elements, which is not specifically described herein. Alternatively, the substrate 100 may be N-type, and the doping of the corresponding source region 101 and drain region 102 may be adaptively adjusted, and the formation method is similar to that of P-type doping, which is not described herein.
In the embodiment provided in the present disclosure, the source region 101 and the drain region 102 may be implanted with phosphorus ions by using an ion implantation method, and of course, the source region 101 and/or the drain region 102 may be doped by using other processes, which is not limited herein. It should be noted that, between the source region 101 and the drain region 102, a channel region may be formed, where the channel region may have a gate trench 103, and a buried word line structure may be formed in the gate trench 103, where the word line structure is used as a gate of a transistor, and may control the transistor to be turned on or off.
By way of example, the formation of the gate trench 103 may include: the channel region of the substrate 100 is patterned to form the gate trench 103. Specifically, a photoresist is formed on the surface of the substrate 100, and a mask plate is used to expose the photoresist to form a development area, and the pattern of the development area can be the same as the pattern required by the gate trench 103; the developed region is anisotropically etched by a dry etching process to form a gate trench 103. Of course, the above-described method of forming the gate trench 103 is only exemplary, and other methods that may be used to form the gate trench 103 in the channel region are applicable to the present disclosure, which is not limited to the above-described steps of forming the gate trench 103 and combinations thereof.
As shown in fig. 3, in step S20 to step S50, a gate dielectric layer 200, a barrier layer 300, and a conductive layer 400 are sequentially formed in the gate trench 103; a portion of the second conductive layer 420 is removed such that the second gap A2 is greater than the first gap A1.
The gate dielectric layer 200 may be formed on the inner wall of the gate trench 103 by chemical vapor deposition, thermal oxidation, atomic layer deposition, or the like to form a gate dielectric layer 200 attached along with the inner wall. For example, in forming the gate dielectric layer 200, the gate dielectric layer 200 may be formed by removing portions of the gate dielectric layer 200 located on the top surface of the gate trench 103 and on the sidewalls of the gate trench 103 after simultaneously forming the gate dielectric layer 200 on the inner wall and the top surface of the gate trench 103. Of course, the gate dielectric layer 200 may be formed by other methods or steps, which are not particularly limited herein.
The barrier layer 300 is formed between the gate dielectric layer 200 and the conductive layer 400, and the barrier layer 300 may be formed on the gate dielectric layer 200 by a chemical vapor deposition, a physical vapor deposition, an atomic layer deposition, or the like.
The conductive layer 400 is formed on the barrier layer 300, and in particular, the conductive layer 400 may deposit a conductive material on a side of the barrier layer 300 away from the substrate 100 and fill the gate trench 103 with the conductive material. The conductive layer 400 may be made of tungsten, copper, or other materials, and is formed on the barrier layer 300 by vacuum evaporation, magnetron sputtering, atomic layer deposition, or other processes. The top surface of the conductive layer 400 is higher than the top surface of the barrier layer 300, the conductive layer higher than the top surface of the barrier layer 300 is the second conductive layer 420, the conductive layer lower than the top surface of the barrier layer 300 is the first conductive layer 410, a first gap A1 is formed between the edge of the first conductive layer 410 and the inner wall of the gate trench 103, and a second gap A2 is formed between the edge of the second conductive layer 420 and the inner wall of the gate trench 103.
Wherein the second conductive layer 420 may be formed by partial conductive layer etching. Specifically, after the conductive layer 400 is formed on the barrier layer 300, the conductive layer is etched in a direction from the top surface thereof to the substrate 100, that is, a portion of the conductive layer 400 near the top surface is etched to reduce the size of the upper end of the conductive layer 400 in a direction parallel to the substrate 100, thereby forming the second conductive layer 420.
The etching conductive layer can be performed by wet etching or the like to remove a part of the conductive layer. In the process of etching the conductive layer 400, the etching depth of the conductive layer 400 may be detected in real time, so as to precisely control the etching depth of the conductive layer 400 in the etching process. For example, when the conductive layer 400 is etched, the conductive layer 400 may be etched multiple times, after the first etching of the conductive layer 400, whether the etching depth meets the process requirement may be detected, if not, the conductive layer 400 is further etched, and the etching depth is detected again until the detected etching depth of the conductive layer 400 reaches the process requirement of the disclosure, and then the etching is stopped.
It should be noted that, specific structural parameters of the gate dielectric layer 200, the barrier layer 300, and the conductive layer 400 are the same as those set forth in the semiconductor structure, and are not repeated here.
In step S60, a dielectric layer 500 is formed on the second conductive layer 420, and the dielectric layer 500 is made to fill the second gap A2.
As shown in fig. 4, in an embodiment provided by the present disclosure, a dielectric layer 500 is formed on the second conductive layer 420, such that the dielectric layer 500 covers the surfaces of the second conductive layer 420 and the barrier layer 300, and the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200. That is, when the dielectric layer 500 is formed, the dielectric layer 500 fills the gap between the second conductive layer 420 and the gate dielectric layer 200, and the top surface of the formed dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, and a certain gap exists between the edge of the dielectric layer 500 and the inner wall of the gate trench 103.
As shown in fig. 7, in an embodiment provided by the present disclosure, a dielectric layer 500 is formed on the second conductive layer 420, such that the dielectric layer 500 covers the surface of the structure formed by the gate dielectric layer 200, the barrier layer 300 and the conductive layer 400, and the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200. That is, when the dielectric layer 500 is formed, the dielectric layer 500 fills the gap between the second conductive layer 420 and the gate dielectric layer 200 and covers the top surface of the gate dielectric layer 200, and the top surface of the formed dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, and the edge portion of the dielectric layer 500 is attached to the inner wall of the gate trench 103.
The dielectric layer 500 may be formed by atomic deposition, chemical vapor deposition, or the like. Dielectric layer 500 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and preferably dielectric layer 500 is an undoped silicon dioxide layer.
As shown in fig. 5 and 8, after forming the dielectric layer 500 in an embodiment provided in the present disclosure, the dielectric layer 500 may be doped along the top surface of the dielectric layer 500 toward the substrate 100 to form the work function adjusting layer 600 covering the surface of the dielectric layer 500. If the dielectric layer 500 is doped N-type, the dielectric layer 500 may be doped with a group v element of the periodic table by ion implantation, for example, phosphorus ions may be doped along the direction from the top surface of the dielectric layer 500 to the substrate 100; if the dielectric layer 500 is doped P-type, the dielectric layer 500 may be doped by ion implantation using the element of main group iii of the periodic table, for example, boron ions may be doped along the direction from the top surface of the dielectric layer 500 to the substrate 100; of course, the dielectric layer 500 may also be doped to form the work function adjusting layer 600 by using a combination of two doping methods. Note that, when the dielectric layer 500 is doped to form the work function adjusting layer 600, a portion of the dielectric layer 500 is doped, and the dielectric layer 500 is also remained under the work function adjusting layer 600.
In another embodiment provided by the present disclosure, the work function adjusting layer 600 may be formed by forming a film layer to be doped on the dielectric layer 500, and forming the work function adjusting layer 600 after doping the film layer to be doped. The film to be doped and the dielectric layer 500 may be made of the same material, for example, the film to be doped and the dielectric layer 500 may be undoped silicon dioxide layers. The method of forming the work function adjusting layer 600 includes: forming a film layer to be doped covering the dielectric layer on the dielectric layer 500; the film to be doped is doped from top to bottom along the depth direction of the gate trench 103 to form the work function adjusting layer 600.
The methods of forming the work function adjusting layer 600 and the combinations or modifications thereof in the above two embodiments are applicable to the present disclosure, and the present disclosure is not limited to the methods of forming the two work function adjusting layers 600.
In the process of forming the work function adjusting layer 600 through the doping process, if the dielectric layer 500 covers the surfaces of the second conductive layer 420 and the barrier layer 300 and the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, then the formed work function adjusting layer 600 covers the top surface of the dielectric layer 500 and the top surface of the gate dielectric layer 200 at the same time, and the edge of the work function adjusting layer 600 is attached to the inner wall of the gate trench 103; if the dielectric layer 500 covers the surface of the structure formed by the gate dielectric layer 200, the barrier layer 300 and the conductive layer 400, and the top surface of the dielectric layer 500 is higher than the top surface of the gate dielectric layer 200, then the work function adjusting layer 600 is formed to cover the top surface of the dielectric layer 500, and the edge of the work function adjusting layer 600 is attached to the inner wall of the gate trench 103. Of course, the contact relationship between the work function adjusting layer 600 and the dielectric layer 500 or the gate dielectric layer 200 may be adaptively adjusted according to the specific formation structure of the dielectric layer 500.
Due to the limitation of the doping process, the doping concentration or doping thickness of the work function adjusting layer 600 along the depth direction of the gate trench 103 may be the same or different, so that the bottom surface of the work function adjusting layer 600 is not necessarily completely parallel to the top surface of the dielectric layer 500, and the thickness of the work function adjusting layer 600 formed in the depth direction of the trench is not completely the same, preferably, the work function adjusting layer 600 formed is uniform in the thickness direction. The semiconductor structure of the present disclosure may further control the magnitude of the work function by adjusting the work function adjusting layer 600, thereby controlling the magnitude of the gate-induced drain leakage current.
As shown in fig. 6 and 9, after the work function adjusting layer 600, a passivation layer 700 is formed on the surface of the work function adjusting layer 600, and the surface of the passivation layer 700 is made flush with the top surface of the gate trench 103, and the resistivity of the dielectric layer 500 is greater than the resistivity of the passivation layer 700. Specific structural parameters of the passivation layer 700 are described above and are not described here.
It should be noted that although the steps of the method of forming a semiconductor structure in the present disclosure are depicted in a particular order in the figures, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
The embodiment of the disclosure provides a memory which is manufactured by using the method for forming the semiconductor structure. The memory may be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), or the like. Of course, other storage devices are possible and are not listed here.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A semiconductor structure, comprising:
a substrate comprising a source region, a drain region, and a gate trench between the source region and the drain region;
the conductive layer comprises a first conductive layer and a second conductive layer which are sequentially stacked from bottom to top along the depth direction of the grid groove, a first gap is formed between the edge of the first conductive layer and the inner wall of the grid groove in the direction parallel to the substrate, a second gap is formed between the edge of the second conductive layer and the inner wall of the grid groove, and the second gap is larger than the first gap;
The grid dielectric layer covers the inner wall of the grid groove and is at least positioned between the first conductive layer and the inner wall of the grid groove;
a barrier layer located between the gate dielectric layer and the first conductive layer, the barrier layer filling the first gap;
and the dielectric layer covers the surface of the second conductive layer and fills the second gap.
2. The semiconductor structure of claim 1, further comprising a work function tuning layer located on a surface of the dielectric layer.
3. The semiconductor structure of claim 1, wherein a top surface of the gate dielectric layer is flush with a top surface of the second conductive layer.
4. The semiconductor structure of claim 3, wherein a top surface of the dielectric layer is higher than a top surface of the gate dielectric layer, and the dielectric layer covers surfaces of the second conductive layer and the barrier layer.
5. The semiconductor structure of claim 3, wherein a top surface of the dielectric layer is higher than a top surface of the gate dielectric layer, and wherein the dielectric layer covers a surface of the structure formed by the gate dielectric layer, the barrier layer, and the conductive layer together.
6. A method of forming a semiconductor structure, comprising:
providing a substrate, forming a source region, a drain region and a gate trench between the source region and the drain region on the substrate;
forming a gate dielectric layer on the inner wall of the gate trench;
forming a barrier layer on the gate dielectric layer;
forming a conductive layer on the barrier layer, wherein the top surface of the conductive layer is higher than the top surface of the barrier layer, the conductive layer higher than the top surface of the barrier layer is a second conductive layer, the conductive layer lower than the top surface of the barrier layer is a first conductive layer, a first gap is formed between the edge of the first conductive layer and the inner wall of the gate trench, and a second gap is formed between the edge of the second conductive layer and the inner wall of the gate trench;
removing a portion of the second conductive layer in a direction parallel to the substrate so that the second gap is larger than the first gap;
and forming a dielectric layer on the second conductive layer, and enabling the dielectric layer to fill the second gap.
7. The method of forming a semiconductor structure of claim 6, wherein after forming the dielectric layer, the method further comprises:
And doping part of the dielectric layer from the top surface of the dielectric layer to the direction of the substrate so as to form a work function adjusting layer in the dielectric layer.
8. The method of claim 7, wherein forming a work function adjusting layer within the dielectric layer, the method comprising:
and adjusting the doping concentration of the dielectric layer to adjust the work function of the work function adjusting layer.
9. The method of forming a semiconductor structure of claim 6, wherein forming a dielectric layer comprises:
and enabling the dielectric layer to cover the surfaces of the second conductive layer and the barrier layer, wherein the top surface of the dielectric layer is higher than the top surface of the gate dielectric layer.
10. The method of forming a semiconductor structure of claim 6, wherein forming a dielectric layer comprises:
and enabling the dielectric layer to cover the surface of the structure formed by the gate dielectric layer, the barrier layer and the conductive layer together, wherein the top surface of the dielectric layer is higher than the top surface of the gate dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310312017.XA CN116314298A (en) | 2023-03-27 | 2023-03-27 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310312017.XA CN116314298A (en) | 2023-03-27 | 2023-03-27 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116314298A true CN116314298A (en) | 2023-06-23 |
Family
ID=86803076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310312017.XA Pending CN116314298A (en) | 2023-03-27 | 2023-03-27 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116314298A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116507122A (en) * | 2023-06-25 | 2023-07-28 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and memory |
| CN117529100A (en) * | 2023-12-28 | 2024-02-06 | 长鑫集电(北京)存储技术有限公司 | Semiconductor device and method of forming the same |
-
2023
- 2023-03-27 CN CN202310312017.XA patent/CN116314298A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116507122A (en) * | 2023-06-25 | 2023-07-28 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and memory |
| CN116507122B (en) * | 2023-06-25 | 2023-11-07 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and memory |
| CN117529100A (en) * | 2023-12-28 | 2024-02-06 | 长鑫集电(北京)存储技术有限公司 | Semiconductor device and method of forming the same |
| CN117529100B (en) * | 2023-12-28 | 2024-03-26 | 长鑫集电(北京)存储技术有限公司 | Semiconductor device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8507349B2 (en) | Semiconductor device employing fin-type gate and method for manufacturing the same | |
| CN108257919B (en) | Method for forming random dynamic processing memory element | |
| CN112447604B (en) | Memory and forming method thereof | |
| CN116314298A (en) | Semiconductor structure and forming method thereof | |
| US8580669B2 (en) | Method for fabricating semiconductor device | |
| US11139306B2 (en) | Memory device and method for fabricating the same | |
| US20120012925A1 (en) | Semiconductor device and method for manufacturing the same | |
| US20110304028A1 (en) | Semiconductor device and method of manufacturing the same | |
| CN114628526B (en) | Semiconductor structure and manufacturing method thereof | |
| US20070164339A1 (en) | Semiconductor device and manufacturing method thereof | |
| US6569750B2 (en) | Method for forming device isolation film for semiconductor device | |
| US8658491B2 (en) | Manufacturing method of transistor structure having a recessed channel | |
| US7510930B2 (en) | Method for fabricating recessed gate MOS transistor device | |
| CN113517337B (en) | Semiconductor structure and forming method thereof | |
| US20080173939A1 (en) | Semiconductor device and method for fabricating the same | |
| WO2022057369A1 (en) | Semiconductor device and preparation method therefor | |
| CN213635990U (en) | Semiconductor structure | |
| US20230054358A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN114823310A (en) | Memory device, semiconductor structure and forming method thereof | |
| CN115083900A (en) | Semiconductor structure, forming method thereof and memory | |
| US8197275B2 (en) | Method for manufacturing semiconductor device | |
| CN113964127A (en) | Semiconductor structure and preparation method thereof | |
| CN114093818A (en) | Semiconductor structure and preparation method thereof | |
| CN115988877B (en) | Semiconductor structure and manufacturing method thereof | |
| CN117529100B (en) | Semiconductor device and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |