CN116312362A - Display panel and display device - Google Patents
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- CN116312362A CN116312362A CN202310260741.2A CN202310260741A CN116312362A CN 116312362 A CN116312362 A CN 116312362A CN 202310260741 A CN202310260741 A CN 202310260741A CN 116312362 A CN116312362 A CN 116312362A
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- 230000009977 dual effect Effects 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000002834 transmittance Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 8
- 230000003247 decreasing effect Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The application discloses a display panel and a display device. The display panel includes a plurality of pixel circuits and a plurality of light emitting elements; the pixel circuit comprises a driving module, the driving module comprises a double-gate driving transistor, the double-gate driving transistor comprises a first grid electrode and a second grid electrode, the double-gate driving transistor responds to the voltage of the first grid electrode to generate driving current, the double-gate driving transistor responds to the voltage of the second grid electrode to adjust the threshold voltage of the double-gate driving transistor, and at least partial applied voltages of the second grid electrodes of the double-gate driving transistors at different positions are different, so that the difference value of the light-emitting brightness of the light-emitting elements driven by the double-gate driving transistors at different positions under the same gray scale is within a preset range. According to the embodiment of the application, the display uniformity is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
With the progress of society, people's life is increasingly busy and colorful, and pursuit on display panel performance is also higher specification. For example, users are continually seeking better display image quality, faster response speed, lower power consumption, and narrower bezel.
However, in the related art, the display panel still has a problem of uneven display.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which are favorable for improving display uniformity and further favorable for improving display image quality.
In a first aspect, embodiments of the present application provide a display panel including a plurality of pixel circuits and a plurality of light emitting elements; the pixel circuit comprises a driving module, the driving module comprises a double-gate driving transistor, the double-gate driving transistor comprises a first grid electrode and a second grid electrode, the double-gate driving transistor responds to the voltage of the first grid electrode to generate driving current, the double-gate driving transistor responds to the voltage of the second grid electrode to adjust the threshold voltage of the double-gate driving transistor, and at least partial applied voltages of the second grid electrodes of the double-gate driving transistors at different positions are different, so that the difference value of the light-emitting brightness of the light-emitting elements driven by the double-gate driving transistors at different positions under the same gray scale is within a preset range.
In a possible implementation manner of the first aspect, the pixel circuit is connected to the first electrode of the light emitting element through an electrode connection line, and voltages applied to the second gates of the dual gate driving transistors corresponding to the electrode connection lines with different lengths are different;
Preferably, the longer the length of the electrode connection line, the smaller or larger the voltage applied to the second gate of the corresponding dual gate driving transistor.
In a possible implementation manner of the first aspect, the dual gate driving transistor is a PMOS transistor, and the longer the electrode connection line, the smaller the voltage applied to the second gate of the corresponding first driving transistor;
alternatively, the double-gate driving transistor is an NMOS transistor, and the longer the electrode connection line is, the larger the voltage applied to the second gate of the corresponding double-gate driving transistor is.
In a possible implementation manner of the first aspect, the display panel includes a first display area and a second display area, and a light transmittance of the first display area is greater than a light transmittance of the second display area;
the pixel circuit comprises a first pixel circuit and a second pixel circuit, and the light-emitting element comprises a first light-emitting element and a second light-emitting element;
the first pixel circuit is used for driving the first light-emitting element and is positioned outside the first display area;
the second pixel circuit is used for driving the second light-emitting element, and the second pixel circuit and the second light-emitting element are positioned in the second display area;
the driving module of the first pixel circuit comprises a double-gate driving transistor, and the driving module of the second pixel circuit comprises a single-gate driving transistor;
Preferably, the lengths of the electrode connecting lines connected to the plurality of first light emitting elements in the same row gradually increase in a direction of the row and in a direction approaching the center point of the first display area.
In a possible implementation manner of the first aspect, the display panel includes a display area and a binding area, the binding area is located at one side of the display area in a column direction, the plurality of pixel circuits and the plurality of light emitting elements are located in the display area, and the plurality of pixel circuits are distributed in a column and a row;
in the column direction, the voltages applied to the second gates of the double-gate drive transistors in pixel circuits of at least some different rows in the same column of pixel circuits are different.
In a possible implementation manner of the first aspect, the dual gate driving transistor is a PMOS type transistor, and in a column direction and in a direction away from the binding region, a voltage applied to the second gate of the dual gate driving transistor in the same column of pixel circuits is gradually reduced;
alternatively, the double gate driving transistor is an NMOS transistor, and the voltage applied to the second gate of the double gate driving transistor in the same column pixel circuit gradually increases in the column direction and in a direction away from the bonding region.
In a possible implementation manner of the first aspect, the voltages applied to the second gates of the dual gate driving transistors of the plurality of pixel circuits in the same row are the same.
In one possible implementation manner of the first aspect, the display panel includes a voltage division line, one end of the voltage division line is connected to a first voltage terminal, the other end of the voltage division line is connected to a second voltage terminal, and a second gate of the applied dual-gate driving transistor with different voltages is connected to different positions of the voltage division line, wherein the voltage of the first voltage terminal is greater than the voltage of the second voltage terminal;
preferably, the pixel circuit is connected to the first electrode of the light emitting element through an electrode connection line, the dual-gate driving transistor is a PMOS transistor, the longer the length of the electrode connection line, the closer the connection position between the second gate of the corresponding dual-gate driving transistor and the voltage dividing line is to the second voltage end, or the longer the length of the electrode connection line, the closer the connection position between the second gate of the corresponding dual-gate driving transistor and the voltage dividing line is to the first voltage end.
In a possible implementation manner of the first aspect, the display panel includes:
a substrate;
a first metal layer located on one side of the substrate;
a semiconductor layer located at one side of the first metal layer away from the substrate;
a second metal layer located on one side of the semiconductor layer away from the substrate;
The anode layer is positioned on one side of the second metal layer far away from the substrate and is arranged in an insulating way with the metal layer;
the voltage division wiring is positioned on any one of the semiconductor layer, the first metal layer, the second metal layer and the anode layer.
Based on the same inventive concept, in a second aspect, embodiments of the present application provide a display device including the display panel according to the embodiments of the first aspect.
According to the display panel and the display device provided by the embodiments of the application, under the condition that different voltages are applied to the second grid electrode, the adjustment degree of the threshold voltage of the double-grid driving transistor is different, the threshold voltage of the double-grid driving transistor affects the driving current, and under the condition that the lengths of wires connected with pixel circuits at different positions are different, the voltage applied to the second grid electrode can be controlled, so that the purposes that the driving currents received by different light emitting elements driven by the double-grid driving transistor at different positions tend to be the same can be achieved, namely, the difference value of the light emitting brightness of the light emitting elements driven by the double-grid driving transistor at different positions under the same gray scale is within a preset range, thereby being beneficial to improving the display uniformity and further being beneficial to improving the display image quality.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like or similar reference characters designate the same or similar features, and which are not to scale.
Fig. 1 is a schematic structural diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of an IDVG characteristic curve of a dual gate transistor according to an embodiment of the present disclosure;
FIG. 3 shows a timing diagram of the pixel circuit of FIG. 1;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 5 shows a schematic brightness of a display panel;
fig. 6 is a schematic diagram showing another structure of a pixel circuit in a display panel according to an embodiment of the present disclosure;
fig. 7 is a schematic view illustrating another structure of a display panel according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a voltage division trace in a display panel according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram showing another structure of a voltage division trace in a display panel according to an embodiment of the present disclosure;
fig. 10 is a schematic diagram showing a connection between a pixel circuit and a voltage dividing line in a display panel according to an embodiment of the present disclosure;
FIG. 11 is a schematic diagram showing a connection between a pixel circuit and a voltage dividing line in a display panel according to an embodiment of the present disclosure;
fig. 12 is a schematic view showing a film structure of a display panel according to an embodiment of the present disclosure;
fig. 13 shows a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the embodiments herein, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.
Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:
As described above, the related art display panel still has a problem of uneven display.
In order to solve the above technical problems, the inventors of the present application first studied and analyzed the root cause of the above technical problems, and the specific research and analysis procedures are as follows:
the display panel may be provided with a pixel circuit to drive the light emitting element to emit light, and specifically, the pixel circuit may receive a data signal through a data line and a power signal (for example, a power signal ELVDD) through a power line, and generate a driving current according to the received signal, and the driving current may be transmitted to the light emitting element through an electrode connection line, thereby driving the light emitting element to emit light.
However, the lengths of the data lines and the power supply wires corresponding to the pixel circuits at different positions are different, or the lengths of the electrode connecting wires corresponding to the pixel circuits at different positions are different, and the impedances of the wires with different lengths are different, so that the voltage drop and the capacitance value of the parasitic capacitance caused by the wires with different lengths are also different, and the driving currents received by different light emitting elements driven by the pixel circuits at different positions are different, so that the problem of uneven display is caused. Particularly, in the case of low gray scale display or low brightness display, the driving transistor of the pixel circuit may operate in a linear region, and the phenomenon of uneven display is particularly serious in the low gray scale region or low brightness region.
In view of the above-described studies of the inventors, the embodiments of the present application provide a display panel and a display device, which are advantageous in improving display uniformity and thus display image quality. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Fig. 1 is a schematic structural diagram of a pixel circuit of a display panel according to an embodiment of the present application. As shown in fig. 1, the display panel may include a plurality of pixel circuits 10 and a plurality of light emitting elements 20. The Light Emitting element 20 includes, but is not limited to, an Organic Light-Emitting Diode (OLED).
The pixel circuits 10 are distributed at different positions of the display panel, and the light emitting elements 20 may be distributed at different positions of the display panel. The pixel circuits 10 at different positions may receive signals through signal traces of different lengths and generate driving currents according to the signals received thereby. Alternatively, the pixel circuits 10 at different positions may be connected to the light emitting elements driven by the pixel circuits through electrode connection lines of different lengths, so that the driving current generated by the pixel circuits is transmitted to the light emitting elements through the electrode connection lines.
The pixel circuit 10 may include a driving module 11, the driving module 11 includes a driving transistor M1, and the driving transistor M1 may be a dual gate driving transistor M1. The dual gate driving transistor M1 is a four terminal device. Specifically, the dual gate driving transistor M1 may include a first gate TG, a second gate BG, a first pole, and a second pole. Depending on the signal of the first gate of the dual gate driving transistor M1 and its type, it is possible to use its first pole as the source (S), its second pole as the drain (D), or its first pole as the drain (D), and its second pole as the source (S), which are not distinguished here.
The dual gate driving transistor M1 may generate a driving current in response to the voltage of the first gate TG, and the dual gate driving transistor M1 may adjust its threshold voltage Vth in response to the voltage of the second gate BG. The voltages applied to the second gates BG of the double gate driving transistors M1 at least partially at different positions are different.
Referring to fig. 2, the abscissa represents the voltage Vg of the first gate TG of the dual-gate driving transistor M1, and the ordinate represents the driving current Ids generated by the dual-gate driving transistor M1. Each characteristic curve in fig. 2 moves with the voltage difference Vbs between the second gate BG and the source S of the dual gate driving transistor M1. Taking an N-type transistor as an example, fig. 2 shows a change of the voltage difference Vbs from-4V to +4v. As the voltage difference Vbs increases, the characteristic curve shifts to the left, which indicates that the double gate driving transistor M1 can be turned on by using the smaller voltage Vg of the first gate TG, i.e., the threshold voltage Vth of the double gate driving transistor M1 decreases. From this, it can be seen that the threshold voltage Vth can be regulated by regulating the voltage difference Vbs, and the larger the voltage difference Vbs, the more negative (smaller) the threshold voltage Vth, and the larger the driving current Ids.
The inventors have also tested two sets of characteristic curves, namely, a case where Vds is equal to a voltage difference Vbs between-4V and +4v at 0.1V and a case where Vds is equal to a voltage difference Vbs between-4V and +4v at 5.1V. For an N-type transistor, the result is that the larger the voltage difference Vbs, the more negative (smaller) the threshold voltage Vth, and the larger the drive current Ids, regardless of whether Vds is equal to 0.1V or Vds is equal to 5.1V.
In this embodiment, under the condition that different voltages are applied to the second gate BG, the adjustment degrees of the threshold voltages Vth of the dual-gate driving transistor M1 are different, and the threshold voltages Vth of the dual-gate driving transistor M1 affect the magnitude of the driving currents thereof, and since the voltages applied to the second gate BG of the dual-gate driving transistor M1 at different positions are different, the difference of the light-emitting brightness of the different light-emitting elements 20 driven by the dual-gate driving transistor M1 at different positions under the same gray level is within a preset range, thereby being beneficial to improving the display uniformity and further beneficial to improving the display quality.
Illustratively, the first gate TG and the second gate BG are top and bottom gates to each other. Specifically, if the first gate TG is a top gate, the second gate BG is a bottom gate; if the first gate TG is a bottom gate, the second gate BG is a top gate.
As an example, please continue to refer to fig. 1, the pixel circuit 10 may further include a data writing module 12, a threshold compensation module 13, a first initialization module 14, a first light emitting control module 15, a second light emitting control module 16, a second initialization module 17, and a storage capacitor Cst. The data writing module 12 may include a second transistor M2, the threshold compensation module 13 may include a third transistor M3, the first initialization module 14 may include a fourth transistor M4, the first light emitting control module 15 may include a fifth transistor M5, the second light emitting control module 16 may include a sixth transistor M6, and the second initialization module 17 may include a seventh transistor M7. It should be noted that, the modules of the pixel circuit shown in fig. 1 and the connection relationship thereof are only an example, and are not intended to limit the present application.
Referring to fig. 1 and 3 in combination, the operation of the pixel circuit 10 may include an initialization phase t1, a data writing phase t2 and a light emitting phase t3.
In the initialization stage t1, the first scan signal S1 controls the first initialization module 14 to be turned on, and the first initialization signal Verf1 is transmitted to the first gate TG of the dual-gate driving transistor M1 to initialize the first gate TG of the dual-gate driving transistor M1.
In the data writing stage t2, the second scan signal S2 controls the data writing module 12 and the threshold compensation module 13 to be turned on, the data signal Vdata is transmitted to the first gate TG of the dual-gate driving transistor M1, and the threshold compensation module 13 compensates the threshold voltage of the dual-gate driving transistor M1.
In addition, in the data writing stage t2, the second scan signal S2 can also control the second initialization module 17 to be turned on, and the second initialization signal Verf2 is transmitted to the first electrode of the light emitting element 20 to initialize the first electrode of the light emitting element 20. The voltage values of the first initialization signal Verf1 and the second initialization signal Verf2 may be the same or different.
In the light emitting stage t3, the light emitting control signal EM controls the first light emitting control module 15 and the second light emitting control module 16 to be turned on, the power signal ELVDD is transmitted to the first electrode of the dual gate driving transistor M1, the dual gate driving transistor M1 generates a driving current, the driving current is transmitted to the light emitting element 20, and the light emitting element 20 emits light.
The second gate BG of the dual gate driving transistor M1 may be always applied with a voltage in the initialization period t1, the data writing period t2, and the light emitting period t 3. This is advantageous in maintaining the stability of the double gate driving transistor M1, and is easy to implement and mass-produce.
The voltage applied to the second gate BG of the same double-gate driving transistor M1 may be kept unchanged. Of course, the voltage applied to the second gate BG of the same dual-gate driving transistor M1 may also be different in different application scenarios according to actual requirements.
In some embodiments, as shown in fig. 4, the pixel circuit 10 may be connected to the first electrode of the light emitting element 20 through an electrode connection line 30. The driving current generated by the pixel circuit 10 may be transmitted to the light emitting element 20 through the electrode connection line 30. The voltages applied to the second gates of the dual gate driving transistors corresponding to the electrode connection lines 30 of different lengths are different. Illustratively, the longer the length of the electrode connection line 30, the voltage applied to the second gate electrode of the corresponding dual gate driving transistor may be gradually increased or gradually decreased.
In some embodiments, the first electrode of the light emitting element 20 may be an anode, and the electrode connection line 30 connects the anode of the light emitting element 20.
For example, the line width and material of the different electrode connection lines 30 may be the same, that is, the impedance of the different electrode connection lines 30 may be the same per unit length.
Specifically, as shown in fig. 4, the pixel circuits 10 may be distributed in the row direction X and the column direction Y, and fig. 4 illustrates the 1 st to n th pixel circuits 10 in a certain row and the light emitting elements 20 connected thereto. The 1 st pixel circuit 10 is connected to the light emitting element 20 through the electrode connection line 30 (1), the 2 nd pixel circuit 10 is connected to the light emitting element 20 through the electrode connection line 30 (2), the 3 rd pixel circuit 10 is connected to the light emitting element 20 through the electrode connection line 30 (3), the 4 th pixel circuit 10 is connected to the light emitting element 20 through the electrode connection line 30 (4), and so on, the nth pixel circuit 10 is connected to the light emitting element 20 through the electrode connection line 30 (n). The wiring lengths of the electrode connection lines 30 (1) to 30 (n) may be different, so that voltage drops caused by the electrode connection lines 30 (1) to 30 (n) are different, and when the currents generated by the pixel circuits are the same, the driving currents received by the light emitting elements 20 connected by the electrode connection lines 30 (1) to 30 (n) may be different due to the voltage drops of the electrode connection lines. In this embodiment, the voltages applied to the second gate BG of the dual-gate driving transistor M1 in the 1 st pixel circuit 10 to the n-th pixel circuit 10 may be different, for example, the voltages applied to the second gate BG of the dual-gate driving transistor M1 in the 1 st pixel circuit 10 to the second gate BG of the dual-gate driving transistor M1 in the n-th pixel circuit 10 may be gradually increased or gradually decreased, so that the threshold voltages of the dual-gate driving transistor M1 in the 1 st pixel circuit 10 to the n-th pixel circuit 10 may be adjusted to generate different driving currents, thereby being beneficial to achieving the uniformity of the driving currents received by the light emitting elements 20 connected by the electrode connecting lines 30 (1) to 30 (n), and enabling the brightness of the light emitting elements 20 connected by the electrode connecting lines 30 (1) to 30 (n) to be consistent under the same gray scale, thereby improving the display uniformity.
In some examples, the dual gate driving transistor M1 may be a PMOS type transistor. The threshold voltage of the PMOS transistor is less than 0. The inventors have found that, when the double gate driving transistor M1 is a PMOS transistor, the larger the threshold voltage is, the larger the corresponding driving current is. In addition, the smaller the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the larger the forward shift of the threshold voltage of the dual-gate driving transistor M1, that is, the smaller the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the larger the threshold voltage of the dual-gate driving transistor M1.
Since the longer the length of the electrode connecting line 30 is, the larger the voltage drop is, the smaller the driving current received by the connected light emitting element is, and the lower the luminance is. In contrast, in the case where the dual-gate driving transistor M1 is a PMOS transistor, the longer the electrode connection line 30, the smaller the voltage VB applied to the second gate BG of the corresponding dual-gate driving transistor M1, and thus the larger the threshold voltage of the dual-gate driving transistor M1 is, the larger the driving current of the dual-gate driving transistor M1, and further the driving current received by the light emitting element connected to the longer electrode connection line 30 is increased, and the luminance of the light emitting element is increased.
For example, still taking fig. 4 as an example, the voltage VB1 is applied to the second gate BG of the dual gate driving transistor M1 of the 1 st pixel circuit 10, the voltage VB2 is applied to the second gate BG of the dual gate driving transistor M1 of the 2 nd pixel circuit 10, the voltage VB3 is applied to the second gate BG of the dual gate driving transistor M1 of the 3 rd pixel circuit 10, and so on, the voltage VBn is applied to the second gate BG of the dual gate driving transistor M1 of the n-th pixel circuit 10.
As an example, in the same row of light emitting elements 20, the length of the electrode connecting line 30 to which the light emitting elements 20 are connected may gradually increase in a direction approaching the center of the row. Still referring to fig. 4, for example, 2n light emitting elements 20 may be located in the same row, the pixel circuit 10 connected to the n light emitting elements 20 on the left side is located on the left side of the row of light emitting elements 20, the pixel circuit 10 connected to the n light emitting elements 20 on the right side is located on the right side of the row of light emitting elements 20, taking the n light emitting elements 20 on the left side as an example, the wiring length from the electrode connection line 30 (1) to the electrode connection line 30 (n) is gradually increased, the voltage drop from the electrode connection line 30 (1) to the electrode connection line 30 (n) is gradually increased, and the driving current received by the light emitting elements 20 connected to the electrode connection line 30 (1) to the electrode connection line 30 (n) is gradually decreased when the driving current of the 1 st pixel circuit 10 to the n pixel circuit 10 is the same. As shown in fig. 5, the inventors collected the luminance of two of the light emitting elements, where L01 represents the luminance of the center point of one of the rows and L02 represents the luminance of the center point of the other row. It can be seen that the brightness of the light emitting element 20 gradually decreases as the length of the electrode connecting line 30 to which the light emitting element 20 is connected gradually increases in the direction approaching the center of the row.
In contrast, in the case where the double-gate driving transistor M1 is a PMOS-type transistor, when the length of the electrode connection line 30 is gradually increased, the voltages VB1 to VBn to which the second gate BG of the double-gate driving transistor M1 is applied in the 1 st to n-th pixel circuits 10 may be gradually reduced, so that the degree of forward shift of the threshold voltages of the 1 st to n-th pixel circuits 10 is gradually increased, so that the driving currents of the 1 st to n-th pixel circuits 10 may be gradually increased to compensate for the brightness decrease caused by the increase of the voltage drop of the electrode connection line 30 (1) to the electrode connection line 30 (n).
In other examples, the dual gate driving transistor M1 may be an NMOS type transistor. The threshold voltage of the NMOS transistor is greater than 0. The inventors have found that when the double gate driving transistor M1 is an NMOS transistor, the smaller the threshold voltage thereof, the larger the corresponding driving current. In addition, the larger the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the larger the negative shift of the threshold voltage of the dual-gate driving transistor M1, that is, the larger the voltage VB applied to the second gate BG of the dual-gate driving transistor M1, the smaller the threshold voltage of the dual-gate driving transistor M1.
Since the longer the length of the electrode connecting line 30 is, the larger the voltage drop is, the smaller the driving current received by the connected light emitting element is, and the lower the luminance is. In contrast, in the case where the double-gate driving transistor M1 is an NMOS type transistor, the longer the electrode connection line 30, the larger the voltage VB applied to the second gate BG of the corresponding double-gate driving transistor M1, and thus the larger the threshold voltage of the double-gate driving transistor M1 will be negatively shifted, the larger the driving current of the double-gate driving transistor M1, and further the driving current received by the light emitting element connected to the longer electrode connection line 30 is increased, and the luminance of the light emitting element is increased.
For example, still taking fig. 4 as an example, the voltage VB1 is applied to the second gate BG of the dual gate driving transistor M1 of the 1 st pixel circuit 10, the voltage VB2 is applied to the second gate BG of the dual gate driving transistor M1 of the 2 nd pixel circuit 10, the voltage VB3 is applied to the second gate BG of the dual gate driving transistor M1 of the 3 rd pixel circuit 10, and so on, the voltage VBn is applied to the second gate BG of the dual gate driving transistor M1 of the n-th pixel circuit 10.
The wiring length of the electrode connection lines 30 (1) to 30 (n) is gradually increased, the voltage drop of the electrode connection lines 30 (1) to 30 (n) is gradually increased, and the driving current received by the light emitting element 20 connected to the electrode connection lines 30 (1) to 30 (n) is gradually decreased when the driving currents of the 1 st to nth pixel circuits 10 to 10 are the same, so that the luminance of the light emitting element 20 connected to the electrode connection lines 30 (1) to 30 (n) is gradually decreased.
In contrast, in the case where the double-gate driving transistor M1 is an NMOS-type transistor, when the length of the electrode connection line 30 is gradually increased, the voltages VB1 to VBn to which the second gate BG of the double-gate driving transistor M1 among the 1 st to nth pixel circuits 10 are applied may be gradually increased, so that the degree of negative shift of the threshold voltages of the 1 st to nth pixel circuits 10 to 10 is gradually increased, so that the driving currents of the 1 st to nth pixel circuits 10 may be gradually increased to compensate for the decrease in luminance caused by the increase in the voltage drop of the electrode connection line 30 (1) to the electrode connection line 30 (n).
In some embodiments, as shown in fig. 4, the display panel 100 may include a first display area AA1 and a second display area AA2, and the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA 2. In this way, the photosensitive components such as the camera may be disposed corresponding to the position of the first display area AA1, thereby implementing the full-screen technology.
In order to improve the light transmittance of the first display area AA1, the pixel circuit corresponding to the light emitting element in the first display area AA1 may be externally arranged.
Specifically, the pixel circuit 10 may include a first pixel circuit 101 and a second pixel circuit 102. The light emitting element 20 may include a first light emitting element 21 and a second light emitting element 22.
The first light emitting element 21 is located in the first display area AA1, the first pixel circuit 101 is used for driving the first light emitting element 21, and the first pixel circuit 101 is located outside the first display area AA 1. For example, the first pixel circuit 101 may be located in the second display area AA2 or in a non-display area of the display panel. For example, the first pixel circuit 101 and the first light emitting element 21 driven by the first pixel circuit are referred to as a first pixel, and it is understood that in the same first pixel, the front projection of the first pixel circuit 101 on the light emitting surface of the display panel and the front projection of the first light emitting element 21 on the light emitting surface of the display panel do not overlap, and a long electrode connection line 30 is required to connect the two. In addition, at least part of the electrode connecting lines corresponding to different first pixels are different in length.
The second light emitting element 22 and the second pixel circuit 102 are both located in the second display area AA2, and the second pixel circuit 102 is used for driving the second light emitting element 12.
As an example, the second pixel circuit 102 and the second light emitting element 22 driven by the second pixel circuit are referred to as a second pixel, in the same second pixel, the orthographic projection of the second pixel circuit 102 on the light emitting surface of the display panel may overlap with the orthographic projection of the second light emitting element 22 on the light emitting surface of the display panel, the length of the electrode connection line between the second pixel circuit 102 and the second light emitting element 22 is relatively short, and the lengths of the electrode connection lines corresponding to different second pixels are substantially consistent.
The driving module 11 in the first pixel circuit 101 may include a dual gate driving transistor M1. As shown in fig. 6, the driving module 11 in the second pixel circuit 102 may include a single gate driving transistor M1'.
For example, in the first pixel circuit 101 and the second pixel circuit 102, the structures and connection relationships of the other blocks may be the same except for the driving transistors.
In the direction of the row direction X and approaching the center point of the first display area AA1, the lengths of the plurality of electrode connection lines 30 to which the plurality of first light emitting elements 21 are connected in the same row may gradually increase, and correspondingly, the smaller or larger the voltage applied to the second gate of the dual gate driving transistor M1 of the first pixel circuit 101 may be. For example, the dual gate driving transistor M1 of the first pixel circuit 101 is a PMOS type transistor, and the smaller the voltage applied to the second gate of the dual gate driving transistor M1 connected to the plurality of first light emitting elements 21 in the same row in the direction of the row direction X and in the direction close to the center point of the first display area AA 1. For another example, the dual gate driving transistor M1 of the first pixel circuit 101 is an NMOS type transistor, and the larger the voltage applied to the second gate of the dual gate driving transistor M1 connected to the plurality of first light emitting elements 21 in the same row in the direction of the row direction X and the direction close to the center point of the first display area AA 1.
In other examples, as shown in fig. 7, the display panel 100 includes a display area AA and a binding area BA. In the column direction Y, the binding area BA is located at one side of the display area AA. The pixel circuits 10 are distributed in rows and columns in the display area AA. The light emitting elements 20 may also be distributed in rows and columns in the display area AA.
The display panel 100 may further include data lines 41, the data lines 41 extending in the column direction Y, and the pixel circuits 10 of the same column are connected to the same data line 41. The data signal Vdata may be transmitted to the pixel circuit 10 via the data line 41.
In addition, the display panel 100 may further include a power line 42, the power line 42 extending along the column direction Y, and the pixel circuits 10 of the same column are connected to the same power line 42. The power signal ELVDD may be transmitted to the pixel circuit 10 via the power line 42.
The inventors have found that the voltage drop of the data line 41 and/or the power line 42 is larger in the column direction Y and in a direction away from the bonding area BA, and thus the luminance of the light emitting element 20 is gradually decreased.
For this, the voltages VB applied to the second gates BG of the double-gate driving transistors M1 in the pixel circuits of at least some different rows in the same column of pixel circuits may be different. That is, in the column direction Y, the voltage VB applied to the second gate BG of the dual gate driving transistor M1 in the pixel circuit at a different distance from the bonding area BA may be different.
Specifically, as shown in fig. 7, the pixel circuits 10 may be distributed in the row direction X and the column direction Y, the pixel circuits in the same column are connected to the same data line 41 and the same power line 42, the 1 st pixel circuit 10 (1) is connected to the light emitting element 20 (1), the 2 nd pixel circuit 10 (2) is connected to the light emitting element 20 (2), and so on, the nth pixel circuit 10 (n) is connected to the light emitting element 20 (n). Taking the data line 41 as an example, the pixel circuits 10 (1) to 10 (n) are connected to different positions on the data line 41, so that voltage drops caused by the data line 41 on the pixel circuits 10 (1) to 10 (n) are different, and when data signals sent out by the data signal terminals are the same, the data signals received by the pixel circuits 10 (1) to 10 (n) are different due to the voltage drops of the data lines, so that the brightness of the light emitting elements 20 (1) to 20 (n) is gradually reduced. In the embodiment of the present application, the voltages applied to the second gate BG of the dual-gate driving transistor M1 in the 1 st pixel circuit 10 (1) to the n th pixel circuit 10 (n) may be different, so that the threshold voltages of the dual-gate driving transistor M1 in the 1 st pixel circuit 10 to the n th pixel circuit 10 may be adjusted to generate different driving currents, thereby being beneficial to achieving consistent driving currents received by the light emitting elements 20 (1) to 20 (n) and improving display uniformity.
As described above, the dual gate driving transistor M1 may be a PMOS type transistor, and the voltage applied to the second gate BG of the dual gate driving transistor M1 in the same column pixel circuit may be gradually reduced in the column direction and in a direction away from the bonding area BA. As shown in fig. 7, the voltage applied to the second gate BG of the dual gate driving transistor M1 in the pixel circuit 10 (1) to the pixel circuit 10 (n) may be gradually reduced, so that the degree of the forward shift of the threshold voltage of the pixel circuit 10 (1) to the pixel circuit 10 (n) is gradually increased, so that the driving current of the pixel circuit 10 (1) to the pixel circuit 10 (n) may be gradually increased to compensate for the decrease of the brightness caused by the increase of the voltage drop of the data line 41 and/or the power line 42.
As described above, the dual gate driving transistor M1 may be an NMOS type transistor, and the voltage applied to the second gate BG of the dual gate driving transistor M1 in the same column pixel circuit may be gradually increased in the column direction and in a direction away from the bonding area BA. As shown in fig. 7, the voltage applied to the second gate BG of the dual gate driving transistor M1 in the pixel circuit 10 (1) to the pixel circuit 10 (n) may be gradually increased, so that the degree of the negative shift of the threshold voltage of the pixel circuit 10 (1) to the pixel circuit 10 (n) is gradually increased, so that the driving current of the pixel circuit 10 (1) to the pixel circuit 10 (n) may be gradually increased to compensate for the decrease of the brightness caused by the increase of the voltage drop of the data line 41 and/or the power line 42.
With continued reference to fig. 7, the voltages applied to the second gates BG of the dual-gate driving transistors M1 of the pixel circuits 10 in the same row may be the same, so that the second gates BG of the multiple dual-gate driving transistors M1 in the same row may be connected to the same signal terminal through the same wiring, which is beneficial to improving the resolution of the display panel.
In some embodiments, as shown in fig. 8, the display panel may further include a voltage dividing wire 50, one end of the voltage dividing wire 50 is connected to the first voltage terminal VH, and the other end of the voltage dividing wire 50 is connected to the second voltage terminal VL. The second gates of the applied dual gate driving transistors M1 of different voltages are connected to different positions of the voltage dividing trace 50. The first voltage terminal VH and the second voltage terminal VL may provide different voltages, and herein, the voltage of the first voltage terminal VH is greater than the voltage of the second voltage terminal VL is taken as an example. The voltage dividing trace 50 may be understood as a resistor string. The voltage at different locations of the voltage dividing trace 50 is different. In this way, only the voltage dividing wire 50 is needed to apply different voltages to the second gate of the dual-gate driving transistor M1 at different positions, which is simple in structure and low in cost.
Taking the example that the voltage of the first voltage terminal VH is greater than the voltage of the second voltage terminal VL, the pixel circuit is connected to the first electrode of the light emitting element 21 through the electrode connection line 30, and in the case that the dual-gate driving transistor M1 is a PMOS transistor, the longer the electrode connection line 30, the closer the connection position between the second gate of the corresponding dual-gate driving transistor M1 and the voltage dividing trace 50 may be to the second voltage terminal VL, or the longer the length of the electrode connection line 30, the closer the connection position between the second gate of the corresponding dual-gate driving transistor M1 and the voltage dividing trace 50 is to the first voltage terminal VH, in the case that the dual-gate driving transistor M1 is an NMOS transistor.
As shown in fig. 8, the voltage dividing trace 50 may include sequentially arranged position points 1 BG To n BG Location point 1 BG Near the first voltage terminal VH, n BG Near the second voltage terminal VL, thus position point 1 BG To n BG Gradually decreasing in partial pressure.
Referring to fig. 4 and 8 in combination, taking the dual gate driving transistor M1 as a PMOS transistor as an example, the 1 st pixel circuit 10 can be connected to the position point 1 BG The 2 nd pixel circuit 10 can be connected to the position point 2 BG By analogy, the nth pixel circuit 10 may be connected to the position point n BG 。
Alternatively, as shown in FIG. 9, the voltage dividing trace 50 may include sequentially arranged position points 1 BG To n BG Location point 1 BG Near the second voltage terminal VL, n BG Near the first voltage terminal VH, therefore position point 1 BG To n BG The partial pressure of (2) is gradually increased.
Referring to fig. 4 and 9 in combination, taking the dual-gate driving transistor M1 as an NMOS transistor as an example, the 1 st pixel circuit 10 can be connected to the position point 1 BG The 2 nd pixel circuit 10 can be connected to the position point 2 BG By analogy, the nth pixel circuit 10 may be connected to the position point n BG 。
In order to more intuitively illustrate the connection positions of the pixel circuits and the voltage dividing lines at different positions, as shown in fig. 10 and 11, fig. 10 uses the PMOS transistor as the dual-gate driving transistor M1 as an example, the 1 st pixel circuit 10 can be connected to the position point 1BG, the 2 nd pixel circuit 10 can be connected to the position point 2BG, and so on, the nth pixel circuit 10 can be connected to the position point nBG.
In fig. 11, taking the dual gate driving transistor M1 as an NMOS transistor as an example, the 1 st pixel circuit 10 may be connected to the position point 1BG, the 2 nd pixel circuit 10 may be connected to the position point 2BG, and so on, the nth pixel circuit 10 may be connected to the position point nBG.
It should be noted that, in fig. 10 and 12, the 1 st to nth pixel circuits 10 are illustrated with dotted lines to connect to the position points 1BG to nBG for better distinguishing the electrode connection lines 30, and the dotted line positions are not used to define the specific positions of the connection lines between the pixel circuits and the voltage dividing trace 50.
As one example, the voltage differences of adjacent location points on the voltage dividing trace 50 may be equal. For example position point 1 BG And position point 2 BG Voltage difference of (2) position point BG And position point 3 BG Voltage difference of (3) position point BG And position point 4 BG Voltage difference of (4) position point BG And position point 5 BG Is a voltage difference and a position point (n-1) BG And a position point n BG Is equal.
Of course, the voltage difference between adjacent points on the voltage dividing trace 50 can be set to be different according to practical requirements, which is not limited in the present application.
For example, the voltage of the first voltage terminal VH may be less than or equal to the maximum operation voltage of the display panel, for example, the maximum operation voltage of the display panel is 7V, and the voltage of the first voltage terminal VH may be less than or equal to 7V.
The voltage of the second voltage terminal VL may be less than or equal to the minimum operation voltage of the display panel, for example, the minimum operation voltage of the display panel is-7V, and the voltage of the second voltage terminal VL may be less than or equal to-7V.
It is understood that the specific voltage values of the first voltage terminal VH and the second voltage terminal VL may be determined by debugging, which is not particularly limited in this application.
As shown in fig. 4, each row of the first pixel circuits 11 may correspond to one voltage division line 50, or all rows of the first pixel circuits 11 may correspond to the same voltage division line.
In some embodiments, as shown in fig. 12, the display panel may include a substrate 01, a first metal layer M1, a semiconductor layer B, a second metal layer M2, and an anode layer RE. The first metal layer M1 is located on one side of the substrate 01, the semiconductor layer B is located on one side of the first metal layer M1 away from the substrate 01, the second metal layer M2 is located on one side of the semiconductor layer B away from the substrate 01, and the anode layer RE is located on one side of the second metal layer M2 away from the substrate 01. The second metal layer M2 may include a plurality of metal sublayers stacked and insulatively disposed, for example, the second metal layer M2 may include a metal sublayer M21 and a metal sublayer M22. The first metal layer M1, the semiconductor layer B, the second metal layer M2, and the anode layer RE are all disposed to be insulated from each other.
The voltage dividing trace 50 may be located in any one of the first metal layer M1, the semiconductor layer B, the second metal layer M2, and the anode layer RE.
Note that, the transistor in the embodiment of the present application may be an NMOS transistor or a PMOS transistor. For NMOS transistors, the on level is high and the off level is low. That is, when the gate of the NMOS transistor is at a high level, the first and second poles are on, and when the gate of the NMOS transistor is at a low level, the first and second poles are off. For PMOS transistors, the on level is low and the off level is high. That is, when the gate of the PMOS transistor is at a low level, the first and second poles are on, and when the gate of the PMOS transistor is at a high level, the first and second poles are off. In the embodiment, the gate electrode of each transistor is used as the control electrode, and the first electrode may be used as the source electrode, the second electrode may be used as the drain electrode, or the first electrode may be used as the drain electrode, and the second electrode may be used as the source electrode, which is not distinguished herein.
For NMOS transistors, metal oxide semiconductor processes may be used, and in particular Indium Gallium Zinc Oxide (IGZO) may be used. For PMOS type transistors, the preparation may be performed using a polysilicon semiconductor process, and in particular, may be performed using Low Temperature Polysilicon (LTPS).
Based on the same inventive concept, the embodiment of the application also provides a display device, which comprises the display panel provided by the embodiment of the application. Therefore, the display device has the technical characteristics of the display panel provided by the embodiment of the application, and can achieve the beneficial effects of the display panel provided by the embodiment of the application, and the same points can be referred to the description of the display panel provided by the embodiment of the application, and the description is omitted herein.
Fig. 13 is a schematic view illustrating a structure of a display device according to an embodiment of the present application. As shown in fig. 13, a display device 200 provided in an embodiment of the present application includes a display panel provided in any of the above embodiments of the present application. The embodiment of fig. 13 is only an example of a mobile phone, and the display device 200 is described in the following description, and it is understood that the display device 200 provided in the embodiment of the present application may be any electronic product with a display function, including but not limited to the following categories: the embodiment of the invention is not particularly limited to a mobile phone, a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.
These embodiments are not all details described in detail in accordance with the embodiments described hereinabove, nor are they intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A display panel, comprising:
a plurality of pixel circuits and a plurality of light emitting elements;
the pixel circuit comprises a driving module, the driving module comprises a double-gate driving transistor, the double-gate driving transistor comprises a first gate and a second gate, the double-gate driving transistor responds to the voltage of the first gate to generate driving current, the double-gate driving transistor responds to the voltage of the second gate to adjust the threshold voltage of the double-gate driving transistor, and at least partial applied voltages of the second gates of the double-gate driving transistors at different positions are different, so that the difference value of the light-emitting brightness of the light-emitting elements driven by the double-gate driving transistors at different positions under the same gray scale is within a preset range.
2. The display panel according to claim 1, wherein the pixel circuit is connected to a first electrode of the light-emitting element through an electrode connection line, and voltages applied to the second gate electrodes of the double-gate driving transistors corresponding to the electrode connection lines of different lengths are different;
preferably, the longer the electrode connection line is, the smaller or larger the voltage applied to the second gate electrode of the corresponding dual gate driving transistor is.
3. The display panel according to claim 2, wherein the double gate driving transistor is a PMOS transistor, and the longer the electrode connecting line is, the smaller the voltage applied to the second gate of the corresponding double gate driving transistor is;
alternatively, the dual gate driving transistor is an NMOS transistor, and the longer the electrode connection line is, the greater the voltage applied to the second gate of the corresponding dual gate driving transistor is.
4. A display panel according to any one of claims 2 to 3, wherein the display panel comprises a first display region and a second display region, the first display region having a light transmittance that is greater than a light transmittance of the second display region;
The pixel circuit comprises a first pixel circuit and a second pixel circuit, and the light-emitting element comprises a first light-emitting element and a second light-emitting element;
the first light-emitting element is located in the first display area, and the first pixel circuit is used for driving the first light-emitting element and is located outside the first display area;
the second pixel circuit is used for driving a second light-emitting element, and the second pixel circuit and the second light-emitting element are positioned in the second display area;
the driving module of the first pixel circuit includes the double-gate driving transistor, and the driving module of the second pixel circuit includes a single-gate driving transistor;
preferably, the lengths of the electrode connection lines connected to the first light emitting elements in the same row are gradually increased in a direction of the row and in a direction approaching the center point of the first display area.
5. The display panel according to claim 1, wherein the display panel includes a display region and a binding region, the binding region is located at one side of the display region in a column direction, the plurality of pixel circuits and the plurality of light emitting elements are located at the display region, and the plurality of pixel circuits are distributed in a row and a column;
In the column direction, voltages applied to the second gates of the double-gate drive transistors in pixel circuits of at least partially different rows in the same column of the pixel circuits are different.
6. The display panel according to claim 5, wherein the double-gate driving transistor is a PMOS-type transistor, and a voltage applied to the second gate of the double-gate driving transistor in the same column of the pixel circuit is gradually reduced in the column direction and in a direction away from the bonding region;
alternatively, the dual gate driving transistor is an NMOS transistor, and the voltage applied to the second gate of the dual gate driving transistor in the same column of the pixel circuit is gradually increased in the column direction and in a direction away from the bonding region.
7. The display panel according to claim 5, wherein the voltages applied to the second gates of the double gate driving transistors of the plurality of pixel circuits in the same row are the same.
8. The display panel according to claim 1, wherein the display panel includes a voltage dividing line having one end connected to a first voltage terminal and the other end connected to a second voltage terminal, the second gates of the double gate driving transistors of different voltages being applied being connected to different positions of the voltage dividing line, wherein a voltage of the first voltage terminal is greater than a voltage of the second voltage terminal;
Preferably, the pixel circuit is connected to the first electrode of the light emitting element through an electrode connection line, the dual-gate driving transistor is a PMOS transistor, the longer the length of the electrode connection line, the closer the connection position between the second gate of the dual-gate driving transistor and the voltage dividing line is to the second voltage end, or the dual-gate driving transistor is an NMOS transistor, the longer the length of the electrode connection line is, the closer the connection position between the second gate of the dual-gate driving transistor and the voltage dividing line is to the first voltage end.
9. The display panel of claim 8, wherein the display panel comprises:
a substrate;
a first metal layer located on one side of the substrate;
a semiconductor layer located at one side of the first metal layer away from the substrate;
a second metal layer located on one side of the semiconductor layer away from the substrate;
an anode layer located on a side of the second metal layer away from the substrate;
the voltage dividing wire is positioned on any one of the semiconductor layer, the first metal layer, the second metal layer and the anode layer.
10. A display device comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310260741.2A CN116312362A (en) | 2023-03-14 | 2023-03-14 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310260741.2A CN116312362A (en) | 2023-03-14 | 2023-03-14 | Display panel and display device |
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| CN116312362A true CN116312362A (en) | 2023-06-23 |
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| CN202310260741.2A Pending CN116312362A (en) | 2023-03-14 | 2023-03-14 | Display panel and display device |
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