CN116312353A - Display panel and display device - Google Patents

Abstract

The invention discloses a display panel and a display device, wherein the display panel comprises a substrate, a plurality of pixel circuits and a plurality of light-emitting elements, wherein the pixel circuits and the light-emitting elements are positioned on one side of the substrate; in the pixel circuit, a first electrode of the first transistor is electrically connected to the data signal line; the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; the first electrode of the second transistor is electrically connected with the power signal line; a first electrode of the third transistor is electrically connected to the reset signal line; the second electrode of the second transistor and the second electrode of the third transistor are electrically connected with the light-emitting element; the channel region of the first transistor and the channel region of the second transistor are arranged along a first direction; the channel region of the second transistor and the channel region of the third transistor are arranged along a second direction; the first direction and the second direction intersect with the arrangement direction of the pixel circuits. By adopting the technical scheme, the occupied area of the pixel circuit can be reduced, the resolution of the display panel is improved, and the pixel requirement of high resolution is met.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Along with development of display technology, requirements of people on display devices are also higher and higher, for example, display products such as organic electroluminescent devices (Organic Electroluminescence Display, OLED) and liquid crystal displays (Liquid Crystal Display, LCD) are widely applied to near-to-eye fields such as Virtual Reality (VR) and augmented Reality (Augmented Reality, AR) due to their light weight, self-luminescence, high corresponding speed and the like.

Because of the special optical path structure of display products in the near-eye field, higher resolution (i.e., pixel density units (PPI)) is often required in the display products. However, since the pixel circuit of the display device is complex, a large layout space is required, and it is difficult to achieve the pixel requirement of the display device with high PPI under the limited state of the art.

Disclosure of Invention

The invention provides a display panel and a display device, which are used for reducing the occupied area of a pixel circuit and improving the resolution of the display device.

According to an aspect of the present invention, there is provided a display panel including: a substrate, a plurality of pixel circuits on one side of the substrate, and a plurality of light emitting elements on a side of the pixel circuits away from the substrate;

The pixel circuit includes a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected with the data signal line; the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; the first electrode of the second transistor is electrically connected with the power signal line; a first electrode of the third transistor is electrically connected to the reset signal line; the second electrode of the second transistor and the second electrode of the third transistor are electrically connected with the light-emitting element;

the channel region of the first transistor and the channel region of the second transistor are arranged along a first direction; the channel region of the second transistor and the channel region of the third transistor are arranged along a second direction; the first direction intersects the second direction;

the first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction are intersected with the arrangement direction of the pixel circuits.

According to another aspect of the present invention, there is provided a display device including the above display panel.

According to the technical scheme, the first transistor is arranged to receive the data signal, the second transistor and the third transistor are arranged to transmit the power signal and the reset signal to the anode of the light-emitting element at different stages respectively, so that the light-emitting element is regulated and controlled, the number of transistors in the pixel circuit can be reduced, and the occupied area of the pixel circuit is reduced; the channel regions of the first transistor, the second transistor and the third transistor are respectively arranged along two directions different from the arrangement direction of the pixel circuits, and the connecting lines between the transistors form a triangle, so that one transistor of the pixel circuits is positioned outside the straight line of the other two transistors, the length of the pixel circuits in the direction of the straight line of the two transistors is reduced, in addition, the length of the pixel circuits in the arrangement direction is reduced, the occupied area of the pixel circuits is further reduced, the resolution of the display panel is improved, and the pixel requirement of high resolution is met.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic circuit diagram of a pixel circuit in the prior art;

FIG. 2 is a schematic diagram of a layout structure of a display panel according to the prior art;

fig. 3 is a schematic diagram of a film structure of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a layout structure of a pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of layout structures of a first semiconductor layer and a second semiconductor layer according to an embodiment of the present invention;

Fig. 7 is a schematic layout structure diagram of a first transistor, a second transistor and a third transistor according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of layout structures of a first semiconductor layer and a first gate layer according to an embodiment of the present invention;

fig. 9 is a schematic layout structure of a first transistor, a second transistor, and a third transistor according to another embodiment of the present invention;

FIG. 10 is a schematic diagram of a layout structure of a display panel according to another embodiment of the present invention;

FIG. 11 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present invention;

fig. 12 is a schematic view of a film structure of another display panel according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a layout structure of a pixel circuit according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a layout structure of a further pixel circuit according to an embodiment of the present invention;

FIG. 16 is a schematic view of a film structure of another display panel according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of a layout structure of a further pixel circuit according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present invention;

FIG. 19 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present invention;

FIG. 20 is a schematic diagram of layout structures of a first pixel circuit and a second pixel circuit according to an embodiment of the present invention;

fig. 21 is a schematic structural diagram of a first semiconductor layer according to an embodiment of the present invention;

FIG. 22 is a schematic diagram of a film structure of another display panel according to an embodiment of the present invention;

FIG. 23 is a schematic diagram of a layout structure of a further pixel circuit according to an embodiment of the present invention;

fig. 24 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;

fig. 25 is a schematic view of a film structure of another display panel according to an embodiment of the present invention;

FIG. 26 is a schematic diagram of a layout structure of a further pixel circuit according to an embodiment of the present invention;

fig. 27 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In order to reduce the area occupied by the pixel circuit and improve the resolution of the display device, a 3T1C pixel circuit is proposed in the prior art, as shown in fig. 1, the 3T1C pixel circuit 01 includes a first transistor T1, a second transistor T2, a third transistor T3 and a capacitor C, where the second electrode of the first transistor T1 and the gate electrode of the second transistor T2 are electrically connected to a first node N1, and the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are electrically connected to a second node N2; the second node N2 is electrically connected to an anode of the light emitting element LED, and a cathode of the light emitting element LED is electrically connected to the second power supply line PVSS. The number of transistors is reduced by adopting an external compensation mode, so that the structure of the pixel circuit is simplified, and the occupied area of the pixel circuit is reduced.

Fig. 2 is a schematic diagram of a layout structure of a display panel in the prior art, referring to fig. 2, the display panel 01 includes pixel circuits 01 arranged in an array, a second transistor T2 and a third transistor T3 are located in the same direction of a first transistor T1, the second transistor T2 and the third transistor T3 are sequentially arranged along a longitudinal direction, and a connection line of positions of the first transistor T1, the second transistor T2 and the third transistor T3 is a straight line; the second pole of the first transistor T1 is connected with the grid electrode of the second transistor T2 through a bridge type via hole, and the bridge type via hole is the first node N1; the second pole of the second transistor T2 is connected with the second pole of the third transistor T3 through the active layer, and a via hole is arranged at the active layer and used for being connected with a light emitting element LED, and the via hole is the second node N2; the first Scan signal line Scan1 is electrically connected to the gate of the first transistor T1, the second Scan signal line Scan2 is electrically connected to the gate of the third transistor T3, the first Scan signal line Scan1 and the second Scan signal line Scan2 are arranged in the same layer and extend in the lateral direction, and the pixel circuits in the same row may share the first Scan signal line Scan1 and the second Scan signal line Scan2; the pixel circuits in the same row may also share the reset signal line VINT, which extends in the same direction as the first Scan signal line Scan1 and the second Scan signal line Scan2, and both extend in the lateral direction.

Although the pixel circuit in the prior art reduces the occupied area of the pixel circuit by reducing the number of transistors, sharing part of wiring, compressing critical dimensions and the like, so that the pixel density of the display panel is close to or even reaches 1000PPI, the pixel circuit is applied to the near-eye display field such as VR and the like, at least 1500PPI or even more than 2000PPI is required, and the traditional stacking mode is difficult to meet the requirement of high-resolution pixels.

In order to solve the above technical problems, an embodiment of the present invention provides a display panel, including: a substrate, a plurality of pixel circuits on one side of the substrate, and a plurality of light emitting elements on a side of the pixel circuits away from the substrate; the pixel circuit includes a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected with the data signal line; the second pole of the first transistor is electrically connected with the grid electrode of the second transistor; the first electrode of the second transistor is electrically connected with the power signal line; a first electrode of the third transistor is electrically connected to the reset signal line; the second electrode of the second transistor and the second electrode of the third transistor are electrically connected to the light emitting element.

In the pixel circuit, a channel region of a first transistor and a channel region of a second transistor are arranged along a first direction; the channel region of the second transistor and the channel region of the third transistor are arranged along a second direction; the first direction intersects the second direction; the first direction and the second direction are parallel to the plane of the substrate, and the first direction and the second direction are intersected with the arrangement direction of the pixel circuits.

By adopting the technical scheme, the first transistor is arranged to receive the data signal, the second transistor and the third transistor are arranged to respectively transmit the power signal and the reset signal to the anode of the light-emitting element at different stages, so that the light-emitting element is regulated and controlled, the number of transistors in the pixel circuit can be reduced, and the occupied area of the pixel circuit is reduced; the channel regions of the first transistor, the second transistor and the third transistor are respectively arranged along two directions different from the arrangement direction of the pixel circuits, and the connecting lines between the transistors form a triangle, so that one transistor of the pixel circuits is positioned outside the straight line of the other two transistors, the length of the pixel circuits in the direction of the straight line of the two transistors is reduced, in addition, the length of the pixel circuits in the arrangement direction is reduced, the occupied area of the pixel circuits is further reduced, the resolution of the display panel is improved, and the pixel requirement of high resolution is met.

The above is the core idea of the invention, and based on the embodiments of the invention, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

Fig. 3 is a schematic diagram of a film structure of a display panel according to an embodiment of the present invention. Referring to fig. 3, the display panel 04 includes a substrate 10, a plurality of pixel circuits 03 located on one side of the substrate 10, and a plurality of light emitting elements 05 located on a side of the pixel circuits 03 remote from the substrate 10; the pixel circuit 03 includes a first transistor T1, a second transistor T2, and a third transistor T3; the first electrode T11 of the first transistor T1 is electrically connected to the data signal line VDATA; the second pole T12 of the first transistor T1 is electrically connected to the gate T23 of the second transistor T2; the first pole T21 of the second transistor T2 is electrically connected to the power supply signal line PVDD; the first electrode T31 of the third transistor T3 is electrically connected to the reset signal line VINT; the second electrode T22 of the second transistor T2 and the second electrode T32 of the third transistor T3 are electrically connected to the light emitting element 05.

Fig. 4 is a schematic layout diagram of a display panel according to an embodiment of the present invention, and fig. 5 is a schematic layout diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 4 and fig. 5, in a pixel circuit 03, a channel region T01 of a first transistor T1 and a channel region T02 of a second transistor T2 are arranged along a first direction M; the channel region T02 of the second transistor T2 and the channel region T03 of the third transistor T3 are arranged along the second direction N; the first direction M intersects the second direction N; the first direction M and the second direction N are both parallel to the plane in which the substrate 10 is located, and both intersect the arrangement direction of the pixel circuits 03.

Wherein the substrate 10 may be transparent, translucent or opaque, the substrate 10 may be a rigid substrate, such as a glass substrate, a silicon substrate, or the like; the substrate 10 may also be a flexible substrate, such as a flexible resinous material, or formed of a thin polymer, and specific materials may include Polyimide (PI), polyethylene terephthalate (Polyethylene Terephthalate, PET), polyethylene naphthalate (Polyethylene Naphthalate, PEN), or the like.

In an alternative embodiment, the substrate 10 may further include a buffer layer 11, and the buffer layer 11 may include a multi-layered inorganic, organic layer stack structure to block oxygen and moisture, prevent diffusion of moisture or impurities through the substrate 10, and provide a flat surface on the upper surface of the substrate 10.

In an embodiment of the present invention, the active layer of the transistor includes a channel region overlapping the gate electrode in a direction perpendicular to the plane of the substrate, and source and drain regions doped with impurities, respectively, a first pole and a second pole, or a second pole and a first pole, of the transistor. In an alternative embodiment, the active layer of the transistor may comprise a silicon semiconductor material, such as polysilicon or amorphous silicon; the active layer of the transistor may also include an oxide semiconductor material. The light emitting element 05 electrically connected to the pixel circuit 03 includes, but is not limited to, an OLED, a Mini LED, and a Micro OLED, and the light emitting element 05 includes an anode 051, a light emitting layer 052, and a cathode (the cathode is not shown in the figure).

Specifically, with reference to fig. 4 and 5, the center of gravity of the channel region T01 of the first transistor T1 is the position of the first transistor T1, the center of gravity of the channel region T02 of the second transistor T2 is the position of the second transistor T2, and the center of gravity of the channel region T03 of the third transistor T3 is the position of the third transistor T3. The first transistor T1 and the third transistor T3 are respectively located in different directions of the second transistor T2, and the second transistor T2 and the third transistor T3 are respectively located in different directions of the first transistor T1, that is, the connecting lines of the positions of the first transistor T1, the second transistor T2 and the third transistor T3 are broken lines, the first transistor T1, the second transistor T2 and the third transistor T3 are not arranged on the same straight line, and at most two transistors are simultaneously arranged on each straight line.

For example, with continued reference to fig. 4 and 5, the pixel circuit 03 extends along a third direction X and a fourth direction Y, respectively, each of which is parallel to the plane of the substrate 10, and the third direction X and the fourth direction Y intersect, and in a direction perpendicular to the plane of the substrate 10, the pixel circuit 03 is rectangular or diamond-shaped, wherein the pixel circuit 03 is a minimum repeating unit of a circuit structure in the display region in the display panel 04. In an alternative embodiment, the third direction X and the fourth direction Y are perpendicular, and the pixel circuit 03 is rectangular. The first transistor T1 and the second transistor T2 may be arranged in one diagonal direction of the pixel circuit 03, and the second transistor T2 and the third transistor T3 may be arranged in the other diagonal direction.

Taking the pixel circuit 03 as a rectangle as an example, the length L1 of the pixel circuit 03 in the third direction X and the length L2 of the pixel circuit 03 in the fourth direction Y are smaller than the diagonal length of the pixel circuit 03, the first transistor T1 and the second transistor T2 are disposed in one diagonal direction, and the second transistor T2 and the third transistor T3 are disposed in the other diagonal direction, so that the length L1 of the pixel circuit 03 in the third direction X and the length L2 of the pixel circuit 03 in the fourth direction Y can be reduced, thereby reducing the area occupied by the pixel circuit 03 and improving the resolution of the display panel 04.

It should be noted that, in the direction perpendicular to the plane of the substrate, the pixel circuit may also be in an irregular shape, and the figure only illustrates, by way of example, a case where the pixel circuit is rectangular in the direction perpendicular to the plane of the substrate, and the shape of the area occupied by the pixel circuit is not specifically limited in the embodiment of the present invention. The channel types of the first transistor, the second transistor and the third transistor in the pixel circuit can be P-type, N-type, or partially P-type, and partially N-type, and the channel types of the transistors in the pixel circuit are not particularly limited in the embodiment of the invention.

In summary, in the embodiment of the invention, the first transistor is arranged to receive the data signal, the second transistor and the third transistor are arranged to transmit the power signal and the reset signal to the anode of the light-emitting element at different stages respectively, so that the light-emitting element is regulated and controlled, the number of transistors in the pixel circuit can be reduced, and the occupied area of the pixel circuit is reduced; the channel region of the first transistor, the channel region of the second transistor and the channel region of the third transistor are respectively arranged along two directions different from the arrangement direction of the pixel circuit, and the connecting lines between the transistors form a triangle, so that one transistor of the pixel circuit is positioned outside the straight line of the other two transistors, the length of the pixel circuit in the direction of the straight line of the two transistors is reduced, in addition, the length of the pixel circuit in the arrangement direction is reduced, the occupied area of the pixel circuit is further reduced, the resolution of the display panel is improved, and the pixel requirement of high resolution is met.

In an alternative embodiment, with continued reference to FIG. 4 and FIG. 5,0.9L 1/L2 1.1.

For example, the length L1 of the pixel circuits 03 in the third direction X may be obtained by dividing the length of all the pixel circuits 03 in the third direction X in the display panel 04 by the number of the pixel circuits 03 arranged in the third direction X, and the length L2 of the pixel circuits 03 in the fourth direction Y may be obtained by dividing the length of all the pixel circuits 03 in the fourth direction Y in the display panel 04 by the number of the pixel circuits 03 arranged in the fourth direction Y. The length L1 of the pixel circuit 03 in the third direction X is approximately equal to the length L2 of the pixel circuit 03 in the fourth direction Y, and the length difference is less than or equal to 1 μm, which is beneficial to uniform display and improves the display effect of the display panel.

Optionally, the length L1 of the pixel circuit in the third direction has a value range: l1 is more than or equal to 7 mu m and less than or equal to 9 mu m; the length L2 of the pixel circuit in the fourth direction has a value range of: l2 is more than or equal to 7 mu m and less than or equal to 9 mu m. Thus, the high-resolution pixel requirement in the near-eye display field can be met.

In order to achieve the high resolution effect and ensure the display effect while achieving the high resolution, the embodiments of the present invention also provide a plurality of setting modes.

In an alternative embodiment, in the pixel circuit 03, part of the transistors may include a silicon semiconductor material, and the other thin film transistors TFT may include an oxide semiconductor material, for example, the active layer of the first transistor T1 is an oxide semiconductor active layer, and the active layer of the second transistor T2 is a silicon active layer.

Exemplary, the active layer of the first transistor T1 may be made of metal oxide materials such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium Tin Zinc Oxide (ITZO), indium zinc aluminum oxide (IAZO), etc., so that the leakage current of the first transistor T1 may be reduced, and the potential of the first node N1 may be maintained stable; the second transistor T2 may be manufactured by using a polysilicon technology such as low temperature polysilicon (Low Temperature Poly-Silicon, LTPS), so that the charging speed of the second transistor T2 may be increased, and the response speed of the pixel circuit 03 may be improved. In addition, the third transistor T2 and the third transistor T3 may be configured to have a dual-gate structure, for example, the second bottom gate T24 is disposed on a side of the active layer of the second transistor T2 away from the gate T23 thereof, and the third bottom gate T34 is disposed on a side of the active layer of the third transistor T3 away from the gate T33 thereof, as shown in fig. 3, so that the control capability of the second transistor T2 and the third transistor T3 on the channel region T02 and the channel region T03 may be improved, thereby further improving the operation stability and reliability of the pixel circuit 03.

Alternatively, the first transistor T1 at least partially overlaps the second transistor T2 in a direction perpendicular to the plane of the substrate 10.

For example, for ease of understanding, fig. 6 is a schematic layout structure diagram of a first semiconductor layer and a second semiconductor layer according to an embodiment of the present invention, and referring to fig. 3 and fig. 6, the first transistor T1 and the second transistor T2 are located on different layers. The display panel 04 includes a first semiconductor layer 21 located on a side of the substrate 10 and a second semiconductor layer 22 located on a side of the first semiconductor layer 21 away from the substrate 10; the first semiconductor layer 21 includes an active layer of the second transistor T2, and the second semiconductor layer 22 includes an active layer of the first transistor 1. In the direction perpendicular to the plane of the substrate 10, the active layer of the first transistor T1 and the active layer of the second transistor T2 partially overlap, so that the occupied area of the active layer of the transistor in the pixel circuit 03 can be reduced, the occupied area of the transistor in the pixel circuit 03 is reduced, the number of pixel circuits arranged in a unit area is further increased, and high resolution is facilitated.

Further, the active layer of the third transistor T3 is connected to the active layer of the transistor T2 as an integral structure, and the first semiconductor layer 21 includes the active layer of the third transistor T3. On the one hand, the method can reduce the process difficulty, reduce the quantity of deposited semiconductor layers, improve the production efficiency, and on the other hand, the occupied area of the active layer of the transistor can be reduced, thereby being beneficial to high resolution.

Optionally, fig. 7 is a schematic layout structure diagram of a first transistor, a second transistor, and a third transistor provided in an embodiment of the present invention, and referring to fig. 3 and fig. 7, a second pole T12 of the first transistor T1 is electrically connected to a gate T23 of the second transistor T2 through a first via H01.

Illustratively, the display panel 04 further includes a first gate layer 31 on a side of the substrate 10 and a second gate layer 32 on a side of the first gate layer 31 remote from the substrate 10; the first gate layer 31 is located between the first semiconductor layer 21 and the second semiconductor layer 22, and the second gate layer 32 is located on a side of the second semiconductor layer remote from the substrate 10; the first gate layer 31 includes a gate T23 of the second transistor T2 and a gate T33 of the third transistor, and the second gate layer 32 includes a gate T13 of the first transistor 1. In the direction perpendicular to the plane of the substrate 10, the second pole T12 of the first transistor T1 overlaps the gate T23 of the second transistor T2, and the electrical connection between the second pole T12 of the first transistor T1 and the gate T23 of the second transistor T2 can be achieved only by one first via H01, so that the bridge via can be reduced, which is beneficial to reducing the area occupied by the pixel circuit.

Optionally, fig. 8 is a schematic layout structure diagram of a first semiconductor layer and a first gate layer provided in an embodiment of the present invention, and referring to fig. 8, an active layer of a second transistor T2 extends along a second direction N.

Illustratively, the active layer of the second transistor T2 is located in the first semiconductor layer 21, the first pole T21, the channel region T02 and the second pole T22 of the second transistor T2 are sequentially arranged along the second direction N, the first pole T21, the channel region T02 and the second pole T22 of the second transistor T2 are all located on the same line, and the active layer of the second transistor T2 is linear, so that the length of the active layer of the second transistor T2 can be reduced. In this way, the occupied area of the active layer in the pixel circuit 03 is reduced, and the number of the pixel circuits 03 in a unit area is increased. In an alternative embodiment, the first pole T31, the channel region T03, and the second pole T32 of the third transistor T3 are also sequentially arranged along the second direction N, the first pole T31, the channel region T03, and the second pole T32 of the third transistor T3 are all on the same line, and the active layer of the third transistor T3 is also linear.

Further, with continued reference to fig. 8, the length of the channel region T02 of the second transistor T2 is equal to the length of the gate T23 of the second transistor T2 along the second direction N. By reducing the length of the channel region T02 of the second transistor T2 to be equal to the length of the gate T23 of the second transistor T2 in the second direction N, the area occupied by the channel region T02 of the second transistor T2 can be reduced, which is advantageous for meeting the high resolution requirement of the display panel.

Alternatively, referring to fig. 9, the active layer of the first transistor T1 extends in the first direction M; the value range of the included angle alpha between the first direction M and the second direction N is as follows: alpha is more than or equal to 75 degrees and less than or equal to 105 degrees.

The first electrode T11, the channel region T01, and the second electrode T12 of the first transistor T1 extend in the first direction M in sequence, the first electrode T11, the channel region T01, and the second electrode T12 of the first transistor T1 are all located on the same straight line, and the active layer of the first transistor T1 is linear. The active layers of the first transistor T1 and the second transistor T2 each extend in only a single direction, and the length of the active layer of the transistor in the pixel circuit 01 can be reduced. The included angle alpha between the first direction M and the second direction N is larger than or equal to 75 degrees and smaller than or equal to 105 degrees, so that excessive overlapping between the first transistor T1 and the second transistor T2 in the direction perpendicular to the plane of the substrate 10 or signal interference or misconnection between the first transistor T1 and the second transistor T2 can be avoided when the included angle alpha is too small; on the other hand, when the included angle α is too large, it is avoided that the length of the pixel circuit 03 in the first direction M and the length of the pixel circuit 03 in the second direction N are increased, which is not beneficial to improving the resolution of the display panel 04.

Optionally, with continued reference to fig. 9, the display panel 04 further includes a first Scan signal line Scan1, where the first Scan signal line Scan1 is electrically connected to the gate T13 of the first transistor T1; the first Scan signal line Scan1 includes a first portion Scan1-1 extending in the third direction X and a second portion Scan1-2 extending in the second direction N, and the first portion Scan1-1 and the second portion Scan1-2 are connected to each other.

For example, fig. 10 is a schematic layout structure of another display panel according to an embodiment of the present invention, and referring to fig. 3, 9 and 10, in order to save space and reduce routing, the first Scan signal line Scan1 may be located on the second gate layer 32, and the first Scan signal line Scan1 includes the gate T13 of the first transistor T1, which may reduce the connection via and reduce the occupied area of the pixel circuit 03. At least part of the first Scan signal lines Scan1 extend along the third direction X, a plurality of second portions Scan1-2 extending along the second direction N may be connected to a plurality of first portions Scan1-1 extending along the third direction X, and the first Scan signal lines Scan1 are arranged along the fourth direction Y, so that the pixel circuits 03 arranged along the third direction X can share the same first Scan signal line Scan1, which may reduce the number of signal traces and is beneficial to high resolution of the display panel 04. Each pixel circuit 03 includes a first portion Scan1-1 and a second portion Scan1-2 of the first Scan signal line Scan1, where the first Scan signal line Scan1 is a broken line, so that the length of the first Scan signal line Scan1 can be increased in a limited space, and thus, the length of the pixel circuit 03 in the third direction X can be reduced, which is beneficial to high resolution of the display panel 04.

Optionally, with continued reference to fig. 9 and 10, the display panel 04 further includes a second Scan signal line Scan2, and the second Scan signal line Scan2 is electrically connected to the gate T33 of the third transistor T3; the second Scan signal line Scan2 includes a third portion Scan2-3 extending in the third direction X and a fourth portion Scan2-4 extending in the first direction M, and the third portion Scan2-3 and the fourth portion Scan2-4 are connected to each other.

For example, referring to fig. 3, 9 and 10, the second Scan signal line Scan2 may be located at the first gate layer 31, and the second Scan signal line Scan2 includes the gate electrode T33 of the third transistor T3, which may reduce the connection via and the occupied area of the pixel circuit 03. At least part of the second Scan signal lines Scan2 extend along the third direction X, a plurality of fourth portions Scan2-4 extending along the first direction M may be connected to a plurality of third portions Scan2-3 extending along the third direction X, and the second Scan signal lines Scan2 are arranged along the fourth direction Y, so that the pixel circuits 03 arranged along the third direction X share the same second Scan signal line Scan2, each pixel circuit 03 includes the third portion Scan2-3 and the fourth portion Scan2-4 of the second Scan signal line Scan2, and the second Scan signal line Scan2 is a broken line, so that the length of the second Scan signal line Scan2 can be increased in a limited space, and the length of the pixel circuit 03 in the third direction X can be reduced, which is beneficial to the high resolution of the display panel 04.

Optionally, fig. 11 is a schematic layout structure of another display panel according to an embodiment of the present invention, and referring to fig. 11, reset signal lines VINT of the display panel 04 are arranged along a third direction X and extend along a fourth direction Y; the first electrode T31 of the third transistor T3 of the partial pixel circuit 03 arranged in the third direction X is electrically connected to the same reset signal line VINT.

For example, taking the third direction X as the row direction and the fourth direction Y as the column direction as an example, the reset signal lines VINT extend along the column direction, and the first poles T31 of the third transistors T3 of the pixel circuits 03 located in the same column are electrically connected to the same reset signal line VINT, i.e., the number of reset signal lines VINT may be equal to the number of columns of the pixel circuits 03 in the display panel 04. In order to save space and reduce wiring arrangement, two adjacent pixel circuits 03 in the same row may be symmetrical along the column direction, so that two adjacent pixel circuits 03 in the same row may share a part of the structure, for example, two adjacent pixel circuits 03 in the same row may share a reset signal line VINT, and a first electrode T31 of a third transistor T3 of two adjacent pixel circuits 03 in the same row is electrically connected to the same reset signal line VINT, so that the number of reset signal lines VINT is smaller than the number of columns of the pixel circuits 03, which may further reduce the number of reset signal lines VINT, reduce an area occupied by a single pixel circuit 03, and be beneficial to the display panel 04 meeting a high resolution pixel requirement.

It is understood that when two adjacent pixel circuits 03 are symmetrical along a certain direction, the first direction M and the second direction N of the two adjacent pixel circuits 03 are also symmetrical along the direction, and for convenience of understanding and explanation, the illustrated first direction M and second direction N are taken as examples of the embodiments of the present invention.

With continued reference to fig. 11, the reset signal line VINT extends in the fourth direction Y; at least part of the first Scan signal lines Scan1 and/or the second Scan signal lines Scan2 extend along the third direction X; wherein, the first Scan signal line Scan1 is electrically connected to the gate T13 of the first transistor T1; the second Scan signal line Scan2 is electrically connected to the gate T33 of the third transistor T3. The reset signal line VINT is different from the extending direction of the first Scan signal line Scan1 and/or the second Scan signal line Scan2, so that the length of the pixel circuit 03 in the arrangement direction of the first Scan signal line Scan1 and/or the second Scan signal line Scan2 can be reduced, thereby reducing the area occupied by the pixel circuit 03, and being beneficial to the display panel 04 to meet the pixel requirement of high resolution.

In an alternative embodiment, fig. 12 is a schematic film structure of another display panel according to an embodiment of the present invention, and referring to fig. 12, the display panel 04 further includes: a lap electrode plate 06, a first lap electrode 061 and an inorganic insulating layer 60; the second pole T22 of the second transistor T2 and the second pole T32 of the third transistor T3 are both electrically connected to the landing plate 06; the first overlap electrode 61 is located on the side of the overlap plate 06 remote from the substrate 10; the inorganic insulating layer 60 is located between the overlap plate 06 and the first overlap electrode 61; the bonding pad 06 is electrically connected to the anode 051 of the light emitting element 05 through the first bonding electrode 61.

Illustratively, the display panel 04 further includes a second conductive layer 42 on a side of the second gate layer 32 away from the substrate 10 and a third conductive layer 43 on a side of the second conductive layer 42 away from the substrate 10, the landing plate 06 is located on the second conductive layer 42, and the first landing electrode 61 is located on the third conductive layer 43. The overlap joint polar plate 06 is connected with the first overlap joint electrode 61 electricity through the second via hole H02, through setting up overlap joint polar plate 06 and first overlap joint electrode 61, can reduce the degree of depth of punching, reduces the technology degree of difficulty. The second via hole H02 is formed by punching the inorganic insulating layer 60, and compared with the conventional organic insulating layer, the punching precision of the inorganic insulating layer 60 is higher, so that the size of the second via hole H02 between the lap electrode plate 06 and the first lap electrode 61 is smaller, and in the direction parallel to the plane of the substrate 10, the length d0 of the second via hole H02 has the following range: d0.ltoreq.2μm, and therefore, the area of the overlap electrode plate 06 can be set smaller, as shown in FIG. 13, which is advantageous in reducing the area occupied by the pixel circuit 03.

In an alternative embodiment, fig. 14 is a schematic diagram of a layout structure of another display panel according to an embodiment of the present invention, and referring to fig. 12 and fig. 14, the power signal line PVDD, the reset signal line VINT, and the landing plate 06 are disposed in the same layer and are all located in the second conductive layer 42; the power signal lines PVDD and the reset signal lines VINT each extend in the fourth direction Y and are alternately arranged in the third direction X; the first electrode T21 of the second transistor T2 of the partial pixel circuit 03 arranged in the third direction X is electrically connected to the same power supply signal line PVDD.

Further, fig. 15 is a schematic diagram of a layout structure of a pixel circuit according to another embodiment of the present invention, referring to fig. 12 and 15, the first bonding electrode 061 and the data signal line VDATA are disposed on the same layer, and the first bonding electrode 061 and the data signal line VDATA may be both disposed on the third conductive layer 43, so that the space utilization rate of the pixel circuit 03 may be improved, the number of film layers may be reduced, which is beneficial to simplifying the process and improving the production efficiency. However, in the direction perpendicular to the plane of the substrate 10, the area of the first landing electrode 061 should not be too large, otherwise, the first landing electrode 061 is likely to be connected with the data signal line VDAT by mistake, which affects the display effect.

Optionally, fig. 16 is a schematic diagram of a film structure of another display panel provided by an embodiment of the present invention, and fig. 17 is a schematic diagram of a layout structure of another pixel circuit provided by an embodiment of the present invention. Referring to fig. 16 and 17, the display panel 04 further includes a second overlap electrode 062; the second overlap electrode 062 is located on the side of the first overlap electrode 061 remote from the substrate 10; the first bonding electrode 061 is electrically connected to the anode 051 of the light emitting element 05 through the second bonding electrode 062. Wherein the area of the second landing electrode 062 is larger than the area of the first landing electrode 061 in the direction perpendicular to the plane of the substrate 10.

For example, the display panel 04 further includes the fourth conductive layer 44 on the side of the third conductive layer 43 away from the substrate, in which only the second landing electrode 062 is disposed in the fourth conductive layer 44, and no other conductive structure is disposed, so that the area of the second landing electrode 062 may be set larger in the direction perpendicular to the plane of the substrate 10, and the situation that the second landing electrode 062 is connected by mistake is not easy to occur. The second overlap electrode 062 is electrically connected to the anode 051 of the light emitting element 05 through a third via hole H03, the third via hole H03 is formed by punching a planarization layer 70 located on a side, far away from the substrate 10, of the fourth conductive layer 44, and in a direction perpendicular to the plane of the substrate 10, the area of the second overlap electrode 062 is set larger, so that the length of the third via hole H03 can be set larger in a direction parallel to the plane of the substrate 10, the requirement on punching precision of the third via hole H03 is reduced, and the influence on display effect due to dislocation between the third via hole H03 and the second overlap electrode 062 caused by lower punching precision of the planarization layer 70 is avoided.

In addition, in the direction perpendicular to the plane of the substrate 10, the area of the second overlap electrode 062 is set larger, so that the punching diameter of the third via hole H03 is larger, the resistance is smaller, the current transmission rate is larger, and the light emitting element 05 can respond to the electrical signal of the pixel circuit 03 more quickly, so as to improve the display effect.

In an alternative embodiment, the insulating layer between the first overlap electrode 061 and the second overlap electrode 062 includes an inorganic insulating layer, so that the accuracy of the connection via between the first overlap electrode 061 and the second overlap electrode 062 may be improved, so that the size of the connection via between the first overlap electrode 061 and the second overlap electrode 062 is smaller, which is beneficial to reducing the area occupied by the pixel circuit 03.

After the area occupied by the pixel circuit 03 is reduced, the gate of the transistor overlaps with other traces for transmitting electrical signals with varying potential in a direction perpendicular to the plane of the substrate 10, which causes signal interference to the gate of the transistor. In order to solve the problem of signal interference, an embodiment of the present invention further provides a display panel, where fig. 18 (a) is a schematic layout structure diagram of the display panel when the shielding electrode plate is not prepared, and fig. 18 (b) is a schematic layout structure diagram of the display panel after the shielding electrode plate is provided. Referring to fig. 16 and 18, the display panel 04 further includes a shielding electrode plate C01; the shielding electrode plate C01 is located at a side of the gate T33 of the third transistor T3 away from the substrate 10, and the shielding electrode plate C01 is also located at a side of the data signal line VDATA close to the substrate 10; in a direction perpendicular to the plane of the substrate 10, the shield plate C01 overlaps the gate T33 of the third transistor T3 and the data signal line VDATA.

The display panel 04 also includes, illustratively, a first conductive layer 41 between the first gate layer 31 and the second semiconductor layer 22. In a direction perpendicular to the plane of the substrate 10, the gate T33 of the third transistor T3 overlaps the data signal line VDATA, and the signal interference of the data signal line VDATA on the gate T33 of the third transistor T3 can be shielded by the shielding plate C01. The shielding plate C01 may be electrically connected to a signal line of a fixed potential such as a power signal line PVDD or a ground line to shield signal interference.

Further, with continued reference to fig. 18, in a direction perpendicular to the plane of the substrate 10, the shielding plate C01 covers the first Scan signal line Scan1, and the first Scan signal line Scan1 is electrically connected to the gate T33 of the third transistor T3, so that signal interference of signal lines such as the data signal line VDATA and the reset signal line VINT on the first Scan signal line Scan1 can be shielded.

Optionally, fig. 19 is a schematic layout structure of another display panel provided by an embodiment of the present invention, and fig. 20 is a schematic layout structure of a first pixel circuit and a second pixel circuit provided by an embodiment of the present invention. Referring to fig. 19 and 20, the pixel circuit 03 includes a first pixel circuit 031 and a second pixel circuit 032 adjacent to each other; the first pixel circuit 031 and the second pixel circuit 032 are arranged along the third direction X; the first pole T31 of the third transistor T3 of the first pixel circuit 031 is multiplexed to the first pole T31 of the third transistor T3 of the second pixel circuit 032; the channel region T03 of the third transistor T3 of the first pixel circuit 031 partially overlaps the channel region T03 of the third transistor T3 of the second pixel circuit 032.

Specifically, the adjacent first pixel circuit 031 and second pixel circuit 032 share the first pole T31 and part of the channel region T03 of the third transistor T3, so that on one hand, the area occupied by the first pole T31 and the channel region T03 of the third transistor T3 in the pixel circuit 03 can be reduced, thereby reducing the area occupied by the pixel circuit 03; on the other hand, the area occupied by the first electrode T31 of the third transistor T3 and the channel region T03 in the pixel circuit 03 is reduced, more space can be reserved for arranging the first overlap electrode 061 or the overlap electrode plate 06, the punching precision of the first overlap electrode 061 or the overlap electrode plate 06 on the side far away from the substrate 10 can be reduced, and the product yield is improved.

As an example, the third transistor T3 active layer T30 is located on the first semiconductor layer 21, fig. 21 is a schematic structural view of the first semiconductor layer provided in the embodiment of the present invention, and referring to fig. 21, the third transistor T3 active layer T30 includes a first semiconductor portion 201, and a second semiconductor portion 202 and a third semiconductor portion 203 respectively connected to the first semiconductor portion 201; the second semiconductor portion 202 and the third semiconductor portion 203 are mirror symmetrical in the extending direction of the first semiconductor 201 portion; the first semiconductor portion 201 and the second semiconductor portion 202 constitute an active layer T30 of the third transistor T3 of the first pixel circuit 031; the first semiconductor portion 201 and the third semiconductor portion 203 constitute an active layer T30 of the third transistor T3 of the second pixel circuit 032. In this way, the length of the active layer T30 of the third transistor T3 in the extending direction of the portion of the first semiconductor 201 can be reduced, and the length of the active layer T30 of the third transistor T3 in the third direction X can be reduced, thereby reducing the area occupied by the pixel circuit 03, which is advantageous for high resolution of the display panel 04.

In an alternative embodiment, fig. 22 is a schematic film structure of another display panel according to an embodiment of the present invention, and referring to fig. 22, the overlap electrode 06 is disposed in different layers from the power signal line PVDD and the reset signal line VINT. Illustratively, the power signal line PVDD and the reset signal line VINT are located on a side of the active layer of the first transistor T1 near the substrate 10, and the landing plate 06 is located on a side of the gate T11 of the first transistor far from the substrate 10. Through setting up overlap joint polar plate 06 with power signal line PVDD and reset signal line VINT abnormal layer, can increase overlap joint polar plate 06's area, be difficult for the misconnection simultaneously, reduce the punching precision of overlap joint polar plate 06 one side of keeping away from the substrate 10, improve the product yield.

Further, fig. 23 is a schematic layout structure of another pixel circuit according to the embodiment of the present invention, and referring to fig. 22 and 23, the overlap electrode plate 06 is arranged in different layers with respect to the power signal line PVDD and the reset signal line VINT, so that the area of the power signal line PVDD can be increased, and meanwhile, the power signal line PVDD is not easy to be connected by mistake. In an alternative embodiment, the power supply signal line PVDD overlaps the second pole T12 of the first transistor T1 in a direction perpendicular to the plane in which the substrate 10 lies.

Specifically, the overlapping portion of the power signal line PVDD and the second electrode T12 of the first transistor T1 forms a capacitor C, one end of the capacitor C is electrically connected to the power signal line PVDD, the other end of the capacitor C is electrically connected to the gate T23 of the second transistor T2 through the second electrode T12 of the first transistor T1, and when the first transistor T1 does not transmit a data signal, the capacitor C can maintain the stability of the potential of the gate T23 of the second transistor T2, so that the light emitting element 05 can stably emit light, and the display effect of the display panel 04 is improved; in addition, the capacitor C multiplexes the power signal line PVDD and the active layer of the first transistor T1 to serve as a capacitor plate, so that the space of the pixel circuit 03 is effectively utilized, the occupied area of the pixel circuit 03 is reduced, and the display effect is improved while the display panel 04 meets the pixel requirement of high resolution.

In an alternative embodiment, a capacitor C' is disposed between the first node N1 and the second node N2, as shown in fig. 24, and preferably, the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. In the light emitting stage, the capacitor C' can maintain the stability of the potential of the gate T23 of the second transistor T2, thereby improving the display effect.

Fig. 25 is a schematic diagram of a film structure of another display panel according to an embodiment of the present invention, and fig. 26 is a schematic diagram of a layout structure of another pixel circuit according to an embodiment of the present invention. Referring to fig. 25 and 26, the landing plate 06 is disposed in different layers from the power supply signal line PVDD and the reset signal line VINT, and the landing plate 06 overlaps the second pole T12 of the first transistor T1 in a direction perpendicular to the plane of the substrate 10. The overlapping part of the lap electrode plate 06 and the second electrode T12 of the first transistor T1 forms a capacitor C ', one end of the capacitor C' is electrically connected with the anode 051 of the light emitting element 05, the other end of the capacitor C 'is electrically connected with the grid electrode T23 of the second transistor T2 through the second electrode T12 of the first transistor T1, and in the light emitting stage, the capacitor C' can maintain the stability of the potential of the grid electrode T23 of the second transistor T2, so that the light emitting element 05 can stably emit light, and the display effect of the display panel 04 is improved; in addition, the capacitor C' multiplexes the overlap electrode plate 06 and the active layer of the first transistor T1 to serve as a capacitor electrode plate, which effectively utilizes the space of the pixel circuit 03, is favorable to reducing the area occupied by the pixel circuit 03, and further makes the display panel 04 meet the pixel requirement of high resolution and improve the display effect.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 27 is a schematic structural diagram of the display device provided in the embodiment of the present invention, as shown in fig. 27, where the display device 09 includes the display panel 04 provided in any embodiment of the present invention. The display device 09 provided by the embodiment of the present invention may be a mobile phone as shown in fig. 27, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart wristband, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal and the like, and the embodiment of the invention is not particularly limited thereto

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (17)

1. A display panel, comprising: a substrate, a plurality of pixel circuits on one side of the substrate, and a plurality of light emitting elements on one side of the pixel circuits away from the substrate;

the pixel circuit includes a first transistor, a second transistor, and a third transistor; a first electrode of the first transistor is electrically connected with a data signal line; a second pole of the first transistor is electrically connected with a gate of the second transistor; the first pole of the second transistor is electrically connected with a power signal line; a first electrode of the third transistor is electrically connected with a reset signal line; a second electrode of the second transistor and a second electrode of the third transistor are electrically connected to the light emitting element;

the channel region of the first transistor and the channel region of the second transistor are arranged along a first direction; the channel region of the second transistor and the channel region of the third transistor are arranged along a second direction; the first direction intersects the second direction;

the first direction and the second direction are parallel to the plane where the substrate is located, and the first direction and the second direction are intersected with the arrangement direction of the pixel circuits.

2. The display panel according to claim 1, wherein an active layer of the first transistor is an oxide semiconductor active layer and an active layer of the second transistor is a silicon active layer; the first transistor at least partially overlaps the second transistor in a direction perpendicular to a plane in which the substrate lies.

3. The display panel of claim 2, wherein the second pole of the first transistor is electrically connected to the gate of the second transistor through a first via.

4. The display panel of claim 1, wherein an active layer of the second transistor extends in the second direction.

5. The display panel of claim 4, wherein a length of a channel region of the second transistor is equal to a length of a gate of the second transistor in the second direction.

6. The display panel of claim 4, wherein an active layer of the first transistor extends along the first direction; the value range of the included angle alpha between the first direction and the second direction is as follows: alpha is more than or equal to 75 degrees and less than or equal to 105 degrees.

7. The display panel according to claim 1, wherein the pixel circuits are arranged in a third direction and a fourth direction, respectively, the third direction and the fourth direction intersecting;

The length of the pixel circuit in the third direction is L1, and the length of the pixel circuit in the fourth direction is L2, wherein L1/L2 is more than or equal to 0.9 and less than or equal to 1.1.

8. The display panel according to claim 7, wherein a length L1 of the pixel circuit in the third direction has a value ranging from: l1 is more than or equal to 7 mu m and less than or equal to 9 mu m; the length L2 of the pixel circuit in the fourth direction has a value range of: l2 is more than or equal to 7 mu m and less than or equal to 9 mu m.

9. The display panel of claim 7, further comprising: a first scan signal line electrically connected to a gate of the first transistor;

the first scan signal line includes a first portion extending in the third direction and a second portion extending in the second direction, the first portion and the second portion being connected to each other.

10. The display panel of claim 7, further comprising: a second scan signal line electrically connected to a gate electrode of the third transistor;

the second scan signal line includes a third portion extending in the third direction and a fourth portion extending in the first direction, the third portion and the fourth portion being connected to each other.

11. The display panel according to claim 7, wherein the reset signal line is arranged in the third direction and extends in the fourth direction;

a first electrode of a portion of the third transistors of the pixel circuits arranged in the third direction is electrically connected to the same reset signal line.

12. The display panel according to claim 7, wherein the reset signal line extends in the fourth direction;

the display panel further comprises a first scanning signal line and a second scanning signal line; the first scanning signal line is electrically connected with the grid electrode of the first transistor; the second scanning signal line is electrically connected with the gate electrode of the third transistor; at least part of the first scanning signal line and/or the second scanning signal line extends along the third direction.

13. The display panel of claim 7, wherein the pixel circuit comprises adjacent first and second pixel circuits; the first pixel circuit and the second pixel circuit are arranged along the third direction;

a first pole of a third transistor of the first pixel circuit is multiplexed to a first pole of a third transistor of the second pixel circuit; a channel region of the third transistor of the first pixel circuit partially overlaps a channel region of the third transistor of the second pixel circuit.

14. The display panel according to claim 13, wherein the active layer of the third transistor includes a first semiconductor portion, and a second semiconductor portion and a third semiconductor portion connected to the first semiconductor portion, respectively; the second semiconductor portion and the third semiconductor portion are mirror symmetrical in the extending direction of the first semiconductor portion;

the first semiconductor portion and the second semiconductor portion constitute an active layer of a third transistor of the first pixel circuit; the first semiconductor portion and the third semiconductor portion constitute an active layer of a third transistor of the second pixel circuit.

15. The display panel of claim 1, further comprising: the electrode comprises a lap-joint polar plate, a first lap-joint electrode and an inorganic insulating layer;

the second pole of the second transistor and the second pole of the third transistor are electrically connected with the lap electrode plate; the first overlap electrode is positioned at one side of the overlap electrode plate away from the substrate; the inorganic insulating layer is positioned between the lap electrode plate and the first lap electrode;

the overlap electrode plate is electrically connected with the anode of the light-emitting element through the first overlap electrode.

16. The display panel of claim 15, wherein the first landing electrode is disposed on the same layer as the data signal line;

the display panel further includes a second overlap electrode; the second overlap electrode is positioned on one side of the first overlap electrode away from the substrate;

the first lap electrode is electrically connected with the anode of the light-emitting element through the second lap electrode;

wherein, in the direction perpendicular to the plane of the substrate, the area of the second overlap electrode is larger than the area of the first overlap electrode.

17. A display device comprising the display panel of any one of claims 1-16.

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