CN116306839A - Frequency adjusting device, processing core, many-core system and working method - Google Patents
Frequency adjusting device, processing core, many-core system and working method Download PDFInfo
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- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/061—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using biological neurons, e.g. biological neurons connected to an integrated circuit
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Abstract
The present disclosure provides a frequency adjustment device comprising at least one frequency adjustment module, each frequency adjustment module comprising: a plurality of neurons including a first neuron, and a second neuron and a plurality of third neurons connected in series in sequence; a plurality of gating units including a first gating unit connected between the output terminal of the second neuron and the input terminal of the first neuron, and a plurality of second gating units connected between the output terminal of each third neuron and the input terminal of the first neuron, respectively; the gating signal generation unit is used for generating gating signals according to the input signals of the input ends of the second neurons and the required output signals, and independently controlling the on-off states of the gating units so that the frequency adjustment module forms a frequency adjustment circuit; the frequency adjusting circuit is used for enabling the output end of the first neuron to generate a required output signal according to the input signal of the input end of the second neuron. The disclosure also provides a processing core, a many-core system and a working method.
Description
Technical Field
The disclosure relates to the field of computer technology, and in particular, to a frequency adjustment device, a processing core, a many-core system and a working method.
Background
High performance brain-like computing and brain simulation techniques are important means for studying brain science, wherein a large number of neurons are required to co-operate to perform basic functions of the human brain, while a large-scale brain simulation system is required to accurately simulate brain functions.
At present, when the system performs brain simulation, the processor and the nerve components work and operate according to the global synchronous signals, each component lacks independent triggering behaviors, and the control mechanism of the system has poor flexibility.
Disclosure of Invention
The present disclosure provides a frequency adjustment device, a processing core, a many-core system, and a method of operation.
In a first aspect, the present disclosure provides a frequency adjustment device comprising at least one frequency adjustment module, each of the frequency adjustment modules comprising:
a plurality of neurons including a first neuron, and a second neuron and a plurality of third neurons connected in series in sequence;
a plurality of gating units including a first gating unit connected between an output of the second neuron and an input of the first neuron, and a plurality of second gating units connected between an output of each of the third neurons and an input of the first neuron, respectively;
the gating signal generation unit is used for generating gating signals according to the input signals of the input ends of the second neurons and the required output signals, and independently controlling the on-off states of the gating units so that the frequency adjustment module forms a frequency adjustment circuit; the frequency adjusting circuit is used for enabling the output end of the first neuron to generate a required output signal according to the input signal of the input end of the second neuron.
In a second aspect, the present disclosure provides a processing core comprising: at least one frequency adjustment device, wherein each of the frequency adjustment devices adopts the frequency adjustment device according to the above embodiment;
the processing core is used for outputting at least one path of corresponding output signals by utilizing at least one frequency adjusting device.
In a third aspect, the present disclosure provides a many-core system, comprising: at least one frequency adjustment device, wherein each of the frequency adjustment devices employs the frequency adjustment device according to any one of claims 1 to 9;
each frequency adjusting device is connected with the trigger input end of at least part of the processing cores and is used for performing trigger control on the connected processing cores and triggering the connected processing cores to execute preset operation tasks.
In a fourth aspect, the present disclosure provides a working method applied to a processing core, where a trigger input end of the processing core is connected to a frequency adjustment device; the method comprises the following steps:
and responding to the output signal output by the frequency adjusting device, and executing a preset operation task.
The frequency adjusting device comprises at least one frequency adjusting module, the frequency adjusting module can independently control the on-off state of each gating unit through a gating signal generating unit in the frequency adjusting module, links among neurons are configured, various signal transmission and processing functions are achieved, the many-core system can achieve targeted control of part of processing cores through the frequency adjusting device, trigger control is achieved through a global synchronization mechanism, meanwhile trigger control is achieved based on output signals of the frequency adjusting device, and control flexibility is improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
fig. 1 is a schematic structural diagram of a frequency adjustment module according to an embodiment of the disclosure;
fig. 2a is a schematic structural diagram of a frequency adjustment circuit according to an embodiment of the disclosure;
fig. 2b is a schematic diagram of another frequency adjustment circuit according to an embodiment of the disclosure;
fig. 3a is a schematic structural diagram of another frequency adjustment module according to an embodiment of the disclosure;
fig. 3b is a schematic diagram of a frequency adjustment circuit according to another embodiment of the present disclosure
Fig. 4 is a schematic structural diagram of a frequency adjustment circuit according to another embodiment of the disclosure;
fig. 5 is a schematic structural diagram of a frequency adjustment circuit according to another embodiment of the disclosure;
fig. 6 is a schematic structural diagram of a frequency adjustment circuit according to another embodiment of the disclosure;
FIG. 7 is a schematic diagram of a processing core according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a many-core system according to an embodiment of the disclosure;
FIG. 9 is a schematic diagram of another many-core system provided in an embodiment of the present disclosure;
fig. 10 is a flowchart of a working method provided in an embodiment of the present disclosure.
Detailed Description
For a better understanding of the technical solutions of the present disclosure, exemplary embodiments of the present disclosure will be described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic structural diagram of a frequency adjustment module according to an embodiment of the disclosure. The frequency adjusting module belongs to a frequency adjusting device, and the frequency adjusting device comprises at least one frequency adjusting module; the frequency adjustment module includes: a plurality of neurons, a plurality of gating units, and a gating signal generation unit.
Wherein the plurality of neurons comprises: the first neuron, and the second neuron and the plurality of third neurons connected in series in sequence.
The plurality of gating cells includes: a first gating unit connected between the output of the second neuron and the input of the first neuron, and a plurality of second gating units respectively connected between the output of each third neuron and the input of the first neuron.
The gating signal generation unit is used for generating gating signals according to the input signals of the input ends of the second neurons and the required output signals, and independently controlling the on-off states of the gating units so that the frequency adjustment module forms a frequency adjustment circuit, and the frequency adjustment circuit is used for enabling the output ends of the first neurons to generate the required output signals according to the input signals of the input ends of the second neurons. The gating signal generation unit configures links among the neurons by controlling the on-off state of each gating unit.
The frequency adjustment of the frequency adjustment circuit is embodied in that the issuing frequency of the first neuron is adjusted by controlling the input of the first neuron, and a required output signal is obtained; and in the embodiments described hereinafter, its frequency adjustment is also embodied in achieving frequency adjustment between the input signal and the output signal.
The frequency adjusting circuit in each embodiment of the present disclosure is composed of neurons, and is a neuromorphic circuit.
The paths among the neurons are all in one-way conduction, and the arrow in the figure shows the signal transmission direction.
In some embodiments, the input signal to the input of the second neuron comprises a trigger signal comprising an excitatory trigger signal for the second neuron and an inhibitory trigger signal, which in some embodiments is continuously sent to the input of the second neuron according to a preset clock; alternatively, in some embodiments, the input signal includes not only the trigger signal, but also an output signal generated by the output end of the first neuron, and the output signal is not only used as the output of the frequency adjustment module, but also used as a feedback signal to be fed back to the input end of the second neuron, so that the frequency adjustment module is a self-excited loop frequency adjustment module, and the trigger signal is sent only once and is used for triggering the self-excited loop frequency adjustment module to start working.
In some embodiments, the frequency adjustment device comprises only one frequency adjustment module, whereby in the frequency adjustment device, the input of the second neuron of the frequency adjustment module receives the input signal externally and the output of the first neuron of the frequency adjustment module generates the output signal externally.
In some embodiments, the frequency adjustment device includes a plurality of frequency adjustment modules, and the plurality of frequency adjustment modules are sequentially connected in series, so that in the frequency adjustment device, an input signal is externally received by an input end of a second neuron connected in series with a first frequency adjustment module, and an output signal is externally generated by an output end of a first neuron connected in series with a last frequency adjustment module; the on-off states of the gating units of the frequency adjustment modules connected in series in sequence can be different, so that the functions corresponding to the frequency adjustment modules are correspondingly different. Alternatively, in some embodiments, the plurality of frequency adjustment modules are connected in a combined manner, and accordingly, the frequency adjustment device corresponds to a multiple-input single-output, a single-input multiple-output, a multiple-input multiple-output, or the like.
In some embodiments, the frequency adjustment module further comprises: a parameter configurator.
The parameter configurator is used for configuring the neuron parameters of each neuron in the frequency adjustment circuit according to the release parameters corresponding to the preset output signals.
Wherein the neuron parameters comprise weights and firing thresholds. Thus, in some embodiments, a neuron fires when its membrane potential meets firing conditions determined according to the corresponding weights and firing thresholds, the output signal being a regular firing on the corresponding time axis. In some embodiments, the first neurons are uniformly distributed according to a period, and the distribution parameters comprise an oscillation frequency, an oscillation period and the like; or in some embodiments, the first neuron issues multiple times in one period, but the respective time intervals of the respective issues are unequal, and the issue parameters comprise the number of times of the respective issues in a preset time period, the issue interval between the respective issues in the time period, and the like; or in some embodiments, the release parameters further include delay parameters corresponding to the output signal, etc.
In some embodiments, the gating signal generation unit is configured to control the on-off state of the gating unit according to the output type corresponding to the required output signal and the frequency relationship between the required output signal and the input signal.
Wherein the output types include: the type of waveform division of the output signal according to the frequency adjustment module, such as oscillation output type and the like; or dividing types of the input signals according to the processing modes of the frequency adjustment module, such as frequency division output types, frequency multiplication output types and the like; alternatively, the types may be divided according to the relative sizes corresponding to the oscillation frequency or the oscillation period of the output signal, such as the first type having a larger frequency, or the like.
The embodiment of the disclosure provides a frequency adjustment device, wherein a frequency adjustment module is set based on neurons, has a dynamic configuration function, and can be used for independently controlling the on-off state of each gating unit through a gating signal generation unit in the frequency adjustment module, and configuring links among the neurons to realize various signal transmission and processing functions.
Various frequency adjustment circuits configured based on the output type of the desired output signal in the embodiments of the present disclosure are described in detail below.
Fig. 2a is a schematic structural diagram of a frequency adjustment circuit according to an embodiment of the disclosure, and fig. 2b is a schematic structural diagram of another frequency adjustment circuit according to an embodiment of the disclosure. Specifically, in response to the situation that the output type is the oscillation output type, the gating signal generating unit is used for controlling the first gating unit to be connected and each second gating unit to be disconnected, corresponding to fig. 2a, or the gating signal generating unit is used for controlling the first gating unit to be disconnected and only one second gating unit to be connected, corresponding to fig. 2b; as shown in fig. 2a and fig. 2b, the connection relation and the working state of each component in the frequency adjustment circuit are shown, the arrow shows the data transmission direction, the frequency adjustment circuit corresponds to the condition that the output type is the oscillation output type, and the gating signal generation unit completes the control of the on-off state of each gating unit, and then the frequency adjustment module forms two kinds of frequency adjustment circuits.
The formed frequency adjusting circuit is used for generating an output signal with preset frequency according to an input signal, wherein the input signal is a trigger signal; specifically, the output type is an oscillation output type, the type requires the first neuron to issue uniformly according to the period, the output signal has a fixed oscillation period, and the output signal can be used as an input signal of a processing core or the like to realize functions such as triggering or the like, or used as an input signal of other frequency adjustment modules to enable the other frequency adjustment modules to process and output the input signal.
In fig. 2a, the input end of the second neuron receives a stable input signal, performs a release once every time the corresponding release condition is satisfied, and transmits the stable input signal to the input end of the first neuron through the first gate control unit, and performs a release once every time the corresponding release condition is satisfied based on the first neuron, so as to generate an output signal at the output end thereof; in fig. 2b, two third neurons are exemplarily shown, the input end of the second neuron receives a stable input signal, the firing is performed once every time the corresponding firing condition is met, the third neurons are output to the third neurons of the next stage, the third neurons in the frequency adjustment circuit are fired step by step and transmitted to the input end of the first neurons through the second gating unit in the frequency adjustment circuit, based on which the first neurons are fired once every time the corresponding firing condition is met, to generate output signals at the output end thereof, in fig. 2b, a case where a plurality of third neurons are included in the frequency adjustment circuit is exemplarily shown, and in other embodiments, the frequency adjustment circuit includes at least one third neuron corresponding to a case where the first gating unit is turned off and only one second gating unit is turned on.
Fig. 3a is a schematic structural diagram of another frequency adjustment module according to an embodiment of the disclosure, and fig. 3b is a schematic structural diagram of another frequency adjustment circuit according to an embodiment of the disclosure. As shown in fig. 3a, in the frequency adjustment module, the plurality of gating units further includes: and a third gating unit connected between the output terminal of the first neuron and the input terminal of the second neuron. Accordingly, in response to the case that the output type is the oscillation output type, the gating signal generation unit is further configured to control the third gating unit to communicate, wherein an arrow in the figure shows a signal transmission direction. Fig. 3a shows a frequency adjustment module including a third gating unit, fig. 3b shows a connection relationship and an operating state of each component in a frequency adjustment circuit corresponding to the frequency adjustment module, where the frequency adjustment circuit corresponds to a case that an output type is an oscillation output type, and after the gating signal generating unit completes control of an on-off state of each gating unit, the frequency adjustment circuit is formed by the frequency adjustment module.
The third gating unit is used as a feedback circuit for connecting the output end of the first neuron with the input end of the second neuron, and at the moment, the output signal is used as the output of the frequency adjusting module and is also used as a feedback signal to be fed back to the input end of the second neuron, so that the frequency adjusting module is a self-excited loop frequency adjusting module.
The input end of the second neuron receives a trigger signal, releases once when corresponding release conditions are met, outputs the trigger signal to the third neuron of the next stage, releases the trigger signal step by step, and transmits the trigger signal to the input end of the first neuron through the second gating unit in the frequency adjusting circuit, releases once when the corresponding release conditions are met based on the first neuron, so as to generate an output signal at the output end of the trigger signal, and feeds back the output signal to the input end of the second neuron while outputting the output signal outwards, thereby realizing self-excitation by the circulation of the flow.
Fig. 4 is a schematic structural diagram of another frequency adjustment circuit according to an embodiment of the disclosure. Specifically, in response to the output type being a frequency multiplied output type, the gating signal generation unit is configured to control the first gating unit to be connected and at least one second gating unit to be connected. As shown in fig. 4, the frequency adjustment circuit is a frequency adjustment circuit formed by a frequency adjustment module after the gating signal generation unit completes the control of the on-off state of each gating unit corresponding to the case that the type of the output signal is the frequency multiplication output type.
The frequency adjusting circuit is configured to generate a desired output signal according to an input signal, where the frequency of the output signal is k times the frequency of the input signal, k is a positive number, and in some embodiments, k is a preset gain; specifically, the output type is a frequency multiplication output type, and the type corresponds to the condition that the frequency adjustment module carries out frequency multiplication processing on the input signal, at the moment, the first neuron is uniformly distributed according to the period, the frequency of the corresponding generated output signal is larger than that of the input signal, and the frequency of the corresponding generated output signal are fixed in proportion, namely k; in some embodiments, k is an integer, for example, taking the case shown in the figure that includes two third neurons, k may be 3, and the frequency of the output signal may be three times the frequency of the input signal; or the first neuron fires multiple times in one period but the respective firing times are not equal in time interval, and the respective generated output signals change more frequently in the same time period.
Two third neurons are exemplarily shown in the figure, the input end of the second neuron receives an input signal, the second neuron performs one time of issuing every time the corresponding issuing condition is met, the third neuron is output to the third neuron of the next stage and is transmitted to the input end of the first neuron through the first gating unit, the third neuron in the frequency adjusting circuit is issued step by step, and the third neuron is transmitted to the input end of the first neuron through all the second gating units in the frequency adjusting circuit, and based on the first neuron, the first neuron performs one time of issuing every time the corresponding issuing condition is met, so as to generate a frequency-doubled output signal at the output end of the first neuron.
Fig. 5 is a schematic structural diagram of another frequency adjustment circuit according to an embodiment of the disclosure. Specifically, in response to the case that the output type is the frequency division output type, the gating signal generation unit is configured to control the first gating unit to be on and each second gating unit to be off. As shown in fig. 5, the frequency adjustment circuit is a frequency adjustment circuit formed by a frequency adjustment module after the gating signal generation unit completes the control of the on-off state of each gating unit corresponding to the case that the output type is the frequency division output type.
The frequency adjusting circuit is used for generating a required output signal according to an input signal, wherein the frequency of the input signal is k times of the frequency of the output signal, and k is a positive number; specifically, the output type is a frequency division output type, and the type corresponds to the situation that the frequency adjustment module carries out frequency division processing on the input signal, at this time, the first neuron is evenly distributed according to the period, the frequency of the corresponding generated output signal is smaller than the frequency of the input signal, and the ratio of the frequency to the frequency of the input signal is fixed and is 1/k.
The input end of the second neuron receives an input signal, performs one-time issuing every time when corresponding issuing conditions are met, and transmits the input signal to the input end of the first neuron through the first gating unit, and performs one-time issuing every time when corresponding issuing conditions are met based on the first neuron so as to generate an output signal after frequency division at the output end of the first neuron.
Fig. 6 is a schematic structural diagram of a frequency adjustment circuit according to another embodiment of the disclosure. Specifically, in response to a case where the output type is a delayed output type, the gating signal generation unit is configured to control the first gating unit to be turned off and only one second gating unit to be in a turned-on state. As shown in fig. 6, the frequency adjustment circuit is a frequency adjustment circuit formed by a frequency adjustment module after the gating signal generation unit completes the control of the on-off state of each gating unit corresponding to the case that the output type is the delayed output type.
The formed frequency adjusting circuit is used for carrying out time delay processing on the input signal to generate a required output signal; specifically, the output type is a Delay output type, and the type corresponds to the condition that the frequency adjustment module carries out Delay processing on the input signal, at this time, the first neuron is evenly distributed according to the period, the correspondingly generated output signal is delayed for a period of time on a time axis compared with the input signal, and Delay (Delay) in the figure is used for indicating that each neuron carries out Delay processing, so that each neuron has a Delay effect.
Two third neurons are exemplarily shown in the figure, the input end of the second neuron receives an input signal, the input signal is issued once every time the corresponding issuing condition is met, the input signal is output to the third neuron of the next stage, the third neuron in the frequency adjustment circuit is issued step by step and is transmitted to the input end of the first neuron through the second gating unit in the frequency adjustment circuit, and the output signal after delay is generated at the output end of the output signal based on the first neuron which is issued once every time the corresponding issuing condition is met.
It should be noted that, the above description of the frequency adjustment circuit corresponding to each output type is only a specific implementation manner provided by the embodiments of the present disclosure, which does not limit the technical solution of the present disclosure, and other ways of implementing the functions corresponding to the types by controlling the on/off state of the gate control unit are also applicable to the technical solution of the present disclosure. And corresponding to the situation that the frequency adjusting device comprises a plurality of frequency adjusting modules which are sequentially connected in series, the frequency adjusting modules corresponding to the frequency adjusting circuit can be correspondingly combined, for example, in the frequency adjusting device, the frequency adjusting module corresponding to the oscillation output type, the frequency adjusting module corresponding to the frequency division output type and the frequency adjusting module corresponding to the frequency multiplication output type are sequentially connected in series, the frequency adjusting module corresponding to the oscillation output type and the frequency adjusting module corresponding to the time delay output type are sequentially connected in series, and the like.
Fig. 7 is a schematic structural diagram of a processing core according to an embodiment of the present disclosure. As shown in fig. 7, the processing core includes at least one frequency adjustment device (a case including a plurality of frequency adjustment devices is exemplarily shown in the figure), wherein each frequency adjustment device employs the frequency adjustment device as in any of the above embodiments.
The processing core is used for outputting at least one output signal by utilizing at least one frequency adjusting device. There are various setting modes, for example, the processing core includes a frequency adjusting device, and outputs one path of output signal to the outside; or the processing core comprises a plurality of frequency adjusting devices, and each frequency adjusting device respectively outputs one path of output signals to the outside; or the processing core comprises a plurality of frequency adjusting devices, at least part of the frequency adjusting devices are connected in series, and the processing core outputs one or more output signals.
Fig. 8 is a schematic structural diagram of a many-core system according to an embodiment of the disclosure. As shown in fig. 8, the many-core system includes at least one frequency adjustment device (a case including a plurality of frequency adjustment devices is exemplarily shown in the drawings), where each frequency adjustment device employs the frequency adjustment device as in any one of the above embodiments.
Each frequency adjusting device is connected with the trigger input end of at least part of the processing cores and is used for performing trigger control on the connected processing cores and triggering the connected processing cores to execute preset operation tasks. .
There are various cases, for example, a many-core system as shown in fig. 8 includes a plurality of frequency adjustment devices, each of which is connected to a part of a processing core, and the connection objects of each of which are different or partially coincident or identical; alternatively, the many-core system includes a single frequency adjustment device coupled to some or all of the processing cores; alternatively, the many-core system includes a plurality of frequency adjustment devices, each frequency adjustment device being coupled to all of the processing cores.
In some embodiments, as shown in fig. 8, the many-core system further includes a phase control module; the phase control module is connected with the trigger input end of each processing core and is used for outputting a phase control signal so as to trigger and control each processing core and trigger the processing core to execute a preset operation task.
The trigger input end is connected with a processing core of the frequency adjusting device and is used for executing a preset operation task according to one of output signals correspondingly output by the connected frequency adjusting device or a phase control signal output by the phase control module.
If the processing core is connected with a frequency adjusting device, executing an operation task according to an output signal or a phase control signal of the frequency adjusting device; if the processing core is connected with a plurality of frequency adjusting devices, an operation task is executed according to one of output signals output by the frequency adjusting devices, or an operation task is executed according to a phase control signal.
In some embodiments, the frequency adjustment means is a separately provided device; or in some embodiments, the frequency adjustment means is provided in the processing core; or in some embodiments, the frequency adjustment device and the phase control module are disposed in one processing core.
Fig. 9 is a schematic structural diagram of another many-core system according to an embodiment of the disclosure. As shown in fig. 9, the frequency adjustment device may be provided in the processing core.
The embodiment of the disclosure provides a many-core system, wherein the many-core system can realize targeted control of part of processing cores by utilizing a frequency adjusting device, and trigger control is performed based on an output signal of the frequency adjusting device while trigger control is performed by utilizing a global synchronization mechanism, so that control flexibility is improved.
Fig. 10 is a flowchart of a working method provided in an embodiment of the present disclosure. As shown in fig. 9, the method is applied to a processing core, wherein a trigger input end of the processing core is connected with a frequency adjusting device; the method comprises the following steps:
step S1, responding to an output signal output by the frequency adjusting device, and executing a preset operation task.
In some embodiments, the trigger input of the processing core is also connected to the phase control module; as shown in FIG. 10, the method further comprises
And S2, responding to the phase control signal output by the phase control module, and executing a preset operation task.
According to the working method, for the single processing core which is independently arranged, the touch control precision of the single processing core can be improved through multiple triggers; if the method is applied to a many-core system, each processing core can work according to various triggers, not only fixed phase driving but also event driving can be realized, and the many-core system can also independently control part of the processing cores.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, it will be apparent to one skilled in the art that features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with other embodiments unless explicitly stated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (15)
1. A frequency adjustment device comprising at least one frequency adjustment module, each of said frequency adjustment modules comprising:
a plurality of neurons including a first neuron, and a second neuron and a plurality of third neurons connected in series in sequence;
a plurality of gating units including a first gating unit connected between an output of the second neuron and an input of the first neuron, and a plurality of second gating units connected between an output of each of the third neurons and an input of the first neuron, respectively;
the gating signal generation unit is used for generating gating signals according to the input signals of the input ends of the second neurons and the required output signals, and independently controlling the on-off states of the gating units so that the frequency adjustment module forms a frequency adjustment circuit; the frequency adjusting circuit is used for enabling the output end of the first neuron to generate a required output signal according to the input signal of the input end of the second neuron.
2. The frequency adjustment device of claim 1, wherein the frequency adjustment device comprises a plurality of the frequency adjustment modules connected in series in sequence.
3. The frequency adjustment device of claim 1, wherein each of the frequency adjustment modules further comprises:
a parameter configurator, configured to configure a neuron parameter of each neuron in the frequency adjustment circuit according to a release parameter corresponding to a required output signal, where the neuron parameter includes: weights and issue thresholds.
4. The frequency adjustment device according to claim 1, wherein,
the gating signal generation unit is used for controlling the on-off state of the gating unit according to the output type corresponding to the required output signal and the frequency relation between the required output signal and the input signal.
5. The frequency adjustment device according to claim 4, wherein,
the gating signal generation unit is used for controlling the first gating unit to be connected and the second gating units to be disconnected, or is used for controlling the first gating unit to be disconnected and only one second gating unit to be connected;
the formed frequency adjusting circuit is used for generating an output signal with preset frequency according to the input signal, wherein the input signal is a trigger signal.
6. The frequency adjustment device of claim 5, wherein the plurality of gating cells further comprises:
a third gating unit connected between the output of the first neuron and the input of the second neuron;
the gating signal generation unit is further configured to control the third gating unit to communicate in response to the output type being an oscillating output type.
7. The frequency adjustment device according to claim 4, wherein,
the gating signal generation unit is used for controlling the first gating unit to be communicated and at least one second gating unit to be communicated in response to the condition that the output type is a frequency multiplication output type;
the frequency adjusting circuit is used for generating a required output signal according to the input signal, wherein the frequency of the output signal is k times of the frequency of the input signal, and k is a positive number.
8. The frequency adjustment device according to claim 4, wherein,
the gating signal generation unit is used for controlling the first gating unit to be connected and each second gating unit to be disconnected in response to the condition that the output type is the frequency division output type;
the frequency adjusting circuit is used for generating a required output signal according to the input signal, wherein the frequency of the input signal is k times of the frequency of the output signal, and k is a positive number.
9. The frequency adjustment device according to claim 4, wherein,
the gating signal generation unit is used for controlling the first gating unit to be disconnected and only one second gating unit to be in a connected state in response to the condition that the output type is a delayed output type;
the frequency adjusting circuit is used for carrying out time delay processing on the input signal to generate a required output signal.
10. A processing core, comprising: at least one frequency adjustment device, wherein each of the frequency adjustment devices employs the frequency adjustment device according to any one of claims 1 to 9;
the processing core is used for outputting at least one path of corresponding output signals by utilizing at least one frequency adjusting device.
11. A many-core system, comprising: at least one frequency adjustment device, wherein each of the frequency adjustment devices employs the frequency adjustment device according to any one of claims 1 to 9;
each frequency adjusting device is connected with the trigger input end of at least part of the processing cores and is used for performing trigger control on the connected processing cores and triggering the connected processing cores to execute preset operation tasks.
12. The many-core system of claim 11, wherein the frequency adjustment device is disposed within a processing core.
13. The many-core system of claim 11, further comprising: a phase control module;
the phase control module is connected with the trigger input end of each processing core and is used for outputting a phase control signal so as to trigger and control each processing core and trigger the processing core to execute a preset operation task.
14. The working method is applied to a processing core, wherein a trigger input end of the processing core is connected with a frequency adjusting device; the method comprises the following steps:
and responding to the output signal output by the frequency adjusting device, and executing a preset operation task.
15. The method of claim 11, wherein the trigger input of the processing core is further coupled to a phase control module;
the method further comprises the steps of:
and responding to the phase control signal output by the phase control module, and executing a preset operation task.
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