CN116306479A - UVM-based Ethernet PHY universal verification platform and verification method - Google Patents

UVM-based Ethernet PHY universal verification platform and verification method Download PDF

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CN116306479A
CN116306479A CN202310269940.XA CN202310269940A CN116306479A CN 116306479 A CN116306479 A CN 116306479A CN 202310269940 A CN202310269940 A CN 202310269940A CN 116306479 A CN116306479 A CN 116306479A
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module
level
ethernet
sequence
pin
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柯声伟
陈国华
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Lianyun Technology Hangzhou Co ltd
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Lianyun Technology Hangzhou Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/50Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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Abstract

The application discloses a universal verification platform and a verification method for an Ethernet PHY based on UVM, which belong to the field of PHY verification and are used for achieving the effect of comprehensively and accurately verifying PHY functional behaviors. The verification platform comprises: the system comprises a network cable model, a scoreboard, 2 modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module and a second physical interface, wherein the first module to be tested in the 2 modules to be tested is arranged at one end of a verification platform, and the second module to be tested in the 2 modules to be tested is arranged at the other end of the verification platform.

Description

UVM-based Ethernet PHY universal verification platform and verification method
Technical Field
The application belongs to the field of Ethernet port physical layer (Port Physical Layer, PHY) verification, and particularly relates to a universal verification platform and a verification method for an Ethernet PHY based on UVM.
Background
At present, in the modern integrated circuit design link, verification has the same important position as design, and meanwhile, the verification can ensure the correctness of the design and improve the productivity of the design, and provides a guarantee for shortening the chip development period, so that the verification work becomes a key bottleneck in the chip design, and a general verification methodology (Universa l Verification Methodology, UVM) platform written based on the traditional hardware description language becomes a mainstream verification scheme in the industry;
however, the conventional test platform written in the hardware description language cannot provide complete verification of reusability, and thus, there is a problem that PHY function behaviors cannot be comprehensively and accurately verified.
Disclosure of Invention
The embodiment of the application provides a universal verification platform and a verification method for an Ethernet PHY based on UVM, which can solve the problem that the function behavior of the PHY cannot be comprehensively and accurately verified.
In a first aspect, an embodiment of the present application provides a universal authentication platform for a UVM-based ethernet PHY, including: the system comprises a network cable model, a scoreboard, 2 modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module and a second physical interface, wherein a first module to be tested in the 2 modules to be tested is arranged at one end of a verification platform, and a second module to be tested in the 2 modules to be tested is arranged at the other end of the verification platform; wherein the first sequence generator is configured to generate a sequence request, where the sequence request includes a transaction-level sequence; the first ethernet proxy module is configured to receive the sequence request, convert the sequence of the transaction level into pin level excitation, and transmit the pin level excitation to the first physical interface; the first physical interface is used for outputting a first pin level signal to the first module to be tested based on the pin level excitation; the first ethernet proxy module is further configured to obtain the first pin level signal output by the first physical interface, convert the first pin level signal into a first target sequence of a transaction level, and transmit the first target sequence to the scoreboard; the first module to be tested is configured to encode the first pin level signal, convert the encoded data into serial data, and output the serial data to the network cable model; the network cable model is used for transmitting the serial data to the second module to be tested; the second module to be tested is used for obtaining and outputting a second pin level signal by decoding the received serial data; the second ethernet proxy module is configured to obtain the second pin level signal output by the second module to be tested, convert the second pin level signal into a second target sequence of a transaction level, and transmit the second target sequence to the scoreboard; and the scoreboard is used for comparing whether the first target sequence and the second target sequence are the same or not, and determining whether the function of the module to be tested is accurate or not according to the comparison result.
In a second aspect, embodiments of the present application provide a verification method, including: the first Ethernet proxy module of the verification platform receives a sequence request, converts a sequence in the sequence request into pin-level excitation and transmits the pin-level excitation to a first physical interface of the verification platform; the first physical interface outputs a first pin level signal to a first module to be tested of the verification platform based on pin level excitation; the first Ethernet proxy module acquires the first pin level signal output by the first physical interface, converts the first pin level signal into a first target sequence of a transaction level, and transmits the first target sequence to a scoreboard of the verification platform; the first module to be tested encodes the first pin level signal, converts the encoded data into serial data and outputs the serial data to a network cable model of the verification platform; the network cable model transmits the serial data to a second module to be tested of the verification platform; the second module to be tested obtains a second pin level signal and outputs the second pin level signal by decoding the received serial data; the second Ethernet proxy module of the verification platform acquires the second pin level signal output by the second module to be tested, converts the second pin level signal into a second target sequence of a transaction level, and transmits the second target sequence to the scoreboard; and the scoreboard compares whether the first target sequence and the second target sequence are the same, and determines whether the function of the module to be tested is accurate according to a comparison result.
In a third aspect, embodiments of the present application provide an electronic device, which includes the verification platform according to the first aspect.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the authentication method according to the second aspect.
In an embodiment of the present application, the verification platform includes: the system comprises a network cable model, a scoreboard, 2 modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module and a second physical interface, wherein a first module to be tested in the 2 modules to be tested is arranged at one end of a verification platform, and a second module to be tested in the 2 modules to be tested is arranged at the other end of the verification platform; wherein the first sequence generator is configured to generate a sequence request, where the sequence request includes a transaction-level sequence; the first ethernet proxy module is configured to receive the sequence request and convert the transaction-level sequence into pin-level stimuli for transmission to the first physical interface; the first physical interface is used for outputting a first pin level signal to the first module to be tested based on the pin level excitation; the first ethernet proxy module is further configured to obtain the first pin level signal output by the first physical interface, convert the first pin level signal into a first target sequence of a transaction level, and transmit the first target sequence to the scoreboard; the first module to be tested is configured to encode the first pin level signal, convert the encoded data into serial data, and output the serial data to the network cable model; the network cable model is used for transmitting the serial data to the second module to be tested; the second module to be tested is used for obtaining and outputting a second pin level signal by decoding the received serial data; the second ethernet proxy module is configured to obtain the second pin level signal output by the second module to be tested, convert the second pin level signal into a second target sequence of a transaction level, and transmit the second target sequence to the scoreboard; the scoreboard is used for comparing whether the first target sequence and the second target sequence are the same, determining whether the function of the module to be tested is accurate according to the comparison result, so that the verification platform has a definite structure, is favorable for error positioning, can be used for verifying the behaviors of the Ethernet PHY in a scene of an error injection mechanism, can achieve the effect of comprehensively and integrally verifying the Ethernet PHY, and solves the problem that the functional behaviors of the Ethernet PHY cannot be comprehensively and accurately verified.
Drawings
Fig. 1 is a schematic diagram of a universal authentication platform for a UVM-based ethernet PHY according to an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating the verification of an internal PCS module of an Ethernet PHY according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a basic architecture of a verification platform according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a workflow of system level verification of a verification platform provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a workflow of a PCS layer bus driver to internal module level verification provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The following describes in detail the UVM-based ethernet PHY universal verification platform and the verification method provided in the embodiments of the present application through specific embodiments and application scenarios thereof with reference to the accompanying drawings.
Fig. 1 illustrates a UVM-based ethernet PHY generic authentication platform provided by an embodiment of the present invention, and the method may be performed by an electronic device, which may include: a terminal device, wherein the terminal device may be, for example, a computer terminal or the like. In other words, the method may be performed by software or hardware installed in the terminal device, and the authentication platform includes: the system comprises a network cable model, a scoreboard, 2 modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module and a second physical interface, wherein the first module to be tested in the 2 modules to be tested is arranged at one end of a verification platform, and the second module to be tested in the 2 modules to be tested is arranged at the other end of the verification platform.
The first sequence generator is used for generating a sequence request, and the sequence request comprises a transaction-level sequence.
In an embodiment, the first ethernet proxy module includes: the first sequence generator is used for judging whether the sequence request is accepted or not, forwarding the sequence request to a first driver under the condition that the sequence request is accepted, the first driver is used for converting the sequence of the transaction level into pin level excitation and transmitting the pin level excitation to the first physical interface, and the first monitor is used for acquiring the first pin level signal output by the first physical interface, converting the first pin level signal into a first target sequence of the transaction level and transmitting the first target sequence to the scoreboard.
The first module to be tested is configured to encode the first pin level signal, convert the encoded data into serial data, and output the serial data to the network cable model; the network cable model is used for transmitting the serial data to the second module to be tested; the second module to be tested is used for obtaining and outputting a second pin level signal by decoding the received serial data, so as to achieve the effect of clear source and destination of the received and transmitted serial data.
In an embodiment, the second ethernet proxy module includes: the second sequencer, the second driver and the second monitor, wherein the second sequencer and the second driver are different from the first sequencer and the first driver only in name and have the same specific effect; the second monitor is used for acquiring the second pin level signal output by the second module to be tested, converting the second pin level signal into a second target sequence of a transaction level and transmitting the second target sequence to the scoreboard; and the scoreboard is used for comparing whether the first target sequence and the second target sequence are the same, and determining whether the function of the module to be tested is accurate according to the comparison result so as to comprehensively and accurately verify the functional behavior of the Ethernet PHY.
In one embodiment, with continued reference to fig. 2, the verification platform further comprises: a first physical encoding sublayer (Physical Coding Sublayer, PCS) bus driver and a third physical interface, wherein the first physical interface, the second physical interface and the third physical interface are only different in name and function identically; wherein the first ethernet proxy module is further configured to input the pin level stimulus to the first PCS bus driver and transmit the transaction level sequence to the scoreboard; the first PCS bus driver is used for encoding the pin-level excitation, converting parallel data obtained by encoding into serial data, and transmitting the serial data to a PCS module of the first module to be tested through the third physical interface; the PCS module of the first module to be tested is used for decoding the received serial data and sending the Ethernet data obtained by decoding to the second Ethernet proxy module; the second ethernet proxy module is further configured to convert the ethernet data into a transaction-level sequence and transmit the transaction-level sequence to the scoreboard; the scoreboard is further configured to compare whether the transaction-level sequence from the first ethernet proxy module is the same as the transaction-level sequence from the second ethernet proxy module, and determine whether the function of the PCS module of the module to be tested is accurate according to the comparison result, that is, the first PCS bus driver conforms to the electrical behavior of the ethernet protocol, so that the functional accuracy of the PCS layer can be effectively verified, verification of the PCS module level inside the ethernet PHY is achieved, and the problem of lack of verification of the accuracy of the internal module is solved.
In an embodiment, there is also provided a verification method including: the first Ethernet proxy module of the verification platform receives a sequence request, converts a sequence in the sequence request into pin-level excitation and transmits the pin-level excitation to a first physical interface of the verification platform, the first physical interface outputs a first pin-level signal to a first module to be tested of the verification platform based on the pin-level excitation, a first sequence generator of the first Ethernet proxy module judges whether the sequence request is accepted, and forwards the sequence request to a first driver of the first Ethernet proxy module under the condition that the sequence request is accepted, and the first driver converts the transaction-level sequence into pin-level excitation and transmits the pin-level excitation to the first physical interface; the first monitor of the first Ethernet proxy module obtains the first pin level signal output by the first physical interface, converts the first pin level signal into a first target sequence of a transaction level, transmits the first target sequence to the scoreboard, the first to-be-tested module encodes the first pin level signal, converts the encoded data into serial data and outputs the serial data to a network cable model of the verification platform, the network cable model transmits the serial data to a second to-be-tested module of the verification platform, the second to-be-tested module decodes the received serial data to obtain a second pin level signal and outputs the second pin level signal, and the second monitor of the second Ethernet proxy module obtains the second pin level signal output by the second to-be-tested module, converts the second pin level signal into a second target sequence of the transaction level, transmits the second target sequence to the scoreboard, and determines whether the first target sequence and the second target sequence of the second to-be-tested module achieve the same function and the complete function of the test result.
In an embodiment, the verification method further comprises: the first ethernet proxy module inputs the pin-level stimulus to a first physical coding sublayer PCS bus driver of the verification platform and transmits the transaction-level sequence to the scoreboard; the first PC S bus driver encodes the pin-level excitation, converts parallel data obtained by encoding into serial data, and transmits the serial data to a PCS module of the first module to be tested through a third physical interface of the verification platform; the PCS module of the first module to be tested decodes the received serial data and sends the Ethernet data obtained by decoding to the second Ethernet proxy module; the second Ethernet proxy module converts the Ethernet data into a transaction-level sequence and transmits the transaction-level sequence to the scoreboard; the scoreboard compares whether the transaction-level sequence from the first Ethernet proxy module is the same as the transaction-level sequence from the second Ethernet proxy module, and determines whether the PCS module of the module to be tested is accurate according to the comparison result, namely, the first PCS bus driver accords with the electrical behavior of the Ethernet protocol, so that the functional accuracy of the PCS layer can be effectively verified, the verification of the PCS module level inside the Ethernet PHY is achieved, and the problem of lack of verification of the accuracy of the internal module is solved.
The basic architecture and various components of the verification platform shown in fig. 1 are described in detail below by way of specific embodiments.
In an embodiment, fig. 3 shows a basic architecture of the verification platform, where the verification environment (env) of the verification platform is derived from uvm _env and used to include other components, where the components include the first sequence generator, the first ethernet proxy module, the first physical interface, the second ethernet proxy module, the second physical interface, the network cable model, the two modules to be tested, and the PCS layer bus driver in the above embodiment, and the verification environment is just exemplified in the test.
An authentication agent (agent) (including the first ethernet agent module or the second ethernet agent module) is derived from the uvm agent, and is responsible for encapsulating a sequencer (sequencer) (including the first sequencer or the second sequencer), a driver (driver) (including the first driver or the second driver) and a monitor (monitor) (including the first monitor or the second monitor) together, for example, the sequencer forwards a sequence request to the driver, the driver converts a sequence (sequanec) of a transaction level (transaction) into a pin-level stimulus and transmits the pin-level stimulus to an interface (interface) (including the first physical interface or the second physical interface or the third physical interface), the interface outputs a pin-level signal to a first module to be tested based on the pin-level stimulus, the first module to be tested encodes the pin-level signal, converts the encoded data into serial data, outputs the serial data to a network model (channel), and the driver converts the serial data to a serial data, and transmits the serial data to the target-level signal to the target-level module, i.e., the target-level signal to the target-level test board.
Wherein the sequencer (sequencer), derived from uvm _sequencer, is used for monitoring whether there is a request sent by the excitation sequence; a driver derived from uvm _driver for receiving the request for sending the generated stimulus sequence, converting the transaction level transmission into pin level, and transmitting the pin level transmission to the design to be tested (i.e., the first module to be tested and the second module to be tested); a monitor (monitor) derived from uvm _monitor for collecting pin information of the design under test; transaction (transaction), derived from uvm _sequence_item, performs transaction-level communication of the authentication platform; sequences (sequanece), derived from uvm _sequences, for pre-generation of stimulus sequences in test cases; an interface (interface) for verifying signal communication between the platform and the design to be tested; a network model (channel model) uses an industry register level transmission model to simulate the behavior of a network cable in a real environment by digitizing the transmission behavior of analog signals on the network cable, and a scoreboard (scoreboard) for comparing transmitted frame data with received frame data.
The PCS layer bus driver (bfm) encodes the pin-level excitation, converts parallel data obtained by encoding into serial data, transmits the serial data to a PCS module of the first module to be tested through the third physical interface, decodes the received serial data by the PCS module of the first module to be tested, and sends the Ethernet data obtained by decoding to the second Ethernet proxy module; the second Ethernet proxy module converts the Ethernet data into a transaction-level sequence and transmits the transaction-level sequence to the scoreboard, the scoreboard compares whether the transaction-level sequence from the first Ethernet proxy module is identical with the transaction-level sequence from the second Ethernet proxy module or not, and whether the function of the PCS module of the module to be tested is accurate or not is determined according to a comparison result, wherein the first PCS bus driver accords with the electrical behavior of an Ethernet protocol and can effectively verify the functional accuracy of the PCS layer;
the PCS layer bus driver (bfm) is used for creating a PCS which is stimulated to the internal module PCS of the design to be tested and receiving and analyzing information sent by the internal module PCS of the design to be tested. Of course, in the embodiment of the present application, each component of the verification platform is not specifically limited, and may be selected according to actual requirements.
One verification method workflow of the verification platform is described in detail below by way of specific embodiments.
Fig. 4 shows a workflow of a UVM-based ethernet PHY generic authentication platform, which shows the workflow of authentication platform system level authentication. For example, when there is a sequence request, the sequence transmitter arbitrates whether the sequence request is accepted, and if the sequence request is accepted, the sequence request is transmitted to the driver, and the behavior simulates the request and arbitration of data in a real scene; then the driver converts the transaction-level sequence in the sequence request into pin-level excitation, and transmits the pin-level excitation to the interface, and the behavior simulates the transmission of an advanced level to be converted into the excitation of a bottom level and then transmitted to the module to be tested; at the moment, the monitor monitors signals on the pins and converts the pin-level signals into transaction levels and records; the design to be tested (Device under test, DUT) encodes signals, parallel data are converted into serial data for operation, then the serial data are transmitted to the DUT at the opposite end through a network cable model, the DUT at the opposite end receives the data, pin level signals are converted into transaction level data and recorded by the monitor at the opposite end, at the moment, two monitors have two transaction level records and respectively transmit the transaction level records to a scoreboard, the scoreboard compares the two transaction level records, whether the function of the Ethernet PHY to be tested is accurate or not is determined through a comparison result, so that the verifying platform comprehensively and integrally verifies the function accuracy of the Ethernet PHY, and meanwhile, each component of the verifying platform has reusability and can be conveniently transplanted to the verifying platform of other chips. Of course, in the embodiment of the present application, each component of the verification platform is not specifically limited, and may be selected according to actual requirements.
In one embodiment, the PCS layer bus driver may be used to verify an internal codec module, where the PCS layer bus driver simulates a codec behavior during ethernet transmission, sends an ethernet frame to a decoding module in the DUT as an excitation after encoding the ethernet frame in the model, or decodes the ethernet frame encoded by the DUT after receiving the ethernet frame, and recovers ethernet frame data to verify the internal PCS module to be tested, as an example, fig. 5 is a workflow diagram of the PC S layer bus driver verifying the internal codec of the module to be tested, as shown in fig. 5, when there is a sequence request, the sequence transmitter sends a sequence request to the driver if the sequence request is received, where the sequence request simulates a request and arbitration of data in a real scene; the driver then converts the transaction-level transmission into pin-level stimulus, transmits to the PCS layer bus driver, while the monitor records the transaction at this time, inside the PCS layer bus driver (bfm), the pin-level stimulus is encoded, e.g. 100M, the received 100Mb/s code stream, the PCS layer bus driver (bfm) internal state machine is switched to the encoding state, the hundred megabits of data are 4B/5B encoded, the original 100Mb/s is compiled into 125Mb/s, then the state machine is switched to a baseband coding mode (Multi-Level transmission-3, MTL-3), the 5B data stream is coded by using MLT-3 coding and decoding, the signal frequency is reduced, finally the state machine is switched to parallel data conversion into serial data mode, the finally completed coded PCS serial signal is transmitted to a PCS module in DUT, the PCS module in DUT decodes the signal processed by the PCS layer bus driver, and packs the Ethernet data, and sent to the monitors at the opposite end through the interface, at which time the two monitors have two transaction level records, each transmitted to the scoreboard, which compares the two transaction level records, determining whether the Ethernet PHY function to be tested is accurate or not through a comparison result, so that the verification platform has a definite structure, is favorable for error positioning, meanwhile, a bus driver of an Ethernet PCS layer is added, so that the verification platform can accurately simulate the internal coding and decoding conditions of the Ethernet PHY, the method can solve the problem that the existing verification platform is insufficient in verifying the internal modules of the Ethernet PHY when verifying the functional accuracy of the PCS layer and the behavior verification of the Ethernet PHY in the error injection mechanism scene.
The embodiment of the application also provides an electronic device, which is used for executing the universal authentication platform based on the UVM Ethernet PHY, and FIG. 6 is a schematic structural diagram of an electronic device for implementing the embodiments of the application. The electronic device may have a relatively large difference due to different configurations or performances, and may include a processor (processor) 601, a communication interface (Communications Interface) 602, a memory (memory) 603, and a communication bus 604, where the processor 601, the communication interface 602, and the memory 603 complete communication with each other through the communication bus 604. The processor 601 may call a computer program stored in the memory 603 and capable of running on the processor 601, and specific execution steps may refer to the steps of the above-mentioned method embodiments for identifying a subclass service flow, and the same technical effects may be achieved, so that repetition is avoided, and detailed description is omitted herein.
It should be noted that, the electronic device in the embodiment of the present application includes: a server, a terminal, or other devices besides a terminal.
The above electronic device structure does not constitute a limitation of the electronic device, and the electronic device may include more or less components than illustrated, or may combine some components, or may be different in arrangement of components, for example, an input unit, may include a graphics processor (Graphics Processing Unit, GPU) and a microphone, and a display unit may configure a display panel in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit includes at least one of a touch panel and other input devices. Touch panels are also known as touch screens. Other input devices may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
The memory may be used to store software programs as well as various data. The memory may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory may include volatile memory or nonvolatile memory, or the memory may include both volatile and nonvolatile memory. The nonvolatile memory may be a Read-Only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDR AM), double data rate Synchronous DRAM (Double Data Rate SD RAM, ddr SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and direct memory bus RAM (Direct Rambus RA M, DRRAM).
The processor may include one or more processing units; optionally, the processor integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, and the like, and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor.
The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored, and the program or the instruction realizes the process of the embodiment of the verification method when being executed by a processor, and can achieve the same technical effect, so that repetition is avoided, and no further description is given here.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), including several instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the authentication platform and the authentication method described in the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims (10)

1. A universal UVM-based ethernet PHY verification platform, the verification platform comprising: the system comprises a network cable model, a scoreboard, 2 modules to be tested, a first sequence generator, a first Ethernet proxy module, a first physical interface, a second Ethernet proxy module and a second physical interface, wherein a first module to be tested in the 2 modules to be tested is arranged at one end of a verification platform, and a second module to be tested in the 2 modules to be tested is arranged at the other end of the verification platform; wherein,,
the first sequence generator is used for generating a sequence request, wherein the sequence request comprises a transaction-level sequence;
the first ethernet proxy module is configured to receive the sequence request, convert the sequence of the transaction level into pin level excitation, and transmit the pin level excitation to the first physical interface;
the first physical interface is used for outputting a first pin level signal to the first module to be tested based on the pin level excitation;
the first ethernet proxy module is further configured to obtain the first pin level signal output by the first physical interface, convert the first pin level signal into a first target sequence of a transaction level, and transmit the first target sequence to the scoreboard;
the first module to be tested is configured to encode the first pin level signal, convert the encoded data into serial data, and output the serial data to the network cable model;
the network cable model is used for transmitting the serial data to the second module to be tested;
the second module to be tested is used for obtaining and outputting a second pin level signal by decoding the received serial data;
the second ethernet proxy module is configured to obtain the second pin level signal output by the second module to be tested, convert the second pin level signal into a second target sequence of a transaction level, and transmit the second target sequence to the scoreboard;
and the scoreboard is used for comparing whether the first target sequence and the second target sequence are the same or not, and determining whether the function of the module to be tested is accurate or not according to the comparison result.
2. The authentication platform of claim 1, wherein the first ethernet proxy module comprises:
the first sequence generator is used for judging whether the sequence request is accepted or not, and forwarding the sequence request to the first driver under the condition that the sequence request is accepted;
the first driver is configured to convert the transaction-level sequence into pin-level stimuli and transmit the pin-level stimuli to the first physical interface;
and the first monitor is used for acquiring the first pin level signal output by the first physical interface, converting the first pin level signal into a first target sequence of a transaction level and transmitting the first target sequence to the scoreboard.
3. The authentication platform of claim 1, wherein the second ethernet proxy module comprises:
and the second monitor is used for acquiring the second pin level signal output by the second module to be tested, converting the second pin level signal into a second target sequence of a transaction level and transmitting the second target sequence to the scoreboard.
4. A verification platform according to any one of claims 1 to 3, further comprising: a first physical coding sublayer PCS bus driver and a third physical interface; wherein,,
the first ethernet proxy module is further configured to input the pin-level stimulus to the first PCS bus driver and transmit the sequence of transaction levels to the scoreboard;
the first PCS bus driver is used for encoding the pin-level excitation, converting parallel data obtained by encoding into serial data, and transmitting the serial data to a PCS module of the first module to be tested through the third physical interface;
the PCS module of the first module to be tested is used for decoding the received serial data and sending the Ethernet data obtained by decoding to the second Ethernet proxy module;
the second ethernet proxy module is further configured to convert the ethernet data into a transaction-level sequence and transmit the transaction-level sequence to the scoreboard;
the scoreboard is further configured to compare whether the sequence of the transaction level from the first ethernet proxy module is the same as the sequence of the transaction level from the second ethernet proxy module, and determine whether the function of the PCS module of the module to be tested is accurate according to the comparison result.
5. A verification method, characterized in that the verification method is applied to the verification platform of any one of claims 1 to 4, the verification method comprising:
the first Ethernet proxy module of the verification platform receives a sequence request, converts a sequence in the sequence request into pin-level excitation and transmits the pin-level excitation to a first physical interface of the verification platform;
the first physical interface outputs a first pin level signal to a first module to be tested of the verification platform based on pin level excitation;
the first Ethernet proxy module acquires the first pin level signal output by the first physical interface, converts the first pin level signal into a first target sequence of a transaction level, and transmits the first target sequence to a scoreboard of the verification platform;
the first module to be tested encodes the first pin level signal, converts the encoded data into serial data and outputs the serial data to a network cable model of the verification platform;
the network cable model transmits the serial data to a second module to be tested of the verification platform;
the second module to be tested obtains a second pin level signal and outputs the second pin level signal by decoding the received serial data;
the second Ethernet proxy module of the verification platform acquires the second pin level signal output by the second module to be tested, converts the second pin level signal into a second target sequence of a transaction level, and transmits the second target sequence to the scoreboard;
and the scoreboard compares whether the first target sequence and the second target sequence are the same, and determines whether the function of the module to be tested is accurate according to a comparison result.
6. The method of claim 5, wherein the first ethernet proxy module obtaining the first pin-level signal output by the first physical interface and converting the first pin-level signal into a first target sequence of transaction levels, transmitting the first target sequence to a scoreboard of the verification platform, comprising:
the first sequence generator of the first Ethernet proxy module judges whether to accept the sequence request, and forwards the sequence request to the first driver of the first Ethernet proxy module under the condition that the sequence request is accepted;
the first driver converting the transaction-level sequence into pin-level stimuli and transmitting to the first physical interface;
the first monitor of the first Ethernet proxy module acquires the first pin level signal output by the first physical interface, converts the first pin level signal into a first target sequence of a transaction level, and transmits the first target sequence to the scoreboard.
7. The method of claim 5, wherein the second ethernet proxy module of the verification platform obtains the second pin-level signal output by the second module under test and converts the second pin-level signal into a second target sequence of transaction level, and transmitting the second target sequence to the scoreboard, comprising:
and a second monitor of the second Ethernet proxy module acquires the second pin level signal output by the second module to be tested, converts the second pin level signal into a second target sequence of a transaction level, and transmits the second target sequence to the scoreboard.
8. The method as recited in claim 5, further comprising:
the first ethernet proxy module inputs the pin-level stimulus to a first physical coding sublayer PCS bus driver of the verification platform and transmits the transaction-level sequence to the scoreboard;
the first PCS bus driver encodes the pin-level excitation, converts parallel data obtained by encoding into serial data, and transmits the serial data to a PCS module of the first module to be tested through a third physical interface of the verification platform;
the PCS module of the first module to be tested decodes the received serial data and sends the Ethernet data obtained by decoding to the second Ethernet proxy module;
the second Ethernet proxy module converts the Ethernet data into a transaction-level sequence and transmits the transaction-level sequence to the scoreboard;
the scoreboard compares whether the transaction-level sequence from the first Ethernet proxy module is the same as the transaction-level sequence from the second Ethernet proxy module, and determines whether the PCS module of the module to be tested is accurate according to the comparison result.
9. An electronic device comprising the authentication platform of any one of claims 1 to 4.
10. A readable storage medium, characterized in that it stores thereon a program or instructions which, when executed by a processor, implement the steps of the authentication method according to any of claims 5 to 8.
CN202310269940.XA 2023-03-15 2023-03-15 UVM-based Ethernet PHY universal verification platform and verification method Pending CN116306479A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116775394A (en) * 2023-08-18 2023-09-19 腾讯科技(深圳)有限公司 Chip verification method, device, apparatus, storage medium and computer program product

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116775394A (en) * 2023-08-18 2023-09-19 腾讯科技(深圳)有限公司 Chip verification method, device, apparatus, storage medium and computer program product
CN116775394B (en) * 2023-08-18 2024-04-26 腾讯科技(深圳)有限公司 Chip verification method, device, apparatus, storage medium and computer program product

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