CN116306416A - Method, apparatus and medium for generating static timing analysis timing library - Google Patents

Abstract

Methods, apparatus, and media for generating a static timing analysis timing library are provided. The method comprises the following steps: acquiring a first timing library, wherein the first timing library comprises a first timing analysis result obtained by performing timing analysis on an integrated circuit design according to a first process/voltage/temperature setting, and the first timing analysis result comprises a first timing arc obtained by performing timing analysis on the design under the process/voltage/temperature setting corresponding to the first timing analysis result; for a first timing arc, identifying a timing arc type of the first timing arc and identifying a second timing arc to which a minimum end-to-end delay needs to be added by comparing the static timing analysis signature requirement with the timing arc type of the first timing arc; and processing the first time sequence analysis result of the second time sequence arc according to the second process/voltage/temperature setting so as to add the corresponding minimum end-to-end delay, and merging to obtain a second time sequence library after obtaining the second time sequence analysis result. This improves efficiency and saves resources.

Description

Method, apparatus and medium for generating static timing analysis timing library

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, and a medium for generating a static timing analysis timing library.

Background

With the increase of chip integration and the increase of chip design complexity, the time and economic cost of chip production and manufacturing also rapidly increase, so that it is necessary to perform full and complete simulation verification in the chip design stage to ensure that the designed chip meets the expected purpose and functional design after production and manufacturing. In addition, with the development of chip process and the diversification of chip application environments, various factors affecting chip performance possibly existing in the chip production and manufacturing links and chip applications need to be considered, and simulation verification is provided for the factors to cover possible circuit design defects and risks as much as possible. The chip simulation verification comprises the steps of performing static time sequence analysis and meeting the circuit signature requirement. And a timing library with the necessary and accurate information is critical to efficiently and reliably performing static timing analysis. However, the static timing analysis timing library in the prior art is generally generated based on characterization under a fixed working condition, may not meet the circuit signature requirement, and is difficult to cope with complex and changeable requirements caused by development of a chip process and diversification of a chip application environment.

To this end, the present application provides a method, apparatus, and medium for generating a static timing analysis timing library, so as to address technical difficulties in the prior art.

Disclosure of Invention

In a first aspect, the present application provides a method for generating a static timing analysis timing library. The method comprises the following steps: acquiring a first timing library, wherein the first timing library comprises a plurality of first timing analysis results obtained by performing timing analysis on an integrated circuit design according to at least one first process/voltage/temperature setting, and each first timing analysis result in the plurality of first timing analysis results comprises at least one first timing arc obtained by performing timing analysis on the integrated circuit design under the process/voltage/temperature setting corresponding to the first timing analysis result; identifying, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, a timing arc type of the first timing arc and identifying at least one second timing arc for which minimum end-to-end delay needs to be added by comparing static timing analysis signature requirements with the timing arc type of the first timing arc; processing a first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to at least one second process/voltage/temperature setting so as to add minimum end-to-end delay corresponding to the second time sequence arc and obtain at least one second time sequence analysis result corresponding to the at least one second time sequence arc; and combining the plurality of first time sequence analysis results and the at least one second time sequence analysis result to obtain a second time sequence library.

According to the method and the device for analyzing the signature requirements of the static time sequence, the signature requirements of the static time sequence analysis can be adapted, various process angle models, PVT conditions, fixed working conditions, process/voltage/temperature settings and the like can be flexibly adapted through at least one second process/voltage/temperature setting, so that the time sequence library with the minimum end-to-end delay is provided under a specified process angle, adverse effects of temperature reversal effects under advanced process procedures are overcome, various factors which possibly exist in a chip production and manufacturing link and chip application and influence chip performance are solved, verification efficiency of the static time sequence analysis is improved, and resources are saved.

In a possible implementation manner of the first aspect of the present application, the at least one first process/voltage/temperature setting is used to simulate a process condition, an operating voltage and an operating temperature of the integrated circuit design.

In a possible implementation manner of the first aspect of the present application, the at least one first process/voltage/temperature setting is based on a fixed operating condition, and the plurality of first timing analysis results are obtained by performing timing analysis on the integrated circuit design under the fixed operating condition.

In a possible implementation manner of the first aspect of the present application, the plurality of first timing analysis results are further based on an operating state of the integrated circuit design.

In a possible implementation form of the first aspect of the present application, the at least one second process/voltage/temperature setting is different from each of the at least one first process/voltage/temperature setting.

In a possible implementation manner of the first aspect of the present application, the at least one second timing analysis result includes timing constraint information not existing in the plurality of first timing analysis results, the timing constraint information being used to indicate that the integrated circuit design is to be subjected to timing analysis according to the at least one second process/voltage/temperature setting.

In a possible implementation manner of the first aspect of the present application, the at least one first process/voltage/temperature setting is the same first process/voltage/temperature setting.

In a possible implementation manner of the first aspect of the present application, the first timing library is a setup timing library and the same first process/voltage/temperature setting is a slow process/low voltage/high temperature setting, or the first timing library is a hold timing library and the same first process/voltage/temperature setting is a fast process/high voltage/low temperature setting.

In a possible implementation manner of the first aspect of the present application, the at least one first process/voltage/temperature setting includes one or more of the following: slow process/low voltage/high temperature setting, fast process/high voltage/low temperature setting, slow process/low voltage/low temperature setting, fast process/high voltage/high temperature setting.

In a possible implementation manner of the first aspect of the present application, the at least one first timing arc comprises at least one setup timing arc and/or at least one hold timing arc, and the at least one first process/voltage/temperature setting comprises a slow process/low voltage/high temperature setting and a fast process/high voltage/low temperature setting.

In a possible implementation manner of the first aspect of the present application, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, identifying a timing arc type of the first timing arc includes: a timing arc type of the first timing arc is identified based on pins, associated pins, timing sensitivity, and timing class of the first timing arc.

In a possible implementation form of the first aspect of the present application, the static timing analysis signature requires a timing arc type indicating the at least one second timing arc.

In a possible implementation manner of the first aspect of the present application, according to the at least one second process/voltage/temperature setting, processing a first timing analysis result of each of the at least one second timing arc to add a minimum end-to-end delay corresponding to the second timing arc includes: and respectively performing reduction processing on a plurality of original values in the first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to the at least one second process/voltage/temperature setting.

In a possible implementation manner of the first aspect of the present application, the plurality of original values includes a rising delay time, a falling delay time, a rising transition time, and a falling transition time.

In a possible implementation manner of the first aspect of the present application, each timing analysis result in the second timing library includes a tag for indicating whether the minimum end-to-end delay is added, and the tag of the at least one second timing analysis result in the second timing library is yes.

In a possible implementation manner of the first aspect of the present application, the integrated circuit design corresponds to a system-on-chip or a system-on-chip.

In a possible implementation manner of the first aspect of the present application, the static timing analysis signature requirement indicates whether the integrated circuit design has a violation timing and whether the setup timing and the hold timing of the integrated circuit design are qualified.

In a possible implementation form of the first aspect of the present application, the static timing analysis signature requirement is based at least on a process requirement associated with a temperature roll-over effect.

In a possible implementation manner of the first aspect of the present application, the static timing analysis signature requirement at least includes providing a timing library with minimum end-to-end delay at a specified process/voltage/temperature setting, the at least one second process/voltage/temperature setting includes the specified process/voltage/temperature setting, and the at least one first process/voltage/temperature setting does not include the specified process/voltage/temperature setting.

In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.

In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of generating a new timing library based on an existing timing library and signature requirements according to an embodiment of the present application;

FIG. 2 is a flow chart of a method for generating a static timing analysis timing library according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.

FIG. 1 is a schematic diagram of generating a new timing library based on an existing timing library and signature requirements according to an embodiment of the present application. As shown in fig. 1, the existing timing library 110 is imported into a timing library analysis and generation module 120 to obtain a new timing library 140. The timing base analysis and generation module 120 also receives signature requirements 130. The timing base analysis and generation module 120 obtains a new timing base 140 based on the existing timing base 110 and the signature requirements 130. Here, both the existing timing library 110 and the new timing library 140 are used for static timing analysis (static timing analysis, STA). Static timing analysis may be used to analyze, modulate, and confirm the timing performance of the gate design. In general, static timing analysis examines two parameters for the same clock edge, one is the setup time (setup time), i.e., the time that the data must be stable before the clock source arrives, and the other is the hold time (hold time), i.e., the time that the data must be stable after the clock source arrives. Static timing analysis analyzes all possible timing paths to verify whether there is a violation of the timing therein, including to verify the setup time and hold time therein. The timing signature (timing signature) requirement can be met if the test result of the static timing analysis is qualified. Various factors affecting chip performance may exist in chip manufacturing and chip applications, which may make the designed chip undesirable for its intended purpose and functional design, and the provision of timing libraries meeting specific requirements during the chip design stage and the use of such timing libraries for static timing analysis helps to reduce the risk of die failure and to cover possible circuit design defects and risks. For example, process variations may affect chip performance, different process conditions, different process recipes may necessitate corresponding timing signature requirements and the provision of timing libraries that meet certain requirements. In addition, variations in chip operating voltage and chip operating temperature may also affect chip performance, and thus need to be considered in chip simulation verification and static timing analysis. In order to ensure that the designed chip can accommodate possible process variations, as well as variations in chip operating voltage and chip operating temperature, it is necessary to consider, for example, on-chip variations (on chip variation, OCV), i.e., differences between chip performance at different locations due to on-chip process variations, when performing static timing analysis using a static timing analysis timing library; the effect of, for example, process/voltage/temperature (Process Voltage Temperature, PVT) settings also needs to be taken into account. The process/voltage/temperature settings include three elements, collectively referred to as PVT, process, voltage (voltage) and temperature (temperature). The process elements in the process/voltage/temperature setting mainly consider process deviation, and the possible reasons for the process deviation are deviation in the production process between different wafers and different batches, for example, deviation of chips caused by differences of processes, machines and the like in the production process, and for example, non-uniform process doping in the manufacturing process. The voltage element in the process/voltage/temperature setting is the chip operating voltage. The temperature element in the process/voltage/temperature setting is the chip operating temperature. A process/voltage/temperature setting is understood to be a basic model or a process corner (process corner). The performance of the same chip under different process conditions, different working voltages and different temperatures is simulated through various process angles, and if the chip design can achieve timing sequence convergence under all process angles, namely the performance of the chip design under various process angles, limit voltages and limit temperatures is simulated, so that the chip design success rate is improved and the difficulty of the chip design is reduced. In addition, the static time sequence analysis is performed by utilizing the static time sequence analysis time sequence library, and more reference factors such as the working state of a chip and the like can be further included. Static timing analysis generally performs timing analysis on models under two extreme PVT conditions, one is a slow process corner model (Slow Corner Model), which refers to a model under slow process, low voltage and high temperature; the other is a fast process corner model (Fast Corner Model), which refers to a model at fast process, high voltage, low temperature. Generally, the timing signature requirements associated with static timing analysis employ a slow process corner model at the time of analysis setup, which allows for extreme settings in view of extreme PVT conditions; a fast process corner model was used in analyzing hold time. Static timing analysis can give the maximum setup time under the slow process corner model and the minimum hold time under the fast process corner model. Static timing analysis can also employ more models and more PVT settings to simulate the performance of chip designs under various process corner and threshold voltage, temperature conditions.

With continued reference to fig. 1, under the prior art process, a temperature inversion effect may occur, thereby affecting the process corner model that performs static timing analysis to satisfy the timing signature requirement, and thus, placing higher demands on the timing library. For example, it is desirable to provide a timing library with a minimum end-to-end Delay (Min Delay) at a given process corner for satisfying timing signature requirements at that given process corner. Here, the minimum end-to-end Delay is relative to the maximum end-to-end Delay (Max Delay). End-to-end delay may be understood as the size of the delay from end to end. The minimum end-to-end delay is a timing constraint that affects the hold relationship because the minimum delay corresponds to the worst case hold relationship. The maximum end-to-end delay affects the build relationship because the maximum delay corresponds to the worst build relationship. Aiming at the temperature reversal effect, the time sequence analysis results under two fixed working conditions are generally considered, one is slow process, low voltage and low temperature, the time delay influenced by the temperature reversal effect under the fixed working condition is the largest, and the performance of the set-up time is poor; the other is a fast process, high voltage, high temperature, such that the delay time under fixed operating conditions, which is affected by the temperature reversal effect, is minimal and the performance of the hold time is poor. As mentioned above, static timing analysis generally performs timing analysis on models under two extreme PVT conditions, one is a slow process corner model (Slow Corner Model), which refers to models under slow process, low voltage, high temperature; the other is a fast process corner model (Fast Corner Model), which refers to a model at fast process, high voltage, low temperature. Thus, static timing analysis timing libraries are typically generated based on characterization under fixed operating conditions, such as the existing timing library 110 shown in FIG. 1. For example, the existing timing library 110 may include timing analysis results at slow process, low voltage, high temperature, i.e., slow process corner model, and at fast process, high voltage, low temperature, i.e., fast process corner model, respectively. The existing timing library 110 may not provide timing analysis results for temperature reversal effects or the existing timing library 110 may include only timing analysis results under fixed operating conditions for temperature reversal effects in advanced process flows (e.g., including timing analysis results at slow, low voltage, low temperature and fast, high voltage, high temperature, respectively). However, the process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc., referenced when creating the existing timing library 110 may not meet the specified process corner or other characteristic requirements imposed on the timing library as required by the current circuit signature requirements. In addition, the development of the chip process may bring new process conditions and new process, which may necessitate the corresponding timing signature requirements and the provision of timing libraries meeting specific requirements. In addition, the diversification of the chip application environment may place new demands on the static timing analysis and timing libraries, for example, the application environment of the high-speed digital communication chip may place specific demands on the timing libraries. In addition, with the popularization and development of advanced process, the influence of temperature reversal effect on chip performance needs to be paid more attention, and therefore, a timing library with minimum end-to-end delay needs to be provided under a specified process corner for satisfying the timing signature requirement under the specified process corner. The existing timing library 110 may not itself meet the requirement of providing a minimum end-to-end delay at a given process corner, or may simply include timing analysis results under fixed operating conditions that do not meet the requirement of the given process corner. In summary, there may be a gap between the timing analysis results provided by the existing timing library 110 and the specified process corner or other characteristics required by the current circuit signature requirements, and thus the simulation verification results obtained based on the static timing analysis performed by the existing timing library 110 may not be sufficient to meet the current circuit signature requirements or timing signature requirements, or it may be difficult to fully consider various factors that may exist in the chip manufacturing process and chip applications that affect the performance of the chip.

With continued reference to FIG. 1, a new timing library 140 is obtained based on the existing timing library 110 and signature requirements 130 by the timing library analysis and generation module 120 based on the existing timing library 110. The existing timing library 110 includes a timing analysis result a 112, a timing analysis result B114, and a timing analysis result C116. The timing analysis results provided by the conventional timing library 110 may be characterization results obtained under fixed working conditions, for example, the timing analysis result a 112 corresponds to static timing analysis under a slow process, low voltage, and high temperature, that is, under a slow process corner model, the timing analysis result B114 corresponds to static timing analysis under a fast process, high voltage, and low temperature, that is, under a fast process corner model, and the timing analysis result C116 corresponds to other process corners, so that performance of the same chip (or chip design) under different process conditions, different working voltages, and different temperatures is simulated through the various process corners corresponding to the timing analysis result a 112, the timing analysis result B114, and the timing analysis result C116. As described above, the timing analysis results provided by the prior timing library 110 may not meet the specific requirements imposed by the signature requirements 130 on the timing library and static timing analysis. For example, signature requirements 130 may require that the chip design achieve timing closure under a particular process corner model that is not covered by timing analysis results provided by the existing timing library 110. As another example, signature requirements 130 may require overcoming adverse effects of temperature reversal effects in advanced process flows or chip designs to be adequate for certain application environments, and thus require providing timing libraries with minimal end-to-end delays at a given process corner, where the timing analysis results provided by existing timing libraries 110 do not have such characteristics. The use of off-the-shelf timing analysis results may better save verification time and improve verification efficiency than re-creating a new timing library according to the signature requirements 130, for which purpose the timing library analysis and generation module 120 may be utilized to import the existing timing library 110 and receive the signature requirements 130, thereby generating a new timing library 140 based on the existing timing library 110 and the signature requirements 130. In this way, the new timing library 140 can retain the existing timing analysis results of the existing timing library 110, and can provide new timing analysis results in combination with the signature requirement 130, and the new timing analysis results are obtained on the existing timing analysis results, so that it is beneficial to quickly obtain the new timing library 140, and to save resources and time. As shown in fig. 1, the new timing library 140 includes a plurality of timing analysis results, among which there are timing analysis result a 112, timing analysis result B114, and timing analysis result C116, that is, the existing timing analysis result of the existing timing library 110. The new timing library 140 further includes a timing analysis result D142, a timing analysis result E144, and a timing analysis result F146. The timing analysis result D142, the timing analysis result E144, and the timing analysis result F146 are new timing analysis results with respect to the existing timing analysis results (the timing analysis result a 112, the timing analysis result B114, and the timing analysis result C116) of the timing library 110. For example, assuming that signature 130 requires overcoming the adverse effects of temperature reversal effects under advanced process conditions and requires providing a timing library with minimal end-to-end delay at a given process corner, timing analysis result D142 corresponds to performing static timing analysis at slow process, low voltage, low temperature (maximum delay affected by temperature reversal effects under such fixed operating conditions, poor performance of setup time), and timing analysis result E144 corresponds to performing static timing analysis at fast process, high voltage, high temperature (minimum delay affected by temperature reversal effects under such fixed operating conditions, poor performance of hold time). The timing analysis result F146 corresponds to static timing analysis under other fixed operating conditions (e.g., corresponding to a specified process corner) to better adapt the signature requirements 130. It should be appreciated that with the popularization and development of advanced process, such as development and application of lower-scale process, the temperature reversal effect plays a greater role in influencing the performance of the chip, and the existing timing library 110 as shown in fig. 1 does not provide a timing library with minimum end-to-end delay at a given process angle, so that the static timing analysis based on the existing timing library 110 is also difficult to satisfy the timing signature requirements such as signature requirements 130 at the given process angle. The method for generating the static timing analysis timing library is described in further detail below in conjunction with FIG. 2.

Fig. 2 is a flowchart of a method for generating a static timing analysis timing library according to an embodiment of the present application. As shown in fig. 2, the method includes the following steps.

Step S202: a first timing library is obtained, wherein the first timing library comprises a plurality of first timing analysis results obtained by performing timing analysis on an integrated circuit design according to at least one first process/voltage/temperature setting, and each first timing analysis result in the plurality of first timing analysis results comprises at least one first timing arc obtained by performing timing analysis on the integrated circuit design under the process/voltage/temperature setting corresponding to the first timing analysis result.

Step S204: for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, identifying a timing arc type of the first timing arc and identifying at least one second timing arc for which a minimum end-to-end delay needs to be added by comparing static timing analysis signature requirements with the timing arc type of the first timing arc.

Step S206: and processing the first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to at least one second process/voltage/temperature setting so as to add the minimum end-to-end delay corresponding to the second time sequence arc and obtain at least one second time sequence analysis result corresponding to the at least one second time sequence arc.

Step S208: and combining the plurality of first time sequence analysis results and the at least one second time sequence analysis result to obtain a second time sequence library.

Referring to the steps described above, the first timing library represents the results of the ready timing analysis, and the first timing library may be, for example, the existing timing library 110 shown in fig. 1. In step S202, the first timing library is obtained, that is, a plurality of first timing analysis results obtained by performing timing analysis on the integrated circuit design according to at least one first process/voltage/temperature setting are obtained. Each first timing analysis result of the plurality of first timing analysis results includes at least one first timing arc obtained by performing timing analysis on the integrated circuit design at a process/voltage/temperature setting corresponding to the first timing analysis result. Here, the first timing arc refers to timing arc (timing arc) data for performing static timing analysis. The time sequence arc data refers to the data of delay information between two nodes, and can be divided into connection delay and unit delay. Where link latency generally refers to the delay information between the output port and the network load. The unit delay refers to delay information from the input port to the output port. Each of the plurality of first timing analysis results included in the first timing library is obtained by performing a timing analysis at a process/voltage/temperature setting corresponding to the first timing analysis result, and the at least one first process/voltage/temperature setting represents a process/voltage/temperature setting referenced when creating the first timing library, which may be more generally understood as a process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc. referenced when creating the first timing library. Next, in step S204, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, a timing arc type of the first timing arc is identified, and at least one second timing arc for which a minimum end-to-end delay needs to be added is identified by comparing a static timing analysis signature requirement with the timing arc type of the first timing arc. As described above, the timing analysis results provided by existing timing libraries may not meet the specific requirements imposed on the timing libraries and static timing analysis by current signature requirements. Therefore, the timing analysis result provided by the first timing library may not meet the static timing analysis signature requirement. Particularly in view of the popularization and development of advanced process flows, such as the development and application of lower-scale process flows, temperature reversal effects play a greater role in influencing the performance of chips and thus require the provision of timing libraries with minimal end-to-end delays at a given process corner. For this purpose, by identifying the timing arc type of the first timing arc and by comparing the static timing analysis signature requirement with the timing arc type of the first timing arc, it is possible to efficiently identify the timing arc that needs to be processed, i.e. at least one second timing arc that needs to be added with minimum end-to-end delay, from the existing timing library, i.e. the first timing library. And the method can flexibly combine the static time sequence analysis signature requirement to identify the time sequence arc needing to be processed, thereby better adapting to the current signature requirement.

In step S206, according to at least one second process/voltage/temperature setting, the first timing analysis result of each second timing arc in the at least one second timing arc is processed so as to add a minimum end-to-end delay corresponding to the second timing arc, so as to obtain at least one second timing analysis result corresponding to the at least one second timing arc. In step S204, the signature requirement is analyzed by comparing the static timing sequence with the timing sequence arc type of the first timing sequence arc, so that the timing sequence arc needing to be processed, that is, at least one second timing sequence arc needing to be added with minimum end-to-end delay, is effectively identified from the existing timing sequence library, that is, the first timing sequence library. Next, in step S206, the first timing analysis result of each second timing arc of the at least one second timing arc is processed according to at least one second process/voltage/temperature setting, so as to add a minimum end-to-end delay corresponding to the second timing arc. In this way, not only is a minimum end-to-end delay corresponding to the second timing arc added, thereby facilitating meeting the requirements with minimum end-to-end delay, but also the process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc. can be flexibly adapted in combination with at least one second process/voltage/temperature setting by processing according to at least one second process/voltage/temperature setting. And the first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc is processed, so that the first time sequence analysis result of the first time sequence library can be utilized, resources are saved, and the rapid generation of a new time sequence library is facilitated. Next, in step S208, the plurality of first timing analysis results and the at least one second timing analysis result are combined to obtain a second timing library. The second timing library thus obtained represents a new timing library, such as new timing library 140 shown in FIG. 1. And the second timing library integrates the ready-made timing analysis results included in the first timing library, i.e., the plurality of first timing analysis results, and the new timing analysis results, i.e., the at least one second timing analysis result. Wherein the at least one second timing analysis result not only adds a minimum end-to-end delay corresponding to the second timing arc, but also by processing in accordance with at least one second process/voltage/temperature setting. Therefore, the second timing library can adapt to the static timing analysis signature requirements, including combining the static timing analysis signature requirements to identify the timing arcs to be processed, and can flexibly adapt to various process corner models, PVT conditions, fixed working conditions, process/voltage/temperature settings, etc. through at least one second process/voltage/temperature setting, thereby being beneficial to providing the timing library with minimum end-to-end delay under a specified process corner, further overcoming adverse effects of temperature reversal effect under advanced process, and being beneficial to coping with various factors which may exist in chip production manufacturing links and chip applications and affect chip performance.

In one possible implementation, the at least one first process/voltage/temperature setting is used to simulate process conditions, operating voltages, and operating temperatures of the integrated circuit design. The at least one first process/voltage/temperature setting represents a process/voltage/temperature setting referenced when creating the first timing library, and may be more generally understood as a process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc. referenced when creating the first timing library. The process conditions of the integrated circuit design may be understood to include process variations, which may be caused by variations in the production process between different wafers and different batches, for example, variations in the chip caused by differences in the process, the machine, etc., and for example, non-uniformity in process doping during the manufacturing process. A process/voltage/temperature setting is understood to be a basic model or a process corner. The performance of the same chip under different process conditions, different working voltages and different temperatures is simulated through various process angles. In some embodiments, the at least one first process/voltage/temperature setting is based on a fixed operating condition, and the plurality of first timing analysis results are obtained by timing analysis of the integrated circuit design under the fixed operating condition. The fixed operating conditions may be fixed process corner models, such as slow process corner models, i.e. models at slow process, low voltage, high temperature, and fast process corner models, i.e. models at fast process, high voltage, low temperature. In some embodiments, the plurality of first timing analysis results is further based on an operating state of the integrated circuit design.

In one possible embodiment, the at least one second process/voltage/temperature setting is different from each of the at least one first process/voltage/temperature setting. The at least one first process/voltage/temperature setting represents a process/voltage/temperature setting referenced when creating the first timing library, and may be more generally understood as a process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc. referenced when creating the first timing library. In the generation process of the second time sequence library, various process corner models, PVT conditions, fixed working conditions, process/voltage/temperature settings and the like are flexibly adapted through at least one second process/voltage/temperature setting. The at least one second process/voltage/temperature setting is here different from each of the at least one first process/voltage/temperature setting, which means that the first time sequence analysis result in which each of the at least one second time sequence arc is located is processed according to the at least one second process/voltage/temperature setting, with a process/voltage/temperature setting different from that used when creating the first time sequence library.

In one possible implementation, the at least one second timing analysis result includes timing constraint information not present in the plurality of first timing analysis results, the timing constraint information being used to indicate timing analysis of the integrated circuit design in accordance with the at least one second process/voltage/temperature setting. Therefore, by the method for generating the static time sequence analysis time sequence library provided by the embodiment of the application, the finally obtained second time sequence library contains the time sequence constraint information which does not exist in the first time sequence library, so that the second time sequence library is obtained by processing again on the basis of the first time sequence library, and the time sequence signature requirement which is difficult to meet by the first time sequence library is met. For example, the timing constraint information may correspond to a requirement for a timing library to overcome adverse effects of temperature reversal effects in advanced process flows, i.e., to provide a timing library with minimal end-to-end delay at a given process corner. Taking fig. 1 as an example, the timing analysis results a 112, B114 included in the existing timing library 110 and the timing analysis result C116 do not have specific timing constraint information (the timing library with the minimum end-to-end delay is provided under the specified process angle), while the timing analysis result D142 in the new timing library 140 corresponds to performing static timing analysis under the slow process, low voltage and low temperature (the delay affected by the temperature inversion effect is the largest under such fixed working condition, the performance of the setup time is poor), and the timing analysis result E144 corresponds to performing static timing analysis under the fast process, high voltage and high temperature (the delay affected by the temperature inversion effect is the smallest under such fixed working condition, the performance of the hold time is poor). Therefore, the new timing library 140 includes specific timing constraint information that is not present in the existing timing library 110, so that the new timing library 140 can better overcome the adverse effect of the temperature inversion effect in the advanced process to meet the current signature requirement.

In one possible embodiment, the at least one first process/voltage/temperature setting is the same first process/voltage/temperature setting. Thus, the first timing library is analyzed under the same first process/voltage/temperature setting to obtain the plurality of first timing analysis results. For example, the first timing library may employ a slow process corner model or contain only build timing arcs, or the first timing library may employ a fast process corner model or contain only hold timing arcs. In some embodiments, the first timing library is a setup timing library and the same first process/voltage/temperature setting is a slow process/low voltage/high temperature setting, or the first timing library is a hold timing library and the same first process/voltage/temperature setting is a fast process/high voltage/low temperature setting. In this way, the first timing library can perform timing analysis on models under two extreme PVT conditions. One is a slow process corner model (Slow Corner Model), which refers to a model at slow process, low voltage, high temperature. The other is a fast process corner model (Fast Corner Model), which refers to a model at fast process, high voltage, low temperature.

In one possible embodiment, the at least one first process/voltage/temperature setting comprises one or more of the following: slow process/low voltage/high temperature setting, fast process/high voltage/low temperature setting, slow process/low voltage/low temperature setting, fast process/high voltage/high temperature setting. It should be appreciated that the first timing library and the associated at least one first process/voltage/temperature setting correspond to existing timing analysis results. The existing timing analysis results provided by the first timing library and the associated at least one first process/voltage/temperature setting may not meet the specific requirements of the timing library set forth by the static timing analysis signature requirements, such as providing the timing library with minimal end-to-end delay at a given process corner. The second timing library can adapt to static timing analysis signature requirements, including combining the static timing analysis signature requirements to identify timing arcs to be processed, and can flexibly adapt to various process corner models, PVT conditions, fixed working conditions, process/voltage/temperature settings, etc. through at least one second process/voltage/temperature setting, thereby being beneficial to providing the timing library with minimum end-to-end delay under a specified process corner, further overcoming adverse effects of temperature reversal effect under advanced process, and being beneficial to coping with various factors which may exist in chip production and manufacturing links and chip applications and influence chip performance.

In one possible embodiment, the at least one first timing arc comprises at least one setup timing arc and/or at least one hold timing arc, the at least one first process/voltage/temperature setting comprising a slow process/low voltage/high temperature setting and a fast process/high voltage/low temperature setting. It should be appreciated that the first timing library and the associated at least one first process/voltage/temperature setting correspond to existing timing analysis results. The existing timing analysis results provided by the first timing library and the associated at least one first process/voltage/temperature setting may not meet the specific requirements of the timing library set forth by the static timing analysis signature requirements, such as providing the timing library with minimal end-to-end delay at a given process corner. The second timing library can adapt to static timing analysis signature requirements, including combining the static timing analysis signature requirements to identify timing arcs to be processed, and can flexibly adapt to various process corner models, PVT conditions, fixed working conditions, process/voltage/temperature settings, etc. through at least one second process/voltage/temperature setting, thereby being beneficial to providing the timing library with minimum end-to-end delay under a specified process corner, further overcoming adverse effects of temperature reversal effect under advanced process, and being beneficial to coping with various factors which may exist in chip production and manufacturing links and chip applications and influence chip performance.

In one possible implementation, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, identifying a timing arc type of the first timing arc includes: the timing arc type of the first timing arc is identified based on a pin (pin), an associated pin (correlated pin), a timing sense (timing sense), and a timing type (timing type) of the first timing arc. Here, timing sensitivity refers to the characteristic that a timing arc has as to how the output varies for different transition types of the input. The timing class refers to information such as a combination class that the timing arc has. The timing arc type of the first timing arc can be identified from the information of the first timing arc. Thereby facilitating the identification of the timing arcs that need to be processed in conjunction with the static timing analysis signature requirements. In some embodiments, the static timing analysis signature requires a timing arc type that indicates the at least one second timing arc. In this manner, adapting the static timing analysis signature requirements is facilitated, including combining the static timing analysis signature requirements to identify timing arcs that need to be processed.

In one possible implementation, processing the first timing analysis result of each of the at least one second timing arc according to the at least one second process/voltage/temperature setting to add a minimum end-to-end delay corresponding to the second timing arc includes: and respectively performing reduction processing on a plurality of original values in the first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to the at least one second process/voltage/temperature setting. In this way, the generation of new timing analysis results, i.e. the addition of a minimum end-to-end delay corresponding to the second timing arc, is conveniently achieved by the subtraction process on the basis of the existing timing analysis results, i.e. the plurality of original values. In some embodiments, the plurality of primitive values includes a rise delay time (rise delay), a fall delay time (fall delay), a rise transition time (rise transition), and a fall transition time (fall transition). Here, the rising delay time and the falling delay time are used to describe delay characteristics of the timing arc, and the rising transition time and the falling transition time are used to describe level inversion characteristics of the timing arc. By performing the subtraction processing on the plurality of original values, the delay characteristic and the level inversion characteristic of the timing arc are changed, so that the minimum end-to-end delay corresponding to the second timing arc can be added. In some embodiments, each of the second timing analysis results in the second timing library includes a tag indicating whether a minimum end-to-end delay is added, the tag of the at least one second timing analysis result in the second timing library being yes. In this way, the timing arc with the smallest end-to-end delay can be better identified by tag filtering.

In one possible implementation, the integrated circuit design corresponds to a system-on-chip or a system-on-chip. It should be appreciated that the integrated circuit design may correspond to any suitable chip application, such as high-speed digital communications.

In one possible implementation, the static timing analysis signature requirement indicates whether the integrated circuit design has violating timing and whether the setup and hold timings of the integrated circuit design are verified as acceptable. Therefore, the static time sequence analysis signature is favorably adapted to meet the complex and changeable requirements caused by the development of chip process procedures, the diversification of chip application environments and the like.

In one possible implementation, the static timing analysis signature requirement is based at least on process requirements associated with a temperature roll-over effect. Thus, the influence of the temperature reversal effect on the performance of the chip is fully considered.

In one possible implementation, the static timing analysis signature requirement includes at least providing a timing library with minimal end-to-end delay at a specified process/voltage/temperature setting, the at least one second process/voltage/temperature setting includes the specified process/voltage/temperature setting, and the at least one first process/voltage/temperature setting does not include the specified process/voltage/temperature setting. The at least one first process/voltage/temperature setting represents a process/voltage/temperature setting referenced when creating the first timing library, and may be more generally understood as a process corner model, PVT conditions, fixed operating conditions, process/voltage/temperature settings, etc. referenced when creating the first timing library. The existing timing analysis results provided by the first timing library and the associated at least one first process/voltage/temperature setting may not meet the specific requirements of the timing library set forth by the static timing analysis signature requirements. Here, the static timing analysis signature requirement includes at least providing a timing library with minimal end-to-end delay at a specified process/voltage/temperature setting, but the at least one first process/voltage/temperature setting does not include the specified process/voltage/temperature setting, making it difficult to satisfy the static timing analysis signature requirement with the first timing library. To this end, by a method for generating a static timing analysis timing library provided by embodiments of the present application, the second timing library is obtained, and by processing according to at least one second process/voltage/temperature setting, the static timing analysis signature requirements can be flexibly adapted in combination with the at least one second process/voltage/temperature setting. The at least one second process/voltage/temperature setting includes the specified process/voltage/temperature setting, which means that the static timing analysis using the second timing library can meet the static timing analysis signature requirement, thereby facilitating the provision of the timing library with minimal end-to-end delay at a specified process corner to overcome adverse effects of temperature reversal effects under advanced process flows, and facilitating the coping with various factors that may exist in chip manufacturing links and chip applications that affect chip performance.

Fig. 3 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 300 includes: one or more processors 310, a communication interface 320, and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected by a bus 340. Optionally, the computing device 300 may further include an input/output interface 350, where the input/output interface 350 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 310 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 300 performing various operations may refer to specific details in the above-described embodiments, such as the processor 310 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the embodiment of the present application, the computing device 300 may be used to implement some or all of the functions of one or more components in the apparatus embodiments described above, and the communication interface 320 may be used in particular for communication functions and the like necessary for implementing the functions of these apparatuses, components, and the processor 310 may be used in particular for processing functions and the like necessary for implementing the functions of these apparatuses, components.

It should be appreciated that the computing device 300 of fig. 3 may include one or more processors 310, and that the plurality of processors 310 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or the plurality of processors 310 may constitute a processor sequence or processor array, or the plurality of processors 310 may be separated into primary and secondary processors, or the plurality of processors 310 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 300 shown in FIG. 3, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 300 may include more or fewer components than shown in fig. 3, or combine certain components, or split certain components, or have a different arrangement of components.

Processor 310 may take many specific forms, for example, processor 310 may include one or more combinations of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and embodiments of the present application are not limited in detail. Processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be formed by a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 310 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 320 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.

The memory 330 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 330 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 330 may also be used to store program code and data such that processor 310 invokes the program code stored in memory 330 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 300 may contain more or fewer components than shown in FIG. 3, or may have a different configuration of components.

Bus 340 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 340 may be divided into an address bus, a data bus, a control bus, and the like. The bus 340 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 3 for clarity of illustration, but does not represent only one bus or one type of bus.

The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated. Embodiments of the present application also provide a system that includes a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.

Claims (20)

1. A method for generating a static timing analysis timing library, the method comprising:

acquiring a first timing library, wherein the first timing library comprises a plurality of first timing analysis results obtained by performing timing analysis on an integrated circuit design according to at least one first process/voltage/temperature setting, and each first timing analysis result in the plurality of first timing analysis results comprises at least one first timing arc obtained by performing timing analysis on the integrated circuit design under the process/voltage/temperature setting corresponding to the first timing analysis result;

Identifying, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, a timing arc type of the first timing arc and identifying at least one second timing arc for which minimum end-to-end delay needs to be added by comparing static timing analysis signature requirements with the timing arc type of the first timing arc;

processing a first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to at least one second process/voltage/temperature setting so as to add minimum end-to-end delay corresponding to the second time sequence arc and obtain at least one second time sequence analysis result corresponding to the at least one second time sequence arc;

combining the plurality of first timing analysis results and the at least one second timing analysis result to obtain a second timing library,

wherein identifying, for each first timing arc included in each of the plurality of first timing analysis results included in the first timing library, a timing arc type of the first timing arc includes:

a timing arc type of the first timing arc is identified based on pins, associated pins, timing sensitivity, and timing class of the first timing arc.

2. The method of claim 1, wherein the at least one first process/voltage/temperature setting is used to simulate process conditions, operating voltages, and operating temperatures of the integrated circuit design.

3. The method of claim 2, wherein the at least one first process/voltage/temperature setting is based on a fixed operating condition, the plurality of first timing analysis results being obtained by timing analysis of the integrated circuit design under the fixed operating condition.

4. The method of claim 3, wherein the plurality of first timing analysis results are further based on an operating state of the integrated circuit design.

5. The method of claim 1, wherein the at least one second process/voltage/temperature setting is different from each of the at least one first process/voltage/temperature setting.

6. The method of claim 5, wherein the at least one second timing analysis result includes timing constraint information not present in the plurality of first timing analysis results, the timing constraint information being used to indicate timing analysis of the integrated circuit design in accordance with the at least one second process/voltage/temperature setting.

7. The method of claim 5, wherein the at least one first process/voltage/temperature setting is the same first process/voltage/temperature setting.

8. The method of claim 7, wherein the first timing library is a setup timing library and the same first process/voltage/temperature setting is a slow process/low voltage/high temperature setting, or wherein the first timing library is a hold timing library and the same first process/voltage/temperature setting is a fast process/high voltage/low temperature setting.

9. The method of claim 5, wherein the at least one first process/voltage/temperature setting comprises one or more of: slow process/low voltage/high temperature setting, fast process/high voltage/low temperature setting, slow process/low voltage/low temperature setting, fast process/high voltage/high temperature setting.

10. The method of claim 5, wherein the at least one first timing arc comprises at least one setup timing arc and/or at least one hold timing arc, the at least one first process/voltage/temperature setting comprising a slow process/low voltage/high temperature setting and a fast process/high voltage/low temperature setting.

11. The method of claim 1, wherein the static timing analysis signature requirement indicates a timing arc type of the at least one second timing arc.

12. The method of claim 5, wherein processing the first timing analysis results for each of the at least one second timing arc to add a minimum end-to-end delay corresponding to the second timing arc according to the at least one second process/voltage/temperature setting comprises:

and respectively performing reduction processing on a plurality of original values in the first time sequence analysis result of each second time sequence arc in the at least one second time sequence arc according to the at least one second process/voltage/temperature setting.

13. The method of claim 11, wherein the plurality of raw values comprises a rise delay time, a fall delay time, a rise transition time, and a fall transition time.

14. The method of claim 12, wherein each timing analysis result in the second timing library includes a tag indicating whether a minimum end-to-end delay is added, the tag of the at least one second timing analysis result in the second timing library being yes.

15. The method of claim 1, wherein the integrated circuit design corresponds to a system-on-chip or a system-on-chip.

16. The method of claim 1, wherein the static timing analysis signature requirement indicates whether the integrated circuit design has a violation timing and whether a setup timing and a hold timing of the integrated circuit design are verified.

17. The method of claim 1, wherein the static timing analysis signature requirement is based at least on a process requirement associated with a temperature roll-over effect.

18. The method of claim 5, wherein the static timing analysis signature requirements include at least providing a timing library with minimal end-to-end delay at a specified process/voltage/temperature setting, the at least one second process/voltage/temperature setting includes the specified process/voltage/temperature setting, and the at least one first process/voltage/temperature setting does not include the specified process/voltage/temperature setting.

19. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 18 when executing the computer program.

20. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 18.

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