CN116304502A - Sparse fast Fourier transform FPGA implementation method based on insert ordering - Google Patents

Abstract

The invention discloses a sparse fast Fourier transform FPGA implementation method based on insertion ordering, and belongs to the fields of digital signal processing and embedding. The method for calculating the amplitude based on the insert ordering replaces the method for calculating the average in the traditional method, and the sparse fast Fourier transform with higher amplitude calculation accuracy is realized. And (3) carrying out buffering, rearrangement, filtering, downsampling, FFT/IFFT, threshold selection, positioning circulation and sequencing estimation on the signals with sparse frequency domains, and finally outputting the results. Compared with the traditional sparse fast Fourier transform, the method can more rapidly finish operations such as caching, rearrangement, filtering, downsampling, threshold selection and the like, and the calculated fault tolerance rate is remarkably improved.

Description

Sparse fast Fourier transform FPGA implementation method based on insert ordering

Technical Field

The invention belongs to the field of digital signal processing and embedded systems, and particularly relates to a sparse fast Fourier transform FPGA implementation method based on insert ordering.

Background

Discrete fourier transform (Discrete Fourier Transform, DFT) is one of the most fundamental mathematical theoretical algorithms in the digital signal processing arts, playing a role in the analysis, design and application of discrete-time signal systemsAn extremely important role is played. The most widespread method of computing DFT is the fast fourier transform (Fast Fourier Transform, FFT). For a signal of length N, the time complexity of the FFT algorithm is O (N log N). Complexity O (log N) with direct computation DFT ² ) In comparison, the FFT algorithm greatly simplifies the operation process, the operation time can be shortened by one to two orders of magnitude, and the revolutionary progress of the signal processing technology is greatly promoted.

However, with rapid developments in radar, sonar, navigation, etc., the data that needs to be processed is getting larger and larger. Since the time complexity of the FFT algorithm is proportional to the length of the signal, the difficulty of hardware implementation is very high when the number of points of the input data is very large. In the above-mentioned field, there are a large number of frequency domain sparse signals, i.e. only a very small part of all fourier coefficients thereof is significantly non-zero, while the values of the remaining majority of coefficients are very small or even negligible. For coefficient characteristics of signals, researchers have proposed a series of FFT improvement algorithms, but all of these algorithms have some drawbacks and are difficult to implement in hardware and apply to practical engineering.

Until 2012, hassanieh and indik at MIT proposed a practical algorithm called sparse fast fourier transform (Sparse Fast Fourier Transform, SFFT), whose theoretical algorithm complexity could reach O (K log N). The core idea of the SFFT algorithm is that the frequency points of an original signal are classified into a bucket, and an FFT operation with a large number of points (N points) is converted into a plurality of small points (B points, B is far smaller than the FFT operation with N, and then a plurality of large-value frequency points of the original signal are reconstructed with high probability according to a certain rule.

In terms of hardware implementation, there are two implementation methods for the algorithm of MIT. The first is a fundamental version based on the SFFT algorithm, and the second is a sub-nyquist version based on the SFFT. Both implementations are fixed parameters, which do not allow signal parameterization, that is to say the number of sampling points N and the sparseness phase K of the input signal are both fixed. These hardware implementations all suffer from drawbacks that have not yet progressed to a fairly mature level in computational efficiency, compatibility, and fault tolerance.

Disclosure of Invention

The invention aims to provide a sparse fast Fourier transform FPGA implementation method based on insert ordering, and aims to solve the problems of low fault tolerance, relatively fixed hardware parameters and the like in the traditional SFFT hardware implementation scheme.

In order to solve the technical problems, the specific technical scheme of the invention is as follows:

the invention relates to a sparse fast Fourier transform FPGA (field programmable gate array) implementation method based on insert sequencing, which is characterized in that a sparse fast Fourier transform hardware implementation scheme, called SFFT (field-effect transistor) system for short, is supported, and a main device is the FPGA; the FPGA comprises a RAM, a control counter, a FIFO, an FFT-IP core and an insertion sequencer; for the sparse signals of the frequency domain, firstly, buffering, rearrangement, filtering, downsampling, FFT/IFFT, threshold selection, positioning circulation and sequencing estimation are carried out on the input signals, and finally, the calculation result is output; the method comprises the following steps:

step 1, preprocessing an input signal, including signal buffering, rearrangement, filtering and downsampling;

step 2, performing FFT/IFFT conversion on the data processed in the step 1;

and step 3, selecting and sorting the data processed in the step 2, and selecting a threshold value.

And step 4, positioning and circulating according to the threshold value output in the step 3, and selecting a large-value frequency point.

And 5, performing insertion sorting, determining the amplitude of the large-value frequency point selected in the step 4, and then sorting and calculating a final result.

So far, the steps 1 to 5 finish a sparse fast Fourier transform FPGA implementation method based on insert ordering.

Preferably, the data preprocessing in the step 1 specifically includes:

step 1.1, when input data enter the system, firstly storing the data, specifically:

step 1.1A, invoking a RAM in an FPGA to store input data, and setting the SFFT system to be 200Mhz all the time;

step 1.1B, a counter is arranged at the input end of the RAM, and the quantity of stored data is controlled by calculating the number of input points, so that the purpose of acquiring enough data is realized.

Step 1.2, the preprocessing operation of the data is specifically expressed as follows:

step 1.2A calculates the rearranged position of the corresponding point of the original signal and the position after downsampling according to the effective length of the filter, and the specific steps are as follows:

x-sampt(mod(i，B))＝origx(index)*filter_time(i)+x_sampt(mod(i，B))(1)

index＝index+σ (2)

wherein x_sample is a rearranged, filtered and downsampled signal, origx is an original signal, filter_time is a filtered time domain value, i is between 0 and the effective length of the filter, B is the time domain length of the signal after preprocessing, mod (i, B) is a storage position of the rearranged, filtered and downsampled signal, sigma is a randomly generated rearrangement coefficient, and index is a position of the rearranged signal.

And step 1.2B, calling a new RAM to store the processed data.

Preferably, the step 2 specifically includes:

performing FFT/IFFT operation on the data processed in the step 1; wherein the FFT/IFFT operation is implemented by calling the Xilinx FFT-IP core.

Preferably, the selecting and sorting in the step 3 is specifically:

step 3.1, selecting and sorting the data processed in the step 2; the sequencer is designed based on an insert sequencing algorithm and comprises two identical amplitude register sets, wherein the register length of each register set is K;

step 3.2, in each clock period, comparing the input data with all data in the first amplitude register group, recording one ticket when the input data is larger than one data in the first amplitude register group, and calculating the final ticket number; when the ticket number is more than 0, the ticket number is several, the input data is inserted into the first amplitude register group, and the minimum data in the first amplitude register group is used as the input data to be transmitted to the second amplitude register group; when the ticket number is 0, transmitting the input data to a second amplitude register group, and performing the same insertion comparison; the 2K values left by the final two sets of registers are the largest 2K values arranged from large to small;

and 3.3, transmitting the amplitude of the minimum data in the second amplitude register set to a subsequent module as a threshold value, and outputting the frequency points of the data in the two amplitude register sets to the subsequent module.

Preferably, the positioning cycle in the step 4 is specifically:

step 4.1, the large-value frequency points transmitted in the step 3 are restored into original frequency points and stored in a frequency point register set in a first round of circulation;

step 4.2, the second round of circulation restores the large value frequency point transmitted in the step 3 into an original frequency point and stores the original frequency point in the shift register group, the original frequency point calculated by the two rounds of circulation is compared by utilizing the sequencer in the step 3, if the frequency point register group and the shift register group have the same frequency point, the corresponding frequency point in the shift register group is cleared, and the highest bit of the frequency point corresponding to the frequency point register group is pulled up; after the comparison is finished, non-0 frequency points in the shift register are sequentially stored into a frequency point register group;

step 4.3, mapping the original frequency point stored in the frequency point register into a large-value frequency point of the FFT/IFFT calculation result in the step 3, comparing the corresponding amplitude with the threshold transmitted by the third round of circulation step 3, and eliminating the original frequency point with the amplitude smaller than the threshold and the highest bit lower; and transmitting the frequency points after screening and the amplitude values of each round of circulation to a sequencing estimation module.

Preferably, the sorting in the step 5 is specifically:

step 5.1, respectively sequencing the real part and the imaginary part of each frequency point, and selecting a median value as the final amplitude value of the point;

and 5.2, sequencing the amplitudes of all the candidate frequency points, and selecting the maximum K as final results to be output.

The implementation method of the insertion ordering sparse fast Fourier transform FPGA has the following advantages:

1. the data preprocessing module provided by the invention can finish signal time domain rearrangement, filtering and downsampling in a pipeline mode, and reduces operation time.

2. The positioning circulation method provided by the invention effectively solves the problem of dependence on the screening results of the previous two rounds in the traditional SFFT hardware implementation scheme, and improves the fault tolerance rate of frequency point screening.

3. The result calculation method based on the insert ordering greatly improves the calculation accuracy of the final result, and does not need to carry out amplitude compensation calculation.

Drawings

FIG. 1 is an overall flow chart of an embodiment 1 of the invention, a sparse fast Fourier transform FPGA implementation method based on insert ordering;

FIG. 2 is a block diagram of a data preprocessing module according to the present invention;

FIG. 3 is a diagram of a pick sequencer based on an insert sequencing algorithm in accordance with the present invention;

FIG. 4 is a positioning cycle comparator of the present invention;

FIG. 5 is a block diagram illustrating an insert sort result calculation module according to the present invention;

FIG. 6 shows the actual test results in an embodiment of the present invention;

FIG. 7 shows the theoretical result of direct FFT in an embodiment of the invention.

Detailed Description

For a better understanding of the objects, structures and functions of the present invention, a method for selecting a ue based on random aggregate beamforming is described in further detail below with reference to the accompanying drawings.

Examples

The embodiment illustrates the flow of applying the sparse fast Fourier transform FPGA implementation method based on insert ordering to the fast Fourier transform of 32768 points of input signals.

As can be seen from fig. 1, the method comprises the steps of:

step A, storing, rearranging, filtering and downsampling the input data;

specifically to the implementation of this example, after comprehensively considering the operation precision and the resource consumption, this embodiment sets the total data length N to 32768, the downsampling length B to 512, the signal sparsity K to 4, and the number of sfft cycles to 8; fig. 2 shows a structure of a data preprocessing module, after data is input, the data is firstly stored in a RAM1, then an address is calculated by an address calculating unit, an original signal is taken out from the RAM1, a corresponding filter value is taken out from the ROM, a corresponding downsampled value is taken out from a RAM2, and operations of rearrangement, filtering, downsampling and the like of a change point are completed, wherein the operations are specifically shown as follows:

x_sampt(mod(i，B))＝origx(index)*filter_time(i)+x_sampt(mod(i，B)) (1)

index＝index+σ (2)

wherein x_sample is a rearranged, filtered and downsampled signal, origx is an original signal, filter_time is a filtered time domain value, i is between 0 and the effective length of the filter, B is the time domain length of the signal after pretreatment, mod (i, B) is a storage position of the rearranged, filtered and downsampled signal, sigma is a randomly generated rearrangement coefficient, and index is the position of the rearranged signal; the AND processing mode can not only perform data reordering, filtering and downsampling operations in a pipeline manner, but also reduce multiplication operations in a data rearrangement stage, and greatly reduce operation time.

B, performing FFT/IFFT conversion on the data processed in the step A, and then selecting the largest 2K of the results;

the parameters of the FFT-IP core are set as: the FFT type is selected as a radio-4 Burst I/O, the rounding type is selected to be rounded, the calculation result is not truncated, the input bit width and the output bit width are 20 bits and 30 bits, and the data type is selected as a fixed-point signed number; the threshold selection module is shown in fig. 3, and in this example, the length of the register set is 8, so that the maximum 8 points can be selected, and the register storage mode is as follows: the high 15 bits store data, the middle 20 bits store the imaginary part, and the low 20 bits store the real part.

Step C, carrying out reconstruction filtering on the large-value frequency points, and selecting candidate frequency points;

fig. 4 is a positioning cycle comparator, firstly, reconstructing the large-value frequency points screened by the first round of threshold value selection module, restoring the large-value frequency points into original frequency points, and storing the result into a frequency point register set, wherein the storage mode is as follows: the highest position 0, the low-order storage frequency point; then reconstructing the large-value frequency points screened by the second round of threshold value selection module, storing the result into a shift register group, comparing the result with data in the frequency point register group, if the frequency point register group and the shift register group have the same frequency point, clearing the corresponding frequency point in the shift register group, and pulling up the highest bit of the corresponding position of the frequency point register group; after the comparison is finished, non-0 frequency points in the shift register are sequentially stored into a frequency point register group; and finally, mapping the original frequency points in the frequency point register into a bucket, comparing the corresponding amplitude with the threshold value transmitted by the threshold value selection module, and deleting the frequency points with the amplitude smaller than the threshold value and the high order of 0 to obtain candidate frequency points. The positioning and circulating module is different from the traditional candidate value voting module in that:

(1) The number of the candidate frequency points screened by the traditional candidate value voting structure is just K, and the number of the candidate frequency points screened by the positioning cyclic comparator is larger than K, so that the possibility of 'missed selection' can be avoided to a large extent;

(2) The traditional candidate value voting structure is very dependent on the correctness of the previous two voting calculation, and if 'miss selection' and 'miss selection' occur in the previous two voting calculation, the final calculation result is influenced by the errors; the positioning cyclic comparator can integrate the screening results of the previous three times, and selects the frequency points which are screened out twice in the three times of operation as candidate frequency points, thereby greatly improving the calculated fault tolerance.

Step D, inserting and sorting the screened frequency points, and calculating a final result;

FIG. 5 is a structure of calculation of the insertion ordering result, wherein the real part and the imaginary part calculated by eight cycles of each candidate frequency point are passed through a first insertion ordering comparator, and the median value is selected as the final amplitude value of the frequency point; then all candidate frequency points pass through a second comparator to sort the amplitude values of the candidate frequency points, and the maximum K of the candidate frequency points are selected as large value results of SFFT calculation; it can be seen that the insert ordering result calculation has several significant differences from the conventional result calculation structure:

(1) The traditional result calculation structure calculates the average value of the real part and the imaginary part of each frequency point, and the insertion ordering result calculation structure respectively takes the median value of the real part and the imaginary part of each frequency point, so that the operation can avoid errors caused by the collision problem in the data rearrangement stage to a great extent, and the accuracy of the calculation result is improved;

(2) The number of candidate frequency points transmitted from the candidate value voting module is exactly K, and the candidate frequencies transmitted from the positioning circulation module are larger than K, so that the second ranking is performed, and the largest K of the K candidate frequency points are selected.

Fig. 6 is a result calculated by hardware in the present embodiment, and fig. 7 is a result obtained by directly performing FFT calculation on original data.

Table 1 shows the comparison of the operation speed and the resource consumption (BRAM) relative to the FFT-IP core of Xilinx company in the embodiment of the invention. At the operation speed, the operation time of the invention in the example is greatly reduced compared with that of the FFT-IP core, and the resource consumption is about 36% of the FFT-IP core (in the example of BRAM, the size of each block of BRAM is 36 KB)

It will be understood that the invention has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (6)

1. A sparse fast Fourier transform FPGA implementation method based on insert ordering is characterized by comprising the following steps: the sparse fast Fourier transform hardware system supported by the method is an SFFT system, and the system comprises an FPGA; the FPGA comprises a RAM, a control counter, a FIFO, an FFT-IP core and an insertion sequencer; the method comprises the following steps:

step 1, preprocessing an input signal, including signal buffering, rearrangement, filtering and downsampling;

step 2, performing FFT or IFFT on the data processed in the step 1;

step 3, performing insertion sorting operation on the data processed in the step 2, and selecting a threshold value;

step 4, positioning and circulating according to the threshold value output in the step 3, and selecting a large-value frequency point;

and 5, performing insertion sequencing, determining the amplitude corresponding to each large-value frequency point selected in the step 4, and performing insertion sequencing on the amplitude of the large-value frequency point to calculate a final result.

2. The implementation method of the sparse fast fourier transform FPGA based on the insert ordering according to claim 1, wherein the data preprocessing in step 1 specifically includes:

step 1.1, when input data enter an SFFT system, firstly storing the data, specifically:

step 1.1A, an RAM is called in an FPGA to store input data, and a clock of an SFFT system is set to be 200Mhz;

step 1.1B, setting a counter at the input end of the RAM, and controlling the quantity of stored data by calculating the number of input points so as to achieve the purpose of acquiring enough data;

step 1.2, the preprocessing operation of the data is specifically expressed as follows:

step 1.2A, calculating the rearranged position of the corresponding point of the original signal and the position after downsampling according to the effective length of the filter, wherein the specific steps are as follows:

x_sampt(mod(i，B))＝origx(index)*filter_time(i)+x_sampt(mod(i，B)) (1)

index＝index+σ (2)

wherein x_sample is a rearranged, filtered and downsampled signal, origx is an original signal, filter_time is a filtered time domain value, i is between 0 and the effective length of the filter, B is the time domain length of the signal after pretreatment, mod (i, B) is a storage position of the rearranged, filtered and downsampled signal, sigma is a randomly generated rearrangement coefficient, and index is the position of the rearranged signal;

and step 1.2B, calling a new RAM to store the processed data.

3. The implementation method of the sparse fast fourier transform FPGA based on the insert ordering according to claim 1, wherein the step 2 specifically is: performing FFT or IFFT operation on the data processed in the step 1; wherein the FFT or IFFT operations are implemented by calling the Xilinx FFT-IP core.

4. The method for implementing the sparse fft FPGA based on the insert-rank according to claim 1, wherein the selecting rank in the step 3 is specifically:

step 3.1, performing insertion sorting on the data processed in the step 2; the sequencer is designed based on an insert sequencing algorithm and comprises two identical amplitude register sets, wherein the register length of each register set is K;

step 3.2, in each clock period, comparing the input data with all data in the first amplitude register group, recording one ticket when the input data is larger than one data in the first amplitude register group, and then calculating the final ticket number; when the ticket number is more than 0, the ticket number is several, the input data is inserted into the first amplitude register group, and the minimum data in the first amplitude register group is used as the input data to be transmitted to the second amplitude register group; when the ticket number is 0, transmitting the input data to a second amplitude register group, and performing the same insertion sequencing; the 2K values left by the final two sets of registers are the largest 2K values arranged from large to small;

and 3.3, transmitting the amplitude of the minimum data in the second amplitude register set to a subsequent module as a threshold value, and outputting the frequency points of the data in the two amplitude register sets to the subsequent module.

5. The sparse fast fourier transform FPGA implementation method based on insert ordering of claim 1, wherein the positioning loop in step 4 is specifically:

step 4.1, the large-value frequency points transmitted in the step 3 are restored into original frequency points and stored in a frequency point register set in a first round of circulation;

step 4.2, the second round of circulation restores the large value frequency point transmitted in the step 3 into an original frequency point and stores the original frequency point in the shift register group, the original frequency point calculated by the two rounds of circulation is compared by utilizing the sequencer in the step 3, if the frequency point register group and the shift register group have the same frequency point, the corresponding frequency point in the shift register group is cleared, and the highest bit of the frequency point corresponding to the frequency point register group is pulled up; after the comparison is finished, non-0 frequency points in the shift register are sequentially stored into a frequency point register group;

step 4.3, mapping the original frequency point stored in the frequency point register into a large-value frequency point of the FFT/IFFT calculation result in the step 3, and then comparing the corresponding amplitude with the threshold value transmitted by the third round of circulation step 3 to eliminate the original frequency point with the amplitude smaller than the threshold value and the highest bit lower; and transmitting the frequency points after screening and the amplitude values of each round of circulation to a sequencing estimation module.

6. The method for implementing the sparse fft FPGA based on the insert-ordering of claim 1, wherein the ordering in step 5 is specifically:

step 5.1, respectively sequencing the real part and the imaginary part of each frequency point, and selecting a median value as the final amplitude value of the point;

and 5.2, sequencing the amplitudes of all the candidate frequency points, and selecting the maximum K as final results to be output.

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