CN116303149A - Method and system for expanding controller interface based on BMC chip - Google Patents

Method and system for expanding controller interface based on BMC chip Download PDF

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CN116303149A
CN116303149A CN202310561821.1A CN202310561821A CN116303149A CN 116303149 A CN116303149 A CN 116303149A CN 202310561821 A CN202310561821 A CN 202310561821A CN 116303149 A CN116303149 A CN 116303149A
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CN116303149B (en
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江旭
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Hunan Bojiang Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C

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Abstract

The invention discloses a method and a system for realizing controller interface expansion based on a BMC chip. For the Linux application layer, all external devices have independent device nodes, all the device nodes conform to the standard definition of Linux device nodes, and nodes of a local interface, a logic external topology interface and a virtual device driving layer are consistent to an application program, so that the Linux application layer is completely compatible with the use of the external topology interface of a third party application.

Description

Method and system for expanding controller interface based on BMC chip
Technical Field
The invention relates to the technical field of BMC (baseboard management controller), in particular to a method and a system for realizing controller interface expansion based on a BMC chip.
Background
The BMC (Baseboard Management Controller ) of the server is a control unit with independent power supply and independent IO interfaces, which is deployed on the server and is used for monitoring the running state of the server, and can perform functions and control operations such as obtaining detailed running information of the server, controlling software and hardware resources, configuring network, deploying software, managing users, managing safety and the like.
The BMC needs rich peripheral interfaces to meet the requirement of the monitoring function of the server main board, and the current general BMC chip is difficult to meet the requirements of the number and the types of interfaces needed by different servers; in the existing interface expansion scheme, each device interface needs to construct a protocol corresponding to the interface in the Linux application layer to distinguish the types of the expanded bus and the external devices, namely, a standard Linux peripheral driving node cannot be provided for each device on each external bus, and the external interfaces cannot be used by a third party application program.
Disclosure of Invention
The invention mainly aims to provide a method and a system for realizing controller interface expansion based on a BMC chip, and aims to solve the problem that in the existing interface expansion scheme, a standard Linux peripheral driving node cannot be independently provided for equipment on each external bus, and the external interface cannot be used by a third-party application program.
The technical scheme provided by the invention is as follows:
a method for realizing controller interface expansion based on BMC chip is applied to an interface expansion system; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus; the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel and an SPI main controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for connecting with external equipment in a communication way; the method comprises the following steps:
When data needs to be sent to the appointed external equipment and the interface expansion system meets a first condition, the BMC module obtains the data needing to be sent and marks the data as first data, wherein the first condition is as follows: the SPI master controller driver is provided with virtual bus controller drivers in a constructed and registered mode, so that the virtual bus controller drivers are in one-to-one correspondence with the logic external topology interfaces, and a virtual device driving layer is also provided with the virtual bus controller drivers in a constructed and registered mode;
the virtual bus controller driver acquires a communication protocol corresponding to the appointed external equipment, marks the communication protocol as a target protocol, analyzes the first data by adopting the target protocol, adds a privately-owned protocol segment, and submits the first data to the SPI main controller driver;
the SPI master controller drives to send first data from the SPI master controller interface to the SPI slave controller interface through an SPI bus;
the FPGA module acquires first data through the SPI slave controller interface, carries out protocol analysis on the first data and sends the first data to the SPI slave controller for driving;
the SPI slave controller drives to send the first data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive.
Preferably, the SPI slave controller driver sends the first data to the specified external device through the corresponding logical extension interface through the logical extension interface driver, and then further includes:
When the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as second data, and then carries out protocol packaging on the second data;
the SPI slave controller drives to send second data from the SPI slave controller interface to the SPI master controller interface through an SPI bus;
the SPI main controller driver receives the second data from the SPI main controller interface, submits the second data to the virtual bus controller driver for private data protocol analysis, encapsulates the private data protocol analysis into a data format required by the corresponding virtual device driving layer, and returns the data to the corresponding virtual device driving layer.
Preferably, the FPGA module is further provided with a logic control core layer; the method further comprises the steps of:
the FPGA module abstracts each logic extension interface into a structure for initializing, sending and receiving data so as to register a controller core layer;
after the FPGA module is electrified, the logic control core layer initializes the FPGA module;
the SPI master controller driver sends first data to the SPI slave controller interface through the SPI bus from the SPI master controller interface, and then still includes:
the logic control core layer calls the SPI to acquire first data from the controller driver, then analyzes the first data based on a target protocol, and creates a data processing thread according to the target protocol;
The data processing thread distributes the first data to a logic external expansion interface driver corresponding to the appointed external equipment;
the logic extension interface driver performs privatization processing on the first data and sends the first data to the appointed external equipment through the logic extension interface.
Preferably, the logic extension interface driver performs privatization processing on the first data, and sends the first data to the specified external device through the logic extension interface, and then the method further includes:
when the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as third data, and then carries out protocol packaging on the third data;
and the logic control core layer submits the packed third data to the response queue, and monitors the third data of different response queues to asynchronously send the third data to the BMC module through the SPI bus.
Preferably, the method further comprises:
when the data needs to be sent to the appointed external equipment and the interface expansion system does not meet the first condition, the BMC module obtains the data needing to be sent and marks the data as fourth data;
the Linux application layer packs the fourth data through a protocol and then sends the fourth data to an SPI main controller driver of the Linux kernel layer;
The SPI master controller drives the fourth data to be sent from the SPI master controller interface to the SPI slave controller interface through the SPI bus;
the FPGA module acquires fourth data through the SPI slave controller interface, carries out protocol analysis on the fourth data and sends the fourth data to the SPI slave controller for driving;
the SPI slave controller drives to send fourth data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive;
when the appointed external equipment responds to a sending request of fourth data and sends response data, the FPGA module obtains the response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as fifth data, and then carries out protocol packaging on the fifth data;
the SPI slave controller drives the fifth data to be sent from the SPI slave controller interface to the SPI master controller interface through an SPI bus;
the SPI main controller drives to send fifth data to a Linux application layer through a Linux kernel;
and the Linux application layer performs protocol unpacking processing on the fifth data.
Preferably, the BMC module adopts Loongson 2K0500 as a processing chip; the FPGA module adopts a high cloud GW2R as a processing chip; the logic external expansion interface comprises an SPI interface, a GPIO interface, a UART interface, a PWM interface, a TACH interface, an IIC interface and an ADC interface; the external equipment comprises a temperature sensor, a voltage sensor, a fan rotating speed sensor, a BIOS module of the server, a watchdog module of the server main board and a BMC module; a real-time system based on FreeRtos is operated at the soft core end of the FPGA module; and the program of the soft core end of the FPGA module is stored in the SPIflash of the FPGA module.
Preferably, the virtual bus controller driver is configured to define a set of different bus transfer method functions; the SPI master controller is used for matching different SPI master controller interfaces through the equipment tree; the logic control core layer is used for uniformly receiving data from the SPI slave controller interface and calling controller drivers of different logic ends to finish data transmission; the logic extension interface driver is used for registering the driver to the logic control core layer; the virtual device driving layer is provided with a hwmon_ops interface and an IIC driver; the method further comprises the steps of:
the hwmon_ops interface is used for finding out an i2c_adapter structure body driven by the virtual bus controller by calling an i2c_master_send interface of the IIC core layer and calling a transmission interface thereof to perform data reading and data writing;
IIC drives register IIC core layers;
the IIC driver triggers the probe initialization driver to register the hwmon driver.
Preferably, the virtual bus controller driver is provided with an i2c_adapter structure and an iiqdev device tree node; the method further comprises the steps of:
the i2c_adapter structure registers the IIC core layer;
the iiqdev device tree node constructs an iic_client device description structure by binding with the i2c_adapter structure;
The iic_client device description structure and IIC driver determine the type of IIC bus by matching the name or ID;
initializing a probe driver to construct an xxx_master bus controller structure and a spi_master bus controller structure;
the spixxx driver device driver realizes SPI bus type pairing with the external device through a name, and triggers a probe driver after the driver is matched with the external device;
the spiflash driver and the spixxx driver device driver respectively register the SPI core layer.
Preferably, the SPI main controller is provided with a spiBoard info structure and an acpi node; the method further comprises the steps of:
the SPI master controller driven spi_master bus controller structure body registers an SPI core layer, and is bound with the master bus controller structure body through bus_id information to construct a spidevice equipment description structure body driven by the virtual bus controller;
the SPI_transfer transmission interface driven by the SPI master controller calls the spi_write interface function of the SPI core layer to find a structural body of the SPI master bus controller driven by the SPI master controller and call the transmission interface to realize actual data transmission;
the SPI_transfer transmission interface driven by the SPI main controller transmits data to the FPGA module through an SPI bus;
The probe driving structure driven by the SPI main controller constructs a spi_master bus controller structure driven by the SPI main controller;
the platform device structure body driven by the SPI main controller is matched with the platform driver platform driving structure body through the type of the matched platform bus;
the device tree spi controller node parses the platform device structure.
The invention also provides an interface expansion system which is applied to any method for realizing controller interface expansion based on the BMC chip; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus; the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel and an SPI main controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for communication connection with external equipment.
Through the technical scheme, the following beneficial effects can be realized:
according to the method for expanding the controller interface based on the BMC chip, for the Linux kernel layer, various drivers conform to the matching mechanism of devices, buses and drivers of the Linux standard, nodes of an expansion interface and nodes of peripheral drivers hung by the expansion interface can be defined in a device tree, and various drivers can be loaded in a kernel module mode. All kinds of equipment have independent equipment nodes for the Linux application layer, the equipment nodes meet the standard definition of Linux equipment nodes, and the nodes of the local interface, the logic external expansion interface and the virtual equipment driving layer are consistent for application programs, so that the application of the external expansion interface by a third party is compatible.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a first embodiment of a method for implementing controller interface expansion based on a BMC chip according to the present invention;
FIG. 2 is a schematic block diagram of a fifth embodiment of an interface expanding system according to the present invention;
FIG. 3 is a schematic diagram of a hardware connection structure of a second embodiment of an interface expansion system according to the present invention;
fig. 4 is a schematic block diagram of a third embodiment of an interface expanding system according to the present invention.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The invention provides a method and a system for realizing controller interface expansion based on a BMC chip.
As shown in fig. 1, fig. 2 and fig. 4, in a first embodiment of a method for implementing interface expansion of a controller based on a BMC chip provided by the present invention, the method is applied to an interface expansion system; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus, the BMC is used as a master device, and the FPGA is used as a slave device; the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel (not shown in fig. 2) and an SPI master controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for connecting with external equipment in a communication way; the SPI is driven by the controller and the logic external expansion interface to be a program of a soft core end of the FPGA module; the embodiment comprises the following steps:
Step S110: when data needs to be sent to the appointed external equipment and the interface expansion system meets a first condition, the BMC module obtains the data needing to be sent and marks the data as first data, wherein the first condition is as follows: the SPI master controller driver is built and registered with a virtual bus controller driver, so that the virtual bus controller driver corresponds to the logic external topology interface one by one, and a virtual device driver layer is also built and registered on the virtual bus controller driver.
Specifically, when the application of the BMC module needs to send data to the specified external device, the BMC module obtains the data to be sent.
Step S120: the virtual bus controller driver acquires a communication protocol corresponding to the appointed external device, marks the communication protocol as a target protocol, analyzes the first data by adopting the target protocol, attaches a privately-owned protocol segment, and submits the first data to the SPI main controller driver.
Specifically, by calling the target protocols corresponding to different external devices, it is determined to which logic extension interface (i.e. which external device corresponds) the data received from the SPI master controller interface and the third data to be sent specifically belong to, so that threads are created according to the different data types, and different device driving registration on the FPGA module is conveniently called.
Specifically, the specific steps of the virtual bus controller driving to acquire the communication protocol corresponding to the specified external device are as follows: the Linux application layer calls an interface of the virtual device driving layer, the virtual device driving layer calls a virtual bus controller driving interface, and finally the interface is submitted to the SPI main controller for driving.
Step S130: the SPI master controller drives to send the first data from the SPI master controller interface to the SPI slave controller interface through the SPI bus.
Step S140: the FPGA module acquires first data through the SPI slave controller interface, and sends the first data to the SPI slave controller for driving after carrying out protocol analysis on the first data.
Step S150: the SPI slave controller drives to send the first data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive.
According to the method for expanding the controller interface based on the BMC chip, for the Linux kernel layer, various drivers conform to the matching mechanism of devices, buses and drivers of the Linux standard, nodes of an expansion interface and nodes of peripheral drivers hung by the expansion interface can be defined in a device tree, and various drivers can be loaded in a kernel module mode. For the Linux application layer, various external devices have independent device nodes, and various device nodes accord with the standard definition of Linux device nodes, and the nodes of the local interface, the logic external expansion interface and the virtual device driving layer are consistent to the application program, so that the application of the external expansion interface by a third party is compatible.
In addition, the existing interface extension scheme has the following defects:
1. because the external devices can only be uniformly identified as single SPI devices, the BMC module cannot be integrated into a Linux device bus driving model in a single device driving module mode, team cooperation and parallel development in a modularized mode are difficult to realize, and therefore development efficiency is low, code maintainability is poor, and expansibility is poor.
2. All the communication of the logic external expansion interfaces are communicated through one SPI bus, the application layer is represented as a single SPI device, the device can only be opened by one application at the same time, the access to the logic external expansion interfaces can only be serially accessed by the external devices corresponding to the single logic external expansion interfaces, and after the access to the external devices corresponding to the other logic external expansion interfaces is completed, the access to the external devices corresponding to the other logic external expansion interfaces is switched, so that the multi-port access data throughput efficiency is extremely low.
3. When the number and the type of the logic external expansion interfaces are required to be increased or the chips of the logic external expansion interfaces are required to be replaced, the SPI slave controller drives and the data logic processing have a deeper coupling relation, so that the logic external expansion interfaces are poor in expansibility and multi-platform portability, repeated development is caused, and the development and debugging workload is increased.
In a second embodiment of the method for implementing controller interface expansion based on a BMC chip provided by the present invention, based on the first embodiment, step S160 further includes the following steps:
step S210: when the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as second data, and then carries out protocol packaging on the second data.
Step S220: the SPI slave controller driver sends the second data from the SPI slave controller interface to the SPI master controller interface through the SPI bus.
Step S230: the SPI main controller driver receives the second data from the SPI main controller interface, submits the second data to the virtual bus controller driver for private data protocol analysis, encapsulates the private data protocol analysis into a data format required by the corresponding virtual device driving layer, and returns the data to the corresponding virtual device driving layer.
Specifically, after the second data is returned to the corresponding virtual device driving layer, the Linux application layer obtains the second data from the virtual device driving layer so as to meet the user requirement.
In a third embodiment of the method for realizing controller interface expansion based on the BMC chip provided by the invention, based on the second embodiment, the FPGA module is further provided with a logic control core layer; namely, a logic control core layer, a logic external topology interface driver and an SPI slave controller driver (actually, the slave controller driver in the FPGA module can be a slave controller driver corresponding to any one of SPI, GPIO, IIC or UART, in the embodiment, the SPI slave controller driver is taken as an example) jointly form a soft core end of the FPGA module; the embodiment further comprises the following steps:
Step S310: the FPGA module abstracts each logical extension interface into a structure that initializes, sends, and receives data to register the controller core layer.
Step S320: after the FPGA module is powered on, the logic control core layer initializes the FPGA module.
Step S130, further comprising the following steps:
step S330: the logic control core layer calls the SPI to acquire first data from the controller driver, then analyzes the first data based on a target protocol, and creates a data processing thread according to the target protocol.
Step S340: and the data processing thread distributes the first data to a logic external expansion interface driver corresponding to the appointed external equipment.
Step S350: the logic extension interface driver performs privatization processing on the first data and sends the first data to the appointed external equipment through the logic extension interface.
In a fourth embodiment of the method for implementing controller interface expansion based on a BMC chip according to the present invention, based on the third embodiment, step S350 further includes the following steps:
step S410: when the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as third data, and then carries out protocol packaging on the third data.
Step S420: and the logic control core layer submits the packed third data to the response queue, and monitors the third data of different response queues to asynchronously send the third data to the BMC module through the SPI bus.
Specifically, in this embodiment, the device driver is implemented by adopting layered construction, and a layer of virtual bus controller driver is additionally constructed on the conventional Linux bus and device driver layer, and a virtual device driver layer mounted on the logic external topology interface is reconstructed on the virtual bus controller driver.
The method has the advantages that data processing can be performed in parallel and asynchronously, so that the data throughput efficiency of the logic external expansion interface is improved, different external devices can be identified into different device nodes and can be simultaneously accessed by multiple applications in parallel, so that data of the multiple logic external expansion interfaces are submitted to an SPI bus in parallel, a Freertos system is adopted at a soft core end of an FPGA module, a multi-task parallel processing request is adopted through response of the corresponding logic external expansion interface, and parallel response of the multiple logic external expansion interfaces is realized by asynchronously submitting the data to a response queue.
In addition, the logic external expansion interface is driven and realized, namely, the logic external expansion interface of the soft core end of the FPGA module is driven and abstracted into a uniform interface, and the logic control core layer is constructed to perform uniform driving management.
The software architecture of the system for realizing controller interface expansion based on the BMC chip provided by the embodiment can well solve the problems of the traditional scheme; thereby improving the data concurrency and data throughput efficiency of the multiport (i.e. a plurality of logic external expansion interfaces); the software architecture has the advantages of good compatibility, expansibility, portability, code maintainability and the like; and a high-cohesion low-coupling frame is realized by means of layered decoupling, modularization is realized by driving, repeated development of codes is greatly reduced, and the parallel development efficiency of software is improved.
The software architecture provides standard Linux equipment nodes for external devices and buses and an application layer by additionally constructing a layer of virtual bus controller driver on the traditional Linux bus and device driver layer, so that the software architecture can be compatible with the application of third-party application programs. And can be developed by a standard Linux driving module when a logic external interface and external equipment are added.
In addition, different external devices can be identified into different device nodes and can be simultaneously accessed by multiple applications in parallel, so that data of multiple logic external expansion interfaces are parallelly submitted to an SPI bus, a Freertos system is adopted at a soft core end of an FPGA module, a multi-port parallel response is realized by responding to multiple ports, a multi-task parallel processing request is adopted, and the multi-port parallel response is asynchronously submitted to a response queue, and therefore the multi-port data concurrency data throughput efficiency is improved.
Meanwhile, the logic external expansion interface drive abstraction at the soft core end of the FPGA module is a unified interface, and a developer can add corresponding external equipment drive by only adding drive registration for the corresponding logic external expansion interface through constructing a logic control core layer to perform unified drive management.
In addition, when the processing chip of the BMC module or the chip of the logic external expansion interface is required to be replaced, the frame core code is not required to be changed, and only the difference part codes of the system and the logic control core layer are required to be modified, so that the transplanting between different platforms can be better carried out, and the code maintenance is more convenient.
In a fifth embodiment of the method for implementing controller interface expansion based on a BMC chip according to the present invention, based on the first embodiment, the method further includes the following steps:
step S510: when the data needs to be sent to the appointed external equipment and the interface expansion system does not meet the first condition, the BMC module obtains the data needing to be sent and marks the data as fourth data.
Step S520: and the Linux application layer packages the fourth data through a protocol (namely SPI communication protocol) and then sends the fourth data to an SPI main controller driver of the Linux kernel layer.
Step S530: the SPI master controller drives and sends fourth data to the SPI slave controller interface through the SPI bus.
Step S540: the FPGA module acquires fourth data through the SPI slave controller interface, carries out protocol analysis on the fourth data and sends the fourth data to the SPI slave controller for driving.
Step S550: the SPI slave controller drives to send fourth data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive.
Step S560: when the appointed external equipment responds to the sending request of the fourth data and sends out response data, the FPGA module obtains the response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as fifth data, and then carries out protocol packaging on the fifth data.
Step S570: the SPI slave controller drives and sends the fifth data from the SPI slave controller interface to the SPI master controller interface through the SPI bus.
Step S580: the SPI main controller drives to send the fifth data to the Linux application layer through the Linux kernel.
Step S590: the Linux application layer performs protocol unpacking processing (namely SPI communication protocol) on the fifth data.
Specifically, the FPGA module is used as a device of an external expansion port, namely, the FPGA module is provided with a plurality of logic external expansion interfaces, so that interface expansion is realized, and the adaptability of an application scene and the universality of a BMC scheme are ensured; the multiple logic external expansion interfaces can improve concurrent data throughput efficiency; the software architecture of the system for realizing controller interface expansion based on the BMC chip has the advantages of good compatibility, expansibility, portability, code maintainability and the like. In addition, the embodiment realizes a high-cohesion low-coupling frame in a layered decoupling mode, drives to realize modularization, greatly reduces repeated development of codes and improves the parallel development efficiency of software.
As shown in fig. 3, in a sixth embodiment of a method for implementing controller interface expansion based on a BMC chip according to the present invention, based on the third embodiment, the BMC module uses a loongson 2K0500 as a processing chip; the FPGA module adopts a high cloud GW2R as a processing chip; the logic extension interface comprises an SPI interface (particularly comprises an SPIslave interface and an SPIHOST interface), a GPIO interface, a UART interface, a PWM interface, a TACH interface, an IIC interface and an ADC interface; the external equipment comprises a temperature sensor, a voltage sensor, a fan rotating speed sensor, a BIOS module of the server, a watchdog module of the server main board and a BMC module; a real-time system based on FreeRtos is operated at the soft core end of the FPGA module; the program of the soft core end of the FPGA module is stored in the SPIflash of the FPGA module (the SPIflash is in communication link with the FPGA module through an SPI bus).
The tornado 2K0500 and the high cloud GW2R are in communication connection through an SPI bus, a UART bus and an IIC bus.
Specifically, in this embodiment, the Loongson 2K0500 is a BMC system based on a linux kernel. The ADC interface and the IIC interface are used for being in communication connection with the temperature sensor; the ADC interface is also used for being in communication connection with a voltage sensor; the PWM interface or the TACH interface is used for being in communication connection with a fan rotating speed sensor and controlling the rotating speed of the fan; the SPI interface is used for being in communication connection with a BIOS module of the server so as to upgrade the BIOS of the server through the FPGA module; the GPIO interface is used for being in communication connection with the server main board so as to control the power on and power off time sequence of the server through the FPGA module; the IIC interface is also used for communicatively connecting a WatchDog module of the BMC module to provide a WatchDog (WatchDog) function for a processing chip of the BMC module.
Specifically, the software architecture of the system for realizing controller interface expansion based on the BMC chip is divided into two ends, namely a BMC module end and an FPGA module end. The BMC module end is deployed at Loongson 2K0500, and the FPGA module end is deployed at high cloud GW2R; a layer of virtual bus controller driver is built and registered on the SPI main controller driver (actually can be the main controller driver corresponding to any one of SPI, GPIO, IIC or UART, in the embodiment, the SPI main controller driver is taken as an example) at the bottom layer of the BMC module end, and different Linux virtual bus drivers are realized to realize transmission methods and data interaction protocols for defining different expansion bus interfaces so that the virtual bus controller drivers are in one-to-one correspondence with the logic external expansion interfaces; and on the virtual bus controller driver, a virtual device driver layer mounted on the logic external expansion interface is built again, and an XXX kernel subsystem is arranged on the virtual device driver layer. The virtual device driving layer is a logic external interface driving, and is also an SPI device driving for the SPI main controller driving at the bottom layer, and is positioned at the middle layer of the SPI main controller driving at the bottom layer and the SPI main controller driving at the upper layer. The SPI main controller driver, the virtual bus controller driver, the virtual device driver layer and the XXX kernel subsystem are all arranged in the Linux kernel layer. The virtual bus controller driver and virtual device driver layer hierarchy for device drivers.
Specifically, the Loongson 2K0500 master interface and the high cloud GW2R slave interface are in communication connection through an SPI bus, a GPIO bus, an IIC bus and a UART bus.
In a seventh embodiment of the method for implementing controller interface expansion based on the BMC chip, based on the third embodiment, the virtual bus controller driver is used for defining different bus transmission method function sets; the SPI master controller is used for matching different SPI master controller interfaces through the equipment tree; the logic control core layer is used for uniformly receiving data from the SPI slave controller interface and calling controller drivers of different logic ends to finish data transmission; the logic extension interface driver is used for registering the driver to the logic control core layer; the virtual device driver layer is provided with a hwmon_ops interface and an IIC driver (note that, the hwmon interface and the IIC driver are only one specific embodiment of the virtual device driver layer, which is a set of general methods, only IIC driver is taken as an example in the drawings, in the specific practical application of Linux, different device drivers can be selected according to different expanding peripheral devices, namely, different device drivers can be made into a standard driving mode of Linux); the embodiment further comprises the following steps:
Step S710: the hwmon_ops interface finds the i2c_adapt structure driven by the virtual bus controller and invokes its transport interface for data reading and data writing by invoking the i2c_master_send interface (specifically, the client, buf, sizeof (buf) interface) of the IIC core layer.
Specifically, in this embodiment, the hwmon_ops interface and the IIC driver are adopted in the virtual device driver layer, so that the IIC driver uses the i2c_adapter structure for the virtual bus driver of the corresponding IIC, and in practical application, if another virtual bus is adopted, the corresponding virtual bus driver uses another adapter structure or the xxx_master bus controller structure.
Step S720: the IIC driver registers the IIC core layer.
Step S730: the IIC driver triggers probe driver initialization to register the hwmon driver.
The embodiment provides a workflow of a virtual device driving layer of the method.
In an eighth embodiment of the method for implementing controller interface expansion based on a BMC chip provided by the present invention, based on the seventh embodiment, the virtual bus controller driver is provided with an i2c_adapter structure and an iiqdev device tree node; the embodiment further comprises the following steps:
Step S810: the i2c_adapter structure registers the IIC core layer.
Step S820: the iiqdev device tree node constructs the iic_client device description structure by binding with the i2c_adapter structure.
Step S830: the iic_client device description structure and IIC driver determine the type of IIC bus by matching the name or ID.
Step S840: the probe driver initializes to construct an xxx master bus controller structure and a spi master bus controller structure.
Step S850: the spixxx driver device driver realizes SPI bus type pairing with the external device through the name, and triggers the probe driver after the driver is matched with the external device.
Step S860: the spiflash driver and the spixxx driver device driver respectively register the SPI core layer.
The embodiment provides a workflow driven by the virtual bus controller of the method.
In a ninth embodiment of the method for implementing controller interface expansion based on a BMC chip provided by the present invention, based on the eighth embodiment, an SPI master controller is provided with a spiboard info structure and an acpi node, and the method further includes the steps of:
step S910: the SPI master controller driven spi_master bus controller fabric registers with the SPI core layer and binds the master bus controller fabric with the bus_id information to construct a virtual bus controller driven spidevice device description fabric (i.e., an external device).
Step S920: the spi_transfer transmission interface driven by the SPI master calls the spi_write interface function (spi_device) of the SPI core layer to find the SPI master driven SPI master bus controller structure and call the transmission interface to achieve the actual data transmission.
Step S930: and the spi_transfer transmission interface driven by the SPI main controller transmits data to the FPGA module through the SPI bus.
Step S940: the probe driver driven by the SPI master controller constructs a spi_master bus controller structure driven by the SPI master controller.
Step S950: the SPI host controller-driven platform device architecture (i.e., platform driver) is matched to the platform driver architecture by matching the platform bus type.
Step S960: the device tree spi controller node parses the platform device structure.
The embodiment provides the working flow driven by the SPI main controller of the method.
Specifically, the virtual bus controller driven basic protocol packet structure includes a head portion, a data portion, and a crc32 portion: the method comprises the following steps:
head part:
struct head{
u16 bustype;// bus type
u16 cmdtype; type of/(command)
u32 length;// length
u32 crc 32;// protocol packet check code }
data portion (drive private protocol portion):
struct data{
void
Figure SMS_1
data；}
in a tenth embodiment of the method for realizing controller interface expansion based on the BMC chip, based on the ninth embodiment, the FPGA module is further provided with an iic controller; the embodiment comprises the following steps:
step S1001: the logic control core layer starts registration operation, wherein the logic control core layer starts registration operation comprising registration and matching, and specifically comprising judging the type of data, initializing the data, receiving the data and sending the data.
Step S1002: each virtual bus controller drives a start interface registration operation.
Step S1003: each virtual bus controller traverses and invokes a corresponding initialization function.
Step S1004: the SPI is initialized from the controller drive.
Step S1005: the SPI slave controller interface circularly monitors the SPI slave device data processing request.
Step S1006: when sending data, the iic controller receives the signal that iic data arrives (i.e. fifo full interrupt or register set), and receives data to the buffer through interrupt or poll operation.
Step S1007: after the iic controller packages the data, the iic controller requests to send the data through the request queue, and then calls the spi_transfer transmission interface to send the data.
Step S1008: when receiving data, the SPI slave controller drives to receive a signal (particularly fifo full interrupt or register setting) of the arrival of the SPI data, so that the data from the SPI master controller drives is received into the buffer.
Step S1009: the SPI slave controller drives to unpack the received data.
Step S1010: the SPI judges the received data from the controller driver to identify the type of the data, thereby calling the corresponding driver sending function.
Step S1011: when the type of data is a hybrid type, data setting and command response are performed by a hybrid mix drive, wherein the data types corresponding to the hybrid mix drive include gpio data, fpga timing data, pwm data, and adc data.
Step S1012: and when the type of the data is IIC data, sending the data to the external equipment through the analysis of the drive command of the IIC.
Step S1013: when the data type is SPI data, the data is sent to the external equipment through SPI driving command analysis, and data setting and command response are performed.
Step S1014: and when the type of the data is UART data, the data is sent to the external equipment through the analysis of the driving command of the UART, and data setting and command response are performed.
Specifically, the embodiment provides a workflow of the FPGA module.
The invention also provides an interface expansion system which is applied to the method for realizing controller interface expansion based on the BMC chip according to any one of the above; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus, the BMC is used as a master device, and the FPGA is used as a slave device; the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel and an SPI main controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for communication connection with external equipment.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and including several instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims (10)

1. A method for realizing controller interface expansion based on a BMC chip is characterized in that the method is applied to an interface expansion system; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus; the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel and an SPI main controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for connecting with external equipment in a communication way; the method comprises the following steps:
when data needs to be sent to the appointed external equipment and the interface expansion system meets a first condition, the BMC module obtains the data needing to be sent and marks the data as first data, wherein the first condition is as follows: the SPI master controller driver is provided with virtual bus controller drivers in a constructed and registered mode, so that the virtual bus controller drivers are in one-to-one correspondence with the logic external topology interfaces, and a virtual device driving layer is also provided with the virtual bus controller drivers in a constructed and registered mode;
The virtual bus controller driver acquires a communication protocol corresponding to the appointed external equipment, marks the communication protocol as a target protocol, analyzes the first data by adopting the target protocol, adds a privately-owned protocol segment, and submits the first data to the SPI main controller driver;
the SPI master controller drives to send first data from the SPI master controller interface to the SPI slave controller interface through an SPI bus;
the FPGA module acquires first data through the SPI slave controller interface, carries out protocol analysis on the first data and sends the first data to the SPI slave controller for driving;
the SPI slave controller drives to send the first data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive.
2. The method for implementing controller interface expansion based on a BMC chip according to claim 1, wherein the SPI slave controller driver sends the first data to the designated external device through the corresponding logical extension interface through the logical extension interface driver, and further comprising:
when the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as second data, and then carries out protocol packaging on the second data;
The SPI slave controller drives to send second data from the SPI slave controller interface to the SPI master controller interface through an SPI bus;
the SPI main controller driver receives the second data from the SPI main controller interface, submits the second data to the virtual bus controller driver for private data protocol analysis, encapsulates the private data protocol analysis into a data format required by the corresponding virtual device driving layer, and returns the data to the corresponding virtual device driving layer.
3. The method for realizing controller interface expansion based on the BMC chip according to claim 2, wherein the FPGA module is further provided with a logic control core layer; the method further comprises the steps of:
the FPGA module abstracts each logic extension interface into a structure for initializing, sending and receiving data so as to register a controller core layer;
after the FPGA module is electrified, the logic control core layer initializes the FPGA module;
the SPI master controller driver sends first data to the SPI slave controller interface through the SPI bus from the SPI master controller interface, and then still includes:
the logic control core layer calls the SPI to acquire first data from the controller driver, then analyzes the first data based on a target protocol, and creates a data processing thread according to the target protocol;
The data processing thread distributes the first data to a logic external expansion interface driver corresponding to the appointed external equipment;
the logic extension interface driver performs privatization processing on the first data and sends the first data to the appointed external equipment through the logic extension interface.
4. The method for implementing controller interface expansion based on BMC chip as claimed in claim 3, wherein the logic external expansion interface driver performs privatization processing on the first data and sends the first data to the designated external device through the logic external expansion interface, and further comprising:
when the external equipment is appointed to respond to the request of the first data, the FPGA module obtains response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as third data, and then carries out protocol packaging on the third data;
and the logic control core layer submits the packed third data to the response queue, and monitors the third data of different response queues to asynchronously send the third data to the BMC module through the SPI bus.
5. The method for implementing controller interface expansion based on a BMC chip of claim 1, further comprising:
when the data needs to be sent to the appointed external equipment and the interface expansion system does not meet the first condition, the BMC module obtains the data needing to be sent and marks the data as fourth data;
The Linux application layer packs the fourth data through a protocol and then sends the fourth data to an SPI main controller driver of the Linux kernel layer;
the SPI master controller drives the fourth data to be sent from the SPI master controller interface to the SPI slave controller interface through the SPI bus;
the FPGA module acquires fourth data through the SPI slave controller interface, carries out protocol analysis on the fourth data and sends the fourth data to the SPI slave controller for driving;
the SPI slave controller drives to send fourth data to the appointed external equipment through the corresponding logic extension interface by the logic extension interface drive;
when the appointed external equipment responds to a sending request of fourth data and sends response data, the FPGA module obtains the response data from the corresponding logic extension interface based on the logic extension interface drive, marks the response data as fifth data, and then carries out protocol packaging on the fifth data;
the SPI slave controller drives the fifth data to be sent from the SPI slave controller interface to the SPI master controller interface through an SPI bus;
the SPI main controller drives to send fifth data to a Linux application layer through a Linux kernel;
and the Linux application layer performs protocol unpacking processing on the fifth data.
6. The method for realizing controller interface expansion based on the BMC chip according to claim 3, wherein the BMC module adopts Loongson 2K0500 as a processing chip; the FPGA module adopts a high cloud GW2R as a processing chip; the logic external expansion interface comprises an SPI interface, a GPIO interface, a UART interface, a PWM interface, a TACH interface, an IIC interface and an ADC interface; the external equipment comprises a temperature sensor, a voltage sensor, a fan rotating speed sensor, a BIOS module of the server, a watchdog module of the server main board and a BMC module; a real-time system based on FreeRtos is operated at the soft core end of the FPGA module; and the program of the soft core end of the FPGA module is stored in the SPIflash of the FPGA module.
7. A method for implementing controller interface expansion based on a BMC chip as claimed in claim 3, wherein the virtual bus controller driver is used to define different bus transfer method function sets; the SPI master controller is used for matching different SPI master controller interfaces through the equipment tree; the logic control core layer is used for uniformly receiving data from the SPI slave controller interface and calling controller drivers of different logic ends to finish data transmission; the logic extension interface driver is used for registering the driver to the logic control core layer; the virtual device driving layer is provided with a hwmon_ops interface and an IIC driver; the method further comprises the steps of:
the hwmon_ops interface is used for finding out an i2c_adapter structure body driven by the virtual bus controller by calling an i2c_master_send interface of the IIC core layer and calling a transmission interface thereof to perform data reading and data writing;
IIC drives register IIC core layers;
the IIC driver triggers probe driver initialization to register the hwmon driver.
8. The method for realizing controller interface expansion based on the BMC chip according to claim 7, wherein the virtual bus controller driver is provided with an i2c_adapter structure and an iiqdev device tree node; the method further comprises the steps of:
The i2c_adapter structure registers the IIC core layer;
the iiqdev device tree node constructs an iic_client device description structure by binding with the i2c_adapter structure;
the iic_client device description structure and IIC driver determine the type of IIC bus by matching the name or ID;
initializing a probe driver to construct an xxx_master bus controller structure and a spi_master bus controller structure;
the spixxx driver device driver realizes SPI bus type pairing with the external device through a name, and triggers a probe driver after the driver is matched with the external device;
the spiflash driver and the spixxx driver device driver respectively register the SPI core layer.
9. The method for realizing controller interface expansion based on the BMC chip according to claim 8, wherein the SPI main controller is provided with a spiBoard info structure and an acpi node; the method further comprises the steps of:
the SPI master controller driven spi_master bus controller structure body registers an SPI core layer, and is bound with the master bus controller structure body through bus_id information to construct a spidevice equipment description structure body driven by the virtual bus controller;
the SPI_transfer transmission interface driven by the SPI master controller calls the spi_write interface function of the SPI core layer to find a structural body of the SPI master bus controller driven by the SPI master controller and call the transmission interface to realize actual data transmission;
The SPI_transfer transmission interface driven by the SPI main controller transmits data to the FPGA module through an SPI bus;
the probe driving structure driven by the SPI main controller constructs a spi_master bus controller structure driven by the SPI main controller;
the platform device structure body driven by the SPI main controller is matched with the platform driver platform driving structure body through the type of the matched platform bus;
the device tree spi controller node parses the platform device structure.
10. An interface expansion system, characterized by being applied to the method for realizing controller interface expansion based on the BMC chip according to any of claims 1-9; the system comprises a server, a BMC module and an FPGA module; the BMC module is deployed on the server; the FPGA module is in communication connection with the BMC module through an SPI bus, and the BMC module comprises a Linux application layer, a Linux kernel layer and an SPI main controller interface; the Linux kernel layer is provided with a Linux kernel and an SPI main controller driver; the FPGA module is provided with an SPI slave controller interface, an SPI slave controller drive, a logic external expansion interface drive and a plurality of logic external expansion interfaces; the logic external expansion interface is used for communication connection with external equipment.
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