CN116302770A - Debugging method and device of chip software, electronic equipment and storage medium - Google Patents

Abstract

The disclosure provides a debugging method and device of chip software, electronic equipment and a storage medium. The chip debugging method comprises the following steps: acquiring a debugging instruction of chip software driven by a peripheral circuit, wherein the debugging instruction comprises an input and output instruction; mapping the input and output instructions into memory read-write instructions; and debugging the chip software driven by the peripheral circuit according to the memory read-write instruction.

Description

Debugging method and device of chip software, electronic equipment and storage medium

Technical Field

The present disclosure relates to the technical field of CPU core design and software simulation debugging, and more particularly, to a method and apparatus for debugging chip software, an electronic device, and a storage medium.

Background

A System On Chip (SOC) requires software debugging at the Pre-silicon stage before silicon. For example, software debugging is performed using an emulation platform or a software emulation platform, or directly on an SOC chip.

Compared with the method for debugging the chip software on the debugging platform, the method for directly debugging the chip software on the SOC chip is more convenient, time-saving and labor-saving. However, if software debugging is performed by using the existing SOC board, software debugging cannot be performed due to the difference between the peripheral circuit of the SOC chip to be debugged and the peripheral circuit of the existing SOC chip.

Disclosure of Invention

The disclosure provides a debugging method and device of chip software, electronic equipment and a storage medium.

According to one aspect of the present disclosure, the present disclosure proposes a method for debugging chip software, including: acquiring a debugging instruction of chip software driven by a peripheral circuit, wherein the debugging instruction comprises an input and output instruction; mapping the input and output instructions into memory read-write instructions; and

and debugging the chip software driven by the peripheral circuit according to the memory read-write instruction.

According to an embodiment of the present disclosure, mapping an input-output instruction to a memory read-write instruction includes: acquiring an input/output address indicated by an input/output instruction; mapping the input/output address into a memory address; and generating a memory read-write instruction according to the memory address.

According to an embodiment of the present disclosure, mapping an input-output address to a memory address includes: performing fixed offset operation on the input and output addresses to obtain an initial address, wherein the initial address is positioned in a memory address segment range; and dividing the initial address into a plurality of address segments, wherein the memory address comprises a plurality of address segments, under the condition that the length of the initial address is determined to be larger than the preset length.

According to an embodiment of the present disclosure, the input/output instructions include an input instruction and an output instruction, the memory read/write instruction includes a memory read instruction and a memory write instruction, and mapping the input/output instruction to the memory read/write instruction includes: mapping the input instruction into a memory read instruction; and mapping the output instruction to a memory write instruction. .

According to the embodiment of the disclosure, according to a memory read-write instruction, debugging is performed on chip software driven by a peripheral circuit, including: generating an interrupt signal based on the input/output instruction; and under the instruction of the interrupt signal, simulating the read-write operation of the peripheral circuit on the chip software by using the interrupt processing program according to the memory read-write instruction so as to simulate the debugging operation of the chip software based on the input/output instruction.

According to an embodiment of the present disclosure, under the instruction of an interrupt signal, a peripheral circuit is simulated to read and write operations of chip software according to a memory address by using an interrupt processing program, including: acquiring a working signal of an interrupt processing program under the indication of an interrupt signal; under the condition that the working signal is determined to be in an enabling state, controlling the interrupt processing program to return to the memory address; and simulating the read-write operation of the peripheral circuit on the chip software according to the memory address by using the interrupt processing program to obtain a read-write result.

According to an embodiment of the present disclosure, under the instruction of an interrupt signal, using an interrupt processing program to simulate a read-write operation of a peripheral circuit on chip software according to a memory address, further includes: simulating a read-write result by using an interrupt processing program; and sending the simulated read-write result to a connection interface with the peripheral circuit.

According to an embodiment of the present disclosure, the method for debugging the chip software further includes: acquiring an analog signal aiming at chip software; under the condition that the analog signal is determined to be in an enabling state, mapping the input and output instruction into a memory read-write instruction so as to debug chip software driven by the peripheral circuit according to the memory read-write instruction; and under the condition that the analog signal is determined to be in a non-enabling state, debugging the chip software driven by the peripheral circuit according to the input and output instruction.

According to an embodiment of the present disclosure, obtaining an input/output address indicated by an input/output instruction includes: identifying an instruction type of an input/output instruction; generating a combined decoding logic according to the instruction type; and decoding the input and output instructions by utilizing the combined decoding logic to obtain the input and output addresses for debugging the chip software.

According to another aspect of the embodiments of the present disclosure, there is provided a debugging device of chip software, including: the acquisition module is used for acquiring a debugging instruction of chip software driven by the peripheral circuit, wherein the debugging instruction comprises an input and output instruction; the mapping module is used for mapping the input and output instructions into memory read-write instructions; and the debugging module is used for debugging the chip software driven by the peripheral circuit according to the memory read-write instruction.

According to another aspect of the embodiments of the present disclosure, there is provided an electronic device including: one or more processors; and a storage means for storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the methods provided in accordance with the embodiments of the present disclosure.

According to another aspect of the disclosed embodiments, there is provided a computer-readable storage medium having stored thereon executable instructions that, when executed by a processor, cause the processor to perform a method provided according to the disclosed embodiments.

According to the embodiment of the disclosure, by utilizing the characteristic that Input/Output (I/O) operations and memory read-write operations of a processor can be implemented by the same instruction, an IO instruction of a peripheral circuit of a chip for performing I/O operations on software is mapped to a memory read-write instruction. When the processor simulates the debugging operation of the peripheral circuit on the chip software, the debugging operation is identified as the memory reading operation, so that the debugging of the peripheral circuit on the chip software is realized. Therefore, software of the SOC chip to be debugged can simulate various peripheral circuits on the existing SOC single board supporting the instruction mapping function to debug the software, so that the time cost and the labor cost of the debugging process are saved, and the software development progress is accelerated.

Drawings

The above and other objects, features and advantages of the embodiments of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure taken in conjunction with the accompanying drawings. It should be noted that throughout the appended drawings, like elements are represented by like or similar reference numerals. In the figure:

FIG. 1 illustrates an application scenario diagram of a method, apparatus, device, medium, and program product for debugging chip software according to an embodiment of the present disclosure;

FIG. 2 illustrates a flow chart of a method of debugging chip software according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a method of debugging chip software according to an embodiment of the present disclosure;

FIG. 4 illustrates a flow chart of a method of debugging chip software according to another embodiment of the present disclosure;

FIG. 5 shows a block diagram of a debugging device of chip software according to an embodiment of the present disclosure; and

fig. 6 shows a block diagram of an electronic device adapted to implement a method of debugging chip software according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments that would be apparent to one of ordinary skill in the art without the benefit of this disclosure are within the scope of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting the disclosure in any way, but are merely examples of embodiments of the disclosure. Conventional structures or constructions will be omitted when they may cause confusion in understanding the present disclosure.

Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be in a general sense understood by those skilled in the art. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Hereinafter, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the drawings, the same reference numerals are given to constituent parts having substantially the same or similar structures and functions, and repeated description thereof will be omitted.

Fig. 1 illustrates an application scenario diagram of a method, apparatus, device, medium, and program product for debugging chip software according to an embodiment of the present disclosure.

As shown in fig. 1, SOC chip 110 is an existing chip after the chip is streamed. The SOC chip 120 is a target chip that is located in the Pre-silicon stage and needs software debugging. The SOC chip 110 and the SOC chip 120 are electrically connected through an I/O interface, and software debugging is performed on the SOC chip 120 by using the SOC chip 110.

For example, the processor 111 of the SOC chip 110 has an analog function. The processor 111 of the SOC chip 110 performs I/O operations on software functions driven by the peripheral circuits 121 of the SOC chip 120 to implement debugging of the chip software by the peripheral circuits 121.

For example, the processor 111 of the SOC chip 110 may be a fifth generation processor CPU of an open source instruction set architecture based on the reduced instruction set (Reduced Instruction Set Computer V, RISC-V) principle. Peripheral circuitry 121 of SOC chip 120 may be a peripheral IP core (Peripheral IP Core) of SOC chip 120. The IP Core is an intellectual property Core (Intellectual Property Core, IP Core). The IP core is a pre-designed circuit function module. The peripheral IP core is a peripheral special function IP core except for an embedded CPU in the SOC chip.

For example, the peripheral IP core operates under the control of a RISC-V CPU that controls the peripheral IP core by performing read and write operations on registers of the peripheral IP core. The registers of the peripheral IP core include control registers and status registers. RISC-V CPU can implement control over peripheral IP core by writing configuration to control registers. The RISC-V CPU can obtain the current working state of the peripheral IP core by reading the data in the state register.

The processor 111 of the SOC chip 110 controls the peripheral circuit 121 of the SOC chip 120 within a certain address range to perform I/O operation on the chip software, and maps the I/O instruction corresponding to the I/O operation to a memory read/write instruction of the SOC chip 110. Thus, the processor 111 of the SOC chip 110 recognizes the I/O operation as a memory read/write operation, and simulates the read/write reaction of the peripheral circuit 121 of the SOC chip 120 through the SOC chip 110, thereby realizing the simulation and debugging of the chip software driven by the peripheral circuit 121 of the SOC chip 120.

Fig. 2 shows a flowchart of a method of debugging chip software according to an embodiment of the present disclosure.

As shown in fig. 2, the debugging method of the chip software of this embodiment includes operations S210 to S230.

In operation S210, a debug instruction for the peripheral circuit-driven chip software is acquired, the debug instruction including an input-output instruction.

In operation S220, the input/output instruction is mapped to a memory read/write instruction.

In operation S230, the chip software driven by the peripheral circuit is debugged according to the memory read-write command.

In the embodiment of the disclosure, a CPU of a chip acquires a debugging instruction of chip software driven by a peripheral circuit, and the chip software is debugged based on the debugging instruction. The input/output instructions (I/O instructions) include an input instruction (I instruction) and an output instruction (O instruction), and the memory read/write instructions (R/W instructions) include a memory read instruction (R instruction) and a memory write instruction (W instruction). The CPU may map an input instruction (I instruction) to a memory read instruction (R instruction) and an output instruction (O instruction) to a memory write instruction (W instruction).

The CPU may perform an input operation on the chip software based on the mapped R instruction, and may perform an output operation on the chip software based on the mapped W instruction.

In the embodiment of the present disclosure, the above-described method of debugging software (operations S210 to S230) may be applied to an SOC chip including a RISC-V CPU. The RISC-V CPU performing operation S220 to map the input-output instruction to a memory read-write instruction may include: acquiring an input/output address corresponding to the input/output instruction; mapping the input/output address into a memory address; and generating a memory read-write instruction according to the memory address.

For example, due to the characteristic that the RISCV CPU performs I/O operation and the instruction for performing memory read/write operation are the same, when the RISC-V CPU performs debugging on software driven by peripheral circuits in a certain I/O address based on the I/O instruction, the I/O address corresponding to the I/O operation can be automatically mapped to the memory read/write address, so that the RISC-V CPU can perform the I/O operation in the software debugging process based on the memory read/write address.

In an embodiment of the present disclosure, the RISC-V CPU performing an operation of acquiring an input-output address corresponding to an input-output instruction may include: identifying an instruction type of an input/output instruction; generating a combined decoding logic according to the instruction type; and decoding the input and output instructions by utilizing the combined decoding logic to obtain the input and output address for debugging the chip software.

For example, debug instructions may belong to input-output instructions of the RISC-V architecture, the types of debug instructions including R-type instructions for register-register operations, L-type instructions for short immediate and memory Load operations, S-type instructions for memory Store operations, B-type instructions for conditional jump operations, U-type instructions for long immediate, and J-type instructions for unconditional jumps.

For example, the debug instruction may be a LOAD/STORE (LOAD/STORE) instruction. The LOAD/STORE instruction is used to access memory and peripheral circuitry. The LOAD instruction is an L-type instruction and the STORE instruction is an S-type instruction. The LOAD instruction is used to copy the effective address of the memory or peripheral circuitry into a register. The STORE instruction is used to copy the effective value (address) of a register into the effective address of a memory or peripheral circuit.

For example, the RISC-V CPU analyzes the content of the 32bit debug instruction to obtain a first function, a second function, a first source register, a second source register, a target register and an operation code of the debug instruction. The RISC-V CPU reads the operation code of the debugging instruction, and determines the instruction type of the debugging instruction by identifying the operation code of the debugging instruction. The first function, the second function, the first source register, the second source register, and the destination register are decoded using a combinational decoding logic corresponding to the instruction type. For example, under the first function and/or the second function, various logic operations are performed on the value of the register and the immediate to obtain the peripheral circuit address of the target chip.

In the embodiment of the disclosure, the operation performed by the RISC-V CPU to map the input/output address to the memory address may include performing a fixed offset operation on the input/output address to obtain an initial address, where the initial address is located in the memory address segment range; and dividing the initial address into a plurality of address segments, wherein the memory address comprises a plurality of address segments, under the condition that the length of the initial address is determined to be larger than the preset length.

For example, the offset address is used to perform a fixed offset operation on the input/output address in the range of the peripheral circuit address segment, so that the input/output address falls into the range of the memory address segment to obtain the initial address. For example, the memory address field may be an address field of a random access memory (Random Access Memory, RAM) of the memory.

The length of the mapped initial address may be greater than the length that the register can store. Thus, the initial address may be divided into a plurality of address segments of smaller length so that the plurality of address segments may be written into the register. For example, the size of the memory occupied by the mapped initial address is 3G, the initial address is divided into a plurality of address segments, and the size of each address segment is 10kb to 1000kb. The smaller address field of the occupied memory is convenient to read and use. The memory address is read in the form of a plurality of address segments.

In the embodiment of the disclosure, the mapped memory address is also output to the bus, and the memory address is read through the bus.

In the disclosed embodiment, after the input/output address is mapped to the memory address by the RISC-V CPU, the I/O interface of the RISC-V CPU connected to the peripheral circuit is recognized as a part of the memory by the RISC-V CPU. RISC-V CPUs may access the I/O interface in the form of access memory units based on memory addresses. RISC-V CPU indirectly drives peripheral circuit to work by reading memory address, so as to raise the convenience of debugging peripheral circuit.

Fig. 3 shows a schematic diagram of a debugging method of chip software according to an embodiment of the present disclosure.

As shown in fig. 3, chip 300a and chip 300b may be SOC chips.

Chip 300a includes a processor 310, memory 320, and I/O interface 330. Processor 310 may be a RISC-V CPU and memory 320 may be RAM. Chip 300a includes peripheral circuitry 340. Peripheral circuitry 340 is a peripheral IP core to be debugged. Chip 300a and chip 300b are connected through I/O interface 330, chip 300a performing a chip software debug method on chip 300 b.

Processor 310 of chip 300a performs debug operations (I/O operations) on software driven by peripheral circuitry 340 of chip 300b via I/O interface 330. The instructions for the processor 310 of the chip 300a to perform the I/O operations are the same as the instructions for the processor 310 of the chip 300a to perform memory read and write operations to the memory 320.

In the disclosed embodiment, the processor 310 includes a simulator 311 and a mapper 312. Simulator 311 may simulate the debug operation of peripheral circuit 340. The mapper 312 may map the I/O address to a memory address.

For example, an enable bit is set for simulator 311 in a status register of processor 310. The state of the analog signal is determined based on the enable bit. When the enable bit is set to a default value or 0, the simulator 311 is in a reset state and the simulation signal is in a disable state. When the enable bit is set to 1, the simulator 311 is in the enable state, and the simulation signal is in the enable state.

When the analog signal is in an enable state, the mapper 312 maps the I/O address to a memory address that falls within the address field of the memory 320. Processor 310 then performs the software debugging operations by peripheral circuitry 340 in accessing memory 320 based on the mapped memory addresses.

A method of debugging software of a chip is exemplarily described with reference to fig. 4. Fig. 4 shows a flowchart of a method of debugging chip software according to another embodiment of the present disclosure.

As shown in fig. 4, the chip debugging method of this embodiment includes operations S410 to S480.

In operation S410, an analog signal for chip software is acquired.

In operation S420, it is determined whether the analog signal is in an enable state. If not, operation S430 is performed, and if yes, operation S440 is performed.

In operation S430, the chip software driven by the peripheral circuit is debugged according to the input/output instruction.

In operation S440, the input-output instruction is mapped to a memory read-write instruction.

In operation S450, an interrupt signal is generated based on the input/output instruction.

In operation S460, it is determined whether the operation signal of the interrupt handler is an enable state. If yes, operation S470 is performed, and if no, operation S480 is performed.

In operation S470, the interrupt handler is utilized to simulate the read/write operation of the peripheral circuit to the chip software according to the memory address, so as to obtain the read/write result.

In operation S480, a next debug instruction for the peripheral circuit-driven chip software is acquired, and execution returns to operation S440.

Referring to fig. 3, the processor 310 of the chip 300a performs a debugging operation (I/O operation) on software driven by the peripheral circuit 340 of the chip 300b through the I/O interface 330 based on a debugging instruction for the software driven by the peripheral circuit 340 of the chip 300 b. Before performing the debug operation, it is determined whether the analog signal for chip 300b is in an enabled state.

After the enable bit of simulator 311 is reset (set to 0), the analog signal for chip 300a may be considered to be in a disabled state, with simulator 311 and mapper 312 not operating. In case that it is determined that the analog signal is in the disabled state, the processor 310 performs operation S430 to output the input/output instruction to the bus and debug the software driven by the peripheral circuit 340 in the IO operation manner through the input/output instruction.

After the enable position of the simulator 311 is set to 1, the simulator 311 and the mapper 312 can be considered to operate with respect to the analog signal of the chip 300a as an enable state. In case that it is determined that the analog signal is in the enable state, the processor 310 performs operation S440 through the mapper 312, maps a debug instruction (I/O instruction) of software driven for the peripheral circuit 340, obtains a memory read/write instruction, and inputs the memory read/write instruction to the bus.

After the processor 310 receives the memory read/write command, the simulator 311 generates an interrupt signal.

In the embodiment of the present disclosure, the interrupt signal of the simulator 311 may be the interrupt signal having the highest priority among all interrupt signals of the processor 310, and cannot be masked. After the simulator 311 generates the interrupt signal, the interrupt handler may simulate the read/write behavior of the register in the peripheral circuit 340 to the chip software according to the memory read/write command under the instruction of the interrupt signal, so as to simulate the debugging operation of the chip software based on the input/output command.

For example, a working signal of the interrupt processing program is obtained, under the condition that the working signal is in an enabling state, a memory address corresponding to a memory read-write instruction returned by the interrupt processing program is controlled, and a read-write operation of a peripheral circuit on chip software is simulated according to the memory address by the interrupt processing program, so that a read-write result is obtained.

The working signal may be generated by a counter of the interrupt handler.

For example, when the value of the counter is 0, the operation signal is in a disabled state. It may be considered that the interrupt handler has completed the debugging operation of the software driven by the peripheral circuit 340 based on the current memory address, and may acquire the next debugging instruction for the software driven by the peripheral circuit of the chip 300b, and execute operation S440 again.

For example, when the value of the counter is 1, the operation signal is in an enable state. It may be considered that the interrupt handler has not completed the debug operation of the software driven by the peripheral circuitry 340 based on the current memory address. The interrupt return address of the interrupt handler is a memory address so that the processor 310 may repeat a debug operation (I/O operation) based on the memory address. The interrupt handler uses the RAM to simulate read and write operations of the peripheral circuit 340 to obtain read and write results. The read-write result may be considered as a debug result.

In the embodiment of the present disclosure, the interrupt handler is controlled to simulate the read-write result, and the simulated read-write result is sent to the I/O interface with the peripheral circuit 340, so that the peripheral circuit 340 accesses the read-write result to complete the debugging.

According to the embodiment of the disclosure, the I/O address is mapped to the memory address, and the read-write operation of the peripheral circuit is simulated through the memory, so that the debug operation (I/O operation) of the peripheral circuit is identified as the read-write operation of the memory, thereby realizing the simulation and the debug of the software driven by the peripheral circuit. The software driven by the peripheral circuit is debugged through the memory address, so that the time cost and the labor cost of the debugging process can be saved, and the software development progress is accelerated.

Fig. 5 shows a block diagram of a debugging device of chip software according to an embodiment of the present disclosure.

As shown in fig. 5, the chip debug apparatus 500 of this embodiment includes an acquisition module 510, a mapping module 520, and a debug module 530.

The obtaining module 510 is configured to obtain a debug instruction for a chip software driven by a peripheral circuit, where the debug instruction includes an input/output instruction. In an embodiment, the obtaining module 510 may be configured to perform the operation S210 described above, which is not described herein.

The mapping module 520 is configured to map the input/output instruction into a memory read/write instruction. In an embodiment, the mapping module 520 may be configured to perform the operation S220 described above, which is not described herein.

The debugging module 530 is used for debugging the chip software driven by the peripheral circuit according to the memory read-write instruction. In an embodiment, the debug module 530 may be used to perform the operation S230 described above, which is not described herein.

According to an embodiment of the present disclosure, the mapping module 520 includes an acquisition unit, a mapping unit, and a generation unit. The acquisition unit is used for acquiring an input/output address corresponding to the input/output instruction. The mapping unit is used for mapping the input/output address into a memory address. The generating unit is used for generating a memory read-write instruction according to the memory address.

According to the embodiment of the disclosure, the obtaining unit is configured to further identify an instruction type of the input/output instruction, generate a combined decoding logic according to the instruction type, and decode the input/output instruction by using the combined decoding logic to obtain an input/output address for debugging the chip software.

The mapping unit is also used for carrying out fixed offset operation on the input and output addresses to obtain an initial address, wherein the initial address is positioned in the memory address segment range; and dividing the initial address into a plurality of address segments, wherein the memory address comprises a plurality of address segments, under the condition that the length of the initial address is determined to be larger than the preset length.

According to an embodiment of the present disclosure, the debug module 530 includes a generation unit and an emulation unit. The generating unit is used for generating an interrupt signal based on the input and output instructions. The simulation unit is used for simulating the read-write operation of the peripheral circuit on the chip software according to the memory read-write instruction by using the interrupt processing program under the instruction of the interrupt signal so as to simulate the debugging operation of the chip software based on the input/output instruction.

The simulation unit is also used for acquiring a working signal of the interrupt processing program under the instruction of the interrupt signal; under the condition that the working signal is determined to be in an enabling state, controlling the interrupt processing program to return to the memory address; and simulating the read-write operation of the peripheral circuit on the chip software according to the memory address by using the interrupt processing program to obtain a read-write result.

The simulation unit is also used for simulating the read-write result by using the interrupt processing program; and sending the simulated read-write result to a connection interface with the peripheral circuit.

According to an embodiment of the present disclosure, the chip debug apparatus 500 is also used to obtain an analog signal for chip software; under the condition that the analog signal is determined to be in an enabling state, mapping the input and output instruction into a memory read-write instruction so as to debug chip software driven by the peripheral circuit according to the memory read-write instruction; and under the condition that the analog signal is determined to be in a non-enabling state, debugging the chip software driven by the peripheral circuit according to the input and output instruction.

Any of the plurality of modules of the acquisition module 510, the mapping module 520, and the debug module 530 may be combined in one module to be implemented, or any of the plurality of modules may be split into a plurality of modules, according to embodiments of the present disclosure. Alternatively, at least some of the functionality of one or more of the modules may be combined with at least some of the functionality of other modules and implemented in one module. According to embodiments of the present disclosure, at least one of the acquisition module 510, the mapping module 520, and the debug module 530 may be implemented at least in part as hardware circuitry, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system-on-chip, a system-on-substrate, a system-on-package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging circuitry, or in any one of or a suitable combination of any of three implementations of software, hardware, and firmware. Or at least one of the acquisition module 510, the mapping module 520 and the debugging module 530 may be at least partially implemented as a computer program module which, when executed, may perform the corresponding functions.

Fig. 6 shows a block diagram of an electronic device adapted to implement a method of debugging chip software according to an embodiment of the present disclosure.

As shown in fig. 6, the electronic device 600 may be a SOC chip. The electronic device 600 according to the embodiment of the present disclosure includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603. The processor 601 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. Processor 601 may also include on-board memory for caching purposes. The processor 601 may comprise a single processing unit or a plurality of processing units for performing different actions of the method flows according to embodiments of the disclosure.

In the RAM 603, various programs and data necessary for the operation of the electronic apparatus 600 are stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The processor 601 performs various operations of the method flow according to the embodiments of the present disclosure by executing programs in the ROM 602 and/or the RAM 603. Note that the program may be stored in one or more memories other than the ROM 602 and the RAM 603. The processor 601 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in the one or more memories.

According to an embodiment of the present disclosure, the electronic device 600 may further include a main storage unit and a cache unit described in the previous embodiments. The main storage unit and the cache unit are used for storing target data and domain information. The processor 601 performs various appropriate actions and processes on target data and domain information in the main storage unit and/or the cache unit according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 606 into a Random Access Memory (RAM) 603. The main storage unit and the cache unit described in the previous embodiments may also be located in different electronic devices with respect to the processor 610 according to the embodiments of the present disclosure. The processor 601 performs various appropriate actions and processes on target data and domain information in a main storage unit and/or a cache unit of another electronic device according to a program stored in a Read Only Memory (ROM) 602 or a program loaded from a storage section 608 into a Random Access Memory (RAM) 603.

According to an embodiment of the present disclosure, the electronic device 600 may also include an input/output (I/O) interface 605, the input/output (I/O) interface 605 also being connected to the bus 604. The electronic device 600 may also include one or more of the following components connected to the I/O interface 605: an input portion 606 including a keyboard, mouse, etc.; an output portion 607 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 608 including a hard disk and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, or the like. The communication section 609 performs communication processing via a network such as the internet. The drive 610 is also connected to the I/O interface 605 as needed. Removable media 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on drive 610 so that a computer program read therefrom is installed as needed into storage section 608.

The present disclosure also provides a computer-readable storage medium that may be embodied in the apparatus/device/system described in the above embodiments; or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present disclosure.

According to embodiments of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to embodiments of the present disclosure, the computer-readable storage medium may include ROM 602 and/or RAM 603 and/or one or more memories other than ROM 602 and RAM 603 described above.

Embodiments of the present disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowcharts. When the computer program product runs in a computer system, the program code is used for enabling the computer system to realize the debugging method of the chip software provided by the embodiment of the disclosure.

The above-described functions defined in the system/apparatus of the embodiments of the present disclosure are performed when the computer program is executed by the processor 601. The systems, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program may also be transmitted, distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and/or installed from the removable medium 611. The computer program may include program code that may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.

In such an embodiment, the computer program may be downloaded and installed from a network through the communication portion 609, and/or installed from the removable medium 611. The above-described functions defined in the system of the embodiments of the present disclosure are performed when the computer program is executed by the processor 601. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the disclosure.

According to embodiments of the present disclosure, program code for performing computer programs provided by embodiments of the present disclosure may be written in any combination of one or more programming languages, and in particular, such computer programs may be implemented in high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. Programming languages include, but are not limited to, such as Java, c++, python, "C" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (12)

1. A debugging method of chip software comprises the following steps:

acquiring a debugging instruction of chip software driven by a peripheral circuit, wherein the debugging instruction comprises an input and output instruction;

mapping the input and output instructions into memory read-write instructions; and

and debugging the chip software driven by the peripheral circuit according to the memory read-write instruction.

2. The method for debugging the chip software according to claim 1, wherein the mapping the input/output instruction into a memory read/write instruction comprises:

acquiring an input/output address corresponding to the input/output instruction;

mapping the input/output address into a memory address; and

and generating a memory read-write instruction according to the memory address.

3. The method for debugging the chip software according to claim 2, wherein the mapping the input/output address to a memory address comprises:

performing fixed offset operation on the input and output addresses to obtain initial addresses, wherein the initial addresses are positioned in the memory address segment range; and

and dividing the initial address into a plurality of address segments under the condition that the length of the initial address is determined to be larger than the preset length, wherein the memory address comprises the address segments.

4. The method for debugging the chip software according to claim 1, wherein the input-output instructions comprise an input instruction and an output instruction, the memory read-write instructions comprise a memory read instruction and a memory write instruction, and the mapping the input-output instructions into the memory read-write instructions comprises:

mapping the input instruction into the memory read instruction; and

and mapping the output instruction into the memory write instruction.

5. The method for debugging the chip software according to claim 2, wherein the debugging the chip software driven by the peripheral circuit according to the memory read-write instruction comprises:

generating an interrupt signal based on the input/output instruction; and

and under the instruction of the interrupt signal, simulating the read-write operation of the peripheral circuit to the chip software by using an interrupt processing program according to the memory read-write instruction so as to simulate the debugging operation of the chip software based on the input and output instruction.

6. The method for debugging the chip software according to claim 5, wherein the simulating the read-write operation of the peripheral circuit to the chip software by using the interrupt handler according to the memory address under the instruction of the interrupt signal comprises:

acquiring a working signal of the interrupt processing program under the indication of the interrupt signal;

controlling the interrupt handler to return to the memory address under the condition that the working signal is determined to be in an enabling state; and

and simulating the read-write operation of the peripheral circuit to the chip software according to the memory address by using an interrupt processing program to obtain a read-write result.

7. The method for debugging chip software according to claim 6, wherein said simulating the read-write operation of the peripheral circuit to the chip software by using the interrupt handler according to the memory address under the instruction of the interrupt signal further comprises:

simulating the read-write result by using the interrupt handler; and

and sending the simulated read-write result to a connection interface with the peripheral circuit.

8. The debugging method of chip software of claim 1, further comprising:

acquiring an analog signal aiming at the chip software;

under the condition that the analog signal is determined to be in an enabling state, mapping the input and output instruction into a memory read-write instruction so as to debug the chip software driven by the peripheral circuit according to the memory read-write instruction; and

and under the condition that the analog signal is in a non-enabling state, debugging the chip software driven by the peripheral circuit according to the input and output instruction.

9. The method for debugging chip software according to claim 2, wherein the acquiring the input-output address corresponding to the input-output instruction comprises:

identifying the instruction type of the input/output instruction;

generating a combined decoding logic according to the instruction type; and

and decoding the input and output instructions by utilizing the combined decoding logic to obtain the input and output address for debugging the chip software.

10. A debugging apparatus of chip software, comprising:

the acquisition module is used for acquiring a debugging instruction of chip software driven by the peripheral circuit, wherein the debugging instruction comprises an input and output instruction;

the mapping module is used for mapping the input and output instructions into memory read-write instructions; and

and the debugging module is used for debugging the chip software driven by the peripheral circuit according to the memory read-write instruction.

11. An electronic device, comprising:

one or more processors;

storage means for storing one or more programs,

wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the method of any of claims 1-9.

12. A computer readable storage medium having stored thereon executable instructions which, when executed by a processor, cause the processor to perform the method according to any of claims 1 to 9.

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