CN116302097A - Multi-core processor shared data access design method based on spin lock - Google Patents
Multi-core processor shared data access design method based on spin lock Download PDFInfo
- Publication number
- CN116302097A CN116302097A CN202211042527.1A CN202211042527A CN116302097A CN 116302097 A CN116302097 A CN 116302097A CN 202211042527 A CN202211042527 A CN 202211042527A CN 116302097 A CN116302097 A CN 116302097A
- Authority
- CN
- China
- Prior art keywords
- lock
- register
- atomic
- processor core
- atomic lock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000002787 reinforcement Effects 0.000 abstract description 3
- 230000003471 anti-radiation Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 3
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
The invention relates to a design method for sharing data access of multi-core processors based on spin lock. The invention designs two 4N-bit anti-radiation reinforcement atomic lock registers, which can realize two register atomic locks, each register can be divided into a high 2N bit part and a low 2N bit part, wherein the low 2N bit part stores an identification number COREN_ID of a processor core applying the register atomic lock, and the high 2N bit part stores an identification number LOCKn_ID of the processor core currently obtaining the register atomic lock. The method can reduce the dependence of the atomic operation accessing the shared data in the multi-core task scheduling on the software algorithm, further reduce the thread execution error caused by malicious attack on the atomic operation software algorithm, and is a high-safety and high-reliability multi-core scheduling atomic lock implementation method.
Description
Technical Field
The invention belongs to the field of thread synchronization, and relates to a shared data access design method of a multi-core processor based on a high-safety and high-reliability spin lock.
Background
Common general multi-core processor systems (such as desktop-level, server-level, mobile-side high-performance multi-core processors and the like) protect system shared resources by adopting a mode of inquiring and acquiring atomic locks when shared data is required to be accessed according to the requirements of application scenes on high-performance and high-real-time scheduling, and the processor executes the atomic lock operation, so that the atomic lock can be set in an external memory such as DDR (double data rate) and the like to carry out locking and unlocking protection operation on the access of certain multi-core shared resources, and access conflict is avoided when other cores or other threads access the shared data at the same time.
The multi-core processor developed for the application scene in the aerospace field can be influenced by cosmic environmental radiation in terms of high-reliability design and atomic lock data stored in external memories such as DDR (double data rate) and the like; from the high security design, the multi-core scheduling of the existing operating system mainly depends on a software algorithm, and the thread execution error and even the multi-core system crash can be caused by malicious attack aiming at the atomic operation. In order to ensure the reliability of the task, a safer scheduling method is to realize relatively fixed scheduling according to the demands of application programs, and reduce the dependence on software algorithms.
Disclosure of Invention
The technical solution of the invention is as follows: aiming at the high-reliability and high-safety application requirements of the multi-core processor in the aerospace field, the register atomic lock operation meeting the fixed scheduling requirement is provided, and the method is a high-safety and high-reliability multi-core scheduling atomic lock implementation method.
The technical scheme of the invention is as follows: the design method for sharing data access of the multi-core processor based on spin lock realizes the dispatching of threads to the sharing data access by providing a mode of register atomic lock for the multi-core processor; the register atomic lock is realized by a 4N-bit atomic lock register; n is the number of cores of the processor;
dividing an atomic lock register into a high 2N bit part and a low 2N bit part;
setting the low 2N bit of the atomic lock register as a CORNEn_ID area, and storing an identification number CORNEn_ID of a processor core applying for the atomic lock of the register, wherein the low N bit in the CORNEn_ID area represents the value of the CORNEn_ID, and the high N bits CORNEn_ID_WEN are write enabling of corresponding bits of the low N bits respectively;
setting the high 2N bits of the atomic lock register as a LOCKn_ID area, and storing an identification number LOCKn_ID of a processor core currently attempting to acquire the atomic lock of the register, wherein the low N bits in the LOCKn_ID area represent the value of the LOCKn_ID, and the high N bits LOCKn_ID_WEN are write enabling of corresponding bits of the low N bits respectively;
each processor core has the same opportunity to acquire a register atomic lock;
at the same time, the same register atomic lock is at most available to only one processor core.
Preferably, the number of bits of the atomic lock registers is determined according to the number of cores of the processors, each atomic lock register implements a register atomic lock, and the register atomic lock implemented by a single 4N-bit atomic lock register is suitable for checking access schedule of shared addresses by at most N processors.
Preferably, the lock register stores a lock_id area of a processor core identifier currently attempting to acquire the atomic lock of the register, including:
the LOCKn_ID of the lower N bit of the area can be written only when the corresponding enabling bit is valid, the LOCKn_ID is only readable when the corresponding enabling bit is invalid, the value of the LOCKn_ID is 0 and represents that the register atomic lock is in a release state, and when the value of the LOCKn_ID is not 0, the value represents the identification number of the processor core which is currently attempted to acquire the register atomic lock;
the upper N bits LOCKn_ID_WEN of the area are enabled bits of LOCKn_ID, which correspond to write enable bits of lower N bits respectively, the enabled bits are valid when high, the enabled bits are invalid when low, and hardware is automatically cleared after the LOCKn_ID_WEN is written.
Preferably, the atomic lock register stores an identification number coren_id area of a processor core that is applying for the atomic lock of the register, and includes:
the lower N bits CORN_ID of the area can be written only when the corresponding enabling bit is valid, the CORN_ID is only readable when the corresponding enabling bit is invalid, and the CORN_ID stores the identification number of each processor core currently applying the register atomic lock;
the upper N bits CORN_ID_WEN of the region are the enabling bits of CORN_ID, which correspond to the write enabling bits of the lower N bits respectively, the enabling bits are valid when the enabling bits are high, the enabling bits are invalid when the enabling bits are low, and hardware is automatically cleared after the CORN_ID_WEN is written.
Preferably, the processor core acquiring the register atomic lock includes:
the processor core requests the atomic lock of the register, reads the value of LOCKn_ID in the atomic lock register corresponding to the atomic lock of the register, judges whether the atomic lock register is in a release state, if so, writes the identification number of the processor core into the CORN_ID area in the atomic lock register, otherwise, exits the request;
reading the identification number of the processor core currently requesting the atomic lock from a CORN_ID area in the atomic lock register, judging the priority according to the read value, writing the identification number of the processor core into the LOCK_ID of the atomic lock register when the processor core has the highest priority, otherwise, clearing the identification number of the processor core in the CORN_ID area;
judging whether the processor core in the LOCKn_ID of the atomic lock register is unique or not, if so, the processor core successfully acquires the atomic lock of the register, otherwise, clearing the identification numbers of the processor core in the LOCKn_ID area and the COREN_ID area in the atomic lock register, and releasing the atomic lock of the register.
Preferably, the priority judgment mode of each processor core request register atomic lock is a polling mode, in one priority judgment, the priority is granted to the next processor core next to the processor core which takes the atomic lock last time, and if the processor core to which the priority is granted is empty, the priority is extended to the next immediately adjacent processor core.
Preferably, the atomic lock history register is set to store the identification number of the processing core that acquired the atomic lock of the register last time for priority judgment.
Preferably, for an operating system of the multi-core processor, the unlimited quantity of atomic locks are realized through the combination of the global variable locks and the register atomic locks, so as to meet the scheduling requirements of different application scenes in the operating system.
Preferably, the operating system of the multi-core processor uses global variable locks to store locks used for inter-thread scheduling, and sets global variable locks stored at different addresses according to the number requirements of applications, so as to realize the number of atomic locks meeting the application requirements.
Preferably, before and after executing the access operation on the global variable lock, the processor core performs locking and unlocking of the register atomic lock to protect the access operation, and the processor checks the access operation of the global variable lock, including:
reading the global variable to obtain the value of the current global variable lock;
comparing whether the value of the current global variable lock is the same as the expected value, and judging whether the lock is in a release state or not;
if the global variable lock is not in a released state, the request fails;
if the global variable lock is in a released state, the processor core takes the lock and writes a new value to the global variable to indicate that the lock is occupied.
Preferably, performing a locking operation of the register atomic lock includes: if the value of LOCKn_ID in the atomic lock register is judged to be the identification number of the processor core, the atomic lock is not judged to be failed in request, and the request operation is continuously executed after the atomic lock embedding mark is carried out, so that the condition of deadlock caused by the fact that the processor core holding the atomic lock of the register is interrupted and broken and then the atomic lock of the same register is requested again is avoided.
Preferably, the method further comprises:
after the access operation of executing the global variable lock under the protection of the register atomic lock is completed, the processor core performs the unlocking operation of the register atomic lock, which comprises the following steps:
judging whether an atomic lock nesting mark exists or not and whether the global variable lock request is successful or not;
if the request global variable lock is unsuccessful, releasing the register atomic lock and re-requesting the register atomic lock and the global variable lock;
if the request global variable lock is successful and the atomic lock embedding mark is not available, releasing the register atomic lock;
if the request global variable lock is successful and the atomic lock embedding mark exists, the register atomic lock is released when the program which is to be interrupted by embedding does not release the register atomic lock to unlock the register atomic lock.
Preferably, the global variable lock is released by writing a specific value representing lock idleness to the corresponding global variable.
A multi-core processor shared data access system based on spin lock comprises a register atomic lock, wherein the register atomic lock is used for realizing the scheduling of shared data access among different threads of the multi-core processor; each processor core has the same opportunity to acquire a register atomic lock; at the same time, the same register atomic lock can be acquired by one processor core at most;
the register atomic lock is realized by a 4N-bit atomic lock register; n is the number of cores of the processor;
the low 2N bit of the atomic lock register is a CORN_ID area, the identification number CORN_ID of the processor core applying for the atomic lock of the register is saved, wherein the low N bit in the CORN_ID area represents the value of the CORN_ID, and the high N bits CORN_ID_WEN are respectively the write enabling of the corresponding bits of the low N bits;
the upper 2N bits of the atomic lock register are the lock n_id field, which holds the identification number lock_id of the processor core currently attempting to acquire the atomic lock of the register, wherein the lower N bits in the lock n_id field represent the value of lock n_id, and the upper N bits lock n_id WEN are each the write enable of the corresponding bits of the lower N bits.
Preferably, the system further comprises an atomic lock history register, which is used for storing the identification number of the processing core that acquires the atomic lock of the register last time and judging the priority of the processor core in the process of requesting the atomic lock of the register; the priority judgment mode of each processor core request register atomic lock is a polling mode, in the primary priority judgment, the priority is authorized to the next processor core which is close to the processor core which takes the atomic lock last time, and if the processor core which is granted by the priority is empty, the priority is extended to the next processor core which is close to the processor core.
Preferably, the system further comprises a global variable lock, and the processor core performs locking and unlocking of the register atomic lock to protect the access operation before and after executing the access operation on the global variable lock.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention provides a multi-core processor shared data access design method based on high-safety and high-reliability spin lock, which can store atomic lock data in an anti-radiation reinforcement register in a chip, improves the protection capability of the atomic lock data in a cosmic radiation environment, reduces the dependence of the atomic operation for accessing shared data in multi-core task scheduling on a software algorithm, and further reduces thread execution errors caused by malicious attack on the atomic operation software algorithm, and is a high-safety and high-reliability multi-core scheduling atomic lock implementation method;
(2) According to the method, through the hardware implementation characteristics of the atomic lock register, a specific locking and unlocking mode is designed, the dependence of the atomic operation for accessing shared data in multi-core task scheduling on a software algorithm is reduced, and further thread execution errors caused by malicious attack on the atomic operation software algorithm are reduced, so that the method is a high-safety multi-core scheduling atomic lock implementation method;
(3) The invention sets the writing enabling area of the processor core identification number in the atomic lock register, and ensures that each processor core can only modify the identification number corresponding to the processor core when writing operation is executed to the atomic lock register through the hardware design of the enabling bit, and the hardware design ensures the atomicity of the register atomic lock request acquisition operation of the processor core without changing the written state of other processor cores;
(4) According to the invention, the atomic lock register and the atomic lock history register are set, so that the processor core currently applying for the atomic lock of the register and the processor core last acquiring the atomic lock of the register can be obtained, and the transparency of the shared data access state of the multi-core processor system to a user is improved;
(5) The register atomic lock and the global variable lock are combined to realize an unlimited quantity of atomic locks, so that the number requirement of a multi-core processor operating system on the atomic locks can be met, and the flexibility of the multi-core processor on a shared data access mode is improved;
(6) According to the design method for sharing data access of the multi-core processor, the atomic lock embedding mark is arranged, so that the application scene of atomic lock embedding caused by interruption can be met, and the adaptability of a thread scheduling mode of the multi-core processor to an operating system is improved.
Drawings
FIG. 1 is a flow chart of a register atomic lock acquisition in a shared data access method of a multi-core processor of the present invention;
FIG. 2 is a schematic diagram of an atomic lock register structure in a method for sharing data access by a multi-core processor according to the present invention;
FIG. 3 is a diagram of a multiprocessor core request register atomic lock in the shared data access method of the multicore processor of the present invention;
FIG. 4 is a flow chart of unlimited atomic lock design in the shared data access method of the multi-core processor of the present invention.
Detailed Description
The invention is described in further detail below with reference to the attached drawing figures:
in a multi-core processor system, in order to achieve correct scheduling between threads in different processor cores, an atomic lock protection mode is required to access shared data. When the processor core applies for acquiring the atomic lock, firstly, inquiring whether the atomic lock is being held by other processor cores, if the atomic lock is in a release state, successfully acquiring the atomic lock by the processor core, and releasing the held atomic lock after the access to the protected shared resource is performed; if the atomic lock is being held by another processor core, the processor core enters a loop state and continually queries and attempts to acquire the atomic lock until the atomic lock is successfully acquired.
The invention relates to an atomic lock implementation method based on a radiation-resistant reinforcement register, which can effectively ensure the safe access of different threads of a multi-core processor to shared data. The method designs a 4N-bit atomic lock register, can provide a register atomic lock for thread scheduling for a multi-core processor, and can be held by one processor core at most at any running time of a system.
The atomic lock register is used for storing atomic lock data and comprises an identification number COREN_ID of a processor core applying for the atomic lock of the register and an identification number LOCKn_ID of the processor core currently obtaining the atomic lock of the register, and meanwhile, an atomic lock history register is also arranged in the design method, and is used for storing the identification number of the processor core which is obtained from the atomic lock of the register last time and judging the priority of the atomic lock obtaining request of the register, wherein the priority judging mode of the atomic lock of each processor core requesting the atomic lock of the register is a polling mode, so that each processor core has the same opportunity to obtain the atomic lock of the register. In a priority determination of a request register atomic lock, priority is granted to the next processor core immediately adjacent to the processor core that last took the atomic lock, and priority is continued to the next immediately adjacent processor core if the processor core to which priority was granted is empty.
Example 1
Referring to fig. 1, fig. 1 is a flowchart illustrating a process of acquiring a register atomic lock according to an embodiment of the present invention. The step of acquiring the register atomic lock comprises the steps of:
s101, the processor core first reads the processor core identifier lock_id in the atomic lock register, which represents the current holding of the atomic lock of the register.
S102, judging whether the register atomic lock is in a release state, if the LOCKn_ID in the atomic lock register is all 0, indicating that the register atomic lock is in the release state, continuing to execute the request operation for acquiring the register atomic lock, and if the LOCKn_ID is not all 0, indicating that the register atomic lock is not in the release state, and ending the request operation by the processor core.
S103, the processor core writes an identification number core_ID of the processor core into a COREN_ID area in the atomic lock register, wherein the identification number core_ID indicates that the processor core is requesting the atomic lock of the register.
S104, the processor core reads out the processor core identification number which is taken to the register atomic lock last time from the atomic lock history register, reads out each processor core identification number which is currently requesting the register atomic lock from the COREN_ID area in the atomic lock register, and is used for judging the priority of the request for acquiring the register atomic lock.
And S105, the processor core judges the priority according to the read value, if the processor core judges that the processor core has the priority of acquiring the register atomic lock, the subsequent operation of acquiring the register atomic lock is continuously executed, and if the processor core judges that other processor cores currently have the priority of acquiring the register atomic lock according to the priority, the processor core requests that the register atomic lock fails, and S106 is executed.
S106, clearing the identification number core_ID of the processor core in the COREN_ID area, and ending the request operation.
S107, the processor core priority judging result is that the processor core has the priority of taking the atomic lock of the register, and the identification number core_ID of the processor core is written into the LOCK_ID of the atomic lock register.
S108, the processor core reads the LOCKn_ID value from the LOCKn_ID area in the atomic lock register, judges whether the LOCKn_ID area has only the identification number of the processor core, if so, the processor core successfully acquires the atomic lock of the register, executes S110, and if the LOCKn_ID area has a plurality of processor core identification numbers, the processor core requests that the atomic lock of the register fails because of the write operation performed by checking the LOCKn_ID area by a plurality of processors, and executes S109.
S109, the identification number core_ID of the processor core in the LOCKn_ID area and the COREN_ID area is cleared, and the request operation is ended.
S110, successfully acquiring the atomic lock of the register, updating the atomic lock history register, and writing the identification number core_ID of the processor core into the atomic lock history register.
Referring to fig. 2, fig. 2 is a schematic diagram of an atomic lock register. Each atomic lock register may be divided into a high sixteen bits and a low sixteen bits, where the low sixteen bits are the coren_id region, holding the identification number of the processor core that is applying for the register atomic lock, and the high sixteen bits are the lock_id region, holding the identification number of the processor core that is currently acquiring the register atomic lock.
The LOCKn_ID area and the COREN_ID area respectively comprise a data area and a write enable area of each area processor core identification number, the length of the data area is eight bits, so that the register atomic lock is suitable for access scheduling of up to eight processor cores to check shared addresses, meanwhile, through the hardware design of the write enable area, each processor core can only modify the identification number corresponding to the processor core when performing write operation to an atomic lock register, the state written by other processor cores is not changed, and the hardware design ensures the atomicity of the register atomic lock request acquisition operation by the processor cores.
The upper eight bits of the LOCKn_ID_WEN of the LOCKn_ID area are enabled bits of the LOCKn_ID, and the upper eight bits of the LOCKn_ID area are respectively corresponding to the writing enabling of the lower eight bits of the LOCKn_ID of the area, the enabled bits are enabled when being high, the enabled bits are disabled when being low, and the hardware is automatically cleared after the LOCKn_ID_WEN is written. The lower eight bits of the LOCKn_ID area correspond to the identification numbers of the eight processor cores, respectively, and can only be written when their corresponding enable bits are valid, and the LOCKn_ID is only readable when the corresponding enable bits are invalid. When the value of lock_id is 0, the value of lock_id represents the identifier of the processor core that currently acquires the register atomic lock.
The upper eight bits of the COREN_ID area are the enabling bits of the COREN_ID, the enabling bits correspond to the writing enabling bits of the lower eight bits of the COREN_ID of the area respectively, the enabling bits are valid when high, the disabling bits are invalid when low, and the hardware is automatically cleared after the COREN_ID_WEN is written. The lower eight bits of the coren_id region correspond to the identification numbers of the eight processor cores, respectively, and can only be written when the corresponding enable bit is valid, and the coren_id is only readable when the corresponding enable bit is invalid, and the coren_id stores the identification number of the processor core currently applying for the register atomic lock.
When the processor core executes unlocking operation, the identification numbers of the processor core in the LOCK n_ID area and the COREN_ID area in the atomic lock register are cleared, and the atomic lock of the register is released.
Referring to fig. 3, fig. 3 is a schematic diagram of a plurality of processor cores requesting the same register atomic LOCK in the embodiment of the present invention, and it is assumed that the processor cores 0, 1, and 3 are requesting the same register atomic LOCK, the initial value of the atomic LOCK register LOCKREG is 0, and the initial value of the atomic LOCK history register h_lock is 7. In the first step, the values obtained by the three processor cores accessing the atomic lock register are all 0, and the judgment results are that the locks are in a release state, so that the request operation is continuously executed.
Step two, each of the three processor cores writes a respective processor core identification number core0_id, core1_id, core3_id to the coren_id region of the atomic lock register.
Step three, the processor core which holds the lock last time is the core 7 through reading the atomic lock history register, the priority level is judged, the processor core0 has the priority of acquiring the atomic lock of the register, then the processor core0 writes the identification number of the processor core into the LOCKn_ID area of the atomic lock register, the processor core1 and the processor core3 clear the identification number of the processor core in the CORN_ID area of the atomic lock register, the request operation is ended, and a new request is started.
And step four, the processor core0 reads the atomic lock register, confirms that the processor core identification number of the LOCK n_ID area is unique, successfully acquires the atomic lock of the register, and finishes the request operation after writing the processor core identification number into the atomic lock history register.
Step five, after the execution of the protected thread, the processor core0 clears the identification number of the processor core in the atomic lock register coren_id area and the lock_id area, and releases the register atomic lock.
Step six, the processor core1 and the processor core3 inquire that the atomic lock of the register is released, and write the respective processor core identification numbers into the cor en_id area of the atomic lock register.
Step seven, the processor core0 which is the last time the lock is taken is known by reading the atomic lock history register, the processor core1 has priority after priority judgment, the atomic lock of the register is successfully obtained, the atomic lock history register is updated, the processor core3 requests failure, the request operation is ended, and a new request is started.
Step eight, after the processor core1 completes executing the protected thread, the identification number of the processor core in the atomic lock register coren_id area and the lock_id area is cleared, and the register atomic lock is released.
Step nine, the processor core3 inquires that the atomic lock of the register is released, writes the identification number of the processor core into the coren_id area of the atomic lock register, and since the last time the lock is taken to be the processor core1, the priority should be granted to the processor core 2 first, but the processor core 2 does not initiate the lock acquisition request, so the priority is extended to the processor core3, and the processor core3 successfully acquires the atomic lock of the register.
Example 2
For the application based on the multi-core processor on the operating system, the design method can be combined with the global variable to realize unlimited atomic lock so as to meet the scheduling requirements of different application scenes in the operating system. In the multi-core operating system, the global variable is used for storing locks used for scheduling among threads, and global variable locks stored at different addresses can be set according to application requirements, so that the number of atomic locks meeting the application requirements is realized.
When the processor core requests the atomic lock of the register, if the processor core judges that the value of LOCKn_ID in the atomic lock register is the identification number of other processor cores, which represents that the atomic lock of the register is being held by other processor cores, the processor core requests the atomic lock of the register to fail, if the processor core judges that the value of LOCKn_ID in the atomic lock register is the identification number of the processor core, the processor core does not judge that the request fails, and continues to execute the request operation after the atomic lock embedding mark is carried out, so that the deadlock phenomenon caused by the fact that the processor core holding the atomic lock of the register is interrupted and then requests the atomic lock of the same register again is avoided.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating steps of a processor core obtaining a global variable lock, and a process of obtaining the global variable lock includes:
s401, firstly, a processor core performs a register atomic lock locking operation, and reads the value of LOCK n_ID in an atomic lock register.
S402, judging whether the value of LOCKn_ID is the identification number of other processor cores, if so, requesting register atomic lock failure, ending the request operation and starting to make a new request, and if not, executing S403.
S403, judging whether LOCKn_ID is all 0 or the processor core identification number, if LOCKn_ID is the processor core identification number, executing S404, and if LOCKn_ID is all 0, executing S405.
S404, the processor core judges that the value of LOCKn_ID is the identification number of the processor core, and atomic lock embedding marking is carried out.
S405-S406, the processor core continues to perform the request register atomic lock operation, if the request fails, ends this request operation and starts a new request, if the request succeeds, then S407 is performed.
S407, the processor core successfully acquires the register atomic lock, starts the access operation to the global variable lock, reads the global variable to obtain the current value of the global variable lock.
S408, the processor core compares whether the value of the current global variable lock is identical to the expected value, judges whether the lock is in a release state, if the value of the global variable lock is not identical to the expected value, the global variable lock is not in the release state, the request fails, S409 is executed, otherwise, the global variable lock is in the release state, and S410 is executed.
S409, the processor core requests that the global variable lock is unsuccessful, releases the register atomic lock, and begins a new request.
S410, the processor core judges that the global variable lock is in a release state, successfully acquires the lock, and writes a new value into the global variable to indicate that the lock is occupied.
S411, after the processor core requests the global variable lock successfully, judging whether an atomic lock nesting mark exists, if so, ending the request, not releasing the register atomic lock, continuing to execute downwards, namely executing the later user program protected by the atomic lock, and if not, executing S412.
And S412, the processor core judges that the atomic lock embedding mark does not exist, releases the atomic lock of the register, finishes the request, continues to execute downwards, and executes the following user program protected by the atomic lock.
After executing the protected task, the processor core releases the global variable lock by writing a specific value to the global variable lock that represents lock idleness.
The invention is not described in detail in part as being well known in the art.
Claims (16)
1. A multi-core processor shared data access design method based on spin lock is characterized in that: the method comprises the steps that a mode of providing a register atomic lock for a multi-core processor is adopted, so that the scheduling of threads on shared data access is realized; the register atomic lock is realized by a 4N-bit atomic lock register; n is the number of cores of the processor;
dividing an atomic lock register into a high 2N bit part and a low 2N bit part;
setting the low 2N bit of the atomic lock register as a CORNEn_ID area, and storing an identification number CORNEn_ID of a processor core applying for the atomic lock of the register, wherein the low N bit in the CORNEn_ID area represents the value of the CORNEn_ID, and the high N bits CORNEn_ID_WEN are write enabling of corresponding bits of the low N bits respectively;
setting the high 2N bits of the atomic lock register as a LOCKn_ID area, and storing an identification number LOCKn_ID of a processor core currently attempting to acquire the atomic lock of the register, wherein the low N bits in the LOCKn_ID area represent the value of the LOCKn_ID, and the high N bits LOCKn_ID_WEN are write enabling of corresponding bits of the low N bits respectively;
each processor core has the same opportunity to acquire a register atomic lock;
at the same time, the same register atomic lock is at most available to only one processor core.
2. The method according to claim 1, characterized in that: the number of bits of the atomic lock registers is determined according to the number of cores of the processors, each atomic lock register realizes one register atomic lock, and the register atomic lock realized by a single 4N-bit atomic lock register is suitable for the access scheduling of up to N processors checking the shared address.
3. The method according to claim 1, characterized in that: the lock_id area of the atomic lock register for storing the processor core identifier of the atomic lock currently attempting to acquire the atomic lock of the register includes:
the LOCKn_ID of the lower N bit of the area can be written only when the corresponding enabling bit is valid, the LOCKn_ID is only readable when the corresponding enabling bit is invalid, the value of the LOCKn_ID is 0 and represents that the register atomic lock is in a release state, and when the value of the LOCKn_ID is not 0, the value represents the identification number of the processor core which is currently attempted to acquire the register atomic lock;
the upper N bits LOCKn_ID_WEN of the region are enabled bits of LOCKn_ID, which correspond to write enable bits of lower N bits respectively, the enabled bits are valid when high, the enabled bits are invalid when low, and the LOCKn_ID_WEN is automatically cleared after being written.
4. The method according to claim 1, characterized in that: the atomic lock register stores an identification number coren_id area of a processor core applying for the atomic lock of the register, and includes:
the lower N bits CORN_ID of the area can be written only when the corresponding enabling bit is valid, the CORN_ID is only readable when the corresponding enabling bit is invalid, and the CORN_ID stores the identification number of each processor core currently applying the register atomic lock;
the upper N bits CORN_ID_WEN of the region are the enabling bits of CORN_ID, which correspond to the write enabling bits of the lower N bits respectively, are valid when the enabling bits are high, are invalid when the enabling bits are low, and are automatically cleared after the CORN_ID_WEN is written.
5. The method according to claim 1, characterized in that: the processor core fetch register atomic lock includes:
the processor core requests the atomic lock of the register, reads the value of LOCKn_ID in the atomic lock register corresponding to the atomic lock of the register, judges whether the atomic lock register is in a release state, if so, writes the identification number of the processor core into the CORN_ID area in the atomic lock register, otherwise, exits the request;
reading the identification number of the processor core currently requesting the atomic lock from a CORN_ID area in the atomic lock register, judging the priority according to the read value, writing the identification number of the processor core into the LOCK_ID of the atomic lock register when the processor core has the highest priority, otherwise, clearing the identification number of the processor core in the CORN_ID area;
judging whether the processor core in the LOCKn_ID of the atomic lock register is unique or not, if so, the processor core successfully acquires the atomic lock of the register, otherwise, clearing the identification numbers of the processor core in the LOCKn_ID area and the COREN_ID area in the atomic lock register, and releasing the atomic lock of the register.
6. The method according to claim 5, wherein: the priority judgment mode of each processor core request register atomic lock is a polling mode, in the primary priority judgment, the priority is authorized to the next processor core which is close to the processor core which takes the atomic lock last time, and if the processor core which is granted by the priority is empty, the priority is extended to the next processor core which is close to the processor core.
7. The method according to claim 5 or 6, characterized in that: and storing the identification number of the processing core which acquires the atomic lock of the register last time by setting the atomic lock history register for priority judgment.
8. The method according to claim 1, characterized in that: for an operating system of the multi-core processor, unlimited atomic locks are realized through the combination of global variable locks and register atomic locks, so that the scheduling requirements of different application scenes in the operating system are met.
9. The method according to claim 8, wherein: the operating system of the multi-core processor uses the global variable locks to store locks used for inter-thread scheduling, and sets the global variable locks stored at different addresses according to the number requirements of the applications, so as to realize the number of the atomic locks meeting the application requirements.
10. The method according to claim 8, wherein: before and after executing the access operation on the global variable lock, the processor core performs locking and unlocking of the register atomic lock to protect the access operation, and the processor core checks the access operation of the global variable lock and comprises the following steps:
reading the global variable to obtain the value of the current global variable lock;
comparing whether the value of the current global variable lock is the same as the expected value, and judging whether the lock is in a release state or not;
if the global variable lock is not in a released state, the request fails;
if the global variable lock is in a released state, the processor core takes the lock and writes a new value to the global variable to indicate that the lock is occupied.
11. The method according to claim 10, wherein: performing a locking operation of a register atomic lock includes: if the value of LOCKn_ID in the atomic lock register is judged to be the identification number of the processor core, the atomic lock is not judged to be failed in request, and the request operation is continuously executed after the atomic lock embedding mark is carried out, so that the condition of deadlock caused by the fact that the processor core holding the atomic lock of the register is interrupted and broken and then the atomic lock of the same register is requested again is avoided.
12. The method according to claim 11, wherein: the method further comprises the steps of:
after the access operation of executing the global variable lock under the protection of the register atomic lock is completed, the processor core performs the unlocking operation of the register atomic lock, which comprises the following steps:
judging whether an atomic lock nesting mark exists or not and whether the global variable lock request is successful or not;
if the request global variable lock is unsuccessful, releasing the register atomic lock and re-requesting the register atomic lock and the global variable lock;
if the request global variable lock is successful and the atomic lock embedding mark is not available, releasing the register atomic lock;
if the request global variable lock is successful and the atomic lock embedding mark exists, the register atomic lock is released when the program which is to be interrupted by embedding does not release the register atomic lock to unlock the register atomic lock.
13. The unlimited-amount atomic lock of claim 10, wherein: the global variable lock is released by writing a specific value representing lock idleness into the corresponding global variable.
14. A multi-core processor shared data access system based on spin lock, characterized in that: the method comprises the steps of including a register atomic lock, and realizing the scheduling of shared data access among different threads of the multi-core processor through the register atomic lock; each processor core has the same opportunity to acquire a register atomic lock; at the same time, the same register atomic lock can be acquired by one processor core at most;
the register atomic lock is realized by a 4N-bit atomic lock register; n is the number of cores of the processor;
the low 2N bit of the atomic lock register is a CORN_ID area, the identification number CORN_ID of the processor core applying for the atomic lock of the register is saved, wherein the low N bit in the CORN_ID area represents the value of the CORN_ID, and the high N bits CORN_ID_WEN are respectively the write enabling of the corresponding bits of the low N bits;
the upper 2N bits of the atomic lock register are the lock n_id field, which holds the identification number lock_id of the processor core currently attempting to acquire the atomic lock of the register, wherein the lower N bits in the lock n_id field represent the value of lock n_id, and the upper N bits lock n_id WEN are each the write enable of the corresponding bits of the lower N bits.
15. The system according to claim 14, wherein: the atomic lock history register is used for storing the identification number of the processing core which acquires the atomic lock of the register at the last time and judging the priority of the processor core in the process of requesting the atomic lock of the register; the priority judgment mode of each processor core request register atomic lock is a polling mode, in the primary priority judgment, the priority is authorized to the next processor core which is close to the processor core which takes the atomic lock last time, and if the processor core which is granted by the priority is empty, the priority is extended to the next processor core which is close to the processor core.
16. The system according to claim 14, wherein: the system also comprises a global variable lock, and the processor core respectively locks and unlocks the register atomic lock before and after executing the access operation on the global variable lock to protect the access operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211042527.1A CN116302097A (en) | 2022-08-29 | 2022-08-29 | Multi-core processor shared data access design method based on spin lock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211042527.1A CN116302097A (en) | 2022-08-29 | 2022-08-29 | Multi-core processor shared data access design method based on spin lock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116302097A true CN116302097A (en) | 2023-06-23 |
Family
ID=86785631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211042527.1A Pending CN116302097A (en) | 2022-08-29 | 2022-08-29 | Multi-core processor shared data access design method based on spin lock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116302097A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118260090A (en) * | 2024-05-29 | 2024-06-28 | 山东云海国创云计算装备产业创新中心有限公司 | Spin lock management apparatus, spin lock management method, storage medium, and program product |
-
2022
- 2022-08-29 CN CN202211042527.1A patent/CN116302097A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118260090A (en) * | 2024-05-29 | 2024-06-28 | 山东云海国创云计算装备产业创新中心有限公司 | Spin lock management apparatus, spin lock management method, storage medium, and program product |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8775708B2 (en) | Increasing functionality of a reader-writer lock | |
| US8473969B2 (en) | Method and system for speeding up mutual exclusion | |
| CA1324837C (en) | Synchronizing and processing of memory access operations in multiprocessor systems | |
| US8973004B2 (en) | Transactional locking with read-write locks in transactional memory systems | |
| US10929201B2 (en) | Method and system for implementing generation locks | |
| US5579505A (en) | Memory access system and method for granting or preventing atomic or nonatomic memory access requests to shared memory regions | |
| EP3701377B1 (en) | Method and apparatus for updating shared data in a multi-core processor environment | |
| US5872980A (en) | Semaphore access control buffer and method for accelerated semaphore operations | |
| CN102262559B (en) | Resource sharing method and system | |
| US20040068607A1 (en) | Locking memory locations | |
| CN107357648B (en) | Method for realizing spin lock when multi-core CPU accesses resources | |
| US20070124546A1 (en) | Automatic yielding on lock contention for a multi-threaded processor | |
| US11056145B2 (en) | Global secondary path locking technique enabling high read concurrency for read-mostly workloads | |
| US20150052529A1 (en) | Efficient task scheduling using a locking mechanism | |
| US6842809B2 (en) | Apparatus, method and computer program product for converting simple locks in a multiprocessor system | |
| CN106716348A (en) | Shared resources in a data processing appartus for executing a plurality of threads | |
| US20160098361A1 (en) | Optimization of Data Locks for Improved Write Lock Performance and CPU Cache usage in Mulit Core Architectures | |
| JP2001265611A (en) | Computer system, memory management method, storage medium and program transmitter | |
| CN116302097A (en) | Multi-core processor shared data access design method based on spin lock | |
| CN105094993B (en) | The method and device that a kind of multi-core processor, data synchronize | |
| US10310916B2 (en) | Scalable spinlocks for non-uniform memory access | |
| Alon et al. | Deterministic abortable mutual exclusion with sublogarithmic adaptive rmr complexity | |
| CN110837422A (en) | Multithreading access method, multithreading access system, electronic terminal and storage medium | |
| WO2018136847A1 (en) | Locally poll flag in multi processing node system to determine whether a resource is free to use for thread | |
| CN112346879B (en) | Process management method, device, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |