CN116301664B

CN116301664B - Memory controller, memory component, electronic device and command caching method

Info

Publication number: CN116301664B
Application number: CN202310545828.4A
Authority: CN
Inventors: 吴峰; 杜倩倩
Original assignee: Beijing Xiangdixian Computing Technology Co Ltd
Current assignee: Beijing Xiangdixian Computing Technology Co Ltd
Priority date: 2023-05-16
Filing date: 2023-05-16
Publication date: 2023-08-15
Anticipated expiration: 2043-05-16
Also published as: CN116301664A

Abstract

The present disclosure provides a controller, a component, an electronic device, and a command caching method for a memory. The controller comprises a command queue, a write control module and a command scheduling module; the command queue is configured to cache each access command, the command queue comprises a write queue and a read queue, and the head of the write queue and the head of the read queue are respectively arranged at the head of the command queue and the tail of the command queue, or are respectively arranged at the tail of the command queue and the head of the command queue; the write control module is configured to write the currently received write access command into the write queue when receiving the write access command, and write the currently received read access command into the read queue when receiving the read access command; and the command scheduling module is configured to arbitrate each access command in the command queue, and select a target access command from the command scheduling module to access the memory. The command scheduling delay in the process of accessing the memory by the controller is greatly shortened, and the working frequency of the controller chip is improved.

Description

Memory controller, memory component, electronic device and command caching method

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a controller, a component, electronic equipment and a command caching method of a memory.

Background

Memory chips such as synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), synchronous graphic random access memory (Synchronous Graphics Random Access Memory, SGRAM), high bandwidth memory (High Bandwidth Memory, HBM) and the like, which are managed by memory cells (banks), are widely used on chips such as System on Chip (SoC) chips, micro control units (Microcontroller Unit, MCU) and the like, which require the use of memory chips. A memory cell (Bank) is a two-dimensional address memory array consisting of Row (Row) addresses and column (Col) addresses, and may be a memory cell group (Bank Groups) consisting of memory cell (Bank) address numbers.

In the command queue of the controller of the existing memory, the access command (whether read or write) is usually arranged from the head of the queue, in this case, if a certain command needs to be inserted in the middle, all commands need to be arbitrated to confirm the insertion position, and when the command is inserted, all commands after the position need to be moved one position backwards to be inserted, so that the time required for writing the command into the queue is long, thus the time delay required for command scheduling is long, and the working frequency of the controller chip and the access efficiency of the memory are limited.

Disclosure of Invention

The purpose of the present disclosure is to provide a controller, a component, an electronic device and a command caching method for a memory, which solve the technical problem of low access efficiency caused by long command scheduling delay of the memory in the prior art.

According to one aspect of the present disclosure, there is provided a controller of a memory, including a command queue, a write control module, and a command scheduling module;

the command queue is configured to cache each access command, the command queue comprises a write queue and a read queue, and the head of the write queue and the head of the read queue are respectively arranged at the head of the command queue and the tail of the command queue, or are respectively arranged at the tail of the command queue and the head of the command queue;

the write control module is configured to write the currently received write access command into the write queue when receiving the write access command, and write the currently received read access command into the read queue when receiving the read access command;

and the command scheduling module is configured to arbitrate each access command in the command queue, and select a target access command from the command scheduling module to access the memory.

In some embodiments, in the controller of the memory, the write control module is specifically configured to:

When an access command is received and a storage space exists in the command queue, determining a target insertion position of the currently received access command in the command queue according to the access type corresponding to the currently received access command, and writing the currently received access command into the target insertion position of the command queue;

when the access type corresponding to the currently received access command is read access, the target insertion position is located in the read queue, and when the access type corresponding to the currently received access command is write access, the target insertion position is located in the write queue.

when an access command is received and a storage space exists in the command queue, determining a target insertion position of the currently received access command in the command queue according to the access type corresponding to the currently received access command, judging whether the target insertion position is empty, if yes, directly writing the currently received access command into the target insertion position of the command queue, otherwise, pointing the access command at the target insertion position and all access commands between the access command and any storage space along the direction of the storage space, shifting one storage position along the target insertion position, and writing the currently received access command into the target insertion position of the command queue.

In some embodiments, in the controller of the above memory, the memory includes a plurality of memory cells, each memory cell including a plurality of rows;

the storage positions of all access commands corresponding to the same access type and the same storage unit address in the command queue are continuous;

the write control module is specifically configured to:

when an access command is received and a storage space exists in the command queue, determining a target insertion position of the currently received access command in the command queue according to the access type and the storage unit address corresponding to the currently received access command, so that after the currently received access command is inserted into the command queue, the storage positions of all the access commands corresponding to the same access type and the same storage unit address in the command queue are still continuous.

In some embodiments, in the controller of the memory, storage locations of the respective access commands corresponding to the same access type, the same storage unit address, and the same row address in the command queue are consecutive;

the write control module is specifically configured to:

when an access command is received and a storage space exists in the command queue, judging whether the current access command corresponding to the current access command exists in the command queue or not according to the access type, the storage unit address and the row address corresponding to the current access command;

If the access command corresponding to the same access type, the same storage unit address and the same row address with the currently received access command exists, determining the latter storage position of all the access commands corresponding to the same access type, the same storage unit address and the same row address in the command queue as the target insertion position of the currently received access command in the command queue, otherwise, judging whether the access command corresponding to the same access type and the same storage unit address with the currently received access command exists in the command queue currently;

if the access command with the same access type and the same storage unit address corresponding to the current received access command exists, determining the latter storage position of all the access commands with the same access type and the same storage unit address corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue, otherwise, determining the latter storage position of all the access commands with the same access type corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue.

the write control module is specifically configured to:

If the access command with the same access type and the same storage unit address corresponding to the current received access command exists, determining the latter storage position of all the access commands with the same access type and the same storage unit address corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue, otherwise, determining the target insertion position of the current received access command in the command queue according to the access type and the storage unit address corresponding to the current received access command, so that after the current received access command is inserted into the command queue, the access commands with the same access type corresponding to the current received access command in the command queue are arranged according to the increasing sequence of the corresponding storage unit address.

In some embodiments, in the controller of the memory, the command queue is further configured to, when one access command is read, advance each access command in the command queue, which is arranged after the currently read access command, by one storage location according to an access type corresponding to the currently read access command.

According to another aspect of the present disclosure, there is provided a memory access system including the memory controller of any one of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic assembly comprising the memory access system of any of the above embodiments.

According to another aspect of the present disclosure, there is provided an electronic device comprising the electronic assembly of any of the above embodiments.

According to another aspect of the present disclosure, there is provided a command buffering method of a memory, including:

writing the currently received write access command into a write queue of a command queue when receiving the write access command, and writing the currently received read access command into a read queue of the command queue when receiving the read access command;

the head of the write queue and the head of the read queue are respectively at the head of the command queue and the tail of the command queue, or are respectively at the tail of the command queue and the head of the command queue.

In some embodiments, in the command buffering method of the above memory, when a write access command is received, the write access command received currently is written into a write queue of the command queue, and when a read access command is received, the read access command received currently is written into a read queue of the command queue, including the following steps:

In some embodiments, the method for buffering commands in the memory writes the currently received access command into the target insertion position of the command queue, including the following steps:

and judging whether the target insertion position is empty, if so, directly writing the currently received access command into the target insertion position of the command queue, otherwise, directing the access command at the target insertion position and all access commands between the access command and any storage space along the direction of the storage space along the target insertion position, shifting one storage position forward, and writing the currently received access command into the target insertion position of the command queue.

In some embodiments, in the command buffering method of the memory, the memory includes a plurality of memory units, and each memory unit includes a plurality of rows;

When an access command is received and a storage space exists in a command queue, determining a target insertion position of the currently received access command in the command queue according to an access type corresponding to the currently received access command, wherein the method comprises the following steps of:

In some embodiments, in the command buffering method of the memory, storage positions of the respective access commands corresponding to the same access type, the same storage unit address and the same row address in the command queue are consecutive;

when an access command is received and a storage space exists in a command queue, determining a target insertion position of the currently received access command in the command queue according to the access type and the storage unit address corresponding to the currently received access command, wherein the target insertion position comprises the following steps:

Drawings

FIG. 1 is a schematic diagram of a controller of a memory according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a memory access system according to one embodiment of the present disclosure;

fig. 3 is a flowchart illustrating a command buffering method of a memory according to an embodiment of the disclosure.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

Some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.

The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

The controller comprises a command queue, a write control module and a command scheduling module; the command queue is configured to cache each access command, the command queue comprises a write queue and a read queue, and the head of the write queue and the head of the read queue are respectively arranged at the head of the command queue and the tail of the command queue, or are respectively arranged at the tail of the command queue and the head of the command queue; the write control module is configured to write the currently received write access command into the write queue when receiving the write access command, and write the currently received read access command into the read queue when receiving the read access command; and the command scheduling module is configured to arbitrate each access command in the command queue, and select a target access command from the command scheduling module to access the memory.

In the scheme, a queue head and queue tail bidirectional ordering method is adopted to replace a single sequence ordering method, two queues are formed from the direction from the queue head to the queue tail and from the queue tail to the queue head respectively, and ordering is performed simultaneously, which is equivalent to ordering of read access commands and ordering of write access commands in a queue cache (cache area) with a limited length, so that the full utilization of cache space is realized, and in addition, when the received access commands are inserted into the queue for ordering, half of time required for calculation and comparison (in the process of determining target insertion positions) is saved, thereby shortening the time required by command scheduling and improving the access efficiency of a memory. And the write operation can be simultaneously carried out on the write queue and the read queue, so that the speed of writing commands into the queue is increased.

In this scheme, when there is a storage space (empty storage position) in the command queue, the currently received access command, whether it is a read access command or a write access command, can be written into the command queue, and if it is a read access command, the command is inserted into the read queue; if the command is a write access command, the command is inserted into a write queue. That is, the lengths of the read queue and the write queue are respectively dependent on the number of read access commands and write access commands in the access commands which are currently cached and not read in the command queue, so that the problems that a large number of gaps exist in the read queue (or the write queue) and the write queue (or the read queue) overflows are avoided, and the utilization rate of the queue cache is remarkably improved.

One embodiment of the present disclosure provides a controller of a memory, as shown in fig. 1, the controller including a command queue, a write control module, and a command scheduling module;

Wherein the memory includes a plurality of memory cells (banks), each memory cell (Bank) being a memory array including a plurality of rows and a plurality of columns, the plurality of memory cells in the memory being divided into a plurality of memory cell groups (Bank groups).

In some embodiments, the memory includes, but is not limited to, SDRAM, SGRAM, HBM and the like, and the SDRAM includes, but is not limited to, double Data Rate SDRAM (DDR SDRAM), graphics Double Rate synchronous dynamic random access memory (Graphics Double Data Rate Synchronous Dynamic Random Access Memory, GDDR SDRAM), and low power consumption Double Rate synchronous dynamic random access memory (Low Power Double Data Rate SDRAM, LPDDR SDRAM).

The number of memory cells (banks) and the division of the memory cell groups (banks) in the memory are determined according to the requirements of the specification document corresponding to the type of the memory, and are particularly related to the standard protocol specification followed by the memory.

For example, the memory may have 4 memory cells (banks), and the 4 memory cells (banks) may be divided into 4 memory cell groups (Bank groups), one memory cell group (Bank group) including one memory cell (Bank).

For example, the memory may have 16 memory cells (banks), and the 16 memory cells (banks) may be divided into 4 memory cell groups (Bank groups), one memory cell group (Bank group) including 4 memory cells (banks).

In some embodiments, the information of an access command includes not only a corresponding access type (read or write), but also an address of a line of a memory to be accessed by the access command (i.e., a corresponding line address) and an address of a memory cell where the line to be accessed is located (i.e., a corresponding memory cell address), and may also include an address of a memory cell group where the line to be accessed is located (i.e., a corresponding memory cell group address). In addition, the address of the column of the memory to be accessed by an access command (i.e., the corresponding column address) is included in the information of the access command.

The memory location address may be represented by a memory location sequence number (Bank ID), the Row address may be represented by a Row sequence number (Row ID), and each memory location in the command queue may be represented by a memory location sequence number (Entry ID).

Illustratively, as shown in Table 1, there are 16 storage locations in the command queue, storage locations 0 and 15 representing the head and tail of the command queue, respectively, in which the read access command (R) is stored from the head of the command queue (storage location 0) to form a read queue and the write access command (W) is stored from the tail of the command queue (storage location 15) to form a write queue.

TABLE 1 Command queue

It can be understood that the read queue and the write queue are connected end to form a command queue, and the command queue is obtained.

In some embodiments, the controller of the memory includes a command collection module configured to receive an access command sent from an upstream device, decode the received access command, and forward the decoded access command to a write control module write command queue for caching.

In some embodiments, the individual write access commands may be arranged in a desired order in the write queue of the command queue, such as the chronological order of the write queues, etc. In the read queue of the command queue, the read access commands may also be arranged according to a required order, such as a time sequence of writing into the queue, and the like.

In some embodiments, in order to shorten the time required for the command to arbitrate, so as to further shorten the time required for command scheduling, the arrangement of each write access command in the write queue of the command queue and the arrangement of each read access command in the read queue of the command queue may be set according to the arbitration rule of the access command, and relevant information may be put together identically, so that when the command is arbitrated, the location of the target access command may be locked quickly, and the delay required for command scheduling may be further shortened. For example, the arbitration rule of the access command is to select the next target access command according to the row address and the memory cell address of the currently active row, then the access commands corresponding to the same memory cell address may be put together in the read queue and the write queue, the access commands corresponding to the same row address may be put together in the access commands corresponding to the same memory cell address, and then the access commands corresponding to different memory cell addresses may or may not be arranged in the ascending or descending order of the memory cell addresses.

In some embodiments, the write control module is specifically configured to:

The target insertion position is determined according to the arrangement rules of the access commands in the read queue and the write queue, so that the arrangement rules of the access commands in the read queue and the write queue are still met after the currently received access commands are written into the target insertion position of the command queue.

In some embodiments, the determination of whether the command queue has a memory space may be implemented by setting a corresponding counter or flag register, for example, in the scheme of the counter, the initial value of the counter is M (M is the number of memory locations in the command queue), each time an access command is written in the command queue, the counter is decremented by 1, each time an access command is read out of the command queue, the counter is incremented by 1, then when determining whether the command queue has a memory space, the count value of the counter may be directly read to determine that the counter has a memory space, the count value is not 0, the memory space is present, and the count value is 0, and the memory space is not present. In the scheme of the flag register, a flag register with M flag bits can be set, the M flag bits respectively correspond to the M storage positions, one flag bit is valid, which indicates that an access command is available at the corresponding storage position and is not empty, and one flag bit is invalid, which indicates that no access command is available at the corresponding storage position and is empty, so when judging whether a storage space exists in a command queue, each flag bit of the flag register can be directly read to determine, if the invalid flag bit exists, the storage space exists, and if the invalid flag bit does not exist, the storage space does not exist.

In some embodiments, the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, are consecutive;

the write control module is specifically configured to determine, when an access command is received and a storage space exists in the command queue, a target insertion position of the currently received access command in the command queue according to an access type and a storage unit address corresponding to the currently received access command, so that after the currently received access command is inserted into the command queue, storage positions of all access commands corresponding to the same access type and the same storage unit address in the command queue are still continuous.

It can be understood that under the condition that the storage positions of the access commands corresponding to the same access type and the same storage unit address in the command queue are continuous, not only can command scheduling be conveniently performed, but also when the access commands are received and the storage space exists in the command queue, the range of the target insertion position can be rapidly determined to a certain extent according to the access type and the storage unit address corresponding to the currently received access command, for example, if the currently received access command is a read access command and the read access command corresponding to the same storage unit address in the command queue and the currently received read access command is arranged at the head of the read queue or in the middle of the read queue, when the target insertion position is determined, the first access commands can be determined by searching, the whole read queue is not required to be traversed, and the time required by the write control module for determining the target insertion position is shortened to a certain extent.

In some embodiments, the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, the same row address are consecutive; correspondingly, the write control module is specifically configured (first command writing scheme):

The target insertion position determined in this way can realize that the storage positions of the access commands corresponding to the same access type and the same storage unit address in the command queue are continuous and the storage positions of the access commands corresponding to the same access type, the same storage unit address and the same row address in the command queue can also be continuous after the access commands are inserted into the command queue (the access commands are written into the target insertion position). And the access commands of different memory cell addresses corresponding to the same access type in the command queue are ordered according to the writing time of the first access command of each memory cell address in a certain time period.

In addition, the storage positions of all access commands corresponding to the same access type, the same storage unit address and the same row address in the command queue are continuous, and the storage mode can facilitate the command scheduling module to quickly find the access commands hit by all current pages from the command queue, so that the time required by command scheduling is further shortened.

In other embodiments, the write control module is specifically configured (second command writing scheme):

The target insertion position determined in this way can also realize that the storage positions of the access commands corresponding to the same access type and the same storage unit address in the command queue are continuous and the storage positions of the access commands corresponding to the same access type, the same storage unit address and the same row address in the command queue are continuous after the access commands are inserted into the command queue (the access commands are written into the target insertion position). However, unlike the first command writing scheme, in this command writing scheme, access commands of different memory cell addresses corresponding to the same access type in the command queue are arranged in order of increasing memory cell addresses. For example, in the command queue corresponding to table 1, in the read queue (R queue), the access commands are arranged in the order of increasing addresses of the storage units, that is, in the order of Bank0, bank1, and Bank2 from the head of the read queue to the tail of the read queue.

In some embodiments, the determination of the two command writing schemes may be indicated by a writing mode identifier, and the validity and invalidity indicate the first command writing scheme and the second command writing scheme, respectively, or the invalidity and the validity indicate the first command writing scheme and the second command writing scheme, respectively. The writing mode identifier is stored in a corresponding flag register, is valid and invalid, and can be set according to actual requirements. The write control module, upon receiving an access command, determines the first command writing scheme or the second command writing scheme based on the identifier given in the flag register.

After the target insertion position is determined, when the currently received access command is written into the target insertion position, if the target insertion position is a storage space, the currently received access command can be directly inserted, and if the currently received access command is not a storage space, the relevant access command needs to be moved forward in a command queue so as to empty the target insertion position, and then the currently received access command is inserted into the target insertion position.

In some embodiments, the write control module is specifically configured to:

For example, if the write control module currently receives an access command with a corresponding access type, a corresponding memory location address, and a corresponding Row address being read access (R), a corresponding memory Bank0, and a corresponding Row address being Row6, based on the command queue shown in table 1, the target insertion position obtained according to the first command writing scheme or the second command writing scheme is the memory location 3, if the memory locations 8 to 9 are all memory slots, the read access command from the memory location 3 to the memory location 7 may be moved backward by one memory location, and after the movement, the memory location 3 becomes the memory slot, and then the read access command is erased as the target insertion position (the memory location 3). If the write control module currently receives an access command with a corresponding access type, a corresponding memory cell address, and a corresponding Row address of write access (W), a corresponding Row address of Bank3, and a corresponding Row address of Row9, based on the command queue shown in table 1, the target insertion position obtained according to the first command writing scheme or the second command writing scheme is the memory position 9, and based on the command queue shown in table 1, the memory position 9 is known to be the memory space, then the write access command may be directly inserted into the target insertion position (memory position 11), and after the two access commands are written into the command queue, the obtained command queue is shown in table 2.

TABLE 2 Command queue

In some embodiments, before the access command is inserted, in order to facilitate confirmation of the access command in the command queue, the target insertion position is not empty, and may also be implemented by the above-mentioned flag register with M flag bits, which is not described herein again.

It should be noted that, in the read queue or the write queue of the command queue, on the basis of ensuring that the storage positions of the access commands of the same storage unit address in the command queue are continuous, the access commands corresponding to different storage unit addresses may be adjacent to each other or may be separated by at least one storage space, as shown in table 3.

TABLE 3 Command queue

Correspondingly, when the write control module currently receives an access command with a corresponding access type, a storage unit address and a Row address being read access (R), bank0 and Row6 respectively, a target insertion position obtained according to the first command writing scheme or the second command writing scheme is the storage position 3, and based on the above-mentioned flag register with M flag bits, it can also be determined that the storage position 3 is not empty, then the target insertion position (the storage position 3) is set to any storage space (such as the storage position 4), all the access commands in the storage space (the storage position 4) are pointed to the direction of the storage space (the storage position 4) along the target insertion position, and one storage position is shifted (i.e. the command in the storage position 3 is shifted to the storage position 4 after the command is shifted to the storage position), and then the currently received access command is written to the target insertion position (the storage position 3) of the command queue.

In some embodiments, after the command scheduling module reads the target access command from the command queue, in some embodiments, the storage locations of the remaining access commands in the command queue may remain unchanged temporarily until a new access command is written, and then shifted as needed.

In yet other embodiments, the command queue is configured to, each time an access command is read, advance each access command in the command queue that is arranged after the currently read access command by one storage location, according to the access type of the currently read access command, of all commands corresponding to the access type. For example, in the command queue corresponding to table 1, after the read access command in the storage location 0 is read, the read access command in the storage location 0 is moved forward by one storage location. In this way, the storage locations of the respective access commands corresponding to the same access type, the same memory location address in the command queue may be kept continuous, or the storage locations of the respective access commands corresponding to the same access type, the same memory location address, the same row address in the command queue may be kept continuous.

In any of the above embodiments, the validity and invalidity of any of the flags may be represented by a 1-bit flag bit, with 1 being valid and 0 being invalid.

It should be noted that, when the command scheduling module performs command arbitration, all the access commands participating in the arbitration in the command queue conform to the current timing requirement, where the timing requirement is required by the standard protocol specification followed by the used memory. Generally, when two consecutive access commands (two consecutive access commands refer to target access commands that are selected from the command queue in succession) access the same memory cell group, the time interval between the two access commands needs to be equal to or greater than a predetermined Tccdl, and when two consecutive access commands (two consecutive access commands refer to target access commands that are selected from the command queue in succession) access different memory cell groups, the time interval between the two access commands needs to be equal to or greater than a predetermined Tccds. While Tccdl is typically larger than Tccds, it is understood that the shortest time interval between two target access commands that the command scheduling module continuously arbitrates from the command queue may be Tccds (if shorter than this time, none of the access commands in the command queue meet the timing requirements). If the command scheduling module performs command arbitration at the current time, and the determined target access command corresponds to a certain memory cell group address, when the command scheduling module performs command arbitration after the command scheduling module, the time when the access command corresponding to the memory cell group address in the command queue can participate in command arbitration is later than the time when the access command corresponding to other memory cell group addresses can participate in command arbitration, and the command scheduling module performs arbitration on the access commands corresponding to other memory cell group addresses in the command queue, thereby selecting the target access command.

In the time interval of two target access commands read out from the command queue continuously by the command scheduling module, the access commands in the command queue do not meet the time sequence requirement, but the command scheduling module can send corresponding precharge commands or activate commands to the memory according to the requirement.

The time sequence of each access command in the command queue can be monitored through a time sequence control module in the controller, the time sequence control module can inform the time sequence state of each access command to the command scheduling module in real time, and the command scheduling module arbitrates among the access commands meeting the time sequence requirements according to the time sequence state of each access command sent by the time sequence control module. After the command scheduling module performs arbitration each time and selects the target access command, the command scheduling module also feeds back the information (the memory cell address and the memory cell group address) of the selected target access command to the time sequence control module, and timely updates the time sequence state of each access command.

In some embodiments, the controller of the memory further comprises a data processing module and a data transmitting module, wherein the data processing module is configured to receive the data read out from the memory by the read access command, and transmit the data to the data transmitting module after performing cross-clock processing and the like.

The data transmission module is configured to forward the received data to an upstream device.

In some embodiments, the controller of the memory is coupled to the memory protocol through a DFI (DDR PHY Interface) interface module.

As shown in fig. 2, the embodiment of the disclosure further provides a memory access system, including an upstream device, a memory, and a controller of any of the above embodiments.

The upstream device is connected to the memory through the controller to access the memory through the controller.

In some embodiments, the memory includes SDRAM, SGRAM, HBM or the like.

In some embodiments, the above system further comprises: a port Physical layer chip (PHY), connected between the memory and the controller, configured to convert a digital signal of an access command transmitted from the controller into an interface Physical signal of the memory.

In some embodiments, the controller is connected to the port physical layer by a DFI (DDR PHY Interface) protocol.

In some usage scenarios, the product form of the memory access system is a GPU SOC system.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic component including the access system of the memory in any of the above embodiments. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.

Based on the same inventive concept, the embodiments of the present disclosure also provide an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.

Based on the same inventive concept, the embodiments of the present disclosure further provide a command buffering method of a memory, as shown in fig. 3, including:

step S110: writing the currently received write access command into a write queue of a command queue when receiving the write access command, and writing the currently received read access command into a read queue of the command queue when receiving the read access command;

The specific implementation process of the command buffering method of the memory can refer to any embodiment of the controller of the memory, and will not be described herein.

Claims

1. A controller of a memory comprises a command queue, a write control module and a command scheduling module;

the command queue is configured to cache each access command; the command queue comprises a write queue and a read queue, wherein the head of the write queue and the head of the read queue are respectively at the head of the command queue and the tail of the command queue, or are respectively at the tail of the command queue and the head of the command queue;

the write control module is configured to determine a target insertion position of a currently received access command in the command queue according to an access type corresponding to the currently received access command when the access command is received and a storage space exists in the command queue, and determine whether the target insertion position is empty, if yes, directly writing the currently received access command into the target insertion position of the command queue, otherwise, pointing the access command in the target insertion position and all access commands between the access command and any storage space along the direction of the storage space along the target insertion position, shifting one storage position, and writing the currently received access command into the target insertion position of the command queue; when the access type corresponding to the currently received access command is read access, the target insertion position is positioned in the read queue, and when the access type corresponding to the currently received access command is write access, the target insertion position is positioned in the write queue;

The command scheduling module is configured to arbitrate each access command in the command queue, and select a target access command from the command scheduling module to access the memory; the arrangement of each write access command in the write queue and the arrangement of each read access command in the read queue of the command queue are set according to the arbitration rule of the access commands.

2. The controller of a memory according to claim 1, the memory comprising a plurality of memory cells, each memory cell comprising a plurality of rows;

the write control module is specifically configured to:

3. The controller of memory of claim 2, wherein the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, the same row address are consecutive;

the write control module is specifically configured to:

when an access command is received and a storage space exists in the command queue, judging whether the current access command corresponding to the same access type, the same storage unit address and the same row address exists in the command queue according to the access type, the storage unit address and the row address corresponding to the current access command;

If the access command with the same access type and the same storage unit address corresponding to the current received access command exists, determining the subsequent storage position of all the access commands with the same access type and the same storage unit address corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue, otherwise, determining the subsequent storage position of all the access commands with the same access type corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue.

4. The controller of memory of claim 2, wherein the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, the same row address are consecutive;

the write control module is specifically configured to:

if the access command with the same access type and the same storage unit address corresponding to the current received access command exists, determining the latter storage position of all the access commands with the same access type and the same storage unit address corresponding to the current received access command in the command queue as the target insertion position of the current received access command in the command queue, otherwise, determining the target insertion position of the current received access command in the command queue according to the access type and the storage unit address corresponding to the current received access command, so that after the current received access command is inserted into the command queue, the access commands with the same access type corresponding to the command in the command queue are arranged according to the increasing sequence of the corresponding storage unit addresses.

5. The memory controller of claim 1, the command queue further configured to, each time an access command is read, advance each access command in the command queue that is arranged after the currently read access command by one storage location from all commands in the command queue that correspond to the access type according to the access type that corresponds to the currently read access command.

6. A memory access system comprising a controller of a memory as claimed in any one of claims 1 to 5.

7. An electronic component comprising an access system for a memory as claimed in claim 6.

8. An electronic device comprising an electronic assembly as claimed in claim 7.

9. A method of command caching for a memory, the method comprising:

when an access command is received and a storage space exists in a command queue, determining a target insertion position of the currently received access command in the command queue according to an access type corresponding to the currently received access command, judging whether the target insertion position is empty, if yes, directly writing the currently received access command into the target insertion position of the command queue, otherwise, pointing the access command at the target insertion position and all access commands between the access command and any storage space along the direction of the storage space, shifting one storage position along the target insertion position, and writing the currently received access command into the target insertion position of the command queue; when the access type corresponding to the currently received access command is read access, the target insertion position is positioned in a read queue of the command queue, and when the access type corresponding to the currently received access command is write access, the target insertion position is positioned in a write queue of the command queue;

Wherein, the head of the write queue and the read queue are respectively at the head of the command queue and the tail of the command queue, or are respectively at the tail of the command queue and the head of the command queue; the arrangement of each write access command in the write queue and the arrangement of each read access command in the read queue of the command queue are set according to the arbitration rule of the access commands.

10. The method of claim 9, the memory comprising a plurality of memory cells, each memory cell comprising a plurality of rows;

when an access command is received and a storage space exists in the command queue, determining a target insertion position of the currently received access command in the command queue according to an access type corresponding to the currently received access command, wherein the target insertion position comprises the following steps:

11. The method of claim 10, wherein the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, and the same row address are consecutive;

when an access command is received and a storage space exists in the command queue, determining a target insertion position of the currently received access command in the command queue according to the access type and the storage unit address corresponding to the currently received access command, wherein the target insertion position comprises the following steps:

12. The method of claim 10, wherein the memory locations in the command queue for each access command corresponding to the same access type, the same memory location address, and the same row address are consecutive;