CN116301627A - NVMe controller and initialization and data read-write method thereof - Google Patents

Abstract

The invention discloses an NVMe controller, a user API interface provides a user-defined interface for operating the NVMe controller, and a user-defined instruction packaged in the user-defined interface is stored in a user command queue after being called; the queue processing logic checks and maintains the command state of each slot of the user command queue in real time, and transfers to NVMe command processing logic or custom command processing logic for standardized processing according to the command type; the NVMe command processing logic controls DMA transmission logic, write data buffer control, read data buffer control, write data PRP buffer, read data PRP buffer, NVMe command sending queue, NVMe command completion queue, PCIe sending engine, PCIe receiving engine to complete initialization, data reading and data writing according to specific requirements of NVMe standard commands. The invention reduces the interaction frequency of the user program and the NVMe controller and exerts the NVMe protocol performance to the greatest extent.

Description

NVMe controller and initialization and data read-write method thereof

Technical Field

The invention relates to the technical field of data storage, in particular to an NVMe controller based on logic implementation and an initialization and data reading and writing method thereof.

Background

The special solid-state storage medium of the NVMe protocol can fully exert the advantages of high performance, low power consumption, high concurrency and the like of the solid-state storage medium, the SSD of the solid-state electronic disk based on the NVMe protocol is widely applied to a high-speed data acquisition and storage system, and a single NVMe electronic disk breaks through the continuous sequential read-write bandwidth which is not lower than 2 GB/s.

Generally, the NVMe protocol is carried on a PCIe interface, the conventional processor supports a PCIe controller, the PCIe interface downloads a solid-state electronic disk supporting the NVMe protocol, and an NVMe protocol function is implemented on the processor through a software mode. The method has extremely high flexibility and universality, can realize high-performance data access without additional hardware modification, consumes certain processor resources, and is suitable for scenes with low performance requirements and insensitive data transmission delay.

In order to release the processor resource, the processing efficiency of the NVMe protocol is further improved, and the NVMe protocol is generally realized through logic. The FPGA logic completes the instruction processing flow according to the NVMe standard protocol specification, the logic processing NVMe protocol is extremely efficient, and the processor is not required to participate in processing deeply.

Disclosure of Invention

The invention aims to provide an NVMe controller which is logically realized, and meanwhile, a set of custom instructions are packaged, so that a user can directly perform data read-write operation on an NVMe solid-state electronic disk through the custom instructions; providing an initialization method of the NVMe controller, and simplifying the interaction process of a user program and the NVMe controller in the initialization process of NVMe equipment; the invention can remarkably improve the NVMe protocol processing efficiency, reduce the interaction frequency of a user program and the NVMe controller, reduce the resource consumption and time consumption in the protocol processing process, and exert the NVMe protocol performance to the greatest extent.

The invention aims at realizing the following technical scheme:

an NVMe controller includes a user API interface, a data buffer space, a user command queue, a queue processing logic, a custom command processing logic, a DMA transfer logic, a write data buffer control logic, a read data buffer control logic, an NVMe command processing logic, a write data PRP buffer, a read data PRP buffer, an NVMe command send queue, an NVMe command complete queue, a PCIe send engine, a PCIe receive engine, and a command execution status queue;

the user API interface provides a user-defined interface for operating the NVMe controller, and user-defined instructions constructed according to a specific format are packaged in the user-defined interface, wherein the user-defined interface comprises a startup interface, a shutdown interface, a read data interface and a write data interface;

the user command queue comprises a plurality of slots for storing the user-defined commands packaged in the called user API interface;

the queue processing logic checks and maintains the command state of each slot of the user command queue in real time, once a new user-defined command is identified to be written into the slot of the user command queue, the user-defined command in the slot is taken out, and if the user-defined command is a data writing command and a data reading command, the user-defined command is transferred to the NVMe command processing logic for further processing; if the power-on command and the power-off command are the same, the user-defined command processing logic is used for processing;

the customized command processing logic is used for analyzing the customized command, analyzing the customized command into one or more NVMe standard commands defined by standard specifications, and transferring the analyzed NVMe standard commands to the NVMe command processing logic;

after the NVMe command processing logic receives the user-defined command sent by the queue processing logic, the command content is analyzed, an NVMe standard command is constructed, and the DMA transmission logic, the write data buffer control, the read data buffer control, the write data PRP buffer, the read data PRP buffer, the NVMe command sending queue, the NVMe command completion queue, the PCIe sending engine, the PCIe receiving engine, the initialization, the data reading and the data writing are controlled according to the specific requirements of the NVMe standard command.

Preferably, the data buffer space is a buffer space during data transmission, including but not limited to DDR, SRAM; the data buffer space is connected with DMA transmission logic in the controller through an AXI or PCIe bus, and the DMA transmission logic completes the data movement.

Preferably, the write data buffer control and the read data buffer control are logic control modules consisting of FIFOs and BRAMs, and are used for data buffer synchronization between different buses.

Preferably, the write data PRP cache and the read data PRP cache are respectively used for storing data cache addresses during write and read data transmission according to the parallel redundancy protocol PRP.

Preferably, the NVMe command transmission queue and the NVMe command completion queue are used for storing transmission commands and completion commands defined by the NVMe specification.

Preferably, the PCIe sending engine and the PCIe receiving engine are PCIe transceiver control logic, and writing data to and reading data from the NVMe electronic disk are completed.

Preferably, the command execution state queue is a group of caches constructed by using RAM resources in the FPGA, and each slot of the command execution state queue stores state information of completion of command execution of the corresponding slot of the user command queue.

The initialization method of the NVMe controller comprises the following steps:

step A1: after power-on, the upper layer application checks a link state register of the NVMe controller to determine whether the current NVMe controller is connected with the NVMe electronic disk; if the link is established, the step A2 is entered, otherwise, the link state register is continuously checked in a polling way until the initialization is finished after the timeout, and the step A5 is entered;

step A2: calling a starting interface in the user API interface, writing a starting instruction packaged in the starting interface into a user command queue, and initializing an NVMe controller;

step A3: the queue processing logic detects a user command queue in real time, extracts a starting command and then transfers the starting command to the custom command processing logic; the user-defined command processing logic analyzes the starting command, splits the starting command into a plurality of NVMe standard commands, transfers the NVMe standard commands to the NVMe command processing logic for processing, fills the NVMe command sending queue and sends the NVMe standard commands to the NVMe electronic disk;

step A4: the upper layer monitors an initialization state register of the NVMe controller, judges an initialization result, and acquires attribute information of the mounted NVMe electronic disc according to the register information of the NVMe controller and the Identify information in the data receiving RAM if the initialization result is successful; if the time is out, the initialization fails, and the step A5 is entered;

step A5: the NVMe controller initialization is ended.

The data reading method of the NVMe controller comprises the following steps:

step B1: the upper layer application calls a read data interface in the user API interface to carry out data reading operation, and the read data interface constructs a read data command according to the initial sector number, the current transmission sector number and the data cache address transmitted by the application and writes the read data command into an idle slot of a user command queue; wherein the data cache address points to a data cache region in the data cache space;

step B2: the queue processing logic checks and maintains the state of each slot of the user command queue in real time, and once the read data command is identified to be written into the slot of the user command queue, the read data command is taken out and forwarded to the NVMe command processing logic, and the state of the slot is set to be activated;

step B3: the NVMe command processing logic analyzes parameters in the read operation command, and constructs a standard NVMe I/O read command according to a data cache address transmitted by the read data command; the PRP in the NVMe I/O read instruction uses the read data PRP buffer to store the data read address, writes the NVMe I/O read instruction into an NVMe command sending queue, and writes a door bell register of the NVMe electronic disk;

step B4: after receiving the door bell updating operation, the NVMe electronic disk acquires an NVMe I/O reading instruction in an NVMe command sending queue and sends a memory reading request to NVMe command processing logic;

step B5: after receiving a memory read request, NVMe command processing logic sends read return to a PCIe receiving engine within 10 clock cycles, and received data is written into a data buffer space by DMA transmission logic after read data buffer control;

step B6: the PCIe receiving engine receives the command completion status information sent by the NVMe electronic disk and writes the command completion status information into an NVMe command completion queue;

step B7: the NVMe command processing logic monitors command completion states in all slots of an NVMe command completion queue in real time, acquires and analyzes the command completion states when detecting that a new command completion return state exists, and sends the command completion states to the queue processing logic;

step B8: the queue processing logic updates the command state of the corresponding slot position of the command to be complete or abnormal according to the command completion state, and updates the corresponding command state information in the command execution state queue;

step B9: the upper layer application judges the execution result of the operation according to the completion state of the read command, if the completion state is normal, the read command is executed, and if the completion state is abnormal, the reason can be analyzed according to the corresponding state of the slot command in the command execution state queue.

The data writing method of the NVMe controller comprises the following steps:

step C1: the upper layer application calls a data writing interface in the user API interface to carry out data writing operation, and the data writing interface constructs a data writing command according to the initial sector number, the current transmission sector number and the data caching address transmitted by the application and writes the data writing command into the idle slot of the user command queue. Wherein the data cache address points to a data cache region in the data cache space;

step C2: the queue processing logic checks and maintains the state of each slot of the user command queue in real time, and once the writing data command is identified to be written into the slot of the user command queue, the writing data command is taken out and forwarded to the NVMe command processing logic, and the state of the slot is set to be activated;

step C3: the NVMe command processing logic analyzes parameters in the write operation command, and constructs a standard NVMe I/O write command according to a data cache address transmitted by the write data command; PRP in the NVMe I/O write instruction uses write data PRP buffer to store data write address, writes the NVMe I/O write data instruction into NVMe command sending queue, and writes the data write address of NVMe electronic disk;

step C4: after receiving the door bell updating operation, the NVMe electronic disk acquires an NVMe I/O writing instruction in an NVMe command sending queue and sends a memory reading request to NVMe command processing logic;

step C5: after receiving the memory read request, the NVMe command processing logic sends a read return to the PCIe sending engine within 10 clock cycles, starts the DMA transmission logic, takes out data from the data cache space, and sends out the data from the PCIe sending engine after write data buffer control;

step C6: the PCIe receiving engine receives the command completion status information sent by the SSD and writes the command completion status information into an NVMe command completion queue;

step C7: the NVMe command processing logic monitors command completion states in all slots of an NVMe command completion queue in real time, acquires and analyzes the command completion states when detecting that a new command completion return state exists, and sends the command completion states to the queue processing logic;

step C8: the queue processing logic updates the command state of the corresponding slot position of the command to be complete or abnormal according to the command completion state, and updates the corresponding command state information in the command execution state queue;

step C9: and judging the execution result of the operation according to the completion state of the write command, if the completion state is normal, completing the execution of the write command, and if the completion state is abnormal, analyzing the reason according to the corresponding state of the slot command in the command execution state queue.

The invention has the beneficial effects that:

the FPGA is adopted to realize the logic of the NVMe Host end controller, the analysis, the grouping and the processing of the NVMe protocol command are all realized by the logic, the resource consumption of a processor is reduced, and the NVMe protocol processing efficiency is greatly improved; the NVMe command receiving and transmitting queue and the PRP linked list space are constructed by using logic internal resources, so that ultra-low and deterministic delay access is realized; the instruction completion state detection is carried out by a mode that logic polls all slot positions in a completion queue in real time, a traditional NVMe protocol is not used for waiting for a completion queue interrupt signal, then a tail pointer of the completion queue is detected, and elements in the completion queue are sequentially read, so that context switching caused by interrupt is avoided, and the instruction completion processing efficiency is effectively improved; the encapsulated custom instruction greatly simplifies the process of operating the NVMe electronic disc by a user, and the user only needs to pay attention to the data read-write result, so that the maintenance cost of the NVMe protocol is reduced. The invention is applied to the data access equipment pursuing high performance and low delay, reduces the development difficulty of the NVMe function, simplifies the development flow, and greatly improves the NVMe protocol processing efficiency.

Drawings

Fig. 1 is a block diagram of an NVMe controller according to the present invention.

Fig. 2 is an NVMe controller initialization flow chart of the present invention.

Fig. 3 is a flow chart of NVMe data reading and writing in the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples.

Referring to fig. 1, an NVMe controller in this embodiment includes a user API interface 201, a data buffer space 202, a user command queue 101, a queue processing logic 102, a custom command processing logic 103, a DMA transfer logic 104, a write data buffer control logic 105, a read data buffer control logic 106, an NVMe command processing logic 107, a write data PRP buffer 108, a read data PRP buffer 109, an NVMe command transmit queue 110, an NVMe command complete queue 111, a PCIe transmit engine 112, a PCIe receive engine 113, a command execution status queue 114, a data transceiving RAM115, and a data receive RAM116.

The user API interface 201 provides a custom interface for operating the NVMe controller, and custom instructions constructed according to a specific format are encapsulated in the custom interface, including a power-on interface, a power-off interface, a read data interface, a write data interface, a read information interface and a write information interface. Packaging a starting command in a starting interface to finish initialization of a controller and mounting an NVMe electronic disk; packaging a shutdown command in a shutdown interface to finish unloading of the electronic disk and resetting of logic resources; encapsulating a read data command in the read data interface to finish the reading of the NVMe electronic disc data; encapsulating a data writing command in the data writing interface to finish writing the data of the NVMe electronic disc; packaging a read log command, a read ID command, a read characteristic command and a data set management command in the read information interface to finish the reading of the NVMe log and the characteristic information; and packaging a set characteristic command in the write information interface to finish the setting of the NVMe characteristic information.

The data buffer space 202 is a buffer space at the time of data transmission, including but not limited to DDR, SRAM; the data buffer space is connected to the DMA transfer logic 104 in the controller via an AXI or PCIe bus, and the DMA transfer logic 104 completes the data movement.

The modules 101-113 are all logic implementations and are the core processing part of the controller.

The user command queue 101 is a set of buffer spaces inside the FPGA that store custom commands encapsulated in the called user API interface. The depth of the user command queue 101 can be configured according to logic resources as required, the default depth is 64, and the user command queues are connected end to form a ring structure; each slot of the user command queue can store a 64-byte custom instruction, the corresponding slot is automatically filled when the upper layer application calls the user API interface, and each slot represents the execution state of the slot custom command by the corresponding state identifier, and the states comprise idle, active, complete and abnormal.

The queue processing logic 102 checks and maintains the status of each slot command in the user command queue in real time, and once a new custom command is identified to be written into a slot of the user command queue 101, the slot command is fetched, and the custom command processing logic 102 or NVMe command processing logic 107 is forwarded according to the custom command type while the status of the slot is set to active. Queue processing logic 102 may fetch the commands to be executed in multiple user command queues at a time.

Typically, the acquired write data command, read data command, write information command, read information command are transferred to the NVMe command processing logic 107 for further processing; for the power-on command and the power-off command, the processing logic 103 processes the power-on command and the power-off command.

The custom command processing logic 103 is configured to parse the custom command, and parse the custom command into one or more NVMe standard commands defined by standard specifications, for example, a startup command completes an initialization process of an NVMe protocol, where NVMe standard commands such as Identify, get/Set Feature are implemented step by step; the parsed NVMe standard command will go to NVMe command processing logic 107.

After receiving the custom command sent by the queue processing logic 102, the NVMe command processing logic 107 parses the command content, constructs an NVMe standard command, and controls the DMA transfer logic 104, the write data buffer control 105, the read data buffer control 106, the write data PRP buffer 108, the read data PRP buffer 109, the NVMe command sending queue 110, the NVMe command completion queue 111, the PCIe sending engine 112, the PCIe receiving engine 113 to complete operations such as initialization, data reading, data writing, and the like according to specific requirements of the NVMe standard command.

The DMA transfer logic 104 is used for NVMe data transfer, is a controller data transfer engine, and is coupled to the data cache space 202 via an AXI or PCIe bus. When a user performs data writing operation, the DMA transmission logic sends the data of the corresponding address segment in the data cache space 202 to the NVMe electronic disk through the PCIe sending engine 112 after the data of the corresponding address segment is subjected to the data writing buffer control 105; when a user performs data reading operation, after the data received by the PCIe receiving engine 113 passes through the read data buffer control 106, the data is moved to a corresponding read address segment space in the data cache space 202 through DMA transmission logic; the DMA transfer logic 104 is controlled to be started by the NVMe command processing logic 107.

The write data buffer control 105 and the read data buffer control 106 are logic control modules composed of FIFOs and BRAMs, and are used for data buffer synchronization between different buses, so that low delay and deterministic access delay during data transmission between different buses are realized.

The write data PRP buffer 108 and the read data PRP buffer 109 are used to store data buffer addresses at the time of write and read data transmission according to the parallel redundancy protocol (Parallel Redundancy Protocol, PRP), respectively.

The NVMe command send queue 110 and the NVMe command completion queue 111 are a pair of NVMe command send-receive queues for storing send commands or completion commands defined by the NVMe specification.

The PCIe send engine 112 and PCIe receive engine 113 are PCIe transceiver control logic that completes writing data to and reading data from the NVMe electronic disk.

The NVMe command processing logic 107 is configured to process the NVMe command send queue 110 and the NVMe command completion queue 111, organize command frames or parse command execution states according to command types. When data is written or read, the NVMe command processing logic 107 organizes the writing of NVMe command frames into the NVMe command transmit queue 110, updates the write data PRP address to the write data cache 108 or the read data PRP address to the read data PRP cache 109 according to the command transferred by the queue processing logic 102, and starts the DMA transfer logic 104 and the PCIe transmit engine 112 to transmit data or the PCIe receive engine 113 to receive data.

The NVMe command processing logic 107 performs real-time polling checking on the state of the NVMe command completion queue 111, the PCIe receive engine 113 sends the command execution result to the NVMe command completion queue 111, and when the NVMe command processing logic 107 monitors that there is a command execution completion, the command completion state is automatically resolved, and the result is updated to the command execution state queue 114 through the queue processing logic 102.

The command execution state queue 114 is a set of caches built using FPGA internal RAM resources, with a default depth of 64; each slot of the command execution state queue stores state information of completion of command execution of the corresponding slot of the user command queue, and each piece of completion information is 16 bytes.

The data receiving and transmitting RAM115 and the data receiving RAM116 are buffer areas composed of BRAM, and have a size of 1-4 KB, and are used for storing data when management instructions attached with data transmission are executed.

As shown in fig. 2, the initialization method of the NVMe controller provided in this embodiment includes the following steps:

step A1: after power-on, the upper layer application checks a link state register of the NVMe controller to determine whether the current NVMe controller is connected with the NVMe electronic disk; if the link is established, the step A2 is entered, otherwise, the link status register is continuously checked in a polling manner until the initialization is finished after the timeout, and the step A5 is entered.

Step A2: and calling a starting-up interface in the user API interface 201, writing a starting-up instruction packaged in the starting-up interface into the user command queue 101, and initializing the NVMe controller.

Step A3: the queue processing logic 102 detects the user command queue 101 in real time, and after the startup command is extracted, the startup command is transferred to the custom command processing logic 103; the custom command processing logic 103 parses the startup command, splits it into several NVMe standard commands, transfers to the NVMe command processing logic 107, processes it, and fills the NVMe command sending queue 110 and sends it to the NVMe electronic disk.

Step A4: the upper layer monitors an initialization state register of the NVMe controller, judges an initialization result, and acquires attribute information of the mounted NVMe electronic disc according to the register information of the NVMe controller and the Identify information in the data receiving RAM if the initialization result is successful; if the time is out, the initialization fails, and the step A5 is entered.

Step A5: the NVMe controller initialization is ended.

As shown in fig. 3, the data reading method of the NVMe controller provided in this embodiment includes the following steps:

step B1: the upper layer application calls a read data interface in the user API interface 201 to perform data reading operation, and the read data interface constructs a read data command according to parameters transferred by the application, such as a start sector number, the current transmission sector data and a data cache address, and writes the read data command into an idle slot of the user command queue 101. Wherein the data cache address points to a data cache region in the data cache space 202.

Step B2: the queue processing logic 102 checks and maintains the status of each slot of the user command queue 101 in real time, and once it is identified that a read data command is written into a slot of the user command queue 101, fetches the read data command to the NVMe command processing logic 107 while the status of the slot is set to active.

Step B3: the NVMe command processing logic 107 analyzes parameters in the read operation command, and constructs a standard NVMe I/O read command according to the data cache address transmitted by the read data command; the PRP in the NVMe I/O read instruction uses the read data PRP cache 109 to store the data read address, writes the NVMe I/O read instruction into the NVMe command send queue 110, and writes the door bell register of the solid-state electronic disk SSD, triggering the PCIe bus Memory read request.

Step B4: after receiving the door roll update operation, the SSD obtains the NVMe I/O read instruction in the NVMe command sending queue 110, and sends a memory read request to the NVMe command processing logic 107.

Step B5: after receiving the memory read request, the NVMe command processing logic 107 sends a read return to the PCIe receive engine 113 within 10 clock cycles, and the received data is written into the data buffer space 202 by the DMA transfer logic 104 after passing through the read data buffer control 106.

Step B6: the PCIe receive engine receives the command completion status information sent by the SSD and writes it to the NVMe command completion queue 111.

Step B7: the NVMe command processing logic 107 monitors the command completion status in each slot of the NVMe command completion queue 111 in real time, and when detecting that there is a new command completion return status, obtains the command completion status and parses the command completion status, and sends the command completion status to the queue processing logic 102.

Step B8: the queue processing logic 102 updates the corresponding slot command status for this command to complete or abnormal based on the command completion status, and updates the corresponding command status information in the command execution status queue 114.

Step B9: the upper layer application judges the execution result of the operation according to the completion state of the read command, if the completion state is normal, the read command is executed, and if the completion state is abnormal, the reason can be analyzed according to the corresponding state of the slot command in the command execution state queue 114.

The data writing method of the NVMe controller provided in this embodiment is similar to the data reading method, and includes the following steps:

step C1: the upper layer application calls a write data interface in the user API interface 201 to perform data writing operation, and the write data interface constructs a write data command according to parameters transferred by the application, such as a start sector number, the current transmission sector data and a data cache address, and writes the write data command into an idle slot of the user command queue 101. Wherein the data cache address points to a data cache region in the data cache space 202.

Step C2: the queue processing logic 102 checks and maintains the status of each slot of the user command queue 101 in real time, and once a write data command is identified as being written into a slot of the user command queue 101, fetches the write data command from the NVMe command processing logic 107 while the status of the slot is set to active.

Step C3: the NVMe command processing logic 107 analyzes parameters in the write operation command, and constructs a standard NVMe I/O write command according to the data cache address transmitted by the write data command; the PRP in the NVMe I/O write instruction uses the write data PRP cache 108 to store the data write address, writes the NVMe I/O write data instruction into the NVMe command send queue 110, writes into the SSD side bell register, and triggers the PCIe bus Memory write request.

Step C4: after receiving the door roll update operation, the SSD obtains the NVMe I/O write command in the NVMe command sending queue 110, and sends a memory read request to the NVMe command processing logic 107.

Step C5: after receiving the memory read request, the NVMe command processing logic 107 sends a read return to the PCIe send engine 112 within 10 clock cycles, starts DMA transfer logic, fetches data from the data cache space 202, and sends the data out by the PCIe send engine 112 after passing through the write data buffer control 105.

Step C6: the PCIe receive engine receives the command completion status information sent by the SSD and writes it to the NVMe command completion queue 111.

Step C7: the NVMe command processing logic 107 monitors the command completion status in each slot of the NVMe command completion queue 111 in real time, and when detecting that there is a new command completion return status, obtains the command completion status and parses the command completion status, and sends the command completion status to the queue processing logic 102.

Step C8: the queue processing logic 102 updates the corresponding slot command status for this command to complete or abnormal based on the command completion status, and updates the corresponding command status information in the command execution status queue 114.

Step C9: the user determines the execution result of the operation according to the completion state of the write command, if the completion state is normal, the write command is executed, and if the completion state is abnormal, the user can analyze the reason according to the corresponding state of the slot command in the command execution state queue 114.

It will be understood that equivalents and modifications will occur to those skilled in the art in light of the present invention and their spirit, and all such modifications and substitutions are intended to be included within the scope of the present invention as defined in the following claims.

Claims (10)

1. An NVMe controller, comprising a user API interface, a data buffer space, a user command queue, a queue processing logic, a custom command processing logic, a DMA transfer logic, a write data buffer control logic, a read data buffer control logic, an NVMe command processing logic, a write data PRP buffer, a read data PRP buffer, an NVMe command send queue, an NVMe command complete queue, a PCIe send engine, a PCIe receive engine, and a command execution status queue, characterized in that:

the user API interface provides a user-defined interface for operating the NVMe controller, and user-defined instructions constructed according to a specific format are packaged in the user-defined interface, wherein the user-defined interface comprises a startup interface, a shutdown interface, a read data interface and a write data interface;

the user command queue comprises a plurality of slots for storing the user-defined commands packaged in the called user API interface;

the queue processing logic checks and maintains the command state of each slot of the user command queue in real time, once a new user-defined command is identified to be written into the slot of the user command queue, the user-defined command in the slot is taken out, and if the user-defined command is a data writing command and a data reading command, the user-defined command is transferred to the NVMe command processing logic for further processing; if the power-on command and the power-off command are the same, the user-defined command processing logic is used for processing;

the customized command processing logic is used for analyzing the customized command, analyzing the customized command into one or more NVMe standard commands defined by standard specifications, and transferring the analyzed NVMe standard commands to the NVMe command processing logic;

after the NVMe command processing logic receives the user-defined command sent by the queue processing logic, the command content is analyzed, an NVMe standard command is constructed, and the DMA transmission logic, the write data buffer control, the read data buffer control, the write data PRP buffer, the read data PRP buffer, the NVMe command sending queue, the NVMe command completion queue, the PCIe sending engine, the PCIe receiving engine, the initialization, the data reading and the data writing are controlled according to the specific requirements of the NVMe standard command.

2. An NVMe controller according to claim 1, characterized in that the data buffer space is the buffer space at the time of data transmission, including but not limited to DDR, SRAM; the data buffer space is connected with DMA transmission logic in the controller through an AXI or PCIe bus, and the DMA transmission logic completes the data movement.

3. The NVMe controller of claim 1, wherein the write data buffer control and the read data buffer control are logic control modules comprising FIFOs and BRAMs for data buffer synchronization between different buses.

4. The NVMe controller of claim 1, wherein the write data PRP cache and the read data PRP cache are configured to store data cache addresses for write and read data transmissions, respectively, in accordance with the parallel redundancy protocol PRP.

5. The NVMe controller of claim 1, wherein the NVMe command send queue and the NVMe command completion queue are configured to store send commands and completion commands defined by an NVMe specification.

6. The NVMe controller of claim 1, wherein the PCIe send engine and the PCIe receive engine are PCIe transceiver control logic configured to complete writing data to and reading data from the NVMe electronic disk.

7. The NVMe controller of claim 1, wherein the command execution status queue is a set of caches constructed using RAM resources within the FPGA, and each slot of the command execution status queue stores status information of completion of execution of a corresponding slot command of the user command queue.

8. The initialization method of an NVMe controller according to any one of claims 1 to 7, characterized by the steps of:

step A1: after power-on, the upper layer application checks a link state register of the NVMe controller to determine whether the current NVMe controller is connected with the NVMe electronic disk; if the link is established, the step A2 is entered, otherwise, the link state register is continuously checked in a polling way until the initialization is finished after the timeout, and the step A5 is entered;

step A2: calling a starting interface in the user API interface, writing a starting instruction packaged in the starting interface into a user command queue, and initializing an NVMe controller;

step A3: the queue processing logic detects a user command queue in real time, extracts a starting command and then transfers the starting command to the custom command processing logic; the user-defined command processing logic analyzes the starting command, splits the starting command into a plurality of NVMe standard commands, transfers the NVMe standard commands to the NVMe command processing logic for processing, fills the NVMe command sending queue and sends the NVMe standard commands to the NVMe electronic disk;

step A4: the upper layer monitors an initialization state register of the NVMe controller, judges an initialization result, and acquires attribute information of the mounted NVMe electronic disc according to the register information of the NVMe controller and the Identify information in the data receiving RAM if the initialization result is successful; if the time is out, the initialization fails, and the step A5 is entered;

step A5: the NVMe controller initialization is ended.

9. A method of reading data from an NVMe controller according to any one of claims 1 to 7 characterised by the steps of:

step B1: the upper layer application calls a read data interface in the user API interface to carry out data reading operation, and the read data interface constructs a read data command according to the initial sector number, the current transmission sector number and the data cache address transmitted by the application and writes the read data command into an idle slot of a user command queue; wherein the data cache address points to a data cache region in the data cache space;

step B2: the queue processing logic checks and maintains the state of each slot of the user command queue in real time, and once the read data command is identified to be written into the slot of the user command queue, the read data command is taken out and forwarded to the NVMe command processing logic, and the state of the slot is set to be activated;

step B3: the NVMe command processing logic analyzes parameters in the read operation command, and constructs a standard NVMe I/O read command according to a data cache address transmitted by the read data command; the PRP in the NVMe I/O read instruction uses the read data PRP buffer to store the data read address, writes the NVMe I/O read instruction into an NVMe command sending queue, and writes a door bell register of the NVMe electronic disk;

step B4: after receiving the door bell updating operation, the NVMe electronic disk acquires an NVMe I/O reading instruction in an NVMe command sending queue and sends a memory reading request to NVMe command processing logic;

step B5: after receiving a memory read request, NVMe command processing logic sends read return to a PCIe receiving engine within 10 clock cycles, and received data is written into a data buffer space by DMA transmission logic after read data buffer control;

step B6: the PCIe receiving engine receives the command completion status information sent by the NVMe electronic disk and writes the command completion status information into an NVMe command completion queue;

step B7: the NVMe command processing logic monitors command completion states in all slots of an NVMe command completion queue in real time, acquires and analyzes the command completion states when detecting that a new command completion return state exists, and sends the command completion states to the queue processing logic;

step B8: the queue processing logic updates the command state of the corresponding slot position of the command to be complete or abnormal according to the command completion state, and updates the corresponding command state information in the command execution state queue;

step B9: the upper layer application judges the execution result of the operation according to the completion state of the read command, if the completion state is normal, the read command is executed, and if the completion state is abnormal, the reason can be analyzed according to the corresponding state of the slot command in the command execution state queue.

10. The method for writing data to an NVMe controller according to any one of claims 1 to 7, characterized by the steps of:

step C1: the upper layer application calls a data writing interface in the user API interface to carry out data writing operation, and the data writing interface constructs a data writing command according to the initial sector number, the current transmission sector number and the data caching address transmitted by the application and writes the data writing command into the idle slot of the user command queue. Wherein the data cache address points to a data cache region in the data cache space;

step C2: the queue processing logic checks and maintains the state of each slot of the user command queue in real time, and once the writing data command is identified to be written into the slot of the user command queue, the writing data command is taken out and forwarded to the NVMe command processing logic, and the state of the slot is set to be activated;

step C3: the NVMe command processing logic analyzes parameters in the write operation command, and constructs a standard NVMe I/O write command according to a data cache address transmitted by the write data command; PRP in the NVMe I/O write instruction uses write data PRP buffer to store data write address, writes the NVMe I/O write data instruction into NVMe command sending queue, and writes the data write address of NVMe electronic disk;

step C4: after receiving the door bell updating operation, the NVMe electronic disk acquires an NVMe I/O writing instruction in an NVMe command sending queue and sends a memory reading request to NVMe command processing logic;

step C5: after receiving the memory read request, the NVMe command processing logic sends a read return to the PCIe sending engine within 10 clock cycles, starts the DMA transmission logic, takes out data from the data cache space, and sends out the data from the PCIe sending engine after write data buffer control;

step C6: the PCIe receiving engine receives the command completion status information sent by the SSD and writes the command completion status information into an NVMe command completion queue;

step C7: the NVMe command processing logic monitors command completion states in all slots of an NVMe command completion queue in real time, acquires and analyzes the command completion states when detecting that a new command completion return state exists, and sends the command completion states to the queue processing logic;

step C8: the queue processing logic updates the command state of the corresponding slot position of the command to be complete or abnormal according to the command completion state, and updates the corresponding command state information in the command execution state queue;

step C9: and judging the execution result of the operation according to the completion state of the write command, if the completion state is normal, completing the execution of the write command, and if the completion state is abnormal, analyzing the reason according to the corresponding state of the slot command in the command execution state queue.

Images